WO2016145771A1 - 阵列基板及其制作方法以及显示装置 - Google Patents

阵列基板及其制作方法以及显示装置 Download PDF

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Publication number
WO2016145771A1
WO2016145771A1 PCT/CN2015/086632 CN2015086632W WO2016145771A1 WO 2016145771 A1 WO2016145771 A1 WO 2016145771A1 CN 2015086632 W CN2015086632 W CN 2015086632W WO 2016145771 A1 WO2016145771 A1 WO 2016145771A1
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layer
forming
photosensitive
array substrate
pixel
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PCT/CN2015/086632
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English (en)
French (fr)
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辛龙宝
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京东方科技集团股份有限公司
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Priority to US14/912,558 priority Critical patent/US10096660B2/en
Publication of WO2016145771A1 publication Critical patent/WO2016145771A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method of fabricating the same, and a display device.
  • An AMOLED (Active-Matrix Organic Light Emitting Diode) display has a TFT (Thin Film Transistor) and a pixel on the pixel due to the current driving characteristics of the OLED (Organic Light Emitting Diode).
  • Multi-capacitor design such as the circuit structure shown in Figure 1.
  • the corresponding pixel arrangement diagram is shown in Figure 2.
  • the increasing performance requirements for display have made the design of pixel circuits challenging. For example, as shown in FIG. 3, in order to improve the short circuit risk caused by metal climbing in the via hole in the OLED, the pixel defining layer is used to fill the original cathode to be connected to the anode.
  • the vias as shown in Figure 4, cause a decrease in aperture ratio.
  • the capacitance is increased by providing Metal 3 (i.e., a metal that does not belong to the gate metal layer and the source/drain metal layer), as shown in Fig. 6, but the aperture ratio is still lowered.
  • Metal 3 i.e., a metal that does not belong to the gate metal layer and the source/drain metal layer
  • the technical problem to be solved by the present disclosure is how to effectively utilize the surrounding area of the via hole in the case where the opening area is inevitably lost at the via of the display panel (ie, the aperture ratio is lowered).
  • each pixel group has a plurality of sub-pixels, each of the sub-pixels including a light-emitting region and a light-emitting layer missing region, and each pixel group
  • the luminescent layer missing region of the plurality of sub-pixels defines a first region
  • a photosensitive unit is provided for generating an electrical signal based on the sensed light intensity.
  • the light emitting region is provided with a driving transistor, and the light emitting layer missing region is formed with a pixel defining layer, and below the pixel defining layer, the first electrode of each subpixel is electrically connected to the subpixel through a via The source or drain of the drive transistor.
  • the photosensitive unit comprises:
  • a phototransistor having a photosensitive active layer over the planar layer and a channel region of the photosensitive active layer at least partially not covered by the pixel defining layer, the source and the drain being over the planar layer and respectively located at the photosensitive active layer thereof Below the ends, the gate is between the passivation layer and the planar layer.
  • the source and the drain of the phototransistor are in the same layer as the first electrode of the sub-pixel.
  • the photosensitive unit further includes:
  • a readout transistor having an active layer overlying the planarization layer, a source and a drain overlying the planarization layer and underlying its active layer, a gate between the passivation layer and the planarization layer .
  • the photosensitive unit further comprises: a photosensitive cell driving line located above the passivation layer and a photosensitive cell signal readout line located above the planar layer.
  • the present disclosure also proposes a display device comprising the array substrate of any of the above.
  • the display device further includes:
  • the color film substrate is provided with a black matrix in a region corresponding to the photosensitive unit, wherein the black matrix is provided with a notch, and the notch and the photosensitive active layer of the photosensitive transistor of the photosensitive unit The location corresponds.
  • the present disclosure also proposes a method for fabricating an array substrate, comprising:
  • a photosensitive unit After forming a driving transistor of a predetermined sub-pixel, in a first region defined by respective predetermined light-emitting layer missing regions of a plurality of predetermined sub-pixels included in one pixel group, a photosensitive unit is formed for sensing The light intensity generates an electrical signal.
  • the step of forming the photosensitive unit comprises:
  • a pixel defining layer is formed, the channel region of the photosensitive active layer being at least partially not covered by the pixel defining layer.
  • the step of forming the photosensitive unit further includes:
  • a source and a drain of the readout transistor are formed on the flat layer while forming a source and a drain of the phototransistor.
  • the method for fabricating the array substrate further includes:
  • a first electrode of the sub-pixel is formed on the flat layer while forming a source and a drain of the phototransistor.
  • the method for fabricating the array substrate further includes:
  • a fill metal is formed in the source and drain vias in the passivation layer while forming the gate of the phototransistor.
  • the method for fabricating the array substrate further includes:
  • a signal readout line is formed on the flat layer while forming the source and drain of the phototransistor.
  • the photosensitive cells in the non-light-emitting regions of the sub-pixels ie, the light-emitting layer-deficient regions
  • the non-light-emitting regions of the sub-pixels can be fully utilized, that is, the open area lost by the sub-pixels is fully utilized, so that the array
  • the circuit structure in the substrate is more compact and reasonable, and the function of sensitization positioning is also realized.
  • FIG. 7 shows a schematic diagram of a pixel structure in accordance with an embodiment of the present disclosure
  • FIG. 8 is a block diagram showing a structure of a driving transistor according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural view of a photosensitive unit according to an embodiment of the present disclosure.
  • FIG. 10 shows a circuit schematic of a photosensitive unit in accordance with an embodiment of the present disclosure
  • FIG. 11 shows a circuit schematic of a photosensitive unit in accordance with another embodiment of the present disclosure.
  • FIG. 12 shows a schematic diagram of a black matrix in accordance with an embodiment of the present disclosure
  • FIG. 13 shows a schematic diagram of a black matrix according to another embodiment of the present disclosure.
  • 14 to 18 are schematic views showing a method of fabricating an array substrate according to an embodiment of the present disclosure.
  • an array substrate includes a plurality of pixel groups 13, wherein each pixel group 13 has a plurality of sub-pixels 11, each of which includes a light-emitting region and a light-emitting layer missing region. And the luminescent layer missing region of the plurality of sub-pixels 11 of each pixel group 13 defines one first region 12.
  • each pixel group includes four sub-pixels as an example. Actually, each pixel group may also include other numbers of sub-pixels, as long as the luminescent layer missing regions of all sub-pixels in the pixel group. Combine to define a first area. At the same time, the pixel group is not equivalent to a pixel, and the sub-pixel of each pixel group may come from one pixel or may come from a plurality of different pixels. In addition, the first area shown in FIG. 7 is a square, but may be other shapes as long as the photosensitive unit can be provided.
  • a photosensitive unit is provided, and the photosensitive unit is configured to generate an electrical signal based on the sensed light intensity.
  • the light-emitting layer missing region of the sub-pixel is a via region corresponding to the pixel structure thereof.
  • the first region may include, in addition to the light-emitting layer missing region of each of the sub-pixels in one pixel group, an area in which pixel circuits (including driving transistors and corresponding data lines and gate lines) are not disposed between the sub-pixels.
  • the non-light-emitting region of the sub-pixel ie, the missing region of the light-emitting layer
  • the circuit structure in the column substrate is more compact and reasonable, and the function of sensitization positioning is also realized.
  • the light emitting region is provided with a driving transistor, and the light emitting layer missing region is formed with the pixel defining layer 1.
  • the first electrode 2 of each sub-pixel 11 is electrically connected to the source or drain of the driving transistor of the sub-pixel 11 through a via.
  • the first electrode 2 is generally an anode of an organic light emitting diode. However, when the organic light emitting diode is of an inverted type, the first electrode 2 may be the cathode of the organic light emitting diode.
  • the first electrode 2 may be overlapped by a metal and a source or a drain of the driving transistor, and a via hole may be formed in the planar layer 4 to accommodate the metal.
  • the metal can be formed to extend over the surface of the passivation layer 5, and since the passivation layer 5 is generally an insulating structure, the metal extension can form a capacitance with the source or drain to which it is attached. Thereby increasing the capacitance density of the pixel.
  • the photosensitive unit comprises:
  • the photoreceptor transistor 3 has its photosensitive active layer 31 on top of the flat layer 4 and the channel region of the photosensitive active layer 31 is at least partially not covered by the pixel defining layer 1, and its source 32 and drain 33 are located above the flat layer 4. And respectively located under both ends of the photosensitive active layer 31, the gate electrode 34 is located between the passivation layer 4 and the flat layer 5.
  • the source 32 and the drain 33 of the phototransistor 3 are in the same layer as the first electrode 2 of the sub-pixel.
  • the source 32 and the drain 33 of the phototransistor 3 and the first electrode 2 of the sub-pixel are disposed in the same layer, so that the three can be formed by the same photolithography process to simplify the fabrication process.
  • the photosensitive unit further comprises:
  • the readout transistor 6 has an active layer 61 on top of the planarization layer 4, a source 62 and a drain 63 on the planarization layer 4 and below the active layer 61, and a gate 64 on the passivation layer 4. Between the flat layer 5.
  • the photosensitive unit further includes: a photosensitive unit driving line 7 located above the passivation layer 5 and a photosensitive unit signal readout line 8 located above the flat layer 4.
  • the photosensitive active layer 31 and the phototransistor gate 34 can be made of a photosensitive material, and the phototransistor 3 can be converted by sensing external light.
  • the read transistor 6 is transmitted to a corresponding processor for specific calculation to determine the position of the light change, thereby achieving photosensitive positioning.
  • the turn-on and turn-off of the readout transistor 6 can be controlled, and only when the readout transistor 6 is in an on state, the induced current generated by the phototransistor 3 can be transmitted to the processor (not shown) show).
  • the phototransistor 3 presented in FIG. 9 is a triode, and the phototransistor 3 can also be set as a diode according to specific needs. Specifically, when a higher positioning accuracy is required, the photo transistor 3 can be set as a triode; and in the case where the precision is required to be low and the manufacturing process is relatively simple, the photo transistor 3 can be set as a diode.
  • the specific circuit structure of the photosensitive unit can be set as needed, as shown in FIG. 11, in order to increase the capacitance density of the pixel, an additional capacitance can be set in the photosensitive unit.
  • the present disclosure also proposes a display device comprising the array substrate of any of the above.
  • the display device in this embodiment may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device further includes:
  • the color film substrate is provided with a black matrix 9 in a region corresponding to the photosensitive unit, wherein the black matrix 9 is provided with a notch 10, and the notch 10 corresponds to the position of the photosensitive active layer 31 of the photosensitive transistor 3 of the photosensitive unit.
  • Light can be incident from the gap 10, and when the incident light changes (either from nothing or from nothing to nothing, it can be from large to small or from small to large), the induced current generated by the photosensitive unit occurs.
  • the corresponding processor can determine the photosensitive unit whose induced current changes, and then determine its coordinates on the display panel, thereby achieving photosensitive positioning.
  • the black matrix may be disposed only in the first region, or may be disposed in an adjacent region of each of the two sub-pixels, as shown in FIG. 13, to increase the light-shielding area, and to prevent the light-receiving transistor 3 from receiving erroneous determination of light at other positions. .
  • the present disclosure also proposes a method for fabricating an array substrate, comprising:
  • a photosensitive unit for forming the light according to the sensing Strong changes After forming the driving transistor of the predetermined sub-pixel, in the first region defined by the respective predetermined light-emitting layer missing regions of the plurality of predetermined sub-pixels included in one pixel group, a photosensitive unit for forming the light according to the sensing Strong changes generate electrical signals.
  • the step of forming a photosensitive unit comprises:
  • the gate electrode 34 of the phototransistor 3 is formed on the passivation layer 5, and may be formed by using a metal3 method;
  • the source 32 and the drain 33 of the phototransistor 3 are formed on the flat layer 4;
  • a photosensitive active layer 31 is formed on the source 32 and the drain 33;
  • a pixel defining layer 1 is formed, and a channel region of the photosensitive active layer 31 is at least partially not covered by the pixel defining layer 1.
  • the step of forming the photosensitive unit further includes:
  • the source 62 and the drain 63 of the readout transistor 6 are formed on the flat layer 5 while forming the source 32 and the drain 33 of the phototransistor 3.
  • the method for fabricating the array substrate further includes:
  • the first electrode of the sub-pixel is formed on the flat layer 4 while forming the source 32 and the drain 33 of the phototransistor.
  • the first electrode may be an anode of an organic light emitting diode.
  • the first electrode can be made of the same metal as the source 32 and the drain 33, so that the first electrode can function as an anode and can also reflect the organic light emitting diode. Part of the light emitted, thereby increasing the aperture ratio of the organic light emitting diode.
  • the first electrode and the source 32 and the drain 33 can be formed in one process, which simplifies the manufacturing process.
  • the organic light emitting diode is a bottom emitting structure
  • light needs to be emitted downward through the first electrode.
  • a transparent metal oxide can be used to form the first electrode, such as indium tin oxide or indium oxide. Zinc and so on.
  • the method for fabricating the array substrate further includes:
  • a filling metal is formed in the source/drain via hole in the passivation layer 5, and specifically, it may be formed by a metal3 method.
  • the method for fabricating the array substrate further includes:
  • Photosensitive unit driving is formed on the passivation layer 5 while forming the gate electrode 34 of the phototransistor 3 Line 7;
  • the signal readout line 8 is formed on the flat layer 4 while forming the source 32 and the drain 33 of the phototransistor 3.
  • the layer structure in the driving transistor When the layer structure in the driving transistor is formed, the layer structure in the photosensitive unit can be formed by the same photolithography process to reduce the number of processes and simplify the process flow.
  • the technical solution of the present disclosure has been described in detail above with reference to the accompanying drawings.
  • the aperture ratio is inevitably lowered.
  • the non-light-emitting regions of the sub-pixels can be fully utilized, that is, the open area lost by the sub-pixels is fully utilized, so that the circuit structure in the array substrate It is more compact and reasonable, and it also realizes the function of photographic positioning.
  • the term “first” is used for descriptive purposes only and is not to be construed as indicating or implying relative importance.
  • the term “plurality” refers to two or more, unless specifically defined otherwise.

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Abstract

一种阵列基板及其制作方法以及显示装置，该阵列基板包括多个像素组（13），其中每个像素组（13）具有多个子像素（11），每个子像素（11）包括发光区域和发光层缺失区域，且每个像素组（13）的多个子像素（11）的发光层缺失区域限定一个第一区域（12）；在第一区域（12）中，设置有感光单元（3、6、7、8），感光单元（3、6、7、8）用于根据感应到的光强生成电信号。

Description

阵列基板及其制作方法以及显示装置
相关申请的交叉参考
本申请主张在2015年3月16日在中国提交的中国专利申请号No.201510114269.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及显示技术领域，尤其涉及一种阵列基板及其制作方法以及显示装置。
背景技术
AMOLED(Active-matrix organic light emitting diode，主动矩阵有机发光二极体)显示屏由于OLED(有机发光二极体)电流驱动的特性，在像素上带有多TFT(Thin Film Transistor，薄膜晶体管)和多电容的设计，例如图1所示的电路结构。相应的像素排列示意图如图2所示。但是对于显示性能要求的日益提高，使得像素电路在设计上的提升存在巨大挑战。例如图3所示，为了改善OLED中阴极和阳极通过过孔搭接，在过孔中由于金属爬坡所引发的短路风险，现有技术中采用像素界定层来填补原阴极搭接到阳极所用的过孔，如图4所示，会导致开口率降低。
并且，为了提高单位面积像素数，会存在电容过小的问题，如图5所示。现有技术中通过设置Metal3(即，不属于栅金属层和源漏金属层的金属)来提高电容，如图6所示，但是仍会降低开口率。
也就是说，为了弥补像素结构中的种种缺陷，势必会导致开口率降低。
发明内容
(一)要解决的技术问题
本公开文本所要解决的技术问题是，在显示面板的过孔处必然失去开口面积(即，开口率降低)的情况下，如何有效利用过孔的周围区域。
(二)技术方案
为此目的，本公开文本提出了一种阵列基板，该阵列基板包括多个像素组，其中每个像素组具有多个子像素，每个子像素包括发光区域和发光层缺失区域，且每个像素组的所述多个子像素的发光层缺失区域限定一个第一区域；
在所述第一区域中，设置有感光单元，所述感光单元用于根据感应到的光强生成电信号。
可选地，所述发光区域设置有驱动晶体管，所述发光层缺失区域形成有像素界定层，在所述像素界定层之下，每个子像素的第一电极通过过孔电连接至该子像素的驱动晶体管的源极或漏极。
可选地，所述感光单元包括：
感光晶体管，其感光有源层位于平坦层之上且感光有源层的沟道区至少部分不被像素界定层覆盖，其源极和漏极位于平坦层之上且分别位于其感光有源层两端之下，其栅极位于钝化层和平坦层之间。
可选地，所述感光晶体管的源极和漏极与子像素的第一电极处于同一层。
可选地，所述感光单元还包括：
读出晶体管，其有源层位于平坦层之上，其源极和漏极位于平坦层之上且位于其有源层之下，其栅极位于所述钝化层和所述平坦层之间。
可选地，所述感光单元还包括：位于钝化层之上的感光单元驱动线和位于平坦层之上的感光单元信号读出线。
本公开文本还提出了一种显示装置，包括上述任一项所述的阵列基板。
可选地，所述显示装置还包括：
彩膜基板，所述彩膜基板在与所述感光单元对应的区域设置有黑矩阵，其中，所述黑矩阵上设置有缺口，所述缺口与所述感光单元的感光晶体管的感光有源层位置对应。
本公开文本还提出了一种阵列基板制作方法，包括：
在形成预定子像素的驱动晶体管之后，在由一个像素组包括的多个预定子像素的各自预定的发光层缺失区域限定的第一区域中，形成感光单元，所述感光单元用于根据感应到的光强生成电信号。
可选地，所述形成所述感光单元的步骤包括：
在钝化层上形成感光晶体管的栅极；
形成平坦层；
在所述平坦层上形成感光晶体管的源极和漏极；
在所述源极和所述漏极上形成感光有源层；以及
形成像素界定层，所述感光有源层的沟道区至少部分不被所述像素界定层覆盖。
可选地，所述形成所述感光单元的步骤还包括：
在形成感光晶体管的栅极的同时，在所述钝化层上形成读出晶体管的栅极；以及
在形成感光晶体管的源极和漏极的同时，在所述平坦层上形成读出晶体管的源极和漏极。
可选地，所述阵列基板制作方法还包括：
在形成感光晶体管的源极和漏极的同时，在所述平坦层上形成子像素的第一电极。
可选地，所述阵列基板制作方法还包括：
在形成感光晶体管的栅极的同时，在钝化层中的源漏极过孔中形成填充金属。
可选地，所述阵列基板制作方法还包括：
在形成感光晶体管的栅极的同时，在钝化层上形成感光单元驱动线；以及
在形成感光晶体管的源极和漏极的同时，在平坦层上形成信号读出线。
(三)有益效果
本公开文本实施例至少具有如下有益效果：
根据上述技术方案，通过在子像素的不发光区域(即，发光层缺失区域)中设置感光单元，可以充分利用子像素的不发光区域，即子像素失去的开口面积得到了充分利用，使得阵列基板中的电路结构更加紧凑和合理，同时还实现了感光定位的功能。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1至图6示出了现有技术中像素结构中开口率降低的原因；
图7示出了根据本公开文本一个实施例的像素结构的示意图；
图8示出了根据本公开文本一个实施例的驱动晶体管的结构示意图；
图9示出了根据本公开文本一个实施例的感光单元的结构示意图；
图10示出了根据本公开文本一个实施例的感光单元的电路示意图；
图11示出了根据本公开文本另一个实施例的感光单元的电路示意图；
图12示出了根据本公开文本一个实施例的黑矩阵的示意图；
图13示出了根据本公开文本另一个实施例的黑矩阵的示意图；以及
图14至图18示出了根据本公开文本一个实施例的阵列基板制作方法示意图。
附图标号说明：
1-像素界定层；2-子像素的第一电极；3-感光晶体管；31-感光有源层；32-感光晶体管源极；33-感光晶体管漏极；34-感光晶体管栅极；4-平坦层；5-钝化层；6-读出晶体管；61-读出晶体管有源层；62-读出晶体管源极；63-读出晶体管漏极；64-读出晶体管栅极；7-感光单元驱动线；8-感光单元信号读出线；9-黑矩阵；10-缺口；11-子像素；12-第一区域；13-像素组。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得 的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
下面将结合附图和实施例，对本公开文本的具体实施方式作进一步详细描述。以下实施例用于说明本公开文本，但不用来限制本公开文本的范围。
如图7所示，根据本公开文本一个实施例的阵列基板，包括多个像素组13，其中，每个像素组13具有多个子像素11，每个子像素11包括发光区域和发光层缺失区域，且每个像素组13的多个子像素11的发光层缺失区域限定一个第一区域12。
注意在本公开文本中，是以每个像素组包括四个子像素为例进行说明，实际上每个像素组也可以包括其他数量的子像素，只要像素组内的所有子像素的发光层缺失区域组合起来能限定出一个第一区域即可。同时，像素组并不等同于像素，每个像素组的子像素可以来自一个像素，也可以来自多个不同的像素。另外，图7中示出的第一区域为正方形，但是也可以为其他形状，只要能设置感光单元即可。
在第一区域中，设置有感光单元，感光单元用于根据感应到的光强生成电信号。
子像素的发光层缺失区域即其像素结构对应的过孔区域。第一区域除了包括一个像素组中每个子像素的发光层缺失区域之外，还可以包括子像素之间未设置像素电路(包括驱动晶体管以及相应的数据线和栅线)的区域。
通过在第一区域中设置感光单元，可以充分利用子像素的不发光区域(即，发光层缺失区域)，即子像素失去的开口面积得到了充分利用，使得阵 列基板中的电路结构更加紧凑和合理，同时还实现了感光定位的功能。
如图8所示，可选地，发光区域设置有驱动晶体管，发光层缺失区域形成有像素界定层1。在像素界定层之下，每个子像素11的第一电极2通过过孔电连接至该子像素11的驱动晶体管的源极或漏极。
设置感光单元并不会对晶体管中原有的过孔结构进行改动，而是主要设置在每四个晶体管相邻的发光层缺失区域中。其中第一电极2一般情况下是有机发光二极管的阳极。但是在有机发光二极管为倒置型时，第一电极2则可以是有机发光二极管的阴极。
具体地，第一电极2可以通过金属和驱动晶体管的源极或漏极搭接，平坦层4中可以形成过孔来容纳该金属。通过一定的制作工艺，可以使得金属在钝化层5的表面形成一段延伸，并且由于钝化层5一般为绝缘结构，从而金属的延伸段能够和搭接到的源极或漏极形成电容，从而增大像素的电容密度。
如图9所示，可选地，感光单元包括：
感光晶体管3，其感光有源层31位于平坦层4之上且感光有源层31的沟道区至少部分不被像素界定层1覆盖，其源极32和漏极33位于平坦层4之上且分别位于其感光有源层31两端之下，其栅极34位于钝化层4和平坦层5之间。
可选地，感光晶体管3的源极32和漏极33与子像素的第一电极2处于同一层。同层设置感光晶体管3的源极32和漏极33与子像素的第一电极2，可以使得三者通过同一道光刻工艺形成，以简化制作工艺。
可选地，感光单元还包括：
读出晶体管6，其有源层61位于平坦层4之上，其源极62和漏极63位于平坦层4之上且位于其有源层61之下，其栅极64位于钝化层4和平坦层5之间。
可选地，感光单元还包括：位于钝化层5之上的感光单元驱动线7和位于平坦层4之上的感光单元信号读出线8。
感光单元的具体电路结构如图10所示。其中，感光有源层31和感光晶体管栅极34都可以由感光材料制成，感光晶体管3通过感应外界光线变换可 以生成感应电流，通过读出晶体管6传输至相应的处理器进行具体计算，以确定光线变化的位置，从而实现感光定位。
通过为感光单元驱动线7传输不同的信号，可以控制读出晶体管6的开启和关闭，只有当读出晶体管6处于开启状态时，感光晶体管3生成的感应电流才能传输到处理器(图中未示出)。
需要说明的是，图9中所呈现的感光晶体管3是三极管，实际上根据具体需要，也可以将感光晶体管3设置为二极管。具体地，在需要较高定位精度时，可以将感光晶体管3设置为三极管；而在需要精度较低，且需要制作工艺较为简单的情况下，可以将感光晶体管3设置为二极管。
并且，感光单元的具体电路结构可以根据需要设置，如图11所示，为了增加像素的电容密度，可以在感光单元中设置额外的电容。
本公开文本还提出了一种显示装置，包括上述任一项的阵列基板。需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
如图12所示，可选地，显示装置还包括：
彩膜基板，彩膜基板在与感光单元对应的区域设置有黑矩阵9，其中，黑矩阵9上设置有缺口10，缺口10与感光单元的感光晶体管3的感光有源层31位置对应。
光线可以从缺口10射入，当射入的光线发生变化时(可以是从无到有或者从有到无，亦可以是从大变小或从小变大)，感光单元产生的感应电流即发生相应变化，相应的处理器可以确定感应电流发生变化的感光单元，进而确定其在显示面板上的坐标，从而实现感光定位。
具体地，黑矩阵可以只设置在第一区域，也可以设置在每两个子像素的相邻区域，如图13所示，以提高遮光面积，避免感光晶体管3接收到其他位置的光线产生错误判定。
本公开文本还提出了一种阵列基板制作方法，包括：
在形成预定子像素的驱动晶体管之后，在由一个像素组包括的多个预定子像素的各自预定的发光层缺失区域限定的第一区域中，形成感光单元，感光单元用于根据感应到的光强变化生成电信号。
可选地，所述形成感光单元的步骤包括：
如图14所示，在钝化层5上形成感光晶体管3的栅极34，具体可以采用metal3方式形成；
如图15所示，形成平坦层4；
如图16所示，在平坦层4上形成感光晶体管3的源极32和漏极33；
如图17所示，在源极32和漏极33上形成感光有源层31；以及
如图18所示，形成像素界定层1，感光有源层31的沟道区至少部分不被像素界定层1覆盖。
可选地，所述形成感光单元的步骤还包括：
在形成感光晶体管3的栅极34的同时，在钝化层5上形成读出晶体管6的栅极64；以及
在形成感光晶体管3的源极32和漏极33的同时，在平坦层5上形成读出晶体管6的源极62和漏极63。
可选地，所示阵列基板制作方法还包括：
在形成感光晶体管的源极32和漏极33的同时，在平坦层4上形成子像素的第一电极。
第一电极可以是有机发光二极管的阳极。当有机发光二极管为顶发射结构时，可以采用与源极32、漏极33相同的金属制作第一电极，使得第一电极除了起到阳极的作用之外，还能够起到反射有机发光二极管向下发出的部分光线，从而提高有机发光二极管的开口率。并且可以在一道工艺中形成第一电极和源极32、漏极33，简化制作流程。
当有机发光二极管为底发射结构时，光线需要透过第一电极向下射出，此时需要保证第一电极透明，因此可以采用透明金属氧化物来形成第一电极，例如氧化铟锡、氧化铟锌等。
可选地，所述阵列基板制作方法还包括：
在形成感光晶体管3的栅极34的同时，在钝化层5中的源漏极过孔中形成填充金属，具体可以采用metal3方式形成。
可选地，所述阵列基板制作方法还包括：
在形成感光晶体管3的栅极34的同时，在钝化层5上形成感光单元驱动 线7；以及
在形成感光晶体管3的源极32和漏极33的同时，在平坦层4上形成信号读出线8。
在形成驱动晶体管中的层结构时，可以通过同一道光刻工艺形成感光单元中的层结构，以减少工艺次数，简化工艺流程。
以上结合附图详细说明了本公开文本的技术方案，考虑到相关技术中，为了弥补像素结构中的种种缺陷，势必会导致开口率降低。根据本公开文本的技术方案，通过在子像素的不发光区域中设置感光单元，可以充分利用子像素的不发光区域，即子像素失去的开口面积得到了充分利用，使得阵列基板中的电路结构更加紧凑和合理，同时还实现了感光定位的功能。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本公开文本中，术语“第一”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上仅为本公开文本的优选实施例而已，并不用于限制本公开文本，对于本领域的技术人员来说，本公开文本可以有各种更改和变化。凡在本公开文本的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开文本的保护范围之内。

Claims (14)

  1. 一种阵列基板，包括：多个像素组，
    其中，每个像素组具有多个子像素，每个子像素包括发光区域和发光层缺失区域，且每个像素组的所述多个子像素的发光层缺失区域限定一个第一区域；
    在所述第一区域中，设置有感光单元，所述感光单元用于根据感应到的光强生成电信号。
  2. 根据权利要求1所述的阵列基板，其中，所述发光区域设置有驱动晶体管，所述发光层缺失区域形成有像素界定层，在所述像素界定层之下，每个子像素的第一电极通过过孔电连接至该子像素的驱动晶体管的源极或漏极。
  3. 根据权利要求2所述的阵列基板，其中，所述感光单元包括：
    感光晶体管，其感光有源层位于平坦层之上且感光有源层的沟道区至少部分不被所述像素界定层覆盖，其源极和漏极位于平坦层之上且分别位于其感光有源层两端之下，其栅极位于钝化层和平坦层之间。
  4. 根据权利要求3所述的阵列基板，其中，所述感光晶体管的源极和漏极与子像素的第一电极处于同一层。
  5. 根据权利要求3所述的阵列基板，其中，所述感光单元还包括：
    读出晶体管，其有源层位于平坦层之上，其源极和漏极位于平坦层之上且位于其有源层之下，其栅极位于所述钝化层和所述平坦层之间。
  6. 根据权利要求3所述的阵列基板，其中，所述感光单元还包括：位于钝化层之上的感光单元驱动线和位于平坦层之上的感光单元信号读出线。
  7. 一种显示装置，包括根据权利要求1至6中任一项所述的阵列基板。
  8. 根据权利要求7所述的显示装置，还包括：
    彩膜基板，所述彩膜基板在与所述感光单元对应的区域设置有黑矩阵，其中，所述黑矩阵上设置有缺口，所述缺口与所述感光单元的感光晶体管的感光有源层位置对应。
  9. 一种阵列基板制作方法，包括：
    在形成预定子像素的驱动晶体管之后，在由一个像素组包括的多个预定子像素的各自预定的发光层缺失区域限定的第一区域中，形成感光单元，所述感光单元用于根据感应到的光强生成电信号。
  10. 根据权利要求9所述的阵列基板制作方法，其中，所述形成所述感光单元的步骤包括：
    在钝化层上形成感光晶体管的栅极；
    形成平坦层；
    在所述平坦层上形成感光晶体管的源极和漏极；
    在所述源极和所述漏极上形成感光有源层；以及
    形成像素界定层，所述感光有源层的沟道区至少部分不被所述像素界定层覆盖。
  11. 根据权利要求10所述的阵列基板制作方法，其中，所述形成所述感光单元的步骤还包括：
    在形成感光晶体管的栅极的同时，在所述钝化层上形成读出晶体管的栅极；以及
    在形成感光晶体管的源极和漏极的同时，在所述平坦层上形成读出晶体管的源极和漏极。
  12. 根据权利要求10或11所述的阵列基板制作方法，还包括：
    在形成感光晶体管的源极和漏极的同时，在所述平坦层上形成子像素的第一电极。
  13. 根据权利要求10或11所述的阵列基板制作方法，还包括：
    在形成感光晶体管的栅极的同时，在钝化层中的源漏极过孔中形成填充金属。
  14. 根据权利要求10或11所述的阵列基板制作方法，还包括：
    在形成感光晶体管的栅极的同时，在钝化层上形成感光单元驱动线；以及
    在形成感光晶体管的源极和漏极的同时，在平坦层上形成信号读出线。
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