WO2016124104A1 - 一种适用于晶闸管的混合触发电路 - Google Patents

一种适用于晶闸管的混合触发电路 Download PDF

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WO2016124104A1
WO2016124104A1 PCT/CN2016/072469 CN2016072469W WO2016124104A1 WO 2016124104 A1 WO2016124104 A1 WO 2016124104A1 CN 2016072469 W CN2016072469 W CN 2016072469W WO 2016124104 A1 WO2016124104 A1 WO 2016124104A1
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trigger
thyristor
trigger circuit
diode
circuit
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PCT/CN2016/072469
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English (en)
French (fr)
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贺之渊
杨卫刚
吕铮
冯静波
***
于海玉
廖敏
彭玲
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国家电网公司
国网智能电网研究院
中电普瑞电力工程有限公司
国网山东省电力公司电力科学研究院
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Publication of WO2016124104A1 publication Critical patent/WO2016124104A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/06—Circuits specially adapted for rendering non-conductive gas discharge tubes or equivalent semiconductor devices, e.g. thyratrons, thyristors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region

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  • the invention relates to a trigger circuit, in particular to a hybrid trigger circuit suitable for a thyristor.
  • the conventional thyristor is a current-type trigger, that is, the thyristor is triggered to be turned on by injecting a sufficient current into the gate, and once the thyristor is turned on, the gate trigger current is not required. If the gate trigger current still exists after the thyristor is turned on, the poor heat dissipation of the gate will cause the temperature to rise, which will further cause the gate to burn. For the above reasons, the pulse width of the gate trigger circuit is required.
  • the central control board, thyristor and bypass switch trigger board and the BOD trigger board together complete the control and protection functions of the entire sub-module, including the triggering of the thyristor, and the three circuit boards are required. More wires and fiber connections require more interface problems, which results in a complicated structure and difficulty in wiring.
  • the trigger circuit is a pulse group mode, which effectively avoids long-term high level damage to the gate.
  • the present invention provides a hybrid trigger circuit suitable for a thyristor.
  • the software mode trigger circuit can be determined by logic judgment, and the trigger pulse width and the continuous trigger time can be set by software; the hardware mode trigger circuit It can withstand high overvoltage value and can continuously trigger thyristor; software mode trigger circuit has high electrical isolation; hybrid trigger circuit suitable for thyristor has simple structure, easy implementation and low cost.
  • the invention provides a hybrid trigger circuit suitable for a thyristor, the circuit comprising a hardware mode trigger circuit and a software mode trigger circuit; the hardware mode trigger circuit and the software mode trigger circuit are connected in parallel through a gate line and a cathode line for triggering Thyristor.
  • the hardware trigger mode circuit includes a voltage dividing resistor R2, a voltage dividing resistor R3, a storage capacitor C2, a storage capacitor C3, a turning diode BOD, a discharging resistor R4, a current limiting resistor R5, a current limiting resistor R6, an anti-reverse diode D3, and Protection diode D4.
  • the software trigger mode circuit includes a first NAND gate Y1, a second NAND gate Y2, a pull-up resistor R1, a transistor Q1, a pulse transformer T1, an anti-reverse diode D1, and a protection diode D2.
  • One end of the pull resistor R1 is connected to the power supply VCC, the other end is connected to the base of the transistor Q1, and the other end of the pulse transformer T1 is grounded; the protection diode D2 is connected in parallel with the secondary side of the pulse transformer T1, and the anode of the anti-reverse diode D1 and the protection diode D2 The cathode is connected, the cathode of the anti-reverse diode D1 is connected to the gate of the thyristor, and the cathode of the thyristor is connected to the anode of the anti-reverse diode D2.
  • Transistor Q1 is a PNP triode.
  • the anti-reverse diode D1 prevents the energy of the hardware mode trigger circuit from being transferred to the software trigger mode circuit; the anti-reverse diode D3 prevents the energy of the software mode trigger circuit from being transferred to the hardware trigger mode circuit.
  • the software mode trigger circuit can be determined by logic judgment, and the trigger pulse width and continuous trigger time can be set by software
  • the hybrid trigger circuit suitable for the thyristor has a simple structure, is easy to implement, and has low cost.
  • FIG. 1 is a structural diagram of a hybrid trigger circuit suitable for a thyristor in an embodiment of the present invention.
  • the voltage dividing resistor R2 and the voltage dividing resistor R3 are connected in series and connected in parallel with the external capacitor C1, the storage capacitor C2 is connected in parallel with the voltage dividing resistor R3, the turning diode BOD is connected in series with the discharging resistor R4, and is connected in parallel with the storage capacitor C2; the current limiting resistor R5 In series with the storage capacitor C3 and in parallel with the discharge resistor R4, the current limiting resistor R6 is connected in series with the anti-reverse diode D3 and the protection diode D4 in parallel with the storage capacitor C3.
  • the resistor R6 is connected to the anode of the anti-reverse diode D3, and the anti-reverse diode After the cathode of D3 is connected to the cathode of the protection diode D4, the gate of the thyristor is connected, and the anode of the protection diode D4 is connected to the cathode of the thyristor.
  • the storage capacitor C2 is charged by the voltage dividing resistor R2, and the charging time constant is R2 ⁇ C2, and the voltage of the storage capacitor C2 after charging is stable is the same as the voltage of the voltage dividing resistor R3.
  • Hardware mode trigger circuit design special application Because the circuit is used in a relatively harsh electromagnetic environment, it is hoped that the storage capacitor C3 will remain at 0V during the non-operation of the turning diode BOD, if the voltage on the storage capacitor C3 reaches At a certain level, the thyristor SCR will be triggered by mistake. In order to avoid charging the storage capacitor C3 in the harsh electromagnetic environment and the leakage current of the turning diode BOD, the discharge resistor R4 is added, so that the charge on the storage capacitor C3 is discharged through the current limiting resistor R5 and the discharging resistor R4.
  • the trigger signal TRI and the high level signal are input to the two input ends of the first NAND gate Y1, the output end of the first NAND gate Y1 is connected to the input end of the second NAND gate Y2, and the trigger enable signal TRI_EN is input to the second The other input end of the NAND gate Y2, the output end of the second NAND gate Y2 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is connected to the power source VCC, and the collector of the transistor Q1 is connected to one end of the primary side of the pulse transformer T1.
  • One end of the pull resistor R1 is connected to the power supply VCC, the other end is connected to the base of the transistor Q1, and the other end of the pulse transformer T1 is grounded; the protection diode D2 is connected in parallel with the secondary side of the pulse transformer T1, and the anode of the anti-reverse diode D1 and the protection diode D2 The cathode is connected, the cathode of the anti-reverse diode D1 is connected to the gate of the thyristor, and the cathode of the thyristor is connected to the anode of the anti-reverse diode D2.
  • Transistor Q1 is a PNP triode.
  • the software mode trigger circuit works as follows:
  • a logic level identical to the trigger signal TRI is generated at the output of the second NAND gate Y2, that is, There is a period of time for the level signal, which makes the transistor Q1 turn on, that is, the pulse transformer T1
  • the primary side is energized for a period of time, and the same logic level signal as the trigger enable signal TRI_EN is obtained on the secondary side, which triggers the thyristor SCR to be turned on.
  • Software mode trigger circuit design special application software can set the width of the trigger pulse signal, that is, set the width of the trigger signal TRI and the trigger enable signal TRI_EN, and can also continuously issue the trigger thyristor command, the continuous period depends on the recovery time of the pulse transformer T1, Because the pulse transformer conducts energy through the core, the core requires a recovery time.
  • the anti-reverse diode D1 prevents the energy of the hardware mode trigger circuit from being transferred to the software trigger mode circuit; the anti-reverse diode D3 prevents the energy of the software mode trigger circuit from being transferred to the hardware trigger mode circuit.
  • the thyristor is triggered by the logic of the software.
  • the software mode trigger circuit triggers the thyristor pulse width to be set by software
  • the software can issue a continuous trigger command to the thyristor, and the time interval should be as short as possible, depending on the recovery time of the isolated pulse transformer.
  • the total duration of continuous triggering is not too long to avoid damaging the gate of the thyristor.
  • the time interval and total duration of consecutive triggers are set by software.
  • the software mode trigger circuit is isolated from the hardware trigger circuit by the isolated pulse transformer;
  • the software mode trigger circuit is realized by isolating the pulse transformer, and the isolation voltage level is based on the design level of the transformer.
  • the hardware mode trigger circuit realizes hardware overvoltage protection through BOD (Break Over Diode);
  • the hardware mode trigger circuit can only protect against overvoltage, and can be used as an overvoltage backup protection for the software mode trigger circuit. Hardware overvoltage protection is achieved through BOD.
  • the hardware mode trigger circuit can withstand the overvoltage value for a long time
  • the hardware mode trigger circuit can continuously trigger the thyristor
  • the hardware mode trigger circuit can also continuously trigger the thyristor.
  • the continuous trigger time interval can be determined by the resistance value and the capacitance value.
  • the total duration of the continuous trigger is the same as the overvoltage duration.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Electronic Switches (AREA)

Abstract

一种适用于晶闸管的混合触发电路，包括硬件方式触发电路和软件方式触发电路。硬件方式触发电路和软件方式触发电路通过门极线和阴极线并联，用于触发晶闸管。软件方式触发电路通过逻辑判断后触发晶闸管，触发脉冲宽度和连续触发时间均可通过软件设置，并有较高的电气隔离。硬件方式触发电路可承受较高的过压值，并可连续触发晶闸管。该混合触发电路结构简单，易于实现，成本低。

Description

一种适用于晶闸管的混合触发电路 技术领域
本发明涉及一种触发电路，具体涉及一种适用于晶闸管的混合触发电路。
背景技术
常规晶闸管为电流型触发，即在门极注入足够大的电流即可将晶闸管触发导通，晶闸管一旦触发导通，即不需要门极触发电流。如果晶闸管导通后门极触发电流仍然存在，门极散热不好会导致温度升高，进一步会导致门极烧毁，基于以上原因，对门极触发电路的脉冲宽度有一定要求。
在已经投入运行的柔性直流示范工程中，中控板、晶闸管及旁路开关触发板和BOD触发板共同完成对整个子模块的控制和保护功能，包含了对晶闸管的触发，三个电路板需要较多的电线和光纤连接，需要较多的接口问题处理，这就造成了整个子模块结构复杂、接线困难。通过对以上三个电路板的改进，决定将三个电路板集成在一起，这样减少了接线及接口问题的处理，同时采用新一代的控制芯片，使得控制板变得更小，使结构设计和抗干扰设计更加容易，最终形成了晶闸管的混合触发电路。同时该触发电路为脉冲群方式，有效避免长期高电平对门极的损伤。
发明内容
为了克服上述现有技术的不足，本发明提供一种适用于晶闸管的混合触发电路，软件方式触发电路可通过逻辑判断后决定，触发脉冲宽度和连续触发时间均可通过软件设置；硬件方式触发电路可承受较高的过压值，并可连续触发晶闸管；软件方式触发电路有较高的电气隔离；适用于晶闸管的混合触发电路结构简单，易于实现，成本低。
为了实现上述发明目的，本发明采取如下技术方案：
本发明提供一种适用于晶闸管的混合触发电路，所述电路包括硬件方式触发电路和软件方式触发电路；所述硬件方式触发电路和软件方式触发电路通过门极线和阴极线并联，用于触发晶闸管。
所述硬件触发方式电路包括分压电阻R2、分压电阻R3、储能电容C2、储能电容C3、转折二极管BOD、放电电阻R4、限流电阻R5、限流电阻R6、防反二极管D3和保护二极管D4。
所述分压电阻R2和分压电阻R3串联后与外部电容C1并联，储能电容C2与分压电阻R3并联，转折二极管BOD与放电电阻R4串联后与储能电容C2并联；限流电阻R5与储能电容C3串联后与放电电阻R4并联，限流电阻R6与防反二极管D3、保护二极管D4串联后与储能电容C3并联，所述电阻R6连接防反二极管D3的阳极，防反二极管D3的阴极与保护二极管D4的阴极连接后，再接晶闸管的门极，保护二极管D4的阳极与晶闸管阴极相连。
所述储能电容C2通过分压电阻R2进行充电，充电时间常数为R2×C2，储能电容C2充电稳定后的电压与分压电阻R3上的电压相同。
所述软件触发方式电路包括第一与非门Y1、第二与非门Y2、上拉电阻R1、三极管Q1、脉冲变压器T1、防反二极管D1和保护二极管D2。
触发信号TRI和高电平信号输入给第一与非门Y1的两个输入端，第一与非门Y1的输出端连接第二与非门Y2的输入端，触发使能信号TRI_EN输入第二与非门Y2的另一输入端，第二与非门Y2的输出端连接三极管Q1的基极，三极管Q1的发射极连接电源VCC，三极管Q1的集电极连接脉冲变压器T1原边的一端，上拉电阻R1一端连接电源VCC，其另一端连接三极管Q1的基极，脉冲变压器T1原边另一端接地；所述保护二极管D2与脉冲变压器T1副边并联，防反二极管D1的阳极与保护二极管D2的阴极相连，防反二极管D1的阴极连接晶闸管的门极，晶闸管的阴极与防反二极管D2的阳极相连。
三极管Q1为PNP三极管。
防反二极管D1防止硬件方式触发电路的能量传递到软件触发方式电路中；防反二极管D3防止软件方式触发电路的能量传递到硬件触发方式电路中。
与现有技术相比，本发明的有益效果在于：
1)软件方式触发电路可通过逻辑判断后决定，触发脉冲宽度和连续触发时间均可通过软件设置；
2)硬件方式触发电路可承受较高的过压值，并可连续触发晶闸管；
3)软件方式触发电路有较高的电气隔离；
4)适用于晶闸管的混合触发电路结构简单，易于实现，成本低。
附图说明
图1是本发明实施例中适用于晶闸管的混合触发电路结构图。
具体实施方式
下面结合附图对本发明作进一步详细说明。
如图1，本发明提供一种适用于晶闸管的混合触发电路，所述电路包括硬件方式触发电路和软件方式触发电路；所述硬件方式触发电路和软件方式触发电路通过门极线和阴极线并联，用于触发晶闸管。
所述硬件触发方式电路包括分压电阻R2、分压电阻R3、储能电容C2、储能电容C3、转折二极管BOD(Break Over Diode)、放电电阻R4、限流电阻R5、限流电阻R6、防反二极管D3和保护二极管D4。
所述分压电阻R2和分压电阻R3串联后与外部电容C1并联，储能电容C2与分压电阻R3并联，转折二极管BOD与放电电阻R4串联后与储能电容C2并联；限流电阻R5与储能电容C3串联后与放电电阻R4并联，限流电阻R6与防反二极管D3、保护二极管D4串联后与储能电容C3并联，所述电阻R6连接防反二极管D3的阳极，防反二极管D3的阴极与保护二极管D4的阴极连接后，再接晶闸管的门极，保护二极管D4的阳极与晶闸管阴极相连。
所述储能电容C2通过分压电阻R2进行充电，充电时间常数为R2×C2，储能电容C2充电稳定后的电压与分压电阻R3上的电压相同。
硬件方式触发电路工作原理如下：
硬件触发电路目的是保护外部电容C1过电压，即当外部电容C1过电压时，会发出晶闸管触发脉冲。当外部电容C1电压上升到某一值时，储能电容C2通过分压电阻R2进行充电，储能电容C2两端电压为C1×R3/(R2+R3)，即储能电容C2电压也会上升到一定值，当该值超过转折二极管BOD的转折电压时，使得转折二极管BOD动作，转折二极管BOD两端电压降低到4到8V，储能电容C2上电能量C2×(C1×R3/(R2+R3))2/2将通过限流电阻R5给储能电容C3充电，当储能电容C3上电压达到10V左右时，将通过限流电阻R6和防反二 极管D3发出晶闸管触发信号，即完成了一次触发。如果此时外部电容C1上的电压仍然超过某一值，又会重复上述过程，再次完成一次触发。即实现了连续触发功能，连续触发周期与充电时间常数R2×C2和储能电容C1上的电压值有关，储能电容C1上的电压越高，连续触发周期越短。
硬件方式触发电路设计特殊应用：因为该电路在较为恶劣的电磁环境中使用，希望储能电容C3在转折二极管BOD不动作期间，其两端电压保持为0V，如果储能电容C3上的电压达到一定水平，将会误触发晶闸管SCR。为了避免在恶劣电磁环境中和转折二极管BOD的漏电流对储能电容C3充电，加入放电电阻R4，可使得储能电容C3上的电荷通过限流电阻R5和放电电阻R4放掉。
所述软件触发方式电路包括第一与非门Y1、第二与非门Y2、上拉电阻R1、三极管Q1、脉冲变压器T1、防反二极管D1和保护二极管D2。
触发信号TRI和高电平信号输入给第一与非门Y1的两个输入端，第一与非门Y1的输出端连接第二与非门Y2的输入端，触发使能信号TRI_EN输入第二与非门Y2的另一输入端，第二与非门Y2的输出端连接三极管Q1的基极，三极管Q1的发射极连接电源VCC，三极管Q1的集电极连接脉冲变压器T1原边的一端，上拉电阻R1一端连接电源VCC，其另一端连接三极管Q1的基极，脉冲变压器T1原边另一端接地；所述保护二极管D2与脉冲变压器T1副边并联，防反二极管D1的阳极与保护二极管D2的阴极相连，防反二极管D1的阴极连接晶闸管的门极，晶闸管的阴极与防反二极管D2的阳极相连。三极管Q1为PNP三极管。
软件方式触发电路工作原理如下：
触发信号TRI和触发使能信号TRI_EN为外部芯片发出的逻辑电平信号，触发信号TRI和触发使能信号TRI_EN是一对完全相反的逻辑电平信号，触发信号TRI正常为高电平“1”，触发使能信号TRI_EN正常为低电平“0”，当需要发出触发晶闸管命令时，触发信号TRI变为低电平“0”一段时间，触发使能信号TRI_EN变为高电平“1”一段时间，该段时间完全相同，由软件设置长短。触发信号TRI和触发使能信号TRI_EN经过第一与非门Y1和第二与非门Y2逻辑处理后，在第二与非门Y2的输出端产生一个与触发信号TRI相同的逻辑电平，即有一段时间为电平信号，该低电平信号使得三极管Q1导通，即脉冲变压器T1 原边得电一段时间，在副边得到与触发使能信号TRI_EN相同的逻辑电平信号，该信号触发晶闸管SCR导通。
软件方式触发电路设计特殊应用：软件可设置触发脉冲信号的宽度，即设置触发信号TRI和触发使能信号TRI_EN的宽度，还可连续发出触发晶闸管命令，连续周期取决于脉冲变压器T1的恢复时间，因为脉冲变压器通过磁芯传导能量，磁芯需要一个恢复时间。
防反二极管D1防止硬件方式触发电路的能量传递到软件触发方式电路中；防反二极管D3防止软件方式触发电路的能量传递到硬件触发方式电路中。
1)软件方式触发电路可通过软件逻辑判断后触发晶闸管；
当过压或者其他故障情况时，通过软件的逻辑判断后触发晶闸管。
2)软件方式触发电路触发晶闸管脉冲宽度可通过软件设置；
触发晶闸管的脉冲宽度可通过软件设置，根据晶闸管的参数来确定。
3)软件方式触发电路可连续触发晶闸管；
为了可靠触发导通晶闸管，软件可对晶闸管下发连续的触发命令，时间间隔要尽量短，取决与隔离脉冲变压器恢复时间。连续触发总时长不易过长，避免损坏晶闸管门极。连续触发的时间间隔和总时长通过软件设置。
4)软件方式触发电路通过隔离脉冲变压器与硬件方式触发电路隔离；
为了避免电位不同带来的问题，软件方式触发电路通过隔离脉冲变压器来实现，隔离电压等级依据变压器的设计水平。
5)硬件方式触发电路通过BOD(Break Over Diode)来实现硬件过压保护；
硬件方式触发电路只能对过压进行保护，可作为软件方式触发电路的过压后备保护。通过BOD来实现硬件过压保护。
6)硬件方式触发电路可长期承受过压值；
硬件方式触发电路与常规的BOD保护电路不同，可长期承受过电压值，最高可承受过压值的1.5倍。
7)硬件方式触发电路可连续触发晶闸管；
硬件方式触发电路也可连续触发晶闸管，连续触发时间间隔可通过电阻值和电容值来确定，连续触发总时长与过压时长相同。
最后应当说明的是：以上实施例仅用以说明本发明的技术方案而非对其限 制，所属领域的普通技术人员参照上述实施例依然可以对本发明的具体实施方式进行修改或者等同替换，这些未脱离本发明精神和范围的任何修改或者等同替换，均在申请待批的本发明的权利要求保护范围之内。

Claims (8)

  1. 一种适用于晶闸管的混合触发电路，其特征在于：所述电路包括硬件方式触发电路和软件方式触发电路；所述硬件方式触发电路和软件方式触发电路通过门极线和阴极线并联，用于触发晶闸管。
  2. 根据权利要求1所述的适用于晶闸管的混合触发电路，其特征在于：所述硬件触发方式电路包括分压电阻R2、分压电阻R3、储能电容C2、储能电容C3、转折二极管BOD、放电电阻R4、限流电阻R5、限流电阻R6、防反二极管D3和保护二极管D4。
  3. 根据权利要求2所述的适用于晶闸管的混合触发电路，其特征在于：所述分压电阻R2和分压电阻R3串联后与外部电容C1并联，储能电容C2与分压电阻R3并联，转折二极管BOD与放电电阻R4串联后与储能电容C2并联；限流电阻R5与储能电容C3串联后与放电电阻R4并联，限流电阻R6与防反二极管D3、保护二极管D4串联后与储能电容C3并联，所述限流电阻R6连接防反二极管D3的阳极，防反二极管D3的阴极与保护二极管D4的阴极连接后，再接晶闸管的门极，保护二极管D4的阳极与晶闸管阴极相连。
  4. 根据权利要求2或3所述的适用于晶闸管的混合触发电路，其特征在于：所述储能电容C2通过分压电阻R2进行充电，充电时间常数为R2×C2，储能电容C2充电稳定后的电压与分压电阻R3上的电压相同。
  5. 根据权利要求1所述的适用于晶闸管的混合触发电路，其特征在于：所述软件触发方式电路包括第一与非门Y1、第二与非门Y2、上拉电阻R1、三极管Q1、脉冲变压器T1、防反二极管D1和保护二极管D2。
  6. 根据权利要求5所述的适用于晶闸管的混合触发电路，其特征在于：触发信号TRI和高电平信号输入给第一与非门Y1的两个输入端，第一与非门Y1的输出端连接第二与非门Y2的输入端，触发使能信号TRI_EN输入第二与非门Y2的另一输入端，第二与非门Y2的输出端连接三极管Q1的基极，三极管Q1的发射极连接电源VCC，三极管Q1的集电极连接脉冲变压器T1原边的一端，上拉电阻R1一端连接电源VCC，其另一端连接三极管Q1的基极，脉冲变压器T1原边另一端接地；所述保护二极管D2与脉冲变压器T1副边并联，防反二极管D1的阳极与保护二极管D2的阴极相连，防反二极管D1的阴极连接晶闸管的门极， 晶闸管的阴极与防反二极管D2的阳极相连。
  7. 根据权利要求5或6所述的适用于晶闸管的混合触发电路，其特征在于：三极管Q1为PNP三极管。
  8. 根据权利要求2或5所述的适用于晶闸管的混合触发电路，其特征在于：防反二极管D1防止硬件方式触发电路的能量传递到软件触发方式电路中；防反二极管D3防止软件方式触发电路的能量传递到硬件触发方式电路中。
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