WO2016119661A1 - 功率因数校正电路及乘法器 - Google Patents

功率因数校正电路及乘法器 Download PDF

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Publication number
WO2016119661A1
WO2016119661A1 PCT/CN2016/072010 CN2016072010W WO2016119661A1 WO 2016119661 A1 WO2016119661 A1 WO 2016119661A1 CN 2016072010 W CN2016072010 W CN 2016072010W WO 2016119661 A1 WO2016119661 A1 WO 2016119661A1
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Prior art keywords
voltage
bjt
current
transistors
mosfet
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PCT/CN2016/072010
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English (en)
French (fr)
Inventor
尹小平
游剑
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意瑞半导体（上海）有限公司
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Priority to US15/546,647 priority Critical patent/US10171035B2/en
Publication of WO2016119661A1 publication Critical patent/WO2016119661A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1433—Balanced arrangements with transistors using bipolar transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to the field of power management technologies, and in particular, to a multiplier and a power factor correction circuit to which the multiplier is applied.
  • FIG. 1 An implementation of a PFC circuit is shown in Figure 1, which is applied to a boost converter.
  • the converter comprises an inductor L, a switching device S, a freewheeling diode D, an output capacitor Cout and an integrated PFC circuit.
  • the power supply voltage Vac passes through the diode rectifier bridge and is used as an input of the boost converter.
  • the boost converter converts the input voltage to obtain an output voltage Vout.
  • the PFC circuit includes an error amplifier U1, a multiplier U2, a comparator U3, an RS flip-flop U4, a drive module U5, and a Zero Current Detection (ZCD) U6.
  • the PFC circuit samples the output voltage Vout and inputs it to the error amplifier U1.
  • One input of the multiplier U2 is the output error feedback signal Verror of the error amplifier U1, and the other input is the divided voltage signal Vin of the power supply voltage Vac, so that the output current waveform can be made. Become a sine wave following the power supply voltage waveform.
  • the sampling resistor R1 is connected in series with the external switching device S to obtain a switching current signal.
  • the comparator U3 and the RS flip-flop U4 are turned over, and the external switching device S is turned off by the driving module U5.
  • the zero current detecting circuit U6 detects that the inductor current drops to zero, the external switching device S is turned on.
  • the present disclosure provides a multiplier and a power factor correction circuit to which the multiplier is applied.
  • a multiplier comprising:
  • a Gilbert multiplier circuit comprising first and second differential input stages and an output stage; said output stage outputting an output current obtained by an input operation of said first and second differential input stages;
  • a first differential voltage conversion circuit for generating a first differential voltage bias based on the received voltage signal and a first reference voltage to bias the first differential input stage
  • a second differential voltage conversion circuit for generating a second differential voltage bias based on the received voltage signal and a second reference voltage to bias the second differential input stage
  • a bias current generating circuit for generating a bias current biasing the first signal conversion circuit and the second signal conversion circuit
  • the output stage comprises:
  • a current mirror unit comprising two current input terminals and a current output terminal
  • a feedback control unit is configured to ensure that when the voltage signal difference received by the multiplier is zero, the current output terminal has no current output.
  • the current mirror unit is composed of a P-type MOSFET transistor.
  • the second differential voltage conversion circuit includes:
  • MOSFET transistor having a gate connected to a drain and a source connected to the power supply voltage
  • a first BJT transistor pair comprising two NPN-type first BJT transistors; a base and a collector of the two first BJT transistors are connected to a drain of the MOSFET transistor, and an emitter outputs the second differential voltage;
  • a second BJT transistor pair includes two NPN-type second BJT transistors; the bases of the two second BJT transistors respectively receive different voltage signals, and the collectors are respectively connected to the first BJT transistor Emitter
  • a first MOSFET transistor pair includes two first MOSFET transistors; the gates of the two first MOSFET transistors receive the bias current, the source is grounded, and the drains are respectively connected to a second BJT transistor Emitter.
  • a base of the second BJT transistor receives the input voltage or an error feedback voltage, and a base of another BJT transistor receives the second reference voltage.
  • the first differential voltage conversion circuit includes:
  • a second MOSFET transistor pair comprising two second MOSFET transistors; the gates of the two first MOSFET transistors are connected to the drain, and the source is connected to the power supply voltage;
  • a third BJT transistor pair includes two third BJT transistors; the bases of the two third BJT transistors respectively receive different voltage signals, and the collectors respectively connect the drains of the second MOSFET transistors pole;
  • a third MOSFET transistor pair includes two third MOSFET transistors; the gates of the two third MOSFET transistors receive the bias current, the source is grounded, and the drains are respectively connected to a third BJT transistor Emitter
  • a fourth MOSFET transistor pair comprising two fourth MOSFET transistors; two of said fourth a gate of the MOSFET transistor is respectively connected to a gate of the second MOSFET transistor, and a source is connected to the power supply voltage;
  • a fourth BJT transistor pair includes two NPN-type fourth BJT transistors; bases of the two fourth BJT transistors are respectively connected to the drains of one of the fourth MOSFET transistors, and the collector outputs the first difference Voltage;
  • a BJT transistor having a base coupled to the collector and coupled to the emitter of the fourth BJT transistor, the emitter of which is coupled to ground.
  • a base of the third BJT transistor receives the input voltage or an error feedback voltage, and a base of another BJT transistor receives the first reference voltage.
  • the output stage includes a current mirror unit, the current mirror unit includes two current inputs and a current output; the output stage further includes:
  • a first switching element having a first end connected to the current output end of the current mirror unit, a second end connected to an input end of the first operational amplifier, and a control end connected to the first operational amplifier output end;
  • a second switching element has a first end connected to the current output end of the current mirror unit, a second end for outputting the output current, and a control end connected to the first operational amplifier output end.
  • a multiplier comprising:
  • a Gilbert multiplier circuit comprising first and second differential input stages and an output stage; said output stage outputting an output current obtained by an input operation of said first and second differential input stages;
  • a first differential voltage conversion circuit for generating a first differential voltage bias based on the received voltage signal and a first reference voltage to bias the first differential input stage
  • a second differential voltage conversion circuit for generating a second differential voltage bias based on the received voltage signal and a second reference voltage to bias the second differential input stage
  • a bias current generating circuit for generating a bias current biasing the first signal conversion circuit and the second signal conversion circuit
  • the output stage includes a current mirror unit, the current mirror unit includes two current input terminals and a current output terminal; the output stage further includes:
  • a first switching element having a first end connected to the current output end of the current mirror unit, a second end connected to an input end of the first operational amplifier, and a control end connected to the first operational amplifier output end;
  • a second switching element has a first end connected to the current output end of the current mirror unit, a second end for outputting the output current, and a control end connected to the first operational amplifier output end.
  • the second differential voltage conversion circuit includes:
  • MOSFET transistor having a gate connected to a drain and a source connected to the power supply voltage
  • a first BJT transistor pair comprising two NPN-type first BJT transistors; two of said first BJT crystals a base and a collector of the tube are connected to a drain of the MOSFET transistor, and an emitter outputs the second differential voltage;
  • a second BJT transistor pair includes two NPN-type second BJT transistors; the bases of the two second BJT transistors respectively receive different voltage signals, and the collectors are respectively connected to the first BJT transistor Emitter
  • a first MOSFET transistor pair includes two first MOSFET transistors; the gates of the two first MOSFET transistors receive the bias current, the source is grounded, and the drains are respectively connected to a second BJT transistor Emitter.
  • a base of the second BJT transistor receives the input voltage or an error feedback voltage, and a base of another BJT transistor receives the second reference voltage.
  • the first differential voltage conversion circuit includes:
  • a second MOSFET transistor pair comprising two second MOSFET transistors; two second MOSFET transistors having a gate connected to the drain and a source connected to the supply voltage;
  • a third BJT transistor pair includes two third BJT transistors; the bases of the two third BJT transistors respectively receive different voltage signals, and the collectors respectively connect the drains of the second MOSFET transistors pole;
  • a third MOSFET transistor pair includes two third MOSFET transistors; the gates of the two third MOSFET transistors receive the bias current, the source is grounded, and the drains are respectively connected to a third BJT transistor Emitter
  • a fourth MOSFET transistor pair includes two fourth MOSFET transistors; the gates of the two fourth MOSFET transistors are respectively connected to the gate of one of the second MOSFET transistors, and the source is connected to the power supply voltage;
  • a fourth BJT transistor pair includes two NPN-type fourth BJT transistors; bases of the two fourth BJT transistors are respectively connected to the drains of one of the fourth MOSFET transistors, and the collector outputs the first difference Voltage;
  • a BJT transistor having a base coupled to the collector and coupled to the emitter of the fourth BJT transistor, the emitter of which is coupled to ground.
  • a base of the third BJT transistor receives the input voltage or an error feedback voltage, and a base of another BJT transistor receives the first reference voltage.
  • the multiplier further includes:
  • the bias current generation circuit generates the bias current based on a voltage supplied by the voltage feedforward circuit.
  • a power factor correction circuit comprising any one of the above multipliers.
  • the power factor correction circuit is formed in an integrated circuit module.
  • the output current accuracy of the multiplier is improved, and when the input voltage error is 0, there is no current output, that is, more precise. Control the offset voltage of the multiplier.
  • FIG. 1 is a schematic structural view of a boost converter using a PFC circuit in the prior art.
  • FIG. 2 is a schematic structural diagram of a Gilbert multiplier circuit in an exemplary embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the structure of another Gilbert multiplier circuit in an exemplary embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a differential current conversion circuit in an exemplary embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a hyperbolic tangent circuit in an exemplary embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a first differential voltage conversion circuit in an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a second differential voltage conversion circuit in an exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a voltage feedforward circuit in an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another voltage feedforward circuit in an exemplary embodiment of the present disclosure.
  • FIG. 10 is a timing diagram of control signals of a voltage feedforward circuit in an exemplary embodiment of the present disclosure.
  • FIG. 11 is a schematic structural view of a voltage feedforward circuit in the prior art.
  • FIG. 12 is a schematic overall structural view of a multiplier in an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be embodied in a variety of forms and should not be construed as being limited to the embodiments set forth herein. To those skilled in the art. Furthermore, the described technical features or circuit structures may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are set forth However, those skilled in the art will appreciate that the technical solution of the present disclosure may be practiced without one or more of the specific details.
  • a multiplier is first provided in this example embodiment.
  • the multiplier can include a Gilbert multiplier circuit and a bias current generating circuit; since the Gilbert multiplier circuit implements the product of the respective hyperbolic tangent functions of the two voltages, in order to achieve two voltages
  • the direct product between the two needs to first convert the input voltage through the voltage to the differential current, and the converted differential current is then passed through a pair of BJT (bipolar transistor) transistors to generate a differential voltage, thereby obtaining an inverse hyperbolic tangent function.
  • the multiplier in the exemplary embodiment further includes a first differential voltage conversion circuit and a second differential voltage conversion circuit.
  • the multiplier circuit can also be other types of circuits, and the first differential voltage conversion circuit and the second differential voltage conversion circuit can also select settings according to requirements, etc.
  • the exemplary embodiments are not limited thereto.
  • FIG. 2 it is a schematic structural diagram of a Gilbert multiplier circuit.
  • the Gilbert multiplier circuit is the core unit of the multiplier, comprising a second differential input stage consisting of BJT transistors Q1-Q2, a second differential input stage consisting of BJT transistors Q3-Q6, and an output stage Where current source I EE provides a bias current I EE to the Gilbert multiplier circuit.
  • the output stage of the Gilbert multiplier outputs an output current Iout obtained by an input operation of the first differential input stage and the second differential input stage.
  • the Gilbert multiplier circuit uses a bipolar transistor because the exponential nature of the bipolar device makes it more linear than the multiplier using the field effect device.
  • the output stage of the Gilbert multiplier circuit includes a current mirror unit, and the output current Iout of the Gilbert multiplier circuit requires the current mirror unit output.
  • the current mirror unit can only use PMOS devices (ie, P-type MOSFET transistors M2, M3 shown in Figure 3).
  • PMOS devices ie, P-type MOSFET transistors M2, M3 shown in Figure 3.
  • a current mirror consisting of a PMOS device is directly output, since the output resistance is small, when the voltage difference received by the multiplier is 0, there may be a small current output.
  • a folded structure can be considered, but may conflict with a limited voltage space.
  • a feedback control unit is provided for ensuring that the current output terminal has no current output when the voltage signal difference received by the multiplier is zero.
  • the feedback control unit may include a first operational amplifier U1, and the feedback is ensured by the first operational amplifier U1 to ensure that the output current Iout has a high precision.
  • the specific circuit is shown in Figure 3.
  • the current mirror unit includes two current input terminals and a current output terminal.
  • the output stage further includes a first operational amplifier U1, a first switching element S1 and a second switching element S2. The two input ends of the first operational amplifier U1 are respectively connected to the current input end of the current mirror unit.
  • a first end of the first switching element S1 is connected to a current output end of the current mirror unit, and a second end of the first switching element S1 is connected to an input end of the first operational amplifier U1, the first end The control terminal of the switching element S1 is connected to the output terminal of the first operational amplifier U1.
  • a first end of the second switching element S2 is connected to a current output end of the current mirror unit, and a second end of the second switching element S2 is for outputting the output current Iout, the second switching element S2
  • the control terminal is connected to the output end of the first operational amplifier U1.
  • the first differential voltage conversion circuit is configured to generate a first differential voltage bias based on the received voltage signal and a first reference voltage Vref1 to bias the first differential input stage, in the example embodiment
  • the voltage signal received by the voltage conversion circuit is an error feedback voltage Verror.
  • the first differential voltage conversion circuit may receive other voltage signals.
  • the error feedback voltage Verror first needs to be converted by a voltage to a differential current.
  • a differential current conversion circuit is shown in FIG. 4, and in order to realize voltage to differential current conversion, PNP is used in FIG.
  • the type BJT transistor causes a voltage difference between the input voltage and the first reference voltage Vref1 to generate a differential current on the first resistor R2.
  • the generated differential current is then subjected to a differential voltage through a pair of BJT transistors as shown in FIG. 5 to obtain an inverse hyperbolic tangent function.
  • the second differential voltage conversion circuit is configured to generate a second differential voltage bias based on the received voltage signal and a second reference voltage Vref2 to bias the second differential input stage, in the example embodiment
  • the voltage signal received by the voltage conversion circuit is an example of the input voltage Vin.
  • the second differential voltage conversion circuit may receive other voltage signals.
  • the input voltage Vin first undergoes a conversion from a voltage to a differential current, and then performs an inverse hyperbolic tangent conversion. Differential current conversion circuit and The inverse hyperbolic tangent circuit is similar to that in FIGS. 4 and 5 and will not be described again here.
  • a voltage follower can be used to obtain a minimum input voltage Vin close to 0V.
  • the differential current conversion circuit in Figure 4 Due to process limitations, PNP devices with excellent performance may not be provided, and the differential current conversion circuit in Figure 4 only implements a similar level shifting function, so theoretically, NPN type BJT transistors can also be used instead. Therefore, the first differential voltage conversion circuit and the second differential voltage conversion circuit are also improved based on this in the present exemplary embodiment, so that it can be implemented by using an NPN type BJT transistor, thereby greatly expanding the range of use of the circuit. Moreover, the process requirements can be reduced without the use of PNP devices. In addition, the NPN type device has a higher gain (Beta), so the error can also be reduced to some extent.
  • Beta gain
  • the second differential voltage conversion circuit may include a MOSFET transistor M1, a first BJT transistor pair, a second BJT transistor pair, a first resistor R1, and a first MOSFET transistor pair.
  • the gate of the MOSFET transistor M1 is connected to the drain, and the source of the MOSFET transistor is connected to the power supply voltage Vcc.
  • the first BJT transistor pair includes two NPN-type first BJT transistors Q11, Q12; the base and collector of two of the first BJT transistors are connected to the drain of the MOSFET transistor, and the two first BJTs The emitter of the transistor outputs the second differential voltage.
  • the second BJT transistor pair includes two NPN-type second BJT transistors Q21, Q22; the bases of the two second BJT transistors respectively receive different voltage signals, and the two second BJT transistors The collectors are respectively connected to the emitters of the first BJT transistor.
  • the first resistor R1 is coupled between the emitters of the two second BJT transistors.
  • the first MOSFET transistor pair includes two first MOSFET transistors M11, M12; the gates of the two first MOSFET transistors receive the bias current, the sources of the two first MOSFET transistors are grounded, two The drains of the first MOSFET transistors are respectively connected to the emitters of one of the second BJT transistors.
  • the first differential voltage conversion circuit includes a second MOSFET transistor pair, a third BJT transistor pair, a second resistor R2, a third MOSFET transistor pair, and a fourth MOSFET transistor pair.
  • the second MOSFET transistor pair includes two second MOSFET transistors M21, M22; the gates and drains of the two second MOSFET transistors are connected, and the two second MOSFET transistor sources are connected to the power supply voltage Vcc .
  • the third BJT transistor pair includes two third BJT transistors Q31, Q32; the bases of the two third BJT transistors respectively receive different voltage signals, and the collectors of the two third BJT transistors Correspondingly, the drains of one of the BJT transistors are respectively connected.
  • the second resistor R2 is coupled between the emitters of the two third BJT transistors.
  • the third MOSFET transistor pair includes two third MOSFET transistors M31, M32; the gates of the two third MOSFET transistors receive the bias current, the sources of the two third MOSFET transistors are grounded, two The drains of the third MOSFET transistors are respectively connected to the emitters of one of the third BJT transistors.
  • the fourth MOSFET transistor pair includes two fourth MOSFET transistors M41, M42; the gates of the two fourth MOSFET transistors are respectively connected to the gate of one of the second MOSFET transistors, and the two fourth MOSFET transistor sources The pole is connected to the power supply voltage Vcc.
  • the fourth BJT transistor pair includes two NPN-type fourth BJT transistors Q41 and Q42; the bases of the two fourth BJT transistors are respectively connected to the fourth MOSFET. The drain of the transistor, the collectors of the two of the fourth BJT transistors output the first differential voltage.
  • the base of the BJT transistor Q50 is connected to the collector and is connected to the emitter of the fourth BJT transistor. The emitter of the BJT transistor Q50 is grounded, and the BJT transistor Q50 can raise the DC operating level.
  • the bias current generating circuit is configured to generate a bias current biasing the first signal conversion circuit and the second signal conversion circuit based on an external input voltage, for example, a voltage Vff provided by a voltage feedforward circuit, thereby performing 1 /V 2 conversion.
  • the voltage feedforward circuit is configured to hold and output a peak voltage of an input voltage to the voltage feedforward circuit.
  • the input voltage is derived from a voltage proportional to an alternating current supply voltage.
  • the voltage feedforward circuit in the exemplary embodiment mainly includes a logic control unit U2, a third switching element S3, a fourth switching element S4, a fifth switching element S3, and a first capacitor. C1 and a second capacitor C2, etc.; in the present exemplary embodiment, the switching element may include one or more of a MOSFET switch, an IGBT switch, or a BJT switch. among them:
  • the first end of the third switching element S3 is connected to a power supply voltage Vcc, the power supply voltage Vcc is at least higher than the peak voltage of the input voltage Vin, and the control end of the third switching element S3 is responsive to a first control signal.
  • the third switching element S3 is turned on by ⁇ 1.
  • the logic control unit U2 is configured to output a second control signal ⁇ 2 during the peak voltage of the input voltage Vin and a third control signal ⁇ 3 during the non-peak voltage of the input voltage Vin, as described in FIG.
  • the second control signal ⁇ 2, the third control signal ⁇ 3, and the fourth control signal ⁇ 4 described below have a non-overlapping time, thereby Avoid interference and generate noise.
  • the first end of the first capacitor C1 is grounded.
  • the first end of the fourth switching element S4 is connected to the second end of the third switching element S3, and the second end of the fourth switching element S4 is connected to the second end of the first capacitor C1, the fourth switch
  • the control terminal of the element S4 turns on the fourth switching element S4 in response to the second control signal ⁇ 2.
  • the first end of the fifth switching element S3 is connected to the second end of the first capacitor C1, and the control end of the fifth switching element S3 turns on the fifth switching element S3 in response to the third control signal ⁇ 3 .
  • the first end of the second capacitor C2 is grounded, and the second end of the second capacitor C2 is connected to the second end of the fifth switching element S3.
  • the first control signal ⁇ 1 and the second control signal ⁇ 2 are simultaneously supplied, and the first control signal is stopped when the voltage of the second end of the first capacitor C1 is greater than the peak voltage of the input voltage Vin.
  • a first control signal ⁇ 1 and a second control signal ⁇ 2 are provided to turn on the third switching element S3 and the fourth switching element S4, so the power source
  • the voltage Vcc charges the first capacitor C1 via the third switching element S3 and the fourth switching element S4; when the first capacitor C1 is charged to the peak voltage of the input voltage Vin, stopping providing the first
  • the control signal ⁇ 1 stops charging the first capacitor C1.
  • Vff (V C1 ⁇ C1+V C2 ⁇ C2)/(C1+C2) (1)
  • V C1 is the voltage of the second end of the first capacitor C1 before the charge redistribution
  • V C2 is the voltage of the second end of the second capacitor C2 before the charge redistribution
  • the ratio of the capacitance between the first capacitor C1 and the second capacitor C2 in the exemplary embodiment is adjustable, and can be adjusted by controlling the ratio of the capacitance between the first capacitor C1 and the second capacitor C2. a rate of change of the voltage output by the second terminal of the second capacitor C2.
  • the logic control unit U2 is further configured to output a fourth control signal ⁇ 4 during the non-peak voltage of the input voltage Vin.
  • the voltage feedforward circuit in the present exemplary embodiment may further include a fourth switching element S4.
  • the first end of the fourth switching element S4 is connected to the second end of the first capacitor C1, the second end of the fourth switching element S4 is grounded, and the control end of the fourth switching element S4 is responsive to the fourth The fourth switching element S4 is turned on by the control signal ⁇ 4.
  • the fourth control signal ⁇ 4 turns on the fourth switching element S4, and further discharges the first capacitor C1 to prevent a sudden drop in the effective value of the input voltage Vin.
  • the voltage at the second terminal of the first capacitor C1 is still maintained at the peak voltage of the input voltage Vin before the change.
  • the voltage feedforward circuit in the present exemplary embodiment may further include a first comparator U2.
  • the first input end of the first comparator U2 is connected to a reference voltage Vref
  • the second input end of the first comparator U2 is connected to the input voltage Vin
  • the output end of the first comparator U2 outputs the A comparison result signal of the input voltage Vin and the reference voltage Vref is sent to the logic control unit U2, and the logic control unit U2 determines whether it is during the peak voltage period of the input voltage Vin.
  • the logic control unit U2 can determine that the input voltage Vin is During the peak voltage period; if the input voltage Vin is smaller than the reference voltage Vref, the output end of the first comparator U2 outputs a high level signal, and the logic control unit U2 determines that the input voltage Vin is During the non-peak voltage period.
  • the voltage feedforward circuit in the present exemplary embodiment may further include a second comparator U3 (or a second operational amplifier). a first input of the second comparator U3 (or the second operational amplifier) is connected to the input voltage Vin, and a second input of the second comparator U3 (or the second operational amplifier) is connected The first end of the third switching element S3 forms a feedback circuit.
  • the output end of the second comparator U3 (or the second operational amplifier) is based on the input voltage Vin and the voltage of the second end of the first capacitor C1.
  • the comparison result outputs a comparison result signal to the control terminal of the third switching element S3.
  • the second comparator U3 (or the second operational amplifier) outputs a high level signal, that is, the first control signal ⁇ 1, thereby turning on the first switch
  • the power supply voltage Vcc charges the first capacitor C1 through the first switching transistor and the second switching transistor.
  • the voltage of the second terminal of the first capacitor C1 increases with the rise of the input voltage Vin, but the voltage of the second terminal of the first capacitor C1 is still less than the peak voltage of the input voltage Vin, that is, the first capacitor C1
  • the second comparator U3 (or the second operational amplifier) still outputs a high level signal (ie, the first control signal ⁇ 1), thereby keeping the first switching device turned on.
  • the second comparator U3 (or the second operational amplifier) outputs a low level signal, the low level signal turning off the first switching device, Thereby stopping charging of the first capacitor C1.
  • the third switching element S3 is in the off state, the loop between the second comparator U3 (or the second operational amplifier) and the third switching element S3 is kept on, avoiding the occurrence of the third switching element S3 being turned on again.
  • the voltage feedforward circuit may further include a third resistor R3 coupled to the second end of the third switching element S3 and the second capacitor C1. Between the ends, thus acting as a current limiting.
  • the voltage feedforward circuit in the exemplary embodiment is formed on an integrated circuit module, and the first capacitor C1 and the second capacitor C2 can be implemented by using an on-chip capacitor. Because the on-chip capacitance is much smaller than the external capacitor, and the period of the AC signal is long (50Hz corresponds to 20ms), if the on-chip capacitor is used instead of the external capacitor, the problem of the voltage holding time on the on-chip capacitor needs to be solved, that is, the leakage current needs to be considered. The impact of this is especially severe at high temperatures. In the present exemplary embodiment, since the main leakage current is a reverse bias PN junction leakage current connected to the first capacitor C1 and the second capacitor C2. Therefore, referring to FIG.
  • the voltage feedforward circuit in the present exemplary embodiment further introduces a first reverse bias PN junction D1 and a second reverse bias PN junction D2 to balance the total leakage current.
  • the first reverse bias PN junction D1 is coupled between the power supply voltage Vcc and the second terminal of the first capacitor C1; the second reverse bias PN junction D2 is coupled to the power supply voltage Vcc and the The second capacitor C2 is between the second ends.
  • the first reverse biased PN junction D1 and the second reverse biased PN junction D2 are both non-conducting and in a reverse biased state, and the leakage current passes through the first reverse biased PN junction D1 and the The second reverse bias PN junction D2 flows from the power supply voltage Vcc into the first capacitor C1 and the second capacitor C2.
  • the leakage current can compensate for leakage current flowing from the first capacitor C1 and the second capacitor C2.
  • two on-chip capacitors are used to realize the hold and output of the peak voltage of the input voltage Vin without using an external resistor, so the ripple of the capacitor can be eliminated, and the selection of the capacitance and the resistance value can be avoided.
  • the total leakage current is balanced, and the sustain time of the voltage on the on-chip capacitor is increased.
  • the voltage of the on-chip capacitor output remains approximately constant during the sustain time, which is beneficial to stabilize the output of the multiplier, reduce THD (distortion), and improve the power factor correction effect.
  • the bias current generating circuit may be as shown in FIG. 11, and the multiplier overall circuit is as shown in FIG.
  • the bias current of the MOSFET transistor M0 is:
  • the current of the emitter of the first transistor Q11 is:
  • the current of the emitter of the first transistor Q12 is:
  • Iout I EE ⁇ tanh(V1/2Vt) ⁇ tanh(V2/2Vt) (8)
  • I EE is the tail current value
  • V1, V2 are two pairs of input voltages
  • Iout is the output current
  • Iout I EE ⁇ (Vin1-Vref1) ⁇ (Vin2-Vref2)/Vff 2 (9)
  • Equation (9) shows that the circuit contains 1/Vff 2 terms, which realizes the function of voltage feedforward.
  • a power factor correction circuit is also provided in the present exemplary embodiment.
  • the power factor correction circuit includes any one of the multipliers provided in the present exemplary embodiment.
  • the power factor correction circuit can be formed on an integrated circuit module, and the first capacitor C1 and the second capacitor C2 are on-chip capacitors.
  • the specific implementation manner and technical effects of the multiplier have been described in detail, and will not be explained in detail herein.
  • the feedback control unit is used to provide feedback control, which improves the output current accuracy of the multiplier, and ensures that when the input voltage error is 0, there is no current.
  • the output which is the more precise control of the offset voltage of the multiplier.
  • the process requirements can be reduced, and the circuit application range is expanded.
  • the retention of the peak voltage of the input voltage is achieved by setting the first capacitor and the second capacitor, so there is no need to consider the compromise between the external resistor and the external capacitor value in the prior art. select.
  • the output voltage can be slowly changed to facilitate filtering out transient fluctuations of the input voltage;
  • the variation slope of the output voltage can be changed.
  • the first capacitor and the second capacitor can be implemented with on-chip capacitors, thereby saving system cost.
  • the leakage current compensation mechanism by setting the leakage current compensation mechanism, the sustain time of the voltage on the internal capacitor is increased, so that the output voltage remains approximately constant within the maintenance time, which is advantageous for stabilizing the multiplier.

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Abstract

一种乘法器以及应用该乘法器的功率因数校正电路。该乘法器包括一吉尔伯特乘法器电路，包括第一、第二差分输入级以及一输出级；一第一差分电压转换电路；一第二差分电压转换电路；以及一偏置电流生成电路；其中，所述输出级包括：一电流镜单元，包括两电流输入端以及一电流输出端；一反馈控制单元，用于保证在所述乘法器接收到的电压信号差为零时，所述电流输出端没有电流输出，有利于提高乘法器线性度以及乘法器输出电流精度。

Description

功率因数校正电路及乘法器 技术领域
本公开涉及电源管理技术领域，具体涉及一种乘法器以及应用该乘法器的功率因数校正电路。
背景技术
为了更高效的利用电网电能，开关电源技术中已经开始广泛应用功率因数校正技术。现有技术中，通常做法是在电路的二极管整流桥与负载之间***一级功率因数校正(Power Factor Correction，PFC)电路，从而使得从交流电源抽取的电流也是正弦波信号，而且其相位跟随电源电压而变化。加入功率因数校正电路后，功率因数值可以接近于1。
一种PFC电路的实现方式如图1中所示，其应用于一升压变换器(Boost Converter)。该变换器包括电感L、开关器件S、续流二极管D、输出电容Cout以及集成的PFC电路组成。电源电压Vac经过二极管整流桥后作为升压变换的输入，升压变换器对输入的电压进行变换处理后得到输出电压Vout。PFC电路包括误差放大器(Error Amplifier)U1、乘法器U2、比较器U3、RS触发器U4、驱动模块U5以及零电流检测电路(Zero Current Detection，ZCD)U6。PFC电路采样输出电压Vout并输入至误差放大器U1，乘法器U2的一个输入为误差放大器U1的输出误差反馈信号Verror、另一个输入为电源电压Vac的分压信号Vin，这样则可以使得输出电流波形成为跟随电源电压波形的正弦波。采样电阻R1和外部开关器件S串联以获得开关电流信号。当采样电阻R1上的电压高于乘法器U2的输出时，比较器U3和RS触发器U4翻转，并通过驱动模块U5关断外部开关器件S。当零电流检测电路U6检测到电感电流降到0时，开启外部开关器件S。通过上述控制方式，实现了临界导通模式控制，而且实现方式简单，特别适用于中小功率的功率因数校正电路。
然而，现有技术中乘法器在输出电流精度等方案仍存在有待改进之处。
发明内容
针对现有技术中的部分或者全部问题，本公开提供一种乘法器以及应用该乘法器的功率因数校正电路。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
根据本公开的第一方面，提供一种乘法器，包括：
一吉尔伯特乘法器电路，包括第一、第二差分输入级以及一输出级；所述输出级输出由所述第一、第二差分输入级的输入运算得到的输出电流；
一第一差分电压转换电路，用于基于接收到的电压信号以及一第一参考电压生成一第一差分电压偏置所述第一差分输入级；
一第二差分电压转换电路，用于基于接收到的电压信号以及一第二参考电压生成一第二差分电压偏置所述第二差分输入级；
一偏置电流生成电路，用于生成一偏置电流偏置所述第一信号转换电路及第二信号转换电路；
其中，所述输出级包括：
一电流镜单元，包括两电流输入端以及一电流输出端；
一反馈控制单元，用于保证在所述乘法器接收到的电压信号差为零时，所述电流输出端没有电流输出。
在本公开一种示例实施方式中，所述电流镜单元由P型MOSFET晶体管组成。
在本公开一种示例实施方式中，所述第二差分电压转换电路包括：
一MOSFET晶体管，其栅极与漏极连接，源极连接所述电源电压；
一第一BJT晶体管对，包括两个NPN型第一BJT晶体管；两个所述第一BJT晶体管的基极及集电极连接所述MOSFET晶体管的漏极，发射极输出所述第二差分电压；
一第二BJT晶体管对，包括两个NPN型第二BJT晶体管；两个所述第二BJT晶体管的基极分别对应接收相异的两电压信号，集电极分别对应连接一所述第一BJT晶体管的发射极；
一第一电阻，耦接于两个所述第二BJT晶体管的发射极之间；
一第一MOSFET晶体管对，包括两个第一MOSFET晶体管；两个所述第一MOSFET晶体管的栅极接收所述偏置电流，源极接地，漏极分别对应连接一所述第二BJT晶体管的发射极。
在本公开一种示例实施方式中，一所述第二BJT晶体管的基极接收所述输入电压或一误差反馈电压，另一BJT晶体管的基极接收所述第二参考电压。
在本公开一种示例实施方式中，所述第一差分电压转换电路包括：
一第二MOSFET晶体管对，包括两个第二MOSFET晶体管；两个所述第一MOSFET晶体管的栅极与漏极连接，源极连接所述电源电压；
一第三BJT晶体管对，包括两个第三BJT晶体管；两个所述第三BJT晶体管的基极分别对应接收相异的两电压信号，集电极分别对应连接一所述第二MOSFET晶体管的漏极；
一第二电阻，耦接于两个所述第三BJT晶体管的发射极之间；
一第三MOSFET晶体管对，包括两个第三MOSFET晶体管；两个所述第三MOSFET晶体管的栅极接收所述偏置电流，源极接地，漏极分别对应连接一所述第三BJT晶体管的发射极；
一第四MOSFET晶体管对，包括两个第四MOSFET晶体管；两个所述第四 MOSFET晶体管的栅极分别对应连接一所述第二MOSFET晶体管的栅极，源极连接所述电源电压；
一第四BJT晶体管对，包括两个NPN型第四BJT晶体管；两个所述第四BJT晶体管的基极分别对应连接一所述第四MOSFET晶体管的漏极，集电极输出所述第一差分电压；
一BJT晶体管，其基极与集电极连接并连接至所述第四BJT晶体管的发射极，其发射极接地。
在本公开一种示例实施方式中，一所述第三BJT晶体管的基极接收所述输入电压或一误差反馈电压，另一BJT晶体管的基极接收所述第一参考电压。
在本公开一种示例实施方式中，所述输出级包括一电流镜单元，所述电流镜单元包括两电流输入端以及一电流输出端；所述输出级还包括：
一第一运算放大器，其两输入端分别对应连接所述电流镜单元的电流输入端；
一第一开关元件，其第一端连接所述电流镜单元的电流输出端，第二端连接所述第一运算放大器的一输入端，其控制端连接所述第一运算放大器输出端；
一第二开关元件，其第一端连接所述电流镜单元的电流输出端，第二端用于输出所述输出电流，其控制端连接所述第一运算放大器输出端。
根据本公开的第三方面，提供一种乘法器，包括：
一吉尔伯特乘法器电路，包括第一、第二差分输入级以及一输出级；所述输出级输出由所述第一、第二差分输入级的输入运算得到的输出电流；
一第一差分电压转换电路，用于基于接收到的电压信号以及一第一参考电压生成一第一差分电压偏置所述第一差分输入级；
一第二差分电压转换电路，用于基于接收到的电压信号以及一第二参考电压生成一第二差分电压偏置所述第二差分输入级；
一偏置电流生成电路，用于生成一偏置电流偏置所述第一信号转换电路及第二信号转换电路；
其中，所述输出级包括一电流镜单元，所述电流镜单元包括两电流输入端以及一电流输出端；所述输出级还包括：
一第一运算放大器，其两输入端分别对应连接所述电流镜单元的电流输入端；
一第一开关元件，其第一端连接所述电流镜单元的电流输出端，第二端连接所述第一运算放大器的一输入端，其控制端连接所述第一运算放大器输出端；
一第二开关元件，其第一端连接所述电流镜单元的电流输出端，第二端用于输出所述输出电流，其控制端连接所述第一运算放大器输出端。
在本公开一种示例实施方式中，所述第二差分电压转换电路包括：
一MOSFET晶体管，其栅极与漏极连接，源极连接所述电源电压；
一第一BJT晶体管对，包括两个NPN型第一BJT晶体管；两个所述第一BJT晶体 管的基极及集电极连接所述MOSFET晶体管的漏极，发射极输出所述第二差分电压；
一第二BJT晶体管对，包括两个NPN型第二BJT晶体管；两个所述第二BJT晶体管的基极分别对应接收相异的两电压信号，集电极分别对应连接一所述第一BJT晶体管的发射极；
一第一电阻，耦接于两个所述第二BJT晶体管的发射极之间；
一第一MOSFET晶体管对，包括两个第一MOSFET晶体管；两个所述第一MOSFET晶体管的栅极接收所述偏置电流，源极接地，漏极分别对应连接一所述第二BJT晶体管的发射极。
在本公开一种示例实施方式中，一所述第二BJT晶体管的基极接收所述输入电压或一误差反馈电压，另一BJT晶体管的基极接收所述第二参考电压。
在本公开一种示例实施方式中，所述第一差分电压转换电路包括：
一第二MOSFET晶体管对，包括两个第二MOSFET晶体管；两个所述第二MOSFET晶体管的栅极与漏极连接，源极连接所述电源电压；
一第三BJT晶体管对，包括两个第三BJT晶体管；两个所述第三BJT晶体管的基极分别对应接收相异的两电压信号，集电极分别对应连接一所述第二MOSFET晶体管的漏极；
一第二电阻，耦接于两个所述第三BJT晶体管的发射极之间；
一第三MOSFET晶体管对，包括两个第三MOSFET晶体管；两个所述第三MOSFET晶体管的栅极接收所述偏置电流，源极接地，漏极分别对应连接一所述第三BJT晶体管的发射极；
一第四MOSFET晶体管对，包括两个第四MOSFET晶体管；两个所述第四MOSFET晶体管的栅极分别对应连接一所述第二MOSFET晶体管的栅极，源极连接所述电源电压；
一第四BJT晶体管对，包括两个NPN型第四BJT晶体管；两个所述第四BJT晶体管的基极分别对应连接一所述第四MOSFET晶体管的漏极，集电极输出所述第一差分电压；
一BJT晶体管，其基极与集电极连接并连接至所述第四BJT晶体管的发射极，其发射极接地。
在本公开一种示例实施方式中，一所述第三BJT晶体管的基极接收所述输入电压或一误差反馈电压，另一BJT晶体管的基极接收所述第一参考电压。
在本公开一种示例实施方式中，所述乘法器还包括：
一电压前馈电路；所述偏置电流生成电路基于所述电压前馈电路提供的电压生成所述偏置电流。
根据本公开的第二方面，提供一种功率因数校正电路，包括上述任意一种乘法器。
在本公开一种示例实施方式中，所述功率因数校正电路形成于一集成电路模块。
本公开示例实施方式中的乘法器中，通过设置反馈控制单元，利用反馈控制单元提供反馈控制，提高了乘法器输出电流精度，保证了当输入电压误差为0时，没有电流输出，即更精准的控制乘法器的失调电压。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是现有技术中一种应用PFC电路的升压变换器结构示意图。
图2是本公开示例实施方式中一种吉尔伯特乘法器电路的结构示意图。
图3是本公开示例实施方式中另一种吉尔伯特乘法器电路的结构示意图。
图4是本公开示例实施方式中一种差分电流转换电路的结构示意图。
图5是本公开示例实施方式中一种双曲正切电路的结构示意图。
图6是本公开示例实施方式中第一差分电压转换电路的结构示意图。
图7是本公开示例实施方式中第二差分电压转换电路的结构示意图。
图8是本公开示例实施方式中一种电压前馈电路的结构示意图。
图9是本公开示例实施方式中另一种电压前馈电路的结构示意图。
图10是本公开示例实施方式中电压前馈电路的控制信号时序图。
图11是现有技术中一种电压前馈电路的结构示意图。
图12是本公开示例实施方式中一种乘法器的整体结构示意图。
附图标记说明：
背景技术
L               电感
S               开关器件
D               续流二极管
Cout            输出电容
R1              采样电阻
U1              误差放大器
U2              乘法器
U3              比较器
U4              RS触发器
U5              驱动模块
Vac             电源电压
Vin             输入电压
Vout            输出电压
具体实施方式
C1             第一电容
C2             第二电容
D1             第一反偏PN结
D2             第二反偏PN结
S1             第一开关元件
S2             第二开关元件
S3             第三开关元件
S4             第四开关元件
S5             第五开关元件
S6             第六开关元件
Φ1             第一控制信号
Φ2             第二控制信号
Φ3             第三控制信号
Φ4             第四控制信号
U1             第一运算放大器
U2             逻辑控制单元
U3             第一比较器
U4             第二比较器
R1             第一电阻
R2             第二电阻
R3             第三电阻
Q1-Q6         BJT晶体管
Q50            BJT晶体管
Q11、Q12       第一BJT晶体管
Q21、Q22       第二BJT晶体管
Q31、Q32       第三BJT晶体管
Q41、Q42       第四BJT晶体管
M0-M5         场效应晶体管
M11、M12       第一MOSFET晶体管
M21、M22      第二MOSFET晶体管
M31、M32       第三MOSFET晶体管
M41、M42       第四MOSFET晶体管
Vcc             电源电压
Vref             基准电压
Vin              输入电压
Verror           误差反馈电压
Vff              峰值电压
Vref1            第一参考电压
Vref2            第二参考电压
IBias           偏置电流
IEE             电流源
Iout             输出电流
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。此外，所描述的技术特征或电路结构可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而示出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多。
在说明书及权利要求中使用了某些词汇来指称特定的组件，本领域技术人员应可理解，可能会用不同的名词来称呼同一个组件。本说明书及权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在整篇说明书及权利要求当中所提及的“包括”为一开放式的用语，故应解释成“包括但不限定于”。此外，“连接”一词在此包括任何直接及间接的电气连接手段。
本示例实施方式中首先提供了一种乘法器。该乘法器可以包括一吉尔伯特(Gilbert)乘法器电路以及一偏置电流生成电路；由于吉尔伯特乘法器电路实现的是两个电压各自双曲正切函数的乘积，为了实现两个电压之间的直接乘积，需要先将输入电压经过电压到差分电流的转换，转换得到的差分电流再经过一对BJT(双极型晶体管)晶体管产生差分电压，从而得到反双曲正切函数。因此，本示例实施方式中所述乘法器还包括一第一差分电压转换电路以及一第二差分电压转换电路。当然，本领域技术人员容易理解的是，所述乘法器电路也可以为其他类型的电路，而所述第一差分电压转换电路以及第二差分电压转换电路也可以根据需要选择设置等等，本示例实施方式中并不以此为限。
如图2中所示，为一种吉尔伯特乘法器电路的结构示意图。该吉尔伯特乘法器电路为所述乘法器的核心单元，其包括由BJT晶体管Q1-Q2组成的第二差分输入级，由BJT晶体管Q3-Q6组成的第二差分输入级，以及一输出级，其中电流源IEE给吉尔伯特乘法器电路提供偏置电流IEE。所述吉尔伯特乘法器的所述输出级输出由所述第一差分输入 级以及第二差分输入级的输入运算得到的输出电流Iout。本示例实施方式中，所述吉尔伯特乘法器电路之所以采用双极型晶体管，是因为双极性器件的指数特性使得其线性度优于采用场效应器件的乘法器。
本示例实施方式中，所述吉尔伯特乘法器电路的输出级包括一电流镜单元，吉尔伯特乘法器电路的输出电流Iout需要该电流镜单元输出。由于工艺限制，电流镜单元只能采用PMOS器件(即图3中所示的P型MOSFET晶体管M2、M3)。在采用PMOS器件组成的电流镜直接输出时，由于其输出电阻较小，当所述乘法器接收到的电压差为0时，还可能会有小电流输出。在一种解决方案中，可以考虑使用折叠式结构，但可能与有限的电压空间冲突。本示例实施方式中，则设置了一反馈控制单元，用于保证在所述乘法器接收到的电压信号差为零时，所述电流输出端没有电流输出。例如，所述反馈控制单元可以包括一第一运算放大器U1，利用所述第一运算放大器U1形成反馈保证输出电流Iout具有较高的精度。具体电路如图3中所示。所述电流镜单元包括两电流输入端以及一电流输出端；所述输出级还包括一第一运算放大器U1、一第一开关元件S1以及一第二开关元件S2。所述第一运算放大器U1的两输入端分别对应连接所述电流镜单元的电流输入端。所述第一开关元件S1的第一端连接所述电流镜单元的电流输出端，所述第一开关元件S1的第二端连接所述第一运算放大器U1的一输入端，所述第一开关元件S1的控制端连接所述第一运算放大器U1输出端。所述第二开关元件S2的第一端连接所述电流镜单元的电流输出端，所述第二开关元件S2的第二端用于输出所述输出电流Iout，所述第二开关元件S2的控制端连接所述第一运算放大器U1输出端。通过上述电路，保证了当输入电压误差为0时，没有电流输出，得到零失调电压，即可以更精准的控制乘法器的失调电压。
所述第一差分电压转换电路用于基于接收到的电压信号以及一第一参考电压Vref1生成一第一差分电压偏置所述第一差分输入级，本示例实施方式中以所述第一差分电压转换电路所接收到电压信号为一误差反馈电压Verror为例，当然，在其他示例实施方式中，所述第一差分电压转换电路所接收也可以为其他电压信号。具体而言，所述误差反馈电压Verror首先需要经过电压到差分电流的转换，例如，一种差分电流转换电路如图4中所示，图4中为了实现电压到差分电流的转换，使用了PNP型BJT晶体管，使得输入的电压与第一基准电压Vref1之间的电压差在第一电阻R2上产生差分电流。产生的差分电流再经过如图5中所示的一对BJT晶体管产生差分电压，从而得到反双曲正切函数。
所述第二差分电压转换电路用于基于接收到的电压信号以及一第二参考电压Vref2生成一第二差分电压偏置所述第二差分输入级，本示例实施方式中以所述第二差分电压转换电路所接收到电压信号为所述输入电压Vin为例，当然，在其他示例实施方式中，所述第二差分电压转换电路所接收也可以为其他电压信号。具体而言，所述输入电压Vin首先经过电压到差分电流的转换，再进行反双曲正切的转换。差分电流转换电路及 反双曲正切电路与图4及图5中类似，此处不再赘述。此外，为了增加输入的所述输入电压Vin的范围，可以使用电压跟随器得到接近0V的最小输入电压Vin。
由于工艺限制，可能无法提供性能优良的PNP器件，而图4中差分电流转换电路只是实现了类似电平转换的功能，因此理论上也可以用NPN型BJT晶体管替代。因此本示例实施方式中还基于此对所述第一差分电压转换电路以及第二差分电压转换电路进行了改进，使得其可以利用NPN型BJT晶体管实现，从而极大扩展电路的使用范围。而且，不使用PNP器件还可以降低对工艺的要求。此外，NPN型器件具有较高的增益(Beta)，因此也可以在一定程度上减小误差。
参考图6中所示，所述第二差分电压转换电路可以包括一MOSFET晶体管M1、一第一BJT晶体管对、一第二BJT晶体管对、一第一电阻R1以及一第一MOSFET晶体管对。所述MOSFET晶体管M1的栅极与漏极连接，所述MOSFET晶体管的源极连接所述电源电压Vcc。所述第一BJT晶体管对包括两个NPN型第一BJT晶体管Q11、Q12；两个所述第一BJT晶体管的基极及集电极连接所述MOSFET晶体管的漏极，两个所述第一BJT晶体管的发射极输出所述第二差分电压。所述第二BJT晶体管对包括两个NPN型第二BJT晶体管Q21、Q22；两个所述第二BJT晶体管的基极分别对应接收相异的两电压信号，两个所述第二BJT晶体管的集电极分别对应连接一所述第一BJT晶体管的发射极。所述第一电阻R1耦接于两个所述第二BJT晶体管的发射极之间。所述第一MOSFET晶体管对包括两个第一MOSFET晶体管M11、M12；两个所述第一MOSFET晶体管的栅极接收所述偏置电流，两个所述第一MOSFET晶体管的源极接地，两个所述第一MOSFET晶体管的漏极分别对应连接一所述第二BJT晶体管的发射极。
参考图7中所示，所述第一差分电压转换电路包括一第二MOSFET晶体管对、一第三BJT晶体管对、一第二电阻R2、一第三MOSFET晶体管对、一第四MOSFET晶体管对、第四BJT晶体管对以及一BJT晶体管Q50。所述第二MOSFET晶体管对包括两个第二MOSFET晶体管M21、M22；两个所述第二MOSFET晶体管的栅极与漏极连接，两个所述第二MOSFET晶体管源极连接所述电源电压Vcc。所述第三BJT晶体管对包括两个第三BJT晶体管Q31、Q32；两个所述第三BJT晶体管的基极分别对应接收相异的两电压信号，两个所述第三BJT晶体管的集电极分别对应连接一所述BJT晶体管的漏极。所述第二电阻R2耦接于两个所述第三BJT晶体管的发射极之间。所述第三MOSFET晶体管对包括两个第三MOSFET晶体管M31、M32；两个所述第三MOSFET晶体管的栅极接收所述偏置电流，两个所述第三MOSFET晶体管的源极接地，两个所述第三MOSFET晶体管的漏极分别对应连接一所述第三BJT晶体管的发射极。所述第四MOSFET晶体管对包括两个第四MOSFET晶体管M41、M42；两个所述第四MOSFET晶体管的栅极分别对应连接一所述第二MOSFET晶体管的栅极，两个第四MOSFET晶体管源极连接所述电源电压Vcc。所述第四BJT晶体管对包括两个NPN型第四BJT晶体管Q41、Q42；两个所述第四BJT晶体管的基极分别对应连接一所述第四MOSFET 晶体管的漏极，两个所述第四BJT晶体管的集电极输出所述第一差分电压。所述BJT晶体管Q50的基极与集电极连接并连接至所述第四BJT晶体管的发射极，所述BJT晶体管Q50的发射极接地，该BJT晶体管Q50可以提升直流工作电平。
所述偏置电流生成电路，用于基于一外部输入电压，例如一电压前馈电路提供的电压Vff生成一偏置电流偏置所述第一信号转换电路及第二信号转换电路，进而进行1/V2转换。本示例实施方式中，所述电压前馈电路用于保持并输出一输入电压的峰值电压至所述电压前馈电路。本示例实施方式中，所述输入电压来自于与一交流电源电压成比例的电压。参考图8中所示，本示例实施方式中的电压前馈电路主要包括一逻辑控制单元U2、一第三开关元件S3、一第四开关元件S4、一第五开关元件S3、一第一电容C1以及一第二电容C2等等；本示例实施方式中，开关元件可以包括MOSFET开关、IGBT开关或者BJT开关中的一种或多种。其中：
所述第三开关元件S3的第一端连接一电源电压Vcc，所述电源电压Vcc至少高于所述输入电压Vin的峰值电压，所述第三开关元件S3的控制端响应一第一控制信号Φ1而导通所述第三开关元件S3。所述逻辑控制单元U2用于在所述输入电压Vin的峰值电压期间输出一第二控制信号Φ2以及在所述输入电压Vin的非峰值电压期间输出一第三控制信号Φ3，参考图10中所示，为所述逻辑控制单元U2输出的控制信号时序图，可以看出所述第二控制信号Φ2、第三控制信号Φ3以及下述的第四控制信号Φ4之间具有非交叠时间，从而避免干扰而产生噪声。所述第一电容C1的第一端接地。所述第四开关元件S4的第一端连接所述第三开关元件S3第二端，所述第四开关元件S4的第二端连接所述第一电容C1第二端，所述第四开关元件S4的控制端响应所述第二控制信号Φ2而导通所述第四开关元件S4。所述第五开关元件S3的第一端连接所述第一电容C1第二端，所述第五开关元件S3的控制端响应所述第三控制信号Φ3而导通所述第五开关元件S3。所述第二电容C2的第一端接地，所述第二电容C2的第二端连接所述第五开关元件S3第二端。所述第一控制信号Φ1与所述第二控制信号Φ2同时开始提供，并在所述第一电容C1第二端的电压大于所述输入电压Vin的峰值电压时停止提供第一控制信号。
上述电压前馈电路中，在所述输入电压Vin的峰值电压期间提供一第一控制信号Φ1及第二控制信号Φ2导通所述第三开关元件S3及第四开关元件S4，因此所述电源电压Vcc经由所述第三开关元件S3及第四开关元件S4为所述第一电容C1充电；在所述第一电容C1充电至所述输入电压Vin的峰值电压时，停止提供所述第一控制信号Φ1，进而停止为所述第一电容C1充电。在所述输入电压Vin的非峰值电压期间关断所述第四开关元件S4并提供一第三控制信号Φ3导通所述第五开关元件S3，所述第一电容C1的第二端和第二电容C2的第二端连接，所述第一电容C1存储的电荷在所述第一电容C1和第二电容C2之间重新分布，因此所述输入电压Vin的峰值电压可以分享至所述第二电容C2的第二端，并且自所述第二电容C2第二端输出至乘法器。最终所述第二电 容C2第二端输出的电压为：
Vff＝(VC1×C1+VC2×C2)/(C1+C2)         (1)
其中，VC1为所述第一电容C1第二端在电荷再分布前的电压，VC2为所述第二电容C2第二端在电荷再分布前的电压。
上述电压前馈电路中，如果输入电压Vin发生突变，由于是电荷在第一电容C1和第二电容C2之间分享和再分布，因此可以使得第二电容C2第二端输出的电压Vff缓慢变化，从而有利于消除或减小输入电压Vin的瞬态波动所带来的不利影响。而经过若干个周期后即可以实现追踪和保持输入电压Vin的峰值电压的目的。此外，本示例实施方式中所述第一电容C1与所述第二电容C2之间的电容比例可调，进而可以通过控制第一电容C1与所述第二电容C2之间的电容比例而调整所述第二电容C2第二端输出的电压的变化率。
本示例实施方式中，所述逻辑控制单元U2还可以用于在所述输入电压Vin的非峰值电压期间输出一第四控制信号Φ4。参考图9中所示，本示例实施方式中所述电压前馈电路还可以包括一第四开关元件S4。所述第四开关元件S4的第一端连接所述第一电容C1第二端，所述第四开关元件S4的第二端接地，所述第四开关元件S4的控制端响应所述第四控制信号Φ4而导通所述第四开关元件S4。在所述输入电压Vin的非峰值电压期间，所述第四控制信号Φ4导通所述第四开关元件S4，进而对所述第一电容C1进行放电，防止当输入电压Vin有效值突然下降后，第一电容C1第二端的电压仍维持在变化前的输入电压Vin的峰值电压。
继续参考图9中所示，本示例实施方式中所述电压前馈电路还可以包括一第一比较器U2。所述第一比较器U2的第一输入端连接一基准电压Vref，所述第一比较器U2的第二输入端连接所述输入电压Vin，所述第一比较器U2的输出端输出所述输入电压Vin与所述基准电压Vref的比较结果信号至所述逻辑控制单元U2，所述逻辑控制单元U2据此判断是否处于所述输入电压Vin的峰值电压期间。例如，若所述输入电压Vin大于所述基准电压Vref，则所述第一比较器U2的输出端输出一低电平信号，所述逻辑控制单元U2可以据此判断处于所述输入电压Vin的峰值电压期间；若所述输入电压Vin小于所述基准电压Vref，则所述第一比较器U2的输出端输出一高电平信号，所述逻辑控制单元U2据此判断处于所述输入电压Vin的非峰值电压期间。
继续参考图9中所示，本示例实施方式中所述电压前馈电路还可以包括一第二比较器U3(或一第二运算放大器)。所述第二比较器U3(或所述第二运算放大器)的第一输入端连接所述输入电压Vin，所述第二比较器U3(或所述第二运算放大器)的第二输入端连接所述第三开关元件S3第一端，形成反馈电路。在所述第三开关元件S3导通，则所述第二比较器U3(或所述第二运算放大器)的输出端则根据所述输入电压Vin和所述第一电容C1第二端的电压的比较结果输出一比较结果信号至所述第三开关元件S3的控制端。例如，在所述第四开关元件S4导通的初始阶段，所述第一电容C1第二端的 电压为0，则所述第二比较器U3(或所述第二运算放大器)输出一高电平信号，该高电平信号即所述第一控制信号Φ1，从而导通所述第一开关器件，所述电源电压Vcc通过所述第一开关晶体管及第二开关晶体管对所述第一电容C1充电。所述第一电容C1第二端的电压跟随输入电压Vin的升高而升高，但所述第一电容C1第二端的电压仍小于所述输入电压Vin的峰值电压，即所述第一电容C1尚未充电完成，所述第二比较器U3(或所述第二运算放大器)仍输出一高电平信号(即所述第一控制信号Φ1)，从而保持所述第一开关器件导通。在所述第一电容C1第二端的电压不小于所述输入电压Vin的峰值电压时，即所述输入电压Vin已经开始下降，所述第一电平充电完成；由于第一电容C1没有放电通路，因此保持为所述输入电压Vin的峰值电压，所述第二比较器U3(或所述第二运算放大器)输出一低电平信号，该低电平信号关断所述第一开关器件，从而停止为所述第一电容C1充电。虽然第三开关元件S3处于关断状态，但第二比较器U3(或所述第二运算放大器)和第三开关元件S3之间的回路维持导通，避免出现当第三开关元件S3再次开启时，第三开关元件S3对第一电容C1突然充电，导致电压过冲。此外，如图9中所示，所述电压前馈电路还可以包括一第三电阻R3，第三电阻R3耦接于所述第三开关元件S3第二端和所述第一电容C1第二端之间，从而起限流作用。
进一步的，本示例实施方式中的电压前馈电路形成于一集成电路模块，进而所述第一电容C1及第二电容C2可以采用片内电容实现。因为片内电容要远小于外部电容，且交流信号的周期较长(50Hz对应20ms)，若使用片内电容替代外部电容，则需要解决片内电容上电压保持时间的问题，即需要考虑漏电流的影响，这一点在高温时会尤其严重。本示例实施方式中，由于主要的漏电流是与第一电容C1及第二电容C2相连的反偏PN结漏电流。因此继续参考图9中所示，本示例实施方式中的电压前馈电路还引入了一第一反偏PN结D1及一第二反偏PN结D2以平衡总的漏电流。所述第一反偏PN结D1耦接于所述电源电压Vcc和所述第一电容C1第二端之间；所述第二反偏PN结D2耦接于所述电源电压Vcc和所述第二电容C2第二端之间。所述第一反偏PN结D1及所述第二反偏PN结D2正常工作状态下均不导通且处于反偏状态，而漏电流会通过所述第一反偏PN结D1及所述第二反偏PN结D2从电源电压Vcc流入所述第一电容C1及第二电容C2。该漏电流则可以补偿从第一电容C1以及第二电容C2流出的漏电流。
本示例实施方式中采用两个片内电容实现输入电压Vin的峰值电压的保持与输出，而没有使用外部电阻，因此可以消除电容的纹波，避免在电容和电阻取值上折中选择。而且，本示例实施方式中通过设置漏电流补偿机制，平衡总的漏电流，增加了片内电容上电压的维持时间。片内电容输出的电压在维持时间内近似保持不变，有利于稳定乘法器的输出，减小THD(失真)，提高功率因数校正效果。
本示例实施方式中，所述偏置电流生成电路可以如图11中所示，乘法器整体电路如图12中所示。其中MOSFET晶体管M0输出的偏置电流为：
IBias＝Vff/R0           (3)
以图6中的第二差分电压转换电路为例，其中第一晶体管Q11发射极的电流为：
IBias+(Vin-Vref2)/R1              (4)
第一晶体管Q12发射极的电流为：
IBias-(Vin-Vref2)/R1               (5)
因此，图4中差分电压转换电路输出的差分电压为：
2×Vt×tanh-1(Vin-Vref2)/(R1×IBias)           (6)
将上述偏置电流生成电路产生的偏置电流代入公式(6)可得：
2×Vt×tanh-1(Vin-Vref2)×R0/(R1×Vff)           (7)
图吉尔伯特乘法器电路的输出为：
Iout＝IEE×tanh(V1/2Vt)×tanh(V2/2Vt)            (8)
其中IEE为尾电流值，V1，V2为两对输入电压，Iout为输出电流。
将(7)代入(8)可得：
Iout＝IEE×(Vin1-Vref1)×(Vin2-Vref2)/Vff2        (9)
式(9)说明电路含有1/Vff2项，即实现了电压前馈的功能。
本示例实施方式中还提供了一种功率因数校正电路。该功率因数校正电路包括本示例实施方式中所提供的任意一种乘法器。所述功率因数校正电路可以形成于一集成电路模块，所述第一电容C1以及第二电容C2为片内电容。关于本示例实施方式中的功率因数校正电路，其中乘法器的具体实现方式及技术效果已经进行了详细描述，此处将不做详细阐述说明。
综上所述，本公开示例实施方式中的乘法器中，通过设置反馈控制单元，利用反馈控制单元提供反馈控制，提高了乘法器输出电流精度，保证了当输入电压误差为0时，没有电流输出，即更精准的控制乘法器的失调电压。此外本公开示例实施方式中的乘法器中，由于没有使用PNP晶体管，因此可以降低对工艺的要求，扩展了电路应用范围。而且本公开示例实施方式中的电压前馈电路中，通过设置第一电容和第二电容实现了输入电压的峰值电压的保持，因此无需考虑现有技术中外部电阻和外部电容取值的折中选择。而且，由于输入电压的峰值电压的保持是基于所述第一电容和第二电容之间电荷的分享和重新分布实现，因此可以使得输出电压缓慢变化，有利于滤除输入电压的瞬态波动；同时通过设置不同的第一电容和第二电容比例，可以改变输出电压的变化斜率。第一电容和第二电容可以利用片内电容实现，因此可以节约***成本。此外，本示例实施方式中通过设置漏电流补偿机制，增加了内部电容上电压的维持时间，使得输出电压在维持时间内近似保持不变,有利于稳定乘法器。
本公开已由上述相关实施例加以描述，然而上述实施例仅为实施本公开的范例。必需指出的是，已揭露的实施例并未限制本公开的范围。相反地，在不脱离本公开的精神和范围内所作的更动与润饰，均属本公开的专利保护范围。

Claims (10)

  1. 一种乘法器，其特征在于，包括：
    一吉尔伯特乘法器电路，包括第一、第二差分输入级以及一输出级；所述输出级输出由所述第一、第二差分输入级的输入运算得到的输出电流；
    一第一差分电压转换电路，用于基于接收到的电压信号以及一第一参考电压生成一第一差分电压偏置所述第一差分输入级；
    一第二差分电压转换电路，用于基于接收到的电压信号以及一第二参考电压生成一第二差分电压偏置所述第二差分输入级；
    一偏置电流生成电路，用于生成一偏置电流偏置所述第一信号转换电路及第二信号转换电路；
    其中，所述输出级包括：
    一电流镜单元，包括两电流输入端以及一电流输出端；
    一反馈控制单元，用于保证在所述乘法器接收到的电压信号差为零时，所述电流输出端没有电流输出。
  2. 根据权利要求1所述的乘法器，其特征在于，所述电流镜单元由P型MOSFET晶体管组成。
  3. 根据权利要求1所述的乘法器，其特征在于，所述反馈控制单元包括：
    一第一运算放大器，其两输入端分别对应连接所述电流镜单元的电流输入端；
    一第一开关元件，其第一端连接所述电流镜单元的电流输出端，第二端连接所述第一运算放大器的一输入端，其控制端连接所述第一运算放大器输出端；
    一第二开关元件，其第一端连接所述电流镜单元的电流输出端，第二端用于输出所述输出电流，其控制端连接所述第一运算放大器输出端。
  4. 根据权利要求1-3任意一项所述的乘法器，其特征在于，所述第二差分电压转换电路包括：
    一MOSFET晶体管，其栅极与漏极连接，源极连接所述电源电压；
    一第一BJT晶体管对，包括两个NPN型第一BJT晶体管；两个所述第一BJT晶体管的基极及集电极连接所述MOSFET晶体管的漏极，发射极输出所述第二差分电压；
    一第二BJT晶体管对，包括两个NPN型第二BJT晶体管；两个所述第二BJT晶体管的基极分别对应接收相异的两电压信号，集电极分别对应连接一所述第一BJT晶体管的发射极；
    一第一电阻，耦接于两个所述第二BJT晶体管的发射极之间；
    一第一MOSFET晶体管对，包括两个第一MOSFET晶体管；两个所述第一MOSFET晶体管的栅极接收所述偏置电流，源极接地，漏极分别对应连接一所述第二BJT晶体管的发射极。
  5. 根据权利要求4所述的乘法器，其特征在于，一所述第二BJT晶体管的基极接收所述输入电压或一误差反馈电压，另一BJT晶体管的基极接收所述第二参考电压。
  6. 根据权利要求1-3任意一项任意一项所述的乘法器，其特征在于，所述第一差分电压转换电路包括：
    一第二MOSFET晶体管对，包括两个第二MOSFET晶体管；两个所述第二MOSFET晶体管的栅极与漏极连接，源极连接所述电源电压；
    一第三BJT晶体管对，包括两个第三BJT晶体管；两个所述第三BJT晶体管的基极分别对应接收相异的两电压信号，集电极分别对应连接一所述第二MOSFET晶体管的漏极；
    一第二电阻，耦接于两个所述第三BJT晶体管的发射极之间；
    一第三MOSFET晶体管对，包括两个第三MOSFET晶体管；两个所述第三MOSFET晶体管的栅极接收所述偏置电流，源极接地，漏极分别对应连接一所述第三BJT晶体管的发射极；
    一第四MOSFET晶体管对，包括两个第四MOSFET晶体管；两个所述第四MOSFET晶体管的栅极分别对应连接一所述第二MOSFET晶体管的栅极，源极连接所述电源电压；
    一第四BJT晶体管对，包括两个NPN型第四BJT晶体管；两个所述第四BJT晶体管的基极分别对应连接一所述第四MOSFET晶体管的漏极，集电极输出所述第一差分电压；
    一BJT晶体管，其基极与集电极连接并连接至所述第四BJT晶体管的发射极，其发射极接地。
  7. 根据权利要求6所述的乘法器，其特征在于，一所述第三BJT晶体管的基极接收所述输入电压或一误差反馈电压，另一BJT晶体管的基极接收所述第一参考电压。
  8. 根据权利要求1-3、5或7任意一项所述的乘法器，其特征在于，所述乘法器还包括：
    一电压前馈电路；所述偏置电流生成电路基于所述电压前馈电路提供的电压生成所述偏置电流。
  9. 一种功率因数校正电路，其特征在于，包括根据权利要求1-8任意一项所述的乘法器。
  10. 根据权利要求9所述的功率因数校正电路，其特征在于，所述功率因数校正电路形成于一集成电路模块。
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