WO2016112663A1 - 制作阵列基板的方法和阵列基板 - Google Patents

制作阵列基板的方法和阵列基板 Download PDF

Info

Publication number
WO2016112663A1
WO2016112663A1 PCT/CN2015/083543 CN2015083543W WO2016112663A1 WO 2016112663 A1 WO2016112663 A1 WO 2016112663A1 CN 2015083543 W CN2015083543 W CN 2015083543W WO 2016112663 A1 WO2016112663 A1 WO 2016112663A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
transmittance
array substrate
layer
photoresist
Prior art date
Application number
PCT/CN2015/083543
Other languages
English (en)
French (fr)
Inventor
沈奇雨
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/122,213 priority Critical patent/US9818813B2/en
Publication of WO2016112663A1 publication Critical patent/WO2016112663A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • Embodiments of the present invention relate to an array substrate for a display device, and more particularly to a method of fabricating an array substrate and an array substrate fabricated by the method.
  • an organic thin film electroluminescent device an organic light emitting diode (OLED) unit and an active matrix organic light emitting diode (AMOLED) unit have good shock resistance and viewing angle.
  • OLED organic light emitting diode
  • AMOLED active matrix organic light emitting diode
  • a pixel structure includes a pixel defining layer (PDL) for defining a pixel opening, and an OLED unit disposed on the pixel opening.
  • the light-emitting layer disposed between the first electrode layer serving as the transparent anode layer and the second electrode serving as the metal cathode layer on the substrate is made of an organic semiconductor material, and sequentially includes an evaporation hole injection layer and a hole transport layer. And an electron injection layer.
  • the OLED unit acquires an appropriate power supply, holes and electrons are injected from the first electrode layer and the second electrode layer, respectively, and then holes and electrons are conducted to the light-emitting layer, and radiation recombination occurs in the light-emitting layer, and the light-emitting layer is
  • the outer electron absorbing carrier composite releases energy and is in an excited state to realize luminescence, and the emitted light is emitted from the pixel opening.
  • Embodiments of the present invention provide a method of fabricating an array substrate and an array substrate fabricated by the method, which can reduce the number of patterning processes and reduce the number of masks used.
  • a method of fabricating an array substrate including: a flat layer disposed on a thin film transistor layer; and a light emitting device disposed on the flat layer An electrode.
  • the method includes the steps of forming a pixel defining layer for the first electrode, a via for a first electrode, and a spacer on a planar layer by a single patterning process using a single mask.
  • the primary patterning process includes The following steps:
  • the unremoved photoresist was peeled off.
  • the intensity of the exposure light beam passing through the mask is different, so that After the exposure and development processes are performed, a fully retained portion of the photoresist, a first half of the photoresist remains, and a completely removed portion of the photoresist are formed.
  • the photoresist is a positive photoresist
  • the mask includes corresponding to the via, the pixel defining layer, and the spacer, respectively.
  • the transmittance of the exposure beam in the first region is greater than the transmittance in the second region, and the transmittance in the second region is greater than the transmittance in the third region.
  • a transmittance of the exposure beam in the first region is 100%, and a transmittance in a second region is 65% to 75%.
  • the transmittance in the third region is zero.
  • the first region is a through hole that passes through a thickness of the mask, and the thickness of the second region is smaller than a thickness of the third region.
  • the mask further includes a fourth region corresponding to a surface used as a flat layer, and the exposure beam is transmitted through the fourth region The rate is greater than the transmittance in the third region and less than the transmittance in the second region.
  • the transmittance of the exposure beam in the fourth region is 25% to 35%.
  • a first electrode electrically connected to a drain of the thin film transistor layer is formed in the via hole and the pixel defining layer by a physical vapor deposition process, wherein The region where the pixel defining layer is located is formed with a depressed portion with respect to the surface of the flat layer.
  • the photoresist is a negative photoresist
  • the mask includes corresponding to the via, the pixel defining layer, and the spacer, respectively.
  • the transmittance of the exposure beam in the fifth region is smaller than the transmittance in the sixth region, and the transmittance in the sixth region is smaller than the transmittance in the seventh region.
  • the transmittance of the exposure beam in the fifth region is zero, and the transmittance in the sixth region is 25% to 35%.
  • the transmittance of the seventh region is 100%.
  • the thickness of the fifth region is greater than the thickness of the sixth region, and the seventh region is a through hole that passes through the thickness of the mask.
  • the mask further includes an eighth region corresponding to a surface used as a flat layer, and the exposure light beam is transmitted through the eighth region The rate is smaller than the transmittance in the seventh region and greater than the transmittance in the sixth region.
  • the transmittance of the exposure light beam in the eighth region is 65% to 75%.
  • an array substrate is provided, which is fabricated by the method described in the various embodiments above.
  • FIG. 1 is a partial cross-sectional view showing a method of forming a thin film transistor in a process of fabricating an array substrate according to a first exemplary embodiment of the present invention
  • Figure 2 is a partial cross-sectional view showing a flat layer formed on the basis of Figure 1;
  • 3a-3e are partial cross-sectional views showing the operation of forming a via, a pixel defining layer, and a spacer using a patterning process in accordance with the method of the first exemplary embodiment of the present invention on the basis of FIG. 2;
  • Figure 4 is a partial cross-sectional view showing the first electrode layer formed on the basis of Figure 3e;
  • FIG. 5 is a partial cross-sectional view of a mask used in forming a via, a pixel defining layer, and a spacer using a patterning process in a method of fabricating an array substrate in accordance with a second exemplary embodiment of the present invention.
  • a method of fabricating an array substrate comprising: a planar layer disposed on the thin film transistor layer; and a first electrode for the light emitting device disposed on the planar layer .
  • the method includes the steps of: forming a pixel defining layer for the first electrode, a via for a first electrode, and a pixel defining layer on a flat layer by a single patterning process using a single mask Separator.
  • the use of a single mask to form a pixel defining layer, a via, and a spacer on the planar layer by one patterning process reduces the number of patterning processes and reduces the number of masks used, thereby simplifying the fabrication process of the array substrate and reducing the number of mask substrates. production cost.
  • Figure 2 is a partial cross-sectional view showing the formation of a flat layer on the basis of Figure 1;
  • Figures 3a-3e show the method of forming a via, pixel defining by a patterning process according to the method of the first exemplary embodiment of the present invention on the basis of Figure 2
  • a partial cross-sectional view of the operation of the layers and spacers. 2 and 3a-3e, an embodiment of the present invention provides a method of fabricating an array substrate, the array substrate comprising: a flat layer 4 formed of a photosensitive organic resin material disposed on a thin film transistor layer, and a setting A first electrode 51 for the light emitting device on the flat layer 4.
  • the method includes the steps of forming a pixel defining layer 42 for arranging the first electrode, a via 41 for a first electrode, and a spacer on the flat layer 4 by a single patterning process using a single mask 7. 43. Forming the pixel defining layer 42, the via 41, and the spacer 43 by a single patterning process using a single halftone or gray tone mask 7, reducing the number of patterning processes and reducing the number of masks 7 used, thereby simplifying the array substrate The production process reduces the production cost.
  • an array substrate includes, for example, a substrate 1 made of glass or a transparent resin material, a buffer layer 21 formed on the substrate 1, and polysilicon formed on the buffer layer 21.
  • a (P-Si) thin film and a plurality of thin film transistors, a gate insulating layer 22, an intermediate dielectric layer 23, and a passivation layer 24 formed on the polysilicon film.
  • a silicon nitride (SiNx), silicon oxide (SiO2) film is sequentially deposited on the substrate 1 by a plasma chemical vapor deposition method to form a buffer layer 21; and an amorphous silicon (a-Si) film is deposited on the buffer layer 21;
  • the amorphous silicon is converted into polysilicon (Poly-Si) by excimer laser annealing (Excimer Laser Anneal).
  • Forming a polysilicon film then performing a polysilicon island photolithography process and a dry etching process to form a plurality of polysilicon islands required, one of which can be used as a storage capacitor electrically connected to the drain of the thin film transistor Capacitor electrode 31; thereafter, performing an N-channel doping process, for example, performing B+ doping to compensate for the threshold voltage Vth to fabricate a desired N-type channel; performing an n+ doping process,
  • the polysilicon channel doping region 32 corresponding to the source and drain of the thin film transistor is formed as an active layer region, for example, the doping material is PHx+; thereafter, the gate insulating layer 22 is formed on the buffer layer 21.
  • a process of forming a gate layer is performed.
  • a desired gate 35 and another capacitor electrode 37 of the storage capacitor are formed by a thin film deposition process, a photolithography process, and an etch process; and a Lightly Doped Drain (LDD) is further adopted.
  • the doping process forms an LDD doped region (sheet resistance transition region) 33 to reduce leakage current of the low temperature polysilicon thin film transistor; thereafter, a p+ doping process is performed to form a P-type channel in which the dopant material is B+.
  • a process of forming via holes is performed. Specifically, after the p+ doping process is completed, SiNx and SiO2 materials are sequentially deposited, and an activation (hydrogenation) process is performed to form the intermediate dielectric layer 23; then, the intermediate dielectric layer is formed by a photolithography process and an etching process. A first lap via is formed in the gate insulating layer 23 and 23 .
  • a wire bonding process is performed. Specifically, the Ti-Al-Ti metal material is deposited through the first via hole by a PVD deposition method; and the desired wiring layer 34 electrically connected to the source of the thin film transistor is obtained by a photolithography process and an etching process.
  • a process of forming a passivation layer 24 is performed. Specifically, the SiNx thin film material is deposited by a CVD deposition method to form a passivation layer 24; and a second lap via 36 extending to the drain of the thin film transistor is formed in the passivation layer 24 by a photolithography process and an etching process. .
  • a flat layer 4 is formed on the passivation layer 24 on the basis of FIG.
  • the flat layer 4 is made of a photosensitive organic resin material, but the present invention is not limited thereto.
  • the planarization layer 4 can be formed by depositing a thin film of silicon nitride (SiNx) and/or silicon oxide (SiO2) by a plasma chemical vapor deposition method.
  • the primary patterning process comprises the steps of: coating a photoresist 6 on the planar layer 4, as shown in FIG. 3a; exposing and developing the photoresist 6 by using the mask 7. As shown in FIGS. 3b and 3c; a partial planar layer having different thicknesses is removed in different regions of the planar layer 4 by an etching process, as shown in FIG. 3d, thereby forming via holes 41 and spacers 43 on the flat layer. And the pixel defining layer 42; and stripping the unremoved photoresist as shown in Figure 3e.
  • the pixel defining layer 44, the via 41, and the spacer 43 are formed by a single patterning process using a single mask 7, reducing the number of patterning processes and reducing the number of masks 7 used.
  • the array substrate may be an array substrate based on an Organic Light Emitting Diode (OLED) unit or an Active Matrix Organic Light Emitting Diode (AMOLED) unit.
  • OLED Organic Light Emitting Diode
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the OLED unit includes a first electrode layer 5 serving as a transparent anode layer disposed on the pixel defining layer 42, a second electrode (not shown) as a metal cathode layer, and a light emitting layer between the two (not shown) show).
  • the intensity of the exposure beam 10 passing through the mask 7 is different, so that exposure is performed.
  • a photoresist completely remaining portion 63, a photoresist first half remaining portion 62, and a photoresist completely removed portion 61 are formed.
  • the photoresist completely remaining portion 63 corresponds to the spacer 43
  • the first half remaining portion 62 of the photoresist is associated with the pixel defining layer 42. correspond.
  • the glue 7 has a different thickness.
  • first half retention portion of the photoresist is not limited to indicating that the thickness of the remaining photoresist is the entire thickness of the original photoresist after performing the exposure and development processes. Half, but means that the thickness of the remaining photoresist is a part of the entire thickness of the original photoresist, for example, about 40%, 50%, 60%, 70%, 75%, and the like.
  • the photoresist 6 is a positive photoresist
  • the mask 7 includes a first region 71 corresponding to the via 41, the pixel defining layer 42 and the spacer 43, respectively. Two regions 72 and a third region 73.
  • the transmittance of the exposure beam 10 in the first region 71 is greater than the transmittance in the second region 72, and the transmittance 72 in the second region is greater than the transmittance in the third region 73.
  • the transmittance of the exposure beam in the first region is about 100%
  • the transmittance in the second region is about 65%-75%, preferably 70%, and the transmittance in the third region.
  • the exposure beam 10 is ultraviolet light. It will be appreciated that the different transmittances of the exposure beam 10 in different regions are such that the exposure beams passing through the mask 7 have different intensities, thereby performing different degrees of exposure to the photoresist.
  • the first region 71 of the reticle is a through hole that passes through the thickness of the reticle, and the thickness of the second region 72 is less than the thickness of the third region 73.
  • the mask 7 further includes a fourth region 74 corresponding to the surface 44 used as the flat layer 4, and the transmittance of the exposure beam 10 in the fourth region 74 is greater than that of the third region 73.
  • the rate of overshoot is less than the transmittance of the second region 72.
  • the transmittance of the exposure beam 10 in the fourth region 74 is about 25% to 35%, preferably 30%. This As such, after passing through the patterning process, the thickness of all portions of the flat layer can be changed, and the regions of the flat layer 4 other than the via 41, the pixel defining layer 42, and the spacers 43 are made flatter.
  • a first electrode 5 electrically connected to the drain of the thin film transistor layer is formed in the via 41 and the pixel defining layer 42 on the basis of FIG. 3e, wherein the pixel defining layer 42 is located
  • the region is formed with a recess relative to the surface 44 of the flat layer.
  • ITO Indium Tin Oxide
  • PVD physical vapor deposition
  • a via hole 42 and a second overlap are formed on the pixel defining layer 42 by a patterning process.
  • the first electrode layer 5 can be used as an anode of the light-emitting unit.
  • the first electrode layer 5 may be made of, for example, a three-layer material having Indium Tin Oxide (ITO)-silver-ITO, a material such as silver or aluminum, such that the first electrode layer has a comparative Good reflection and conductivity.
  • ITO Indium Tin Oxide
  • the second lap via 36 may not be formed when the passivation layer 24 is formed, but the via hole 41 passing through the flat layer 4 and the passivation layer 24 are simultaneously formed while performing the patterning process on the flat layer. The second overlaps the vias 36 to further simplify the fabrication process.
  • the photoresist is a negative photoresist
  • a single halftone or gray tone mask 8 used in performing a patterning process includes respectively and the via hole. 41.
  • the transmittance of the exposure light beam in the fifth region 81 is smaller than the transmittance in the sixth region 82, and the transmittance in the sixth region 82 is smaller than the transmittance in the seventh region 83.
  • the transmittance of the exposure beam in the fifth region 81 is about zero, and the transmittance in the sixth region 82 is about 25% to 35%, preferably 30%, in the seventh region 83.
  • the pass rate is approximately 100%.
  • the thickness of the fifth region 81 is greater than the thickness of the sixth region 82, which is a through hole that passes through the thickness of the reticle.
  • the reticle 83 further includes an eighth region 84 corresponding to the surface 44 used as a planar layer, the transmittance of the exposure beam at the eighth region 84 being less than the transmittance of the seventh region 83 and greater than the sixth region Transmittance of 82.
  • the transmittance of the exposure beam in the eighth region 84 is approximately 65% to 75%, preferably 70%.
  • the photoresist of the embodiment of the present invention includes a positive photoresist material or a negative photoresist material.
  • the positive photoresist material refers to a substance that is not dissolved in the developer before exposure, and after exposure, the positive photoresist is converted into a substance that can be dissolved in the developer;
  • the negative photoresist material refers to It can be dissolved in the developer, and after exposure, the negative photoresist is converted into a substance that is not dissolved in the developer.
  • the implementation of negative photoresist The process of the patterning process is similar to the process of performing the patterning process by using a positive photoresist, and the technical effects produced are also corresponding, and will not be described herein.
  • an array substrate produced by the method of the above embodiment is provided.
  • Such an array substrate can be applied to a display device.
  • the display device can be any product or component having a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, an electronic paper, and the like.
  • the method for fabricating an array substrate according to the above-described embodiments of the present invention and the array substrate fabricated by the method, the pixel defining layer, the via holes and the spacers are formed on the flat layer by a single patterning process by using a single mask, thereby reducing the patterning process.
  • the number of times reduces the number of masks used, thereby simplifying the fabrication process of the array substrate and reducing the manufacturing cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供一种制作阵列基板的方法，该阵列基板包括：设置在薄膜晶体管层上的平坦层（4）、以及设置在所述平坦层（4）上的用于发光器件的第一电极（5）。该方法包括如下步骤：利用单个掩模板通过一次构图工艺在平坦层（4）上形成用于设置所述第一电极（5）的像素界定层（42）、用于第一电极的过孔（41）、以及隔垫物（43）。该方法减少了构图工艺的次数，减少了掩模板的使用数量。

Description

制作阵列基板的方法和阵列基板
本申请要求于2015年1月13日递交的、申请号为201510016188.3、发明名称为“制作阵列基板的方法和阵列基板”的中国专利申请的优先权，其全部内容通过引用并入本申请中。
技术领域
本发明的实施例涉及一种用于显示装置的阵列基板，尤其涉及一种制作阵列基板的方法和利用该方法制作的阵列基板。
背景技术
目前，作为一种有机薄膜电致发光器件，有机发光二极管(Organic Light Emitting Diode，OLED)单元以及有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)单元，由于具有抗震性好、视角广、操作温度宽、对比度高、可实现柔性显示等特点，不但广泛应用于显示装置中，也广泛应用于照明领域。
一般地，一个像素结构包括用于限定像素开口的像素界定层(PDL)、以及设置在像素开口上的OLED单元。设置在基板上的用做透明阳极层的第一电极层和作为金属阴极层的第二电极之间的发光层由有机半导体材料制成，并依次包括蒸镀空穴注入层、空穴传输层和电子注入层。当OLED单元获取到适当的电力供应时，分别从第一电极层和第二电极层注入空穴和电子，然后将空穴和电子传导至发光层，并在发光层发生辐射复合，发光层的外层电子吸收载流子复合释放能量后处于激发态，实现发光，所发出的光从像素开***出。
发明内容
本发明的实施例提供一种制作阵列基板的方法和利用该方法制作的阵列基板，可以减少构图工艺的次数，减少掩模板的使用数量。
根据本发明的一方面的实施例，提供一种制作阵列基板的方法，所述阵列基板包括：设置在薄膜晶体管层上的平坦层、以及设置在所述平坦层上的用于发光器件的第一电极。所述方法包括如下步骤：利用单个掩模板通过一次构图工艺在平坦层上形成用于设置所述第一电极的像素界定层、用于第一电极的过孔、以及隔垫物。
在根据本发明的一种实施例的制作阵列基板的方法中，所述一次构图工艺包括 如下步骤：
在所述平坦层上涂覆光刻胶；
利用掩模板对所述光刻胶进行曝光和显影；
采用刻蚀工艺，在平坦层的不同区域去除具有不同厚度的部分平坦层，以在平坦层上形成过孔、隔垫物和像素界定层；以及
将未去除的光刻胶剥离。
在根据本发明的一种实施例的制作阵列基板的方法中，在利用掩模板对所述光刻胶进行曝光和显影的步骤中，穿过所述掩模板的曝光光束的强度不同，使得在执行曝光和显影工艺之后，形成光刻胶完全保留部分、光刻胶第一半保留部分、以及光刻胶完全去除部分。其中，所述光刻胶完全保留部分与所述隔垫物相对应，所述光刻胶完全去除部分与所述过孔相对应，所述光刻胶第一半保留部分与所述像素界定层相对应。
在根据本发明的一种实施例的制作阵列基板的方法中，所述光刻胶为正性光刻胶，所述掩模板包括分别与所述过孔、像素界定层和隔垫物相对应的第一区域、第二区域和第三区域。其中，所述曝光光束在所述第一区域的透过率大于在第二区域的透过率，在第二区域的透过率大于在第三区域的透过率。
在根据本发明的一种实施例的制作阵列基板的方法中，所述曝光光束在所述第一区域的透过率为100％，在第二区域的透过率为65％-75％，在第三区域的透过率为零。
在根据本发明的一种实施例的制作阵列基板的方法中，所述第一区域为穿过所述掩模板厚度的通孔，所述第二区域的厚度小于第三区域的厚度。
在根据本发明的一种实施例的制作阵列基板的方法中，所述掩模板还包括与用做平坦层的表面相对应的第四区域，所述曝光光束在所述第四区域的透过率大于在第三区域的透过率并小于在第二区域的透过率。
在根据本发明的一种实施例的制作阵列基板的方法中，所述曝光光束在所述第四区域的透过率为25％-35％。
在根据本发明的一种实施例的制作阵列基板的方法中，在所述过孔和像素界定层采用物理气相沉积工艺形成电连接至所述薄膜晶体管层的漏极的第一电极，其中所述像素界定层所在的区域相对于平坦层的表面形成有凹陷部。
在根据本发明的一种实施例的制作阵列基板的方法中，所述光刻胶为负性光刻胶，所述掩模板包括分别与所述过孔、像素界定层和隔垫物相对应的第五区域、第六 区域和第七区域。其中，所述曝光光束在所述第五区域的透过率小于在第六区域的透过率，在第六区域的透过率小于在第七区域的透过率。
在根据本发明的一种实施例的制作阵列基板的方法中，所述曝光光束在所述第五区域的透过率为零，在第六区域的透过率为25％-35％，在第七区域的透过率为100％。
在根据本发明的一种实施例的制作阵列基板的方法中，所述第五区域的厚度大于第六区域的厚度，所述第七区域为穿过所述掩模板厚度的通孔。
在根据本发明的一种实施例的制作阵列基板的方法中，所述掩模板还包括与用做平坦层的表面相对应的第八区域，所述曝光光束在所述第八区域的透过率小于在第七区域的透过率并大于在第六区域的透过率。
在根据本发明的一种实施例的制作阵列基板的方法中，所述曝光光束在所述第八区域的透过率为65％-75％。
根据本发明的另一方面的实施例，提供一种阵列基板，所述阵列基板由上述各种实施例所述的方法制成。
附图说明
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明，其中：
图1是根据本发明的第一种示例性实施例的方法在制作阵列基板的过程中形成薄膜晶体管时的局部剖视图；
图2是在图1的基础上形成平坦层时的局部剖视图；
图3a-3e表示在图2的基础上根据本发明的第一种示例性实施例的方法采用构图工艺形成过孔、像素界定层和隔垫物的操作过程的局部剖视图；
图4是在图3e的基础上形成第一电极层时的局部剖视图；
图5是根据本发明的第二种示例性实施例的方法在制作阵列基板的过程中采用构图工艺形成过孔、像素界定层和隔垫物时所使用的掩模板的局部剖视图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一 种限制。
根据本发明总体上的发明构思，提供一种制作阵列基板的方法，所述阵列基板包括：设置在薄膜晶体管层上的平坦层以及设置在所述平坦层上的用于发光器件的第一电极。所述方法包括如下步骤：利用单个掩模板通过一次构图工艺在平坦层上形成用于设置所述第一电极的像素界定层、用于第一电极的过孔、以及位于所述像素界定层上的隔垫物。利用单个掩模板通过一次构图工艺在平坦层上形成像素界定层、过孔以及隔垫物，减少了构图工艺的次数，减少了掩模板的使用数量，从而简化了阵列基板的制作工艺，降低了制作成本。
在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
图2是在图1的基础上形成平坦层时的局部剖视图；图3a-3e表示在图2的基础上根据本发明的第一种示例性实施例的方法采用构图工艺形成过孔、像素界定层和隔垫物的操作过程的局部剖视图。参见图2和图3a-3e，本发明的实施例提供一种制作阵列基板的方法，所述阵列基板包括：设置在薄膜晶体管层上的由感光型有机树脂材料形成的平坦层4、以及设置在平坦层4上的用于发光器件的第一电极51。所述方法包括如下步骤：利用单个掩模板7通过一次构图工艺在平坦层4上形成用于设置所述第一电极的像素界定层42、用于第一电极的过孔41、以及隔垫物43。利用单个半色调或者灰色调掩模板7通过一次构图工艺形成像素界定层42、过孔41以及隔垫物43，减少了构图工艺的次数，减少了掩模板7的使用数量，从而简化了阵列基板的制作工艺，降低了制作成本。
图1是根据本发明的第一种示例性实施例的方法在制作阵列基板的过程中形成薄膜晶体管时的局部剖视图。参见图1，根据本发明的一种示例性实施例的阵列基板包括：例如由玻璃或者透明树脂材料制成的基板1、形成在基板1上的缓冲层21、形成在缓冲层21上的多晶硅(P-Si)薄膜、以及形成在多晶硅薄膜上的多个薄膜晶体管、栅极绝缘层22、中间介质层23以及钝化层24。
下面参照图1描述根据本发明一种示例性实施例的制作阵列基板的过程中形成薄膜晶体管的工艺过程。
首先，在基板1上通过等离子体化学气相沉积方法依次沉积氮化硅(SiNx)、氧化硅(SiO2)薄膜以形成缓冲层21；在缓冲层21上沉积非晶硅(a-Si)薄膜；再通过准分子激光退火工艺(Excimer Laser Anneal)，使非晶硅转变为多晶硅(Poly-Si) 形成多晶硅薄膜；然后进行多晶硅岛的光刻工艺和干法刻蚀工艺，以形成所需要的多个多晶硅岛，其中的一个多晶硅岛可以用做与薄膜晶体管的漏极电连接的存储电容的一个电容电极31；之后，执行N型沟道(channel)掺杂工艺，例如执行B+掺杂，以补偿阈值电压Vth，以制作出所需的N型沟道(channel)；执行n+掺杂工艺，以使与薄膜晶体管的源极、漏极对应的多晶硅沟道掺杂区域32形成为有源层区域，例如掺杂材料为PHx+；之后，在缓冲层21上形成栅极绝缘层22。
之后，执行形成栅极层的工艺。详细而言，通过薄膜沉积工艺、光刻工艺和刻蚀工艺形成所需要的栅极35、以及所述存储电容的另一电容电极37；再通过轻掺杂漏区(Lightly Doped Drain，LDD)掺杂工艺形成LDD掺杂区(薄层电阻过渡区)33，以降低低温多晶硅薄膜晶体管的漏电流；之后，执行p+掺杂工艺，以形成P型沟道，其中掺杂材料为B+。
之后，执行形成过孔的工艺。具体而言，在完成p+掺杂工艺后，再依次沉积SiNx和SiO2材料，并执行活化(氢化)工艺，以形成中间介质层23；然后，通过光刻工艺和刻蚀工艺，在中间介质层23和栅极绝缘层22中形成第一搭接过孔。
之后，执行布线绑定(Wire bonding)工艺。具体而言，通过PVD沉积方法穿过第一过孔沉积Ti-Al-Ti金属材料；再通过光刻工艺和刻蚀工艺得到电连接至薄膜晶体管的源极的所需要的布线层34。
之后，执行形成钝化(Passivation)层24的工艺。具体而言，通过CVD沉积方法沉积SiNx薄膜材料，形成钝化层24；再通过光刻工艺和刻蚀工艺在钝化层24中形成延伸到薄膜晶体管的漏极的第二搭接过孔36。
之后，如图2所示，在图1的基础上在钝化层24上形成平坦层4。在一种示例性实施例中，平坦层4由感光型有机树脂材料制成，但本发明并不局限于此。在一种可替换的实施例中，平坦层4可以通过等离子体化学气相沉积方法沉积氮化硅(SiNx)和/或氧化硅(SiO2)薄膜形成。
在本发明的一种实施例中，所述一次构图工艺包括如下步骤：在平坦层4上涂覆光刻胶6，如图3a所示；利用掩模板7对光刻胶6进行曝光和显影，如图3b和3c所示；采用刻蚀工艺，在平坦层4的不同区域去除具有不同厚度的部分平坦层，如图3d所示，从而在平坦层上形成过孔41、隔垫物43和像素界定层42；以及将未去除的光刻胶剥离，如图3e所示。这样，利用单个掩模板7通过一次构图工艺形成像素界定层44、过孔41以及隔垫物43，减少了构图工艺的次数，减少了掩模板7的使用数量。
在一种示例性实施例中，阵列基板可以是一种基于有机发光二极管(Organic Light Emitting Diode，OLED)单元或者有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)单元的阵列基板。例如，OLED单元包括设置在像素界定层42上的用做透明阳极层的第一电极层5、作为金属阴极层的第二电极(未示出)、以及位于二者之间的发光层(未示出)。
在一种实施例中，如图3c所示，在利用掩模板7对光刻胶6进行曝光和显影的步骤中，穿过所述掩模板7的曝光光束10的强度不同，使得在执行曝光和显影工艺之后，形成光刻胶完全保留部分63、光刻胶第一半保留部分62、以及光刻胶完全去除部分61。光刻胶完全保留部分63与隔垫物43相对应，所述光刻胶完全去除部分61与所述过孔41相对应，所述光刻胶第一半保留部分62与像素界定层42相对应。这样，通过控制穿过所述掩模板7的曝光光束的强度不同，可以使光刻胶6的不同部分的性能发生不同的变化，以便于后续的显影操作，并在执行显影工艺之后，使光刻胶7具有不同的厚度。
本领域的技术人员能够理解，本文提及的“光刻胶第一半保留部分”并不仅限于表示在执行曝光和显影工艺之后，所保留的光刻胶的厚度为原来光刻胶整个厚度的一半，而是指所保留的光刻胶的厚度为原来光刻胶整个厚度的一部分，例如大约40％、50％、60％、70％、75％等。
在一种实施例中，所述光刻胶6为正性光刻胶，所述掩模板7包括分别与过孔41、像素界定层42和隔垫物43相对应的第一区域71、第二区域72和第三区域73。所述曝光光束10在第一区域71的透过率大于在第二区域72的透过率，在第二区域的透过率72大于在第三区域73的透过率。例如，所述曝光光束在所述第一区域的透过率大约为100％，在第二区域的透过率大约为65％-75％，优选为70％，在第三区域的透过率大约为零。在一种实施例中，曝光光束10采用紫外光。可以理解，曝光光束10在不同区域的不同透过率，使得穿过掩模板7的曝光光束具有不同的强度，从而对光刻胶执行不同程度的曝光。
在一种实施例中，如图3b所述，掩模板的第一区域71为穿过掩模板厚度的通孔，第二区域72的厚度小于第三区域73的厚度。这样，通过设置掩模板具有不同的厚度，可以使曝光光束在穿过掩模板7之后，具有不同的强度。进一步地，所述掩模板7还包括与用做平坦层4的表面44相对应的第四区域74，所述曝光光束10在所述第四区域74的透过率大于第三区域73的透过率并小于第二区域72的透过率。例如，所述曝光光束10在第四区域74的透过率大约为25％-35％，优选为30％。这 样，在通过构图工艺之后，可以使平坦层的所有部分的厚度发生变化，并且使得平坦层4的除过孔41、像素界定层42和隔垫物43之外的区域更加平坦。
在一种实施例中，在图3e的基础上，在过孔41中和像素界定层42上形成电连接至薄膜晶体管层的漏极的第一电极5，其中所述像素界定层42所在的区域相对于平坦层的表面44形成有凹陷部。具体而言，通过物理气相沉积(PVD)工艺穿过过孔沉积氧化铟锡(Indium Tin Oxide，ITO)材料；再通过构图工艺在像素界定层42上形成穿过过孔42以及第二搭接过孔的第一电极层5。第一电极层5可以用做发光单元的阳极。在一种实施例中，第一电极层5可以由例如具有氧化铟锡(Indium Tin Oxide，ITO)-银-ITO的三层材料、银或铝等材料制成，使得第一电极层具有较好的反射和导电功能。
可以理解，可以在形成钝化层24时不形成第二搭接过孔36，而是在对平坦层执行构图工艺时，同时形成穿过平坦层4的过孔41和穿过钝化层24的第二搭接过孔36，从而进一步简化制作工艺。
图5是根据本发明的第二种示例性实施例的方法在制作阵列基板的过程中采用构图工艺形成过孔、像素界定层和隔垫物时所使用的掩模板的局部剖视图。参见图5，在第二种示例性实施例的方法中，所述光刻胶为负性光刻胶，执行构图工艺所采用的单个半色调或者灰色调掩模板8包括分别与所述过孔41、像素界定层42和隔垫物43相对应的第五区域81、第六区域82和第七区域83。所述曝光光束在所述第五区域81的透过率小于在第六区域82的透过率，在第六区域82的透过率小于在第七区域83的透过率。例如，所述曝光光束在所述第五区域81的透过率大约为零，在第六区域82的透过率大约为25％-35％，优选为30％，在第七区域83的透过率大约为100％。
在一种实施例中，所述第五区域81的厚度大于第六区域82的厚度，所述第七区域83为穿过所述掩模板厚度的通孔。掩模板83还包括与用做平坦层的表面44相对应的第八区域84，所述曝光光束在所述第八区域84的透过率小于第七区域83的透过率并大于第六区域82的透过率。例如，曝光光束在所述第八区域84的透过率大约为65％-75％，优选为70％。
如上所述，本发明实施例的光刻胶包括正性光刻胶材料或负性光刻胶材料。其中，所述正性光刻胶材料是指在曝光前不溶解于显影液，经过曝光后，正性光刻胶转变为能够溶解于显影液中的物质；所述负性光刻胶材料指能够溶解于显影液，经过曝光后，负性光刻胶转变为不溶解于显影液中的物质。可以理解，采用负性光刻胶执行 构图工艺的过程与采用正性光刻胶执行构图工艺的过程类似，所产生的技术效果也相对应，在此不再赘述。
根据本发明更进一步发明的实施例，提供一种由上述实施例的所述的方法制成的阵列基板。这种阵列基板可以应用于显示装置中。显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
根据本发明上述实施例的制作阵列基板的方法和利用该方法制作的阵列基板，利用单个掩模板通过一次构图工艺在平坦层上形成像素界定层、过孔以及隔垫物，减少了构图工艺的次数，减少了掩模板的使用数量，从而简化了阵列基板的制作工艺，降低了制作成本。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种制作阵列基板的方法，所述阵列基板包括：设置在薄膜晶体管层上的平坦层、以及设置在所述平坦层上的用于发光器件的第一电极，其中，所述方法包括如下步骤：
    利用单个掩模板通过一次构图工艺在平坦层上形成用于设置所述第一电极的像素界定层、用于第一电极的过孔、以及隔垫物。
  2. 如权利要求1所述的制作阵列基板的方法，其中，所述一次构图工艺包括如下步骤：
    在所述平坦层上涂覆光刻胶；
    利用掩模板对所述光刻胶进行曝光和显影；
    采用刻蚀工艺，在平坦层的不同区域去除具有不同厚度的部分平坦层，以在平坦层上形成过孔、隔垫物和像素界定层；以及
    将未去除的光刻胶剥离。
  3. 如权利要求2所述的制作阵列基板的方法，其中，在利用掩模板对所述光刻胶进行曝光和显影的步骤中，穿过所述掩模板的曝光光束的强度不同，使得在执行曝光和显影工艺之后，形成光刻胶完全保留部分、光刻胶第一半保留部分、以及光刻胶完全去除部分，
    其中，所述光刻胶完全保留部分与所述隔垫物相对应，所述光刻胶完全去除部分与所述过孔相对应，所述光刻胶第一半保留部分与所述像素界定层相对应。
  4. 如权利要求3所述的制作阵列基板的方法，其中，所述光刻胶为正性光刻胶，所述掩模板包括分别与所述过孔、像素界定层和隔垫物相对应的第一区域、第二区域和第三区域，
    其中，所述曝光光束在所述第一区域的透过率大于在第二区域的透过率，在第二区域的透过率大于在第三区域的透过率。
  5. 如权利要求4所述的制作阵列基板的方法，其中，所述曝光光束在所述第一区域的透过率为100％，在第二区域的透过率为65％-75％，在第三区域的透过率为零。
  6. 如权利要求5所述的制作阵列基板的方法，其中，所述第一区域为穿过所述掩模板厚度的通孔，所述第二区域的厚度小于第三区域的厚度。
  7. 如权利要求4或5所述的制作阵列基板的方法，其中，所述掩模板还包括与用做平坦层的表面相对应的第四区域，所述曝光光束在所述第四区域的透过率大于在第三区域的透过率并小于在第二区域的透过率。
  8. 如权利要求7所述的制作阵列基板的方法，其中，所述曝光光束在所述第四区域的透过率为25％-35％。
  9. 如权利要求7所述的制作阵列基板的方法，其中，在所述过孔和像素界定层采用物理气相沉积工艺形成电连接至所述薄膜晶体管层的漏极的第一电极，其中所述像素界定层所在的区域相对于平坦层的表面形成有凹陷部。
  10. 如权利要求3所述的制作阵列基板的方法，其中，所述光刻胶为负性光刻胶，所述掩模板包括分别与所述过孔、像素界定层和隔垫物相对应的第五区域、第六区域和第七区域，
    其中，所述曝光光束在所述第五区域的透过率小于在第六区域的透过率，在第六区域的透过率小于在第七区域的透过率。
  11. 如权利要求10所述的制作阵列基板的方法，其中，所述曝光光束在所述第五区域的透过率为零，在第六区域的透过率为25％-35％，在第七区域的透过率为100％。
  12. 如权利要求11所述的制作阵列基板的方法，其中，所述第五区域的厚度大于第六区域的厚度，所述第七区域为穿过所述掩模板厚度的通孔。
  13. 如权利要求10或11所述的制作阵列基板的方法，其中，所述掩模板还包括与用做平坦层的表面相对应的第八区域，所述曝光光束在所述第八区域的透过率小于在第七区域的透过率并大于在第六区域的透过率。
  14. 如权利要求13所述的制作阵列基板的方法，其中，所述曝光光束在所述第八区域的透过率为65％-75％。
  15. 一种阵列基板，其中，所述阵列基板由权利要求1-14所述的方法制成。
PCT/CN2015/083543 2015-01-13 2015-07-08 制作阵列基板的方法和阵列基板 WO2016112663A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/122,213 US9818813B2 (en) 2015-01-13 2015-07-08 Method for producing array substrate and array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510016188.3 2015-01-13
CN201510016188.3A CN104538357B (zh) 2015-01-13 2015-01-13 制作阵列基板的方法和阵列基板

Publications (1)

Publication Number Publication Date
WO2016112663A1 true WO2016112663A1 (zh) 2016-07-21

Family

ID=52853860

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/083543 WO2016112663A1 (zh) 2015-01-13 2015-07-08 制作阵列基板的方法和阵列基板

Country Status (3)

Country Link
US (1) US9818813B2 (zh)
CN (1) CN104538357B (zh)
WO (1) WO2016112663A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113552753A (zh) * 2021-07-23 2021-10-26 南京京东方显示技术有限公司 阵列基板的制造方法、阵列基板、显示面板及电子设备

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102308669B1 (ko) * 2014-12-05 2021-10-05 엘지디스플레이 주식회사 유기전계발광 표시장치 및 그 제조방법
CN104538357B (zh) 2015-01-13 2018-05-01 合肥京东方光电科技有限公司 制作阵列基板的方法和阵列基板
CN104932152B (zh) * 2015-06-23 2018-11-02 武汉华星光电技术有限公司 液晶显示面板及液晶显示面板的制造方法
CN105097675B (zh) * 2015-09-22 2018-01-30 深圳市华星光电技术有限公司 阵列基板及其制备方法
TWI578443B (zh) 2015-09-22 2017-04-11 友達光電股份有限公司 多晶矽薄膜電晶體元件及其製作方法
CN105470282B (zh) * 2015-11-20 2020-03-31 Tcl集团股份有限公司 一种无像素bank的TFT-OLED及制备方法
CN105449127B (zh) 2016-01-04 2018-04-20 京东方科技集团股份有限公司 发光二极管显示基板及其制作方法、显示装置
CN106024807B (zh) * 2016-06-07 2019-11-29 上海天马有机发光显示技术有限公司 一种显示面板及其制作方法
CN106887386A (zh) * 2016-12-27 2017-06-23 北京理工大学 准分子激光退火制备桥式沟道多晶硅薄膜的方法
WO2018119652A1 (zh) * 2016-12-27 2018-07-05 深圳市柔宇科技有限公司 阵列基板制作方法
CN106816558B (zh) * 2017-04-14 2019-09-03 京东方科技集团股份有限公司 顶发射有机电致发光显示面板、其制作方法及显示装置
CN110164873B (zh) * 2019-05-30 2021-03-23 京东方科技集团股份有限公司 阵列基板的制作方法、阵列基板、显示面板及显示装置
CN110165084A (zh) * 2019-06-25 2019-08-23 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板和显示装置
CN110767539B (zh) * 2019-10-31 2022-05-06 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN110993661A (zh) * 2019-12-02 2020-04-10 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
CN111276499B (zh) * 2020-03-26 2023-04-07 合肥鑫晟光电科技有限公司 显示用基板及其制备方法、显示装置
CN115000091B (zh) * 2022-05-31 2023-04-25 长沙惠科光电有限公司 一种显示面板的制备方法及显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101794049A (zh) * 2009-01-30 2010-08-04 三星移动显示器株式会社 平板显示装置及其制造方法
CN102856506A (zh) * 2011-06-28 2013-01-02 三星显示有限公司 有机发光显示装置及其制造方法
CN102881695A (zh) * 2011-07-14 2013-01-16 三星显示有限公司 薄膜晶体管阵列基板、其制造方法以及有机发光显示设备
CN103123910A (zh) * 2012-10-31 2013-05-29 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN104538357A (zh) * 2015-01-13 2015-04-22 合肥京东方光电科技有限公司 制作阵列基板的方法和阵列基板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100721569B1 (ko) * 2004-12-10 2007-05-23 삼성에스디아이 주식회사 칼라필터층을 갖는 유기전계발광소자
CN103151305B (zh) * 2013-02-28 2015-06-03 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板、制备方法以及显示装置
JP6300589B2 (ja) * 2013-04-04 2018-03-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
CN103500752A (zh) * 2013-09-27 2014-01-08 京东方科技集团股份有限公司 一种oled像素结构和oled显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101794049A (zh) * 2009-01-30 2010-08-04 三星移动显示器株式会社 平板显示装置及其制造方法
CN102856506A (zh) * 2011-06-28 2013-01-02 三星显示有限公司 有机发光显示装置及其制造方法
CN102881695A (zh) * 2011-07-14 2013-01-16 三星显示有限公司 薄膜晶体管阵列基板、其制造方法以及有机发光显示设备
CN103123910A (zh) * 2012-10-31 2013-05-29 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN104538357A (zh) * 2015-01-13 2015-04-22 合肥京东方光电科技有限公司 制作阵列基板的方法和阵列基板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113552753A (zh) * 2021-07-23 2021-10-26 南京京东方显示技术有限公司 阵列基板的制造方法、阵列基板、显示面板及电子设备
CN113552753B (zh) * 2021-07-23 2024-01-23 南京京东方显示技术有限公司 阵列基板的制造方法、阵列基板、显示面板及电子设备

Also Published As

Publication number Publication date
CN104538357B (zh) 2018-05-01
US9818813B2 (en) 2017-11-14
CN104538357A (zh) 2015-04-22
US20160372531A1 (en) 2016-12-22

Similar Documents

Publication Publication Date Title
WO2016112663A1 (zh) 制作阵列基板的方法和阵列基板
US9543443B2 (en) Thin film transistor assembly, array substrate method of manufacturing the same, and display device
WO2018227750A1 (zh) 柔性tft基板的制作方法
US20160370621A1 (en) Array substrate, manufacturing method thereof and liquid crystal display
US8241933B2 (en) Organic light emitting diode display and method of manufacturing the same
JP6956008B2 (ja) 薄膜トランジスタ、表示基板及び表示基板を有する表示パネル、並びにそれらの製造方法
WO2017092142A1 (zh) 低温多晶硅tft基板的制作方法
US8698251B2 (en) Organic light emitting diode display and method of manufacturing the same
US8946008B2 (en) Organic light emitting diode display, thin film transitor array panel, and method of manufacturing the same
JP7140780B2 (ja) アレイ基板及びその製造方法、表示装置
WO2016206236A1 (zh) 低温多晶硅背板及其制造方法和发光器件
US10192993B2 (en) Thin film transfer, manufacturing method thereof, array substrate and manufacturing method thereof
US10615282B2 (en) Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus
TW201622158A (zh) 薄膜電晶體以及其製作方法
US20150311322A1 (en) Method of manufacturing thin film transistor and organic light emitting diode display
WO2015188594A1 (zh) 多晶硅层及显示基板的制备方法、显示基板
WO2019028955A1 (zh) 有机电致发光显示面板及其制作方法
US9159773B2 (en) Thin film transistor and active matrix organic light emitting diode assembly
WO2016192446A1 (zh) 薄膜晶体管及其制作方法、阵列基板及其制作方法
US7176074B1 (en) Manufacturing method of thin film transistor array substrate
US8946720B2 (en) Organic light emitting diode display device and method of manufacturing the same
KR100934480B1 (ko) 유기 발광 표시 패널 및 그의 제조 방법
WO2019184026A1 (zh) Cmos晶体管的制备方法、阵列基板的制备方法
KR101941438B1 (ko) 유기 전계 발광 표시 패널 및 그의 제조방법
CN107393953B (zh) 低温多晶硅薄膜晶体管及其制作方法、有机发光显示器

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15122213

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15877578

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15877578

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 01/02/2018)

122 Ep: pct application non-entry in european phase

Ref document number: 15877578

Country of ref document: EP

Kind code of ref document: A1