WO2016086626A1 - 一种像素驱动电路、像素驱动方法和显示装置 - Google Patents

一种像素驱动电路、像素驱动方法和显示装置 Download PDF

Info

Publication number
WO2016086626A1
WO2016086626A1 PCT/CN2015/079901 CN2015079901W WO2016086626A1 WO 2016086626 A1 WO2016086626 A1 WO 2016086626A1 CN 2015079901 W CN2015079901 W CN 2015079901W WO 2016086626 A1 WO2016086626 A1 WO 2016086626A1
Authority
WO
WIPO (PCT)
Prior art keywords
intermediate node
transistor
pixel driving
unit
signal line
Prior art date
Application number
PCT/CN2015/079901
Other languages
English (en)
French (fr)
Inventor
青海刚
祁小敬
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/892,188 priority Critical patent/US9691328B2/en
Priority to EP15793665.9A priority patent/EP3048604B1/en
Publication of WO2016086626A1 publication Critical patent/WO2016086626A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to display technology, and more particularly, to a pixel driving circuit and a pixel driving method, and a display device.
  • Organic light-emitting displays are one of the hotspots in the field of flat panel display research today. Compared with liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs) have the advantages of low energy consumption, low production cost, self-illumination, wide viewing angle and fast response. At present, OLEDs have begun to be displayed in mobile phones, PDAs, digital cameras and other display fields. Replace the traditional LCD display. Among them, pixel driving is the core technical content of AMOLED display, which has important research significance.
  • the conventional AMOLED pixel driving circuit uses a 2T1C pixel driving circuit.
  • the circuit consists of only one drive thin film transistor (DTFT), one switched thin film transistor (TFT) (ie T1) and one storage capacitor C.
  • DTFT drive thin film transistor
  • TFT switched thin film transistor
  • the scan line is gated (ie, scanned)
  • the scan signal Vscan is a low level signal
  • T1 is turned on
  • the data signal Vdata is written to the storage capacitor C.
  • Fig. 2 is a timing chart showing the operation of the pixel driving circuit shown in Fig. 1, showing the timing relationship of the scanning signal supplied from the scanning line and the data signal supplied from the data line.
  • AMOLED ability of AMOLED to emit light is driven by the current generated by the driving thin film transistor DTFT in a saturated state. Whether it is a low temperature polysilicon (LTPS) process or an oxide (Oxide) process, due to process non-uniformity, a driving thin film transistor of different positions is caused.
  • the DTFT exhibits a difference in threshold voltage, which is fatal to the consistency of the current-driven device. Because different threshold voltages generate different driving currents when inputting the same driving voltage, causing inconsistency in current flowing through the OLED, resulting in uneven display brightness, thereby affecting the display effect of the entire image.
  • the currently proposed solution is to add a compensation unit to each pixel to eliminate the influence of the threshold voltage Vth by compensating the drive transistor.
  • most existing AMOLED compensation units require the data write switch to remain on during the threshold voltage compensation phase of the drive transistor until the drive transistor is automatically turned off. This phase takes a long time.
  • the data writing time of each row of pixels is shorter and shorter, and for the compensation phase, the data writing switch is always turned on, and the writing is too short. The entry time will not complete the threshold voltage acquisition, so this circuit cannot support high-resolution AMOLED panels.
  • the present disclosure proposes a pixel driving circuit, a pixel driving method, and a display device, which are charged to a data voltage in a short time by setting an additional memory cell, and after the data voltage writing switch is turned off, at a threshold voltage
  • the gate potential of the driving unit is stabilized by an additional memory cell, so that the memory cell in the pixel driving circuit has sufficient time to obtain a voltage related to the data voltage and the threshold voltage of the driving unit by self-discharge, thereby driving the pixel in the pixel driving circuit
  • the threshold voltage of the driving unit is compensated by the memory unit, so that the driving current supplied from the driving unit to the light emitting element is independent of its threshold voltage. Thereby, the time for writing the data voltage is shortened, and the threshold voltage of the driving unit is compensated for, and the high-resolution panel can be supported.
  • a pixel driving circuit for driving a light emitting element.
  • the pixel driving circuit includes: an illumination control signal line for providing an illumination control signal; a driving unit having an input end connected to the first intermediate node, a control end connected to the third intermediate node, and an output end connected to the illumination element One end, the other end of the light-emitting element is connected to the first power line; the first switch unit has an input end connected to the second power line, the control end is connected to the light-emitting control signal line, and the output end is connected to the first intermediate node; a second switch unit, the input end of which is connected to the reference signal line, the control end is connected to the second level scan signal line, and the output end is connected to the second intermediate node; the first storage unit has a first end connected to the first intermediate node a second end connected to the second intermediate node; a second storage unit having a first end connected to the second intermediate node and a second end connected to the third intermediate node; and
  • the second switching unit turns on the reference signal line and the second intermediate node under the control of the second-level scanning signal output by the second-stage scanning signal line, and maintains the a voltage on the second memory cell, thereby stabilizing a voltage of the control terminal of the driving unit, while the light emission control signal turns off the first switching unit, and the first memory unit performs self-discharge through the driving unit,
  • the data voltage and the drive unit threshold voltage are stored in a self-discharge manner.
  • the third switching unit turns on the third intermediate node and the second intermediate node, so that the second storage The unit is discharged.
  • the first switching unit turns on the second power line and the first intermediate node, so that the voltage difference between the control end and the input end of the driving unit is equal to The voltage of the first memory cell, thereby compensating for a threshold voltage of the driving unit such that a driving current supplied by the driving unit to the light emitting element is independent of its threshold voltage.
  • the driving unit includes a driving transistor, a gate of the driving transistor is connected to the third intermediate node, and a first electrode is connected to the one end of the light emitting element, and the second electrode Connected to the first intermediate node, the first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain.
  • the first switching unit includes a first transistor, a first electrode of the first transistor is connected to a second power line, a gate is connected to an emission control signal line, and a second electrode is An intermediate node is connected, the first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain.
  • the second switching unit includes a third transistor, the first electrode of the third transistor is connected to a reference signal line, the gate is connected to the second-level scanning signal line, and the second electrode is The second intermediate node is connected, the first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain.
  • the first storage unit includes a first storage capacitor connected between the first intermediate node and the second intermediate node.
  • the second storage unit includes a second storage capacitor connected between the second intermediate node and the third intermediate node.
  • the third switching unit includes a second transistor, a first electrode of the second transistor is connected to the third intermediate node, and a gate is connected to a third-level scanning signal line.
  • a second electrode is connected to the second intermediate node, the first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain.
  • the charge control unit includes a fourth transistor and a fifth transistor, and the gates of the fourth transistor and the fifth transistor are both connected to the first-stage scan signal line, the fourth transistor The first electrode is connected to the reference signal line, the second electrode is connected to the second intermediate node, the first electrode of the fifth transistor is connected to the data line, and the second electrode is connected to the third intermediate node, the first electrode is One of the source and the drain, the second electrode being the other of the source and the drain.
  • the driving transistor, the switching transistor, the first transistor, the second transistor, and the third transistor are all P-type thin film transistors.
  • a pixel driving method applied to a pixel driving circuit includes: providing a first-level scan signal through the first-level scan signal line, simultaneously providing an illumination control signal through the illumination control signal line, and providing a data signal on the data line, so that the pixel driving circuit enters the first An operation phase; turning off the light emission control signal before or at the same time as the first stage scan signal is turned off, so that the pixel drive circuit enters a second operation phase; and providing the second level scan signal through the second level scan signal line Providing the third-level scan signal through the third-level scan signal line such that the pixel drive circuit enters a third operational phase; and providing the illumination control signal line when the third-pole scan signal is off
  • the illumination control signal causes the pixel drive circuit to enter a drive phase.
  • a display device comprising the above pixel driving circuit.
  • the gate potential of the driving unit is stabilized by the auxiliary memory unit with the data voltage writing switch turned off, so that the memory cell has sufficient time to obtain by self-discharge
  • the data voltage and the drive unit threshold voltage are compensated by the memory cell during the drive phase such that the operating current of the drive unit is no longer affected by the threshold voltage.
  • FIG. 1 is a schematic structural view of a conventional pixel driving circuit
  • FIG. 3 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of operational timings of a pixel driving circuit according to another embodiment of the present disclosure.
  • FIG. 6 is an equivalent circuit diagram of a first operational stage of a pixel driving circuit in accordance with another embodiment of the present disclosure
  • FIG. 7 is an equivalent circuit diagram of a second operational stage of a pixel driving circuit in accordance with another embodiment of the present disclosure.
  • FIG. 8 is an equivalent circuit diagram of a third operational stage of a pixel driving circuit in accordance with another embodiment of the present disclosure.
  • FIG. 9 is an equivalent circuit diagram of a driving phase of a pixel driving circuit according to another embodiment of the present disclosure.
  • FIG. 10 illustrates a flow chart of a pixel driving method in accordance with an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a pixel driving circuit 300 according to an embodiment of the present disclosure.
  • the pixel driving circuit 300 is for driving the light emitting element 3000.
  • the light emitting element 3000 is shown as a light emitting diode OLED.
  • the pixel driving circuit 300 of the embodiment of the present disclosure includes: an emission control signal line EM(n) for providing an illumination control signal; and a first switch unit 310 whose input terminal is connected to the second power supply line ELVDD.
  • the control end is connected to the illumination control signal line EM(n), the output end is connected to the first intermediate node q;
  • the drive unit 320 has an input terminal connected to the first intermediate node q, and the control end is connected to the third intermediate node r, the output end Connected to one end of the light emitting element, the other end of the light emitting element is connected to the first power line ELVSS;
  • the third switch unit 330 has an input end connected to the third intermediate node r, and the control end is connected Connected to the third-level scan signal line S(n+2), the output terminal is connected to the second intermediate node p;
  • the second switch unit 340 has an input terminal connected to the reference signal line Ref, and the control terminal is connected to the second-stage scan signal a line S(n+1), the output terminal is connected to the second intermediate node p;
  • the charging control unit 350 has a first input terminal connected to the reference signal line Ref, a second input terminal connected to the data line data, and a
  • the first switching unit 310 turns on the second power line ELVDD and the first intermediate node. q.
  • the charge control unit 350 turns on the reference signal line Ref and the second intermediate node p, thereby connecting the pair
  • the second switching unit 340 is turned on under the control of the second-stage scanning signal Vs(n+1) outputted by the second-stage scanning signal line s(n+1).
  • the reference signal line Ref and the second intermediate node p maintain a voltage on the second memory unit 370. Since the first stage scan signal causes the charge control unit 350 to be turned off at this stage, the data voltage of the control terminal of the drive unit 320 can be well stabilized by the second memory unit 370.
  • the third switching unit 330 is turned on the third The intermediate node r and the second intermediate node p cause the second memory cell 370 to discharge, that is, the voltage difference across the second memory cell 370 becomes zero.
  • the driving phase is at the light emission control signal line EM(n)
  • the first switching unit 310 turns on the second power line ELVDD and the first intermediate node q such that the voltage difference between the control terminal and the input terminal of the driving unit 320 is equal to the first storage.
  • the sum of the voltages stored by the unit and the second storage unit. Since the voltage difference across the second memory cell is zero, the voltage difference between the control terminal and the input terminal of the driving unit 320 is V1 Vdata+
  • the driving current supplied from the driving unit 320 to the light emitting element 3000 is independent of its threshold voltage Vthd.
  • the first stage scanning signal line, the second stage scanning signal line and the third stage scanning signal line are respectively connected to an output end of the nth stage shift register in the gate driving circuit, an output end of the n+1th stage shift register, and The output of the n+2th shift register.
  • FIG. 4 is a schematic structural diagram of a pixel driving circuit 400 according to another embodiment of the present disclosure.
  • the first switching unit 310 includes a first transistor T1, and the source of the first transistor T1 is connected to the second power line ELVDD, and the gate and the light emission control The signal lines EM(n) are connected, and the drain is connected to the first intermediate node q.
  • the source of the first transistor T1 corresponds to the input end of the first switching unit 310
  • the gate corresponds to the control end of the first switching unit 310
  • the drain corresponds to the output of the first switching unit 310.
  • the driving unit 320 includes a driving transistor DTFT whose source is connected to the first intermediate node q, and the gate and the third intermediate node r Connected, the drain is connected to one end of the light emitting element OLED.
  • the source of the driving transistor DFTF corresponds to the input terminal of the driving unit 310
  • the gate corresponds to the control terminal of the driving unit 310
  • the drain corresponds to the output terminal of the driving unit 310.
  • the third switching unit 330 includes a second transistor T2, and the drain of the second transistor T2 is connected to the third intermediate node r, the gate and the third The level scanning signal lines S(n+2) are connected, and the source is connected to the second intermediate node p.
  • the drain of the second transistor T2 corresponds to the input of the third switching unit 330
  • the gate corresponds to the control terminal of the third switching unit 330
  • the source corresponds to the output of the third switching unit 330.
  • the second switching unit 340 includes a third transistor T3 whose source is connected to the reference signal line Ref, the gate and the second stage.
  • the scanning signal lines S(n+1) are connected, and the drain is connected to the second intermediate node p.
  • the source of the third transistor T3 corresponds to the input of the second switching unit 340
  • the gate corresponds to the control terminal of the second switching unit 340
  • the drain corresponds to the output of the second switching unit 340.
  • the charging control unit 350 The fourth transistor T4 and the fifth transistor T5 are included, the gates of the fourth transistor T4 and the fifth transistor T5 are both connected to the first-stage scanning signal line S(n), and the source of the fourth transistor T4 is connected to the reference signal line Ref.
  • the drain is connected to the second intermediate node p, the source of the fifth transistor is connected to the data line data, and the drain is connected to the third intermediate node r.
  • the gates of the fourth and fifth transistors correspond to the control terminal of the charge control unit 350, the source of the fourth transistor T4 corresponds to the first input of the charge control unit 350, and the drain corresponds to the charge control.
  • the source of fifth transistor T5 corresponds to a second input of charge control unit 350 and the drain corresponds to a second output of charge control unit 350.
  • the first memory unit 360 includes a first storage capacitor C1 connected between the first intermediate node q and the second intermediate node p.
  • the second memory unit 370 includes a second storage capacitor C2 connected between the second intermediate node p and the third intermediate node r.
  • the driving transistor DTFT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 shown in FIG. 4 may all be P-type thin film transistors.
  • the source and drain of the driving transistor DTFT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be interchanged depending on the type of transistor used.
  • the transistor of this type may be an enhancement transistor of the LTPS process or a depletion transistor of an oxide process.
  • the various transistors in accordance with embodiments of the present disclosure may also be other types of transistors.
  • FIG. 5 is a schematic diagram of operational timing of the pixel driving circuit 400 according to an embodiment of the present disclosure.
  • the pixel driving circuit 400 includes four stages, namely, a first operation stage, a second operation stage, a third operation stage, and a fourth operation stage, a driving stage.
  • FIG. 6 is an equivalent circuit diagram of a first operational phase of pixel drive circuit 400 in accordance with an embodiment of the present disclosure.
  • FIG. 7 is an equivalent circuit diagram of a second operational phase of the pixel driving circuit 400 in accordance with an embodiment of the present disclosure.
  • FIG. 8 is an equivalent circuit diagram of a third operational stage of the pixel driving circuit 400 in accordance with an embodiment of the present disclosure.
  • FIG. 9 is an equivalent circuit diagram of a driving phase of the pixel driving circuit 400 according to an embodiment of the present disclosure.
  • the workflow of the pixel driving circuit 400 according to an embodiment of the present disclosure will be described below with reference to FIGS. 5-9.
  • the turn-on level of each transistor is a low level, and the turn-off level is a high level.
  • the high level of the power supply is shown as ELVDD and the low level is shown as ELVSS.
  • All transistors are P-type transistors. Those skilled in the art will recognize that the application is not limited thereto.
  • the first operation phase the first-stage scan signal Vs(n) provided by the first-stage scan signal line S(n) is a low level, the data line provides a data signal Vdata, and the illumination control signal line EM(n) provides illumination control Signal Vemb(n) is low.
  • the remaining control signals that is, the second-stage scan signal and the third-stage scan signal are all at a high level. Therefore, T1, T4, and T5 are turned on, and T2 and T3 are turned off. Whether or not the driving transistor DTFT is turned on or off is related to the magnitude of the data voltage Vdata.
  • Second operation phase Vemb(n) and Vs(n+2) of this phase are high level, and T1 and T2 are cut off. As can be seen from Figure 5, this phase is divided into two time periods. During the first half of time, Vs(n) is at a low level, and Vs(n+1) is at a high level. Therefore, T4 and T5 are turned on, T3 is turned off, and the potential of the gate of the driving transistor DTFT is still Vdata, and the reference signal voltage Vref When T4 is connected to the p point, since T1 is turned off, the storage capacitor C1 starts to discharge through the DTFT, and the potential at the q point starts to decrease from VELVDD.
  • Vs(n) is at a high level and Vs(n+1) is at a low level, so T4, T5 are turned off and T3 is turned on.
  • T4 is turned off, T3 is turned on, so the reference signal voltage Vref is still connected to the p point through T3.
  • Vdata is the threshold voltage of the driving transistor DTFT, at which time the driving transistor DTFT is turned off.
  • -Vref; the voltage across C2 is: Vc2 Vdata-Vref.
  • Vs(n+2) is low level
  • Vs(n), Vs(n+1) and Vemb(n) are high level
  • T2 is turned on
  • the fourth operation phase in this phase, Vemb(n) jumps to a low level, and Vs(n), Vs(n+1), and Vs(n+2) are both high, so T1 is turned on, T2, T3, Both T4 and T5 are cut off.
  • the voltage across C1 is Vdata+
  • the driving current supplied by the driving transistor through the light emitting element OLED is:
  • I oled K(Vgs-
  • ) ⁇ 2 K(Vc1-
  • the illuminating current for driving the OLED is only related to the reference voltage Vref and the data voltage Vdata, and has no relationship with the threshold voltage Vthd of the DTFT, and K is related to the process and design. constant.
  • the relative offset between the rising edge of Vemb(n) and the rising edge of Vs(n) in the first operation phase can be adjusted, that is, the length of time of the first operation phase can be adjusted, which also adjusts the second time.
  • the length of time of the operation phase that is, the length of time required to compensate the threshold voltage of the driving transistor DTFT.
  • the time for compensating the threshold voltage of the driving transistor is the turn-on period of the second-stage scanning signal.
  • the threshold voltage compensation time (second operation phase) of the driving transistor is not shortened, so this The circuit that can adjust the threshold voltage compensation time is especially important for the high-resolution display panel. Otherwise, it may happen that the threshold voltage compensation of the driving transistor has not yet completed and the circuit operation of the next row has been completed, thereby failing to improve the high resolution.
  • the uniformity of the panel display By using the pixel driving circuit of the present application, the time for writing the data voltage is shortened, and sufficient time is ensured to compensate the threshold voltage of the driving unit, so that the high-resolution panel can be supported.
  • FIG. 4 shows only one example of this.
  • FIG. 10 illustrates a flow chart of a pixel driving method in accordance with an embodiment of the present disclosure.
  • the method is applied to a pixel driving circuit according to an embodiment of the present disclosure.
  • the driving method includes: first, at S1010, providing a first-level scan signal through the first-level scan signal line, and simultaneously providing an illumination control signal through the illumination control signal line, so that the pixel drive circuit enters the first operation.
  • a first-level scan signal is provided on the first-level scan signal line, and the light-emission control signal line provides an illumination control signal, and the pixel drive circuit enters the first operation phase. Then, the illumination control signal is turned off and the pixel drive circuit enters the first half of the second operational phase. Then, when the second-stage scan signal line provides the second-stage scan signal, that is, when the first-stage scan signal is turned off, the pixel drive circuit enters the second half of the second operation phase. Then, when the third-level scanning signal line provides the third-level scanning signal, the image The prime drive circuit enters the third phase of operation.
  • an illumination control signal is provided on the illumination control signal line, and the pixel drive circuit enters a driving phase to drive the illumination element to emit light. Since the storage capacitor C1 compensates for the threshold voltage of the driving unit, the driving current supplied from the driving unit to the light emitting element is independent of the threshold voltage of the driving unit.
  • the relative offset of the illumination control signal relative to the first stage scan signal can be adjusted to ensure the length of time of the second phase of operation (ie, the threshold voltage compensation phase) such that the storage capacitor C1 has sufficient time to obtain the data voltage by self-discharge and The threshold voltage of the drive unit.
  • the first transistor, the fourth transistor, and the fifth transistor are turned on.
  • the second transistor and the third transistor are turned off.
  • the third transistor is turned on, the first transistor and the second transistor are turned off, and the fourth transistor and the fifth transistor are turned on in the first half of the second operation phase, in the second The second half of the operational phase is closed.
  • the second transistor is turned on, and the first transistor, the third transistor, the fourth transistor, and the fifth transistor are turned off.
  • the first transistor is turned on, and the second transistor, the third transistor, the fourth transistor, and the fifth transistor are both turned off.
  • the present disclosure further provides a display device including the above-described pixel driving circuit.
  • the pixel circuit has been described in detail in the above embodiments, and details are not described herein again.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素驱动电路（300）和像素驱动方法、显示装置。除了传统像素驱动电路（300）中的存储单元之外，所述像素驱动电路（300）还包括辅助存储单元，用于在充电阶段充电至数据电压，并在阈值电压补偿阶段，在数据电压写入开关关闭的情况下稳定驱动单元（320）的栅极电位，从而使得驱动单元（320）的存储单元拥有充足的时间通过自放电获得数据电压和驱动单元阈值电压，并在驱动阶段由驱动单元（320）的存储单元对驱动单元（320）进行补偿，使得驱动单元（320）的工作电流不再受阈值电压的影响。

Description

一种像素驱动电路、像素驱动方法和显示装置 技术领域
本公开涉及显示技术，更具体地，涉及像素驱动电路和像素驱动方法、显示装置。
背景技术
有机发光显示器(AMOLED)是当今平板显示器研究领域的热点之一。与液晶显示器(LCD)相比，有机发光二极管(OLED)具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，目前，在手机、PDA、数码相机等显示领域OLED已经开始取代传统的LCD显示屏。其中，像素驱动是AMOLED显示器的核心技术内容，具有重要的研究意义。
与TFT-LCD利用稳定的电压控制亮度不同，OLED属于电流驱动，需要稳定的电流来控制发光。如图1所示，传统的AMOLED像素驱动电路采用2T1C像素驱动电路。该电路只有1个驱动薄膜晶体管(DTFT)，一个开关薄膜晶体管(TFT)(即T1)和一个存储电容器C组成。当扫描线选通(即扫描)某一行时，扫描信号Vscan为低电平信号，T1导通，数据信号Vdata写入存储电容器C。当该行扫描结束后，Vscan转变为高电平信号，T1截止，存储在存储电容器C上的栅极电压驱动DTFT，使其产生电流来驱动OLED，保证OLED在一帧显示内持续发光。驱动薄膜晶体管DTFT在达到饱和时的电流公式为Ioled＝K(Vgs-Vth)^2，其中K为与工艺和设计相关的参数，Vgs为驱动薄膜晶体管的栅-源电压，Vth为驱动薄膜晶体管的阈值电压。一旦晶体管的尺寸和工艺确定，参数K就确定了。图2示出了如图1所示的像素驱动电路的操作时序图，示出了扫描线提供的扫描信号和数据线提供的数据信号的时序关系。
AMOLED能够发光是由驱动薄膜晶体管DTFT在饱和状态时产生的电流所驱动，不管是低温多晶硅(LTPS)工艺还是氧化物(Oxide)工艺，由于工艺的不均匀性，都会导致不同位置的驱动薄膜晶体管DTFT出现阈值电压的差异，这对于电流驱动器件的一致性来说是很致命的。因为当输入相同的驱动电压时，不同的阈值电压会产生不同的驱动电流，造成流过OLED的电流的不一致性，使得显示亮度不均匀，从而影响整个图像的显示效果。
目前提出的解决方案是在各像素内加入补偿单元，通过补偿驱动晶体管来消除阈值电压Vth的影响。但是，现有的大多数AMOLED补偿单元在驱动晶体管的阈值电压补偿阶段需要数据写入开关一直开启，直到驱动晶体管自动截止。这个阶段需要较长的时间，对于高分辨率的AMOLED面板而言，每行像素的数据写入的时间越来越短，而对于补偿阶段需要数据写入开关一直开启的电路，过短的写入时间将无法完成阈值电压的获取，从而这种电路无法支持高分辨率的AMOLED面板。
因此，需要一种能够缩短数据电压写入的时间同时确保有充足的时间进行驱动单元阈值电压补偿的像素驱动电路和方法。
发明内容
本公开提出了一种像素驱动电路和像素驱动方法、显示装置，通过设置附加的存储单元，在较短的时间内将其充电至数据电压，并在数据电压写入开关关闭之后，在阈值电压补偿阶段，通过附加的存储单元稳定驱动单元的栅极电位，使得像素驱动电路中的存储单元拥有充足的时间通过自放电获得与数据电压和驱动单元的阈值电压有关的电压，从而在像素驱动电路的驱动阶段，利用存储单元对驱动单元的阈值电压进行补偿，使得驱动单元向发光元件提供的驱动电流与其阈值电压无关。由此，既缩短了数据电压写入的时间，也保证了对驱动单元的阈值电压进行补偿，可以支持高分辨率面板。
根据本公开的第一方面，提供一种像素驱动电路，用于对发光元件进行驱动。所述像素驱动电路包括：发光控制信号线，用于提供发光控制信号；驱动单元，其输入端连接到第一中间节点，控制端连接到第三中间节点，输出端连接到所述发光元件的一端，所述发光元件的另一端连接到第一电源线；第一开关单元，其输入端连接到第二电源线，控制端连接到发光控制信号线，输出端连接到第一中间节点；第二开关单元，其输入端连接到参考信号线，控制端连接到第二级扫描信号线，输出端连接到第二中间节点；第一存储单元，其第一端连接到所述第一中间节点，第二端连接到第二中间节点；第二存储单元，其第一端连接到所述第二中间节点，第二端连接到第三中间节点；第三开关单元，其输入端连接到所述第三中间节点，控制端连接到第三级扫描信号线，输出端连接到所述第二中间节点；充电控制单元，其第一输入端连接到参考信号线，第二输入端连接到数据线， 控制端连接到第一级扫描信号线，第一输出端连接到第二中间节点，第二输出端连接到第三中间节点；其中，在像素驱动电路的第一操作阶段，在发光控制信号线输出的发光控制信号的控制下，第一开关单元导通第二电源线和第一中间节点，在第一级扫描信号线输出的第一级扫描信号的控制下，所述充电控制单元导通参考信号线和第二中间节点，由此对连接于第一中间节点和第二中间节点的第一存储单元进行充电，所述充电控制单元还导通数据线和第三中间节点，由此对连接于第三中间节点和第二中间节点的第二存储单元进行充电。在像素驱动电路的第二操作阶段，在第二级扫描信号线输出的第二级扫描信号的控制下，所述第二开关单元导通所述参考信号线和第二中间节点，保持所述第二存储单元上的电压，从而稳定所述驱动单元的控制端的电压，同时所述发光控制信号使所述第一开关单元断开，所述第一存储单元通过所述驱动单元进行自放电，以自放电的方式存储数据电压和驱动单元阈值电压。在像素驱动电路的第三操作阶段，在第三级扫描信号线输出的第三级扫描信号的控制下，第三开关单元导通第三中间节点和第二中间节点，使得所述第二存储单元放电。在像素驱动电路的驱动阶段，在发光控制信号线输出的发光控制信号的控制下，第一开关单元导通第二电源线和第一中间节点，使得驱动单元的控制端和输入端的电压差等于所述第一存储单元的电压，从而对所述驱动单元的阈值电压进行补偿，使得所述驱动单元向所述发光元件提供的驱动电流与其阈值电压无关。
在本公开的一个实施例中，所述驱动单元包括驱动晶体管，所述驱动晶体管的栅极与所述第三中间节点相连，第一电极与所述发光元件的所述一端相连，第二电极与所述第一中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
在本公开的一个实施例中，所述第一开关单元包括第一晶体管，所述第一晶体管的第一电极与第二电源线相连，栅极与发光控制信号线相连，第二电极与第一中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
在本公开的一个实施例中，所述第二开关单元包括第三晶体管，所述第三晶体管的第一电极与参考信号线相连，栅极与第二级扫描信号线相连，第二电极与第二中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
在本公开的一个实施例中，所述第一存储单元包括第一存储电容器，连接于所述第一中间节点和所述第二中间节点之间。
在本公开的一个实施例中，所述第二存储单元包括第二存储电容器，连接于所述第二中间节点和所述第三中间节点之间。
在本公开的一个实施例中，所述第三开关单元包括第二晶体管，所述第二晶体管的第一电极与所述第三中间节点相连，栅极与第三级扫描信号线相连，第二电极与所述第二中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
在本公开的一个实施例中，所述充电控制单元包括第四晶体管和第五晶体管，所述第四晶体管和第五晶体管的栅极均与第一级扫描信号线相连，所述第四晶体管的第一电极与参考信号线相连，第二电极与第二中间节点相连，所述第五晶体管的第一电极与数据线相连，第二电极与第三中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
在本公开的一个实施例中，所述驱动晶体管、开关晶体管、第一晶体管、第二晶体管以及第三晶体管均为P型薄膜晶体管。
根据本公开的第二方面，提供一种像素驱动方法，应用于根据本公开的像素驱动电路。所述像素驱动方法包括：通过所述第一级扫描信号线提供第一级扫描信号，同时通过所述发光控制信号线提供发光控制信号并在数据线提供数据信号，使得像素驱动电路进入第一操作阶段；在第一级扫描信号关闭之前或同时，关闭所述发光控制信号，使得所述像素驱动电路进入第二操作阶段；通过所述第二级扫描信号线提供所述第二级扫描信号；通过所述第三级扫描信号线提供所述第三级扫描信号，使得所述像素驱动电路进入第三操作阶段；以及在所述第三极扫描信号关闭时通过所述发光控制信号线提供所述发光控制信号，使得所述像素驱动电路进入驱动阶段。
根据本公开的第三方面，提供一种显示装置，包括上述的像素驱动电路。
根据本公开的像素驱动电路和像素驱动方法、显示装置，在数据电压写入开关关闭的情况下借助辅助存储单元来稳定驱动单元的栅极电位，从而使得存储单元拥有充足的时间通过自放电获得数据电压和驱动单元阈值电压，并在驱动阶段由该存储单元对驱动单元进行补偿，使得驱动单元的工作电流不再受阈值电压的影响。
附图说明
通过下面结合附图说明本公开的优选实施例，将使本公开的上述及其它目的、特征和优点更加清楚，其中：
图1是传统像素驱动电路的结构示意图；
图2是传统像素驱动电路的操作时序图；
图3是根据本公开实施例的像素驱动电路的结构示意图；
图4是根据本公开另一实施例的像素驱动电路的结构示意图；
图5是根据本公开另一实施例的像素驱动电路的操作时序的示意图；
图6是根据本公开另一实施例的像素驱动电路的第一操作阶段的等效电路图；
图7是根据本公开另一实施例的像素驱动电路的第二操作阶段的等效电路图；
图8是根据本公开另一实施例的像素驱动电路的第三操作阶段的等效电路图；
图9是根据本公开另一实施例的像素驱动电路的驱动阶段的等效电路图；
图10示出了根据本公开实施例的像素驱动方法的流程图。
具体实施方式
以下参照附图，对本公开的示例实施例进行详细描述。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。
图3是根据本公开实施例的像素驱动电路300的结构示意图。像素驱动电路300用于对发光元件3000进行驱动。在图3中，发光元件3000被示出为发光二极管OLED。如图3所示，本公开实施例的像素驱动电路300包括：发光控制信号线EM(n)，用于提供发光控制信号；第一开关单元310，其输入端连接到第二电源线ELVDD，控制端连接到发光控制信号线EM(n)，输出端连接到第一中间节点q；驱动单元320，其输入端连接到第一中间节点q，控制端连接到第三中间节点r，输出端连接到所述发光元件的一端，所述发光元件的另一端连接到第一电源线ELVSS；第三开关单元330，其输入端连接到所述第三中间节点r，控制端连 接到第三级扫描信号线S(n+2)，输出端连接到第二中间节点p；第二开关单元340，其输入端连接到参考信号线Ref，控制端连接到第二级扫描信号线S(n+1)，输出端连接到第二中间节点p；充电控制单元350，其第一输入端连接到参考信号线Ref，第二输入端连接到数据线data，控制端连接到第一级扫描信号线S(n)，第一输出端连接到第二中间节点p，第二输出端连接到第三中间节点r；第一存储单元360，其第一端连接到第一中间节点q，第二端连接到第二中间节点p；第二存储单元370，其第一端连接到所述第二中间节点p，第二端连接到第三中间节点r。
在像素驱动电路300的第一操作阶段，在发光控制信号线EM(n)输出的发光控制信号Vemb(n)的控制下，第一开关单元310导通第二电源线ELVDD和第一中间节点q。在第一级扫描信号线s(n)输出的第一级扫描信号Vs(n)的控制下，所述充电控制单元350导通参考信号线Ref和第二中间节点p，由此对连接于第一中间节点q和第二中间节点p的第一存储单元360进行充电，使之存储电压V＝VELVDD-Vref，其中VELVDD表示第二电源线ELVDD的电位，Vref表示参考信号线Ref的电位。所述充电控制单元350还导通数据线data和第三中间节点r，由此对连接于第三中间节点r和第二中间节点p的第二存储单元370进行充电，使之存储电压V＝Vdata-Vref，其中Vdata表示数据电压。
在像素驱动电路300的第二操作阶段，在第二级扫描信号线s(n+1)输出的第二级扫描信号Vs(n+1)的控制下，所述第二开关单元340导通所述参考信号线Ref和第二中间节点p，保持所述第二存储单元370上的电压。由于在该阶段第一级扫描信号使得所述充电控制单元350断开，因而通过第二存储单元370可以很好地稳定驱动单元320的控制端的数据电压。同时，由于发光控制信号使得第一开关单元310断开，第一存储单元360通过驱动单元320进行自放电，以此使得第一存储单元360存储与数据电压和驱动单元的阈值电压有关的充电电压，即V1＝Vdata+|Vthd|-Vref，其中Vthd表示驱动单元320的阈值电压。
在像素驱动电路300的第三操作阶段，在第三级扫描信号线S(n+2)输出的第三级扫描信号Vs(n+2)的控制下，第三开关单元330导通第三中间节点r和第二中间节点p，使得第二存储单元370放电，即第二存储单元370两端的电压差变为零。
在像素驱动电路300的第四操作阶段，驱动阶段，在发光控制信号线EM(n) 输出的发光控制信号Vemb(n)的控制下，第一开关单元310导通第二电源线ELVDD和第一中间节点q，使得驱动单元320的控制端和输入端的电压差等于所述第一存储单元和第二存储单元存储的电压之和。由于第二存储单元两端的电压差为零，驱动单元320的控制端和输入端的电压差即为V1＝Vdata+|Vthd|-Vref。此时驱动单元320向发光元件3000提供的驱动电流与其阈值电压Vthd无关。
第一级扫描信号线、第二级扫描信号线和第三级扫描信号线分别连接到栅极驱动电路中第n级移位寄存器的输出端、第n+1级移位寄存器的输出端以及第n+2级移位寄存器的输出端。
图4是根据本公开另一实施例的像素驱动电路400的结构示意图。
如图4所示，在根据本公开实施例的像素驱动电路400中，第一开关单元310包括第一晶体管T1，第一晶体管T1的源极与第二电源线ELVDD相连，栅极与发光控制信号线EM(n)相连，漏极与第一中间节点q相连。在该实施例中，第一晶体管T1的源极对应于第一开关单元310的输入端，栅极对应于第一开关单元310的控制端，漏极对应于第一开关单元310的输出端。
如图4所示，在根据本公开实施例的像素驱动电路400中，驱动单元320包括驱动晶体管DTFT，所述驱动晶体管的源极与第一中间节点q相连，栅极与第三中间节点r相连，漏极与发光元件OLED的一端相连。在该实施例中，驱动晶体管DFTF的源极对应于驱动单元310的输入端，栅极对应于驱动单元310的控制端，漏极对应于驱动单元310的输出端。
如图4所示，在根据本公开实施例的像素驱动电路400中，第三开关单元330包括第二晶体管T2，第二晶体管T2的漏极与第三中间节点r相连，栅极与第三级扫描信号线S(n+2)相连，源极与第二中间节点p相连。在该实施例中，第二晶体管T2的漏极对应于第三开关单元330的输入端，栅极对应于第三开关单元330的控制端，源极对应于第三开关单元330的输出端。
如图4所示，在根据本公开实施例的像素驱动电路400中，第二开关单元340包括第三晶体管T3，第三晶体管T3的源极与参考信号线Ref相连，栅极与第二级扫描信号线S(n+1)相连，漏极与第二中间节点p相连。在该实施例中，第三晶体管T3的源极对应于第二开关单元340的输入端，栅极对应于第二开关单元340的控制端，漏极对应于第二开关单元340的输出端。
如图4所示，在根据本公开实施例的像素驱动电路400中，充电控制单元350 包括第四晶体管T4和第五晶体管T5，第四晶体管T4和第五晶体管T5的栅极均与第一级扫描信号线S(n)相连，第四晶体管T4的源极与参考信号线Ref相连，漏极与第二中间节点p相连，第五晶体管的源极与数据线data相连，漏极与第三中间节点r相连。在该实施例中，第四和第五晶体管的栅极对应于充电控制单元350的控制端，第四晶体管T4的源极对应于充电控制单元350的第一输入端，漏极对应于充电控制单元350的第一输出端，第五晶体管T5的源极对应于充电控制单元350的第二输入端，漏极对应于充电控制单元350的第二输出端。
如图4所示，在根据本公开实施例的像素驱动电路400中，第一存储单元360包括第一存储电容器C1，连接于第一中间节点q和第二中间节点p之间。
如图4所示，在根据本公开实施例的像素驱动电路400中，第二存储单元370包括第二存储电容器C2，连接于第二中间节点p和第三中间节点r之间。
图4所示的驱动晶体管DTFT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5可以均为P型薄膜晶体管。根据所使用的晶体管的类型，驱动晶体管DTFT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5的源极和漏极可以互换。
该型晶体管可以是LTPS工艺的增强型晶体管，也可以是氧化物工艺的耗尽型晶体管。当然，根据本公开实施例的各个晶体管也可以是其他类型的晶体管。
图5是根据本公开实施例的像素驱动电路400的操作时序的示意图。如图5所示，像素驱动电路400包括四个阶段，即第一操作阶段；第二操作阶段；第三操作阶段；以及第四操作阶段，驱动阶段。
图6是根据本公开实施例的像素驱动电路400的第一操作阶段的等效电路图。图7是根据本公开实施例的像素驱动电路400的第二操作阶段的等效电路图。图8是根据本公开实施例的像素驱动电路400的第三操作阶段的等效电路图。图9是根据本公开实施例的像素驱动电路400的驱动阶段的等效电路图。下面结合图5-9来描述根据本公开实施例的像素驱动电路400的工作流程。
假定在该实施例中，各个晶体管的开启电平为低电平，关闭电平为高电平。电源的高电平示出为ELVDD，低电平示出为ELVSS。所有晶体管均为P型晶体管。本领域技术人员可以认识到，本申请并不局限于此。
第一操作阶段：第一级扫描信号线S(n)提供的第一级扫描信号Vs(n)为低电平，数据线提供数据信号Vdata，发光控制信号线EM(n)提供的发光控制信号 Vemb(n)为低电平。其余的控制信号，即第二级扫描信号、第三级扫描信号均为高电平。因此T1、T4、T5开启，T2、T3关闭。驱动晶体管DTFT是否开启或截止和数据电压Vdata的大小有关。在该阶段中，参考信号线Ref提供的参考信号电压Vref通过T4到达p点，ELVDD通过T1对C1充电，Vdata通过T5对C2充电。因此，在该阶段结束时，C1两端的电压为Vc1＝ELVDD-Vref；C2两端的电压为：Vc2＝Vdata-Vref。
第二操作阶段：该阶段的Vemb(n)、Vs(n+2)为高电平，T1、T2截止。从图5可以看出，该阶段分为两个时间段。在前半段时间Vs(n)处于低电平，Vs(n+1)处于高电平，因此T4、T5开启，T3截止，驱动晶体管DTFT的栅极的电位仍为Vdata，而参考信号电压Vref通过T4与p点连通，由于T1截止，存储电容器C1通过DTFT开始放电，q点的电位从VELVDD开始下降。在该阶段的后半段时间，Vs(n)处于高电平，Vs(n+1)处于低电平，因此T4、T5截止，T3开启。虽然T4截止，但T3开启，因此参考信号电压Vref仍然通过T3与p点连通，由于参考信号电压的存在，与驱动晶体管的栅极连接的存储电容器C2的一端将保持电位不变，仍然为Vdata，q点电位会继续下降，直到降为Vdata+|Vthd|，其中Vthd为驱动晶体管DTFT的阈值电压，此时驱动晶体管DTFT截止。此时C1两端的电压为：Vc1＝Vdata+|Vthd|-Vref；C2两端的电压为：Vc2＝Vdata-Vref。
第三操作阶段：该阶段Vs(n+2)为低电平，Vs(n)、Vs(n+1)和Vemb(n)为高电平，因此T2开启，T1、T3、T4、T5都截止。由于T2的开启，C2两端连通，C2放电，其两端的电压差变为0，因此Vc2＝0，C1两端的电压保持不变。
第四操作阶段：该阶段Vemb(n)跳变为低电平，Vs(n)、Vs(n+1)、Vs(n+2)都为高电平，因此T1开启，T2、T3、T4、T5都截止。此时，由于C1两端的电压为Vdata+|Vthd|-Vref，而C2两端的电压为0，因此对于驱动晶体管DTFT，其源极对栅极的电压差即为C1两端的电压差，即Vsg＝Vc1＝Vdata+|Vthd|-Vref。驱动晶体管提供的流过发光元件OLED的驱动电流即为：
Ioled＝K(Vgs-|Vthd|)^2＝K(Vc1-|Vthd|)^2
＝K(Vdata+|Vthd|-Vref-|Vthd|)^2
＝K(Vdata-Vref)^2。
由上式可以知道，驱动OLED的发光电流只与参考电压Vref和数据电压Vdata有关系，而与DTFT的阈值电压Vthd已经没有关系了，K为与工艺和设计相关的 常数。
需要进一步说明的是可以调整第一操作阶段中Vemb(n)上升沿与Vs(n)上升沿之间的相对偏移，即可以调节第一操作阶段的时间长度，这同时也调节了第二操作阶段的时间长度，即对驱动晶体管DTFT的阈值电压进行补偿所需要时间的长度。当然，发光控制信号的关闭时间与第一级扫描信号的关闭时间对齐也是可行的。在这种情况下，对驱动晶体管的阈值电压进行补偿的时间是第二级扫描信号的开启周期。对于高分辨率的显示面板，由于每行的数据电压写入时间(即，第一操作阶段)缩短，但驱动晶体管的阈值电压补偿的时间(第二操作阶段)不会被缩短，因此这种可以调整阈值电压补偿时间的电路对于高分辨率显示面板就显得尤其重要，否则就有可能出现在驱动晶体管的阈值电压补偿还没有完成就已经进入下一行的电路操作的情形，从而无法改善高分辨率面板显示的均匀性。利用本申请的像素驱动电路，既缩短了数据电压写入的时间，也保证了充足的时间对驱动单元的阈值电压进行补偿，因此可以支持高分辨率面板。
虽然在图4中示出了根据本发明的驱动单元、第一、第二和第三开关单元、第一和第二存储单元以及充电控制单元的具体结构，但是本领域技术人员可以明了，这些单元可以采用其他结构。图4仅示出了其中的一个示例。
图10示出了根据本公开实施例的像素驱动方法的流程图。该方法应用于根据本公开实施例的像素驱动电路。如图所示，该驱动方法包括：首先，在S1010，通过所述第一级扫描信号线提供第一级扫描信号，同时通过发光控制信号线提供发光控制信号，使得像素驱动电路进入第一操作阶段；然后在S1020，在第一级扫描信号关闭之前或同时，关闭发光控制信号，使得像素驱动电路进入第二操作阶段；然后在第二级扫描信号线提供第二级扫描信号；在S1030，在第三级扫描信号线提供第三级扫描信号，使得像素驱动电路进入第三操作阶段；然后在S1040，在第三级扫描信号关闭时，在发光控制信号线提供发光控制信号，使得像素驱动电路进入驱动阶段。
如图5所示，在第一级扫描信号线提供第一级扫描信号，发光控制信号线提供发光控制信号，此时像素驱动电路进入第一操作阶段。然后，发光控制信号关闭，像素驱动电路进入第二操作阶段的前半段时间段。然后，在第二级扫描信号线提供第二级扫描信号时，即第一级扫描信号关闭时，像素驱动电路进入第二操作阶段的后半段时间段。然后，在第三级扫描信号线提供第三级扫描信号时，像 素驱动电路进入第三操作阶段。最后，在发光控制信号线提供发光控制信号，像素驱动电路进入驱动阶段，驱动发光元件发光。由于存储电容器C1对驱动单元的阈值电压进行补偿，因此驱动单元向发光元件提供的驱动电流与驱动单元的阈值电压无关。可以调整发光控制信号相对于第一级扫描信号关闭的相对偏移，从而确保第二操作阶段(即阈值电压补偿阶段)的时间长度，使得存储电容器C1有充足的时间通过自放电获得数据电压和驱动单元的阈值电压。
更具体地，结合图4所示的像素驱动电路，在应用图5所示的操作时序时，在像素驱动电路的第一操作阶段，所述第一晶体管、第四晶体管和第五晶体管导通，第二晶体管和第三晶体管截止。在像素驱动电路的第二操作阶段，所述第三晶体管导通，所述第一晶体管、第二晶体管截止，第四晶体管和第五晶体管在第二操作阶段的前半段导通，在第二操作阶段的后半段截止。在像素驱动电路的第三操作阶段，所述第二晶体管导通，所述第一晶体管、第三晶体管、第四晶体管和第五晶体管截止。在像素驱动电路的驱动阶段，所述第一晶体管导通，所述第二晶体管、第三晶体管、第四晶体管和第五晶体管均截止。
本公开还提供一种显示装置，包括上述的像素驱动电路，所述像素电路已在上述实施例中做了详细的说明，此处不再赘述。
应当注意的是，在以上的描述中，仅以示例的方式，示出了本公开的技术方案，但并不意味着本公开局限于上述步骤和结构。在可能的情形下，可以根据需要对步骤和结构进行调整和取舍。因此，某些步骤和单元并非实施本公开的总体发明思想所必需的元素。因此，本公开所必需的技术特征仅受限于能够实现本公开的总体发明思想的最低要求，而不受以上具体实例的限制。
至此已经结合优选实施例对本公开进行了描述。应该理解，本领域技术人员在不脱离本公开的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本公开的范围不局限于上述特定实施例，而应由所附权利要求所限定。

Claims (20)

  1. 一种像素驱动电路，用于对发光元件进行驱动，所述像素驱动电路包括：
    发光控制信号线，用于提供发光控制信号；
    驱动单元，其输入端连接到第一中间节点，控制端连接到第三中间节点，输出端连接到所述发光元件的一端，所述发光元件的另一端连接到第一电源线；
    第一开关单元，其输入端连接到第二电源线，控制端连接到发光控制信号线，输出端连接到第一中间节点；
    第二开关单元，其输入端连接到参考信号线，控制端连接到第二级扫描信号线，输出端连接到第二中间节点；
    第一存储单元，其第一端连接到所述第一中间节点，第二端连接到第二中间节点；
    第二存储单元，其第一端连接到所述第二中间节点，第二端连接到第三中间节点；
    第三开关单元，其输入端连接到所述第三中间节点，控制端连接到第三级扫描信号线，输出端连接到所述第二中间节点；
    充电控制单元，其第一输入端连接到参考信号线，第二输入端连接到数据线，控制端连接到第一级扫描信号线，第一输出端连接到第二中间节点，第二输出端连接到第三中间节点；
    其中，在像素驱动电路的第一操作阶段，
    在发光控制信号线输出的发光控制信号的控制下，第一开关单元导通第二电源线和第一中间节点，
    在第一级扫描信号线输出的第一级扫描信号的控制下，所述充电控制单元导通参考信号线和第二中间节点，由此对连接于第一中间节点和第二中间节点的第一存储单元进行充电，所述充电控制单元还导通数据线和第三中间节点，由此对连接于第三中间节点和第二中间节点的第二存储单元进行充电；
    在像素驱动电路的第二操作阶段，
    在第二级扫描信号线输出的第二级扫描信号的控制下，所述第二开 关单元导通所述参考信号线和第二中间节点，保持所述第二存储单元上的电压，从而稳定所述驱动单元的控制端的电压，同时所述发光控制信号使所述第一开关单元断开，所述第一存储单元通过所述驱动单元进行自放电，以自放电的方式存储数据电压和驱动单元阈值电压；
    在像素驱动电路的第三操作阶段，
    在第三级扫描信号线输出的第三级扫描信号的控制下，第三开关单元导通第三中间节点和第二中间节点，使得所述第二存储单元放电；
    在像素驱动电路的驱动阶段，
    在发光控制信号线输出的发光控制信号的控制下，第一开关单元导通第二电源线和第一中间节点，使得驱动单元的控制端和输入端的电压差等于所述第一存储单元的电压，从而对所述驱动单元的阈值电压进行补偿，使得所述驱动单元向所述发光元件提供的驱动电流与其阈值电压无关。
  2. 根据权利要求1所述的像素驱动电路，其中，所述驱动单元包括驱动晶体管，所述驱动晶体管的栅极与所述第三中间节点相连，第一电极与所述发光元件的所述一端相连，第二电极与所述第一中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
  3. 根据权利要求1所述的像素驱动电路，其中，所述第一开关单元包括第一晶体管，所述第一晶体管的第一电极与第二电源线相连，栅极与发光控制信号线相连，第二电极与第一中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
  4. 根据权利要求1所述的像素驱动电路，其中，所述第二开关单元包括第三晶体管，所述第三晶体管的第一电极与参考信号线相连，栅极与第二级扫描信号线相连，第二电极与第二中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
  5. 根据权利要求1所述的像素驱动电路，其中所述第一存储单元包括第一存储电容器，连接于所述第一中间节点和所述第二中间节点之间。
  6. 根据权利要求1所述的像素驱动电路，其中，所述第二存储单元包括第二存储电容器，连接于所述第二中间节点和所述第三中间节点之间。
  7. 根据权利要求1所述的像素驱动电路，其中，所述第三开关单元包括第二晶 体管，所述第二晶体管的第一电极与所述第三中间节点相连，栅极与第三级扫描信号线相连，第二电极与所述第二中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
  8. 根据权利要求1所述的像素驱动电路，其中，所述充电控制单元包括第四晶体管和第五晶体管，所述第四晶体管和第五晶体管的栅极均与第一级扫描信号线相连，所述第四晶体管的第一电极与参考信号线相连，第二电极与第二中间节点相连，所述第五晶体管的第一电极与数据线相连，第二电极与第三中间节点相连，所述第一电极是源极和漏极中的一个电极，所述第二电极是源极和漏极中的另一个电极。
  9. 根据权利要求2所述的像素驱动电路，其中，所述驱动晶体管为P型薄膜晶体管。
  10. 根据权利要求3所述的像素驱动电路，其中，所述第一晶体管为P型薄膜晶体管。
  11. 根据权利要求4所述的像素驱动电路，其中，所述第三晶体管为P型薄膜晶体管。
  12. 根据权利要求7所述的像素驱动电路，其中，所述第二晶体管为P型薄膜晶体管。
  13. 根据权利要求8所述的像素驱动电路，其中，所述第四晶体管和第五晶体管为P型薄膜晶体管。
  14. 一种像素驱动方法，应用于根据权利要求1-13之一所述的像素驱动电路，所述像素驱动方法包括：
    通过所述第一级扫描信号线提供第一级扫描信号，同时通过所述发光控制信号线提供发光控制信号并在数据线提供数据信号，使得像素驱动电路进入第一操作阶段；
    在第一级扫描信号关闭之前或同时，关闭所述发光控制信号，使得所述像素驱动电路进入第二操作阶段；
    通过所述第二级扫描信号线提供所述第二级扫描信号；
    通过所述第三级扫描信号线提供所述第三级扫描信号，使得所述像素驱动电路进入第三操作阶段；以及
    在所述第三极扫描信号关闭时通过所述发光控制信号线提供所述发光控制信号，使得所述像素驱动电路进入驱动阶段。
  15. 根据权利要求14所述的像素驱动方法，其中，可调整所述发光控制信号的关闭时间与所述第一级扫描信号的关闭时间的相对偏移，以缩短所述第一操作阶段的持续时间。
  16. 根据权利要求14所述的像素驱动方法，其中，在像素驱动电路的第一操作阶段，所述第一开关单元、所述充电控制单元导通，所述第二开关单元和所述第三开关单元断开。
  17. 根据权利要求14所述的像素驱动方法，其中，在像素驱动电路的第二操作阶段，所述第二开关单元导通，所述第一开关单元、所述第三开关单元均断开，所述充电控制单元在所述第一级扫描信号关闭时断开。
  18. 根据权利要求14所述的像素驱动方法，其中，在像素驱动电路的第三操作阶段，所述第三开关单元，所述第一开关单元、所述第二开关单元、所述充电控制单元均断开。
  19. 根据权利要求14所述的像素驱动方法，其中，在像素驱动电路的驱动阶段，所述第一开关单元导通，所述第二开关单元、所述第三开关单元、所述充电控制单元均断开。
  20. 一种显示装置，其特征在于，包括如权利要求1至13任一所述的像素驱动电路。
PCT/CN2015/079901 2014-12-05 2015-05-27 一种像素驱动电路、像素驱动方法和显示装置 WO2016086626A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/892,188 US9691328B2 (en) 2014-12-05 2015-05-27 Pixel driving circuit, pixel driving method and display apparatus
EP15793665.9A EP3048604B1 (en) 2014-12-05 2015-05-27 Pixel driving circuit, pixel driving method and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410738074.5A CN104409043B (zh) 2014-12-05 2014-12-05 像素驱动电路和像素驱动方法、显示装置
CN201410738074.5 2014-12-05

Publications (1)

Publication Number Publication Date
WO2016086626A1 true WO2016086626A1 (zh) 2016-06-09

Family

ID=52646667

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/079901 WO2016086626A1 (zh) 2014-12-05 2015-05-27 一种像素驱动电路、像素驱动方法和显示装置

Country Status (4)

Country Link
US (1) US9691328B2 (zh)
EP (1) EP3048604B1 (zh)
CN (1) CN104409043B (zh)
WO (1) WO2016086626A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409043B (zh) * 2014-12-05 2016-08-24 京东方科技集团股份有限公司 像素驱动电路和像素驱动方法、显示装置
CN106205491B (zh) * 2016-07-11 2018-09-11 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
CN106251810B (zh) * 2016-08-19 2019-09-27 深圳市华星光电技术有限公司 Amoled显示屏驱动方法、驱动电路及显示装置
US10789891B2 (en) 2016-09-19 2020-09-29 Boe Technology Group Co., Ltd. Pixel circuit, driving method thereof, display substrate and display apparatus
CN106128366B (zh) * 2016-09-19 2018-10-30 成都京东方光电科技有限公司 像素驱动电路及其驱动方法和显示装置
CN107170413B (zh) * 2017-07-26 2019-01-18 江苏集萃有机光电技术研究所有限公司 像素电路及像素电路的驱动方法
TWI639149B (zh) * 2018-03-09 2018-10-21 友達光電股份有限公司 畫素電路
US10475391B2 (en) * 2018-03-26 2019-11-12 Sharp Kabushiki Kaisha TFT pixel threshold voltage compensation circuit with data voltage applied at light-emitting device
CN108630151B (zh) * 2018-05-17 2022-08-26 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板及显示装置
CN109754757B (zh) * 2019-03-28 2020-11-06 京东方科技集团股份有限公司 像素驱动电路、显示装置及像素驱动方法
CN112992055B (zh) * 2021-04-27 2021-07-27 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN114005407A (zh) * 2021-11-02 2022-02-01 武汉天马微电子有限公司 显示面板和显示装置
CN115019729B (zh) * 2022-08-04 2022-11-25 惠科股份有限公司 像素驱动电路、显示面板及其控制方法
CN116013205B (zh) * 2023-02-06 2024-05-24 武汉天马微电子有限公司 一种像素电路、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101609840A (zh) * 2008-06-17 2009-12-23 三星移动显示器株式会社 像素及利用所述像素的有机发光显示装置
CN102651192A (zh) * 2011-06-21 2012-08-29 京东方科技集团股份有限公司 有源矩阵有机发光二极体面板及其驱动电路与方法
CN102708789A (zh) * 2011-12-01 2012-10-03 京东方科技集团股份有限公司 像素单元驱动电路和方法、像素单元以及显示装置
CN102982767A (zh) * 2012-12-10 2013-03-20 京东方科技集团股份有限公司 一种像素单元驱动电路、驱动方法及显示装置
US20140333214A1 (en) * 2013-05-07 2014-11-13 Samsung Display Co., Ltd. Pixel circuit and driving method thereof
CN104409043A (zh) * 2014-12-05 2015-03-11 京东方科技集团股份有限公司 像素驱动电路和像素驱动方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100490622B1 (ko) * 2003-01-21 2005-05-17 삼성에스디아이 주식회사 유기 전계발광 표시장치 및 그 구동방법과 픽셀회로
KR101495359B1 (ko) * 2008-12-22 2015-02-24 엘지디스플레이 주식회사 유기전계발광표시장치와 이의 구동방법
KR101549284B1 (ko) * 2011-11-08 2015-09-02 엘지디스플레이 주식회사 유기발광다이오드 표시장치
CN103489393B (zh) * 2012-06-13 2015-12-16 群康科技(深圳)有限公司 显示器
TWI498873B (zh) * 2013-12-04 2015-09-01 Au Optronics Corp 有機發光二極體電路及其驅動方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101609840A (zh) * 2008-06-17 2009-12-23 三星移动显示器株式会社 像素及利用所述像素的有机发光显示装置
CN102651192A (zh) * 2011-06-21 2012-08-29 京东方科技集团股份有限公司 有源矩阵有机发光二极体面板及其驱动电路与方法
CN102708789A (zh) * 2011-12-01 2012-10-03 京东方科技集团股份有限公司 像素单元驱动电路和方法、像素单元以及显示装置
CN102982767A (zh) * 2012-12-10 2013-03-20 京东方科技集团股份有限公司 一种像素单元驱动电路、驱动方法及显示装置
US20140333214A1 (en) * 2013-05-07 2014-11-13 Samsung Display Co., Ltd. Pixel circuit and driving method thereof
CN104409043A (zh) * 2014-12-05 2015-03-11 京东方科技集团股份有限公司 像素驱动电路和像素驱动方法、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3048604A4 *

Also Published As

Publication number Publication date
EP3048604A1 (en) 2016-07-27
CN104409043A (zh) 2015-03-11
CN104409043B (zh) 2016-08-24
US20160351126A1 (en) 2016-12-01
EP3048604B1 (en) 2019-07-03
EP3048604A4 (en) 2017-04-26
US9691328B2 (en) 2017-06-27

Similar Documents

Publication Publication Date Title
WO2016086626A1 (zh) 一种像素驱动电路、像素驱动方法和显示装置
WO2016095477A1 (zh) 像素驱动电路、像素驱动方法和显示装置
US10242625B2 (en) Pixel driving circuit, pixel driving method and display apparatus
US10504436B2 (en) Pixel driving circuits, pixel driving methods and display devices
US9390652B2 (en) Organic light emitting display device and driving method thereof
WO2016045261A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
WO2016187990A1 (zh) 像素电路以及像素电路的驱动方法
WO2018076719A1 (zh) 像素驱动电路及其驱动方法、显示面板和显示装置
WO2016173124A1 (zh) 像素电路、其驱动方法及相关装置
WO2018188390A1 (zh) 像素电路及其驱动方法、显示装置
WO2016045283A1 (zh) 像素驱动电路、方法、显示面板和显示装置
WO2017031909A1 (zh) 像素电路及其驱动方法、阵列基板、显示面板及显示装置
US9905166B2 (en) Pixel driving circuit, pixel driving method and display apparatus
WO2015180352A1 (zh) 像素电路及其驱动方法、有机发光显示面板及显示装置
WO2017117940A1 (zh) 像素驱动电路、像素驱动方法、显示面板和显示装置
US20190287461A1 (en) Driving circuit and driving method thereof, and display device
CN107230452A (zh) 一种像素驱动电路及驱动方法
US20190228708A1 (en) Pixel circuit, pixel driving method and display device
WO2016155183A1 (zh) 像素电路、显示装置及其驱动方法
WO2016187991A1 (zh) 像素电路、驱动方法、有机电致发光显示面板及显示装置
WO2016078282A1 (zh) 像素单元驱动电路和方法、像素单元和显示装置
WO2015014025A1 (zh) 像素驱动电路及其驱动方法、显示装置
US20180247595A1 (en) Pixel driving circuit, driving method for same, and display apparatus
CN205451748U (zh) 像素驱动电路和显示装置
CN204315211U (zh) 像素驱动电路和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14892188

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2015793665

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2015793665

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15793665

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE