WO2016084998A1 - 레이크 수신기 및 그 수신 방법 - Google Patents
레이크 수신기 및 그 수신 방법 Download PDFInfo
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- WO2016084998A1 WO2016084998A1 PCT/KR2014/011461 KR2014011461W WO2016084998A1 WO 2016084998 A1 WO2016084998 A1 WO 2016084998A1 KR 2014011461 W KR2014011461 W KR 2014011461W WO 2016084998 A1 WO2016084998 A1 WO 2016084998A1
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- time
- power metric
- late
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- oscillator
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
- H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/1081—Reduction of multipath noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
- H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
- H04B1/7117—Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
Definitions
- the present invention relates to a terminal for mobile communication.
- 1 shows a mobile communication system.
- a wireless communication system includes at least one base station (BS) 20.
- Each base station 20 provides a service to a terminal 10 in a particular geographic area (generally called a cell) 20a, 20b, 20c.
- the terminal 100 has evolved from a mobile phone that was capable of only a traditional call, to a smart phone that can improve a user experience through various functions.
- MTC Machine Type Communication
- IoT Internet of Things
- devices for MTC or IoT has a specificity that the amount of transmission data is small and the up / down link data transmission and reception occurs occasionally.
- WCDMA the third generation of mobile communication
- MTC or IoT the third generation of mobile communication
- Rake reception function means that when signals transmitted from a base station arrive at a receiver with a time difference (ie, phase difference) due to fading caused by multipaths, two received signals with the time difference are received. It is a function that can be separated. Therefore, time synchronization is important for the rake reception function. If the timing is not correct and a timing offset occurs, performance deterioration occurs.
- the WCDMA receiver performs over sampling to reduce the timing offset.
- the oversampling rate can be doubled again to 8 times oversampling, but the complexity is greatly increased. Also, even with 8x oversampling, timing offsets as small as 1 / 16th of a chip still cannot be overcome.
- the present disclosure aims to solve the above-mentioned problem.
- one disclosure of the present specification proposes a receiver structure that can reduce the timing offset without oversampling.
- the receiver structure according to the present disclosure can control the oscillator using information on timing positions, thereby preventing performance degradation due to timing offset.
- a rake receiver includes an oscillator; A radio frequency integrated circuit (RFIC) for processing analog signals received after a multipath according to a sampling clock and a carrier frequency clock by the oscillator; After assigning a finger to each signal for the signals output from the RFIC and decoding the signal, information about a timing position through time tracking, a power metric sampled at an on-time, And a rake processing unit for outputting the power metric difference between the half- chip early- (Early-time) and the half-chip late (late-time); And adjusting the sampling clock of the oscillator according to a ratio of a power metric difference between the half-chip early-time and half-chip late-late with respect to the power metric sampled at the on-time. It may include an AFC (Auto Frequency Controller) for calculating the ( ⁇ ) value.
- RFIC radio frequency integrated circuit
- a rake receiving method comprises the steps of: processing analog signals received after undergoing multiple paths according to a sampling clock and a carrier frequency clock by an oscillator; Time tracking using the signals provides information on timing position, power metrics sampled at on-time, and early- and late-late late-times. Outputting a power metric difference therebetween; Calculating a beta value according to a ratio of a power metric difference between the half-chip early-time and the half-chip late-late with respect to the power metric sampled at the on-time; ; And adjusting the sampling clock of the oscillator according to the beta ( ⁇ ) value.
- timing offset can be reduced without oversampling, complexity can be reduced compared to using oversampling.
- the disclosure of the present specification by controlling the oscillator using information on timing positions, performance degradation due to timing offset can be prevented.
- 1 shows a mobile communication system.
- FIG. 2 shows a structure of a general RF unit.
- FIG 3 shows a structure of an RF unit according to one disclosure of the present specification.
- FIG. 4 shows a detailed structure of the rake processing unit of FIG.
- FIG. 5 shows an example of the output of the filter shown in FIG. 4.
- FIG. 6 is a block diagram illustrating a wireless communication system in which an embodiment of the present invention is implemented.
- first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.
- first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
- the wireless device to be used may be fixed or mobile, and may include a terminal, a mobile terminal (MT), a user equipment (UE), a mobile equipment (ME), a mobile station (MS), a user terminal (UT), It may be called in other terms such as subscriber station (SS), handheld device, and access terminal (AT).
- MT mobile terminal
- UE user equipment
- ME mobile equipment
- MS mobile station
- UT user terminal
- SS subscriber station
- AT access terminal
- base station refers to a fixed station (fixed station) to communicate with the wireless device, in other terms such as eNB (evolved-NodeB), BTS (Base Transceiver System), Access Point (Access Point) Can be called.
- eNB evolved-NodeB
- BTS Base Transceiver System
- Access Point Access Point
- FIG. 2 shows a structure of a general RF unit.
- a radio frequency integrated circuit (RFIC) 11, an oscillator 12, a rake processor 13, and an auto frequency controller (AFC) 15 may be included.
- the AFC 15 includes an accumulator 15-1, a phase-to-frequency converter 15-2, an alpha ( ⁇ ) processor 15-7, an adder 15-8, and a delay unit Z -1 . (15-9).
- the AFC 15 measures the frequency difference with the transmitter and then controls the oscillator 12 in a direction to reduce the frequency difference.
- the inventor of the present patent applies an offset value that can utilize the aforementioned phenomenon to control the oscillator, thereby improving the timing position in the direction to obtain the maximum SNR.
- the oscillator is controlled to obtain the maximum SNR of the timing position, thereby minimizing performance degradation due to the timing offset. do.
- FIG. 3 a description will be given with reference to FIG. 3.
- FIG. 3 illustrates a structure of an RF unit according to one disclosure of the present specification
- FIG. 4 illustrates a detailed structure of the rake processing unit of FIG. 3.
- a rake receiver includes a radio frequency integrated circuit (RFIC) 131, an oscillator 132, a rake processor 133, and a rake receiver. It may include an Auto Frequency Controller (AFC) 135.
- RFIC radio frequency integrated circuit
- AFC Auto Frequency Controller
- the RFIC 131 receives analog signals that have undergone multiple paths. To this end, the RFIC 131 obtains a sampling clock and a carrier frequency clock from the oscillator 132.
- the rake processor 133 assigns a finger to each signal from signals received through a multipath, and digitally decodes each signal. Through this finger assignment operation, the rake processing unit 133 estimates a phase metric and transfers it to the AFC. In addition, the rake processing unit 133 performs time tracking to obtain information on a timing position.
- the AFC 135 measures the frequency difference with the transmitter and then controls the oscillator 132 in a direction to reduce the frequency difference.
- the AFC includes an accumulator 135-1, a phase-to-frequency converter 135-2, a beta ( ⁇ ) processor 135-4, an alpha ( ⁇ ) processor 135-7, and an adder 15-8. And a delay unit Z -1 135-9.
- the accumulation unit 135-1 accumulates the phase metric transmitted from the rake processing unit 133 for a predetermined period of time.
- the phase-to-frequency converter 135-2 calculates a frequency offset using the accumulated phase metric. To this end, the phase-to-frequency converter 135-2 may use an arc tangent function.
- the beta ( ⁇ ) processing unit 135-4 obtains information on the timing position from the rake processing unit 133, and then obtains beta ( ⁇ ) matching the timing position information.
- the rake processing unit 133 may be improved as shown in FIG.
- the rake processing unit 133 includes a finger unit 133-1, a plurality of down sampling units 133-2, and a plurality of descrambling and despreading units 133-. 3), a plurality of matched filter units 133-4, and the like.
- the plurality of down sampling units 133-2 may include a time-point down-sampling unit for sampling at a point in time, a half-chip fast down sampling unit for sampling at a half-chip fast time point, and a half-chip for sampling at a half-chip late time point. It includes a late down sampling section.
- the rake processing unit 133 calculates the ratio according to Equation 1 below.
- M ontime is a metric at the on-time.
- M early is a metric half-chip early compared to a point in time
- M late is a metric half-chip slower than a point in time.
- the rake processing unit 133 calculates information on the timing position based on the difference between the power at the half time earlier than the power at the right time and the power difference at the half time later. ⁇ ) to the processing unit 135-4.
- the structure of the rake processor 133 shown in FIG. 4 is exemplary, and if there is a separate timing tracker, the structure of the rake processor 133 may not be improved as shown in FIG. 4.
- the beta ( ⁇ ) processor 135-4 when the beta ( ⁇ ) processor 135-4 obtains information on the timing position from the rake processor 133, the beta ( ⁇ ) processor 135-4 may be matched with the timing position information. Find ⁇ ). Subsequently, the beta ( ⁇ ) processor 135-4 compensates the frequency offset by adding the beta ( ⁇ ) to the frequency offset obtained from the phase-to-frequency converter 135-2.
- the alpha processor ⁇ 135-8 is an alpha ⁇ that is a scaling factor with respect to the frequency offset compensation. Multiply by a lot.
- the adder 135-8 adds an output of the delay unit Z- 1 135-9 and an output of the alpha ( ⁇ ) processor 135-8 to output the result to the oscillator 132.
- the AFC controls the oscillator 132 to minimize the timing offset, thereby minimizing performance degradation due to the timing offset.
- FIG. 5 shows an example of the output of the filter shown in FIG . 4 .
- the output power of the matched filter unit 133-3 may be as shown in FIG. 5.
- the x-axis is a section of one chip and a unit is 1/64 chips.
- the value of the timing offset and the M EL_Diff / M Ontime ratio is one-to-one mapping, and the values of the M EL_Diff / M Ontime ratio for the specific timing offset are shown in Table 1 below.
- the current timing position is 1/16 chips ahead of the position representing the maximum SNR. Since the sampling clock frequency is lowered, the timing position flows backward.
- the beta ( ⁇ ) processing unit 135-4 can obtain the value of the beta ( ⁇ ) according to the following equation.
- the x value is a constant for determining the speed of moving to the timing position representing the maximum SNR.
- the auto-correlation characteristic is different according to the scrambling code so that even if the actual frequency offset is 0, the timing offset is measured as if the frequency offset exists by ICI.
- a positive frequency offset may be measured, and a negative frequency offset may be measured.
- the sampling clock frequency is controlled by the AFC 135 so that the sampling clock frequency is lowered.
- the AFC 135 moves to a timing position indicating the maximum SNR, but the latter case moves away from the timing position indicating the maximum SNR.
- the value x must be determined to be larger than the maximum value at which the frequency offset occurs in a direction away from the timing position representing the maximum SNR. This makes it possible to move to the timing position representing the maximum SNR for all scrambling codes.
- the frequency offset measured by the auto-correlation characteristic of the scrambling code is 20 Hz
- the constant x value must be greater than 48.2 because M EL_diff / M Ontime value is 0.4150 at 1/8 chip offset. That is, in the above example, when the x value is set larger than 48.2, the timing position is moved on-time by the oscillator 132.
- Embodiments of the present invention described so far may be implemented through various means.
- embodiments of the present invention may be implemented by hardware, firmware, software, or a combination thereof. Specifically, it will be described with reference to the drawings.
- FIG. 6 is a block diagram illustrating a wireless communication system in which an embodiment of the present invention is implemented.
- the base station 200 includes a processor 210, a memory 220, and an RF unit 230.
- the memory 220 is connected to the processor 210 and stores various information for driving the processor 210.
- the RF unit 230 is connected to the processor 210 to transmit and / or receive a radio signal.
- the processor 210 implements the proposed functions, processes and / or methods. In the above-described embodiment, the operation of the base station may be implemented by the processor 210.
- the wireless device 100 includes a processor 110, a memory 120, and an RF unit 130.
- the memory 120 is connected to the processor 110 and stores various information for driving the processor 110.
- the RF unit 130 is connected to the processor 110 and transmits and / or receives a radio signal.
- Processor 119 implements the proposed functions, processes, and / or methods. In the above-described embodiment, the operation of the wireless device may be implemented by the processor 110.
- the processor may include application-specific integrated circuits (ASICs), other chipsets, logic circuits, and / or data processing devices.
- the memory may include read-only memory (ROM), random access memory (RAM), flash memory, memory card, storage medium and / or other storage device.
- the RF unit may include a baseband circuit for processing a radio signal.
- the above-described technique may be implemented as a module (process, function, etc.) for performing the above-described function.
- the module may be stored in memory and executed by a processor.
- the memory may be internal or external to the processor and may be coupled to the processor by various well known means.
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- Computer Networks & Wireless Communication (AREA)
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- Circuits Of Receivers In General (AREA)
Abstract
Description
샘플 오프셋 | SRRC 출력 파워 | 샘플 오프셋 | SRRC 출력 파워 | 샘플 오프셋 | SRRC 출력 파워 | 샘플 오프셋 | SRRC 출력 파워 |
0 | 1 | 8/32 | 0.8061 | 16/32 | 0.3965 | 24/32 | 0.0857 |
1/32 | 0.9967 | 9/32 | 0.7601 | 17/32 | 0.3468 | 25/32 | 0.0633 |
2/32 | 0.9869 | 10/32 | 0.7111 | 18/32 | 0.2996 | 26/32 | 0.0447 |
3/32 | 0.9707 | 11/32 | 0.6600 | 19/32 | 0.2552 | 27/32 | 0.0297 |
4/32 | 0.9483 | 12/32 | 0.6074 | 20/32 | 0.2139 | 28/32 | 0.0181 |
5/32 | 0.9202 | 13/32 | 0.5541 | 21/32 | 0.1762 | 29/32 | 0.0097 |
6/32 | 0.8868 | 14/32 | 0.5007 | 22/32 | 0.1422 | 30/32 | 0.0041 |
7/32 | 0.8486 | 15/32 | 0.4479 | 23/32 | 0.1120 | 31/32 | 0.0010 |
MEL_Diff/MOntime비율 | ||||||||
타이밍 오프셋 | 1/16 칩 빠름 | 1/16 칩 늦음 | 1/8 칩 빠름 | 1/18 칩 늦음 | 1/4 칩 빠름 | 1/4 칩 늦음 | 1/2 칩 빠름 | 1/2 칩 늦음 |
Ratio | -0.2038 | 0.2038 | -0.4150 | 0.4150 | -0.8937 | 0.8937 | -2.5221 | 2.5221 |
Claims (10)
- 오실레이터와;상기 오실레이터에 의한 샘플링 클럭 및 반송파 주파수 클럭에 따라, 다중 경로를 겪은 후 수신되는 아날로그 신호들을 처리하는 RFIC(Radio Frequency Integrated Circuit)와;상기 RFIC로부터 출력되는 신호들에 대해서 경로 별로 핑거(finger)를 할당한 뒤 디코딩하되, 시간 추적을 통한 타이밍 위치(timing position)에 대한 정보와, 정시점(On-time)에서 샘플링된 파워 메트릭, 그리고 반칩 이른 시점(Early-time)과 반칩 늦은 시점(late-time) 간의 파워 메트릭 차이를 출력하는 레이크 처리부와;상기 정시점(On-time)에서 샘플링된 파워 메트릭 대비 상기 반칩 이른 시점(Early-time)과 반칩 늦은 시점(late-time) 간의 파워 메트릭 차이의 비율에 따라 상기 오실레이터의 상기 샘플링 클럭을 조정할 베타(β) 값을 산출하는 AFC(Auto Frequency Controller)를 포함하는 것을 특징으로 하는 레이크 수신기.
- 제2항에 있어서, 상기 오실레이터의 샘플링 클럭을 조정하기 위한 상기 베타(β) 값은최대 SNR을 나타내는 정시점(On-time)에서 샘플링이 수행되게끔 결정되는 것을 특징으로 하는 레이크 수신기.
- 제4항에 있어서, 상기 AFC는실제 주파수 오프셋은 0이지만, 스크램블링 코드에 따라 자기 상관이 달라져 타이밍 오프셋에 따라 음(0)의 주파수 오프셋이 존재하는 것으로 확인되는 경우, 상기 x의 값을 더 크게 설정하는 것을 특징으로 하는 레이크 수신기.
- 오실레이터에 의한 샘플링 클럭 및 반송파 주파수 클럭에 따라, 다중 경로를 겪은 후 수신되는 아날로그 신호들을 처리하는 단계와;상기 신호들을 이용한 시간 추적을 통해 타이밍 위치(timing position)에 대한 정보와, 정시점(On-time)에서 샘플링된 파워 메트릭, 그리고 반칩 이른 시점(Early-time)과 반칩 늦은 시점(late-time) 간의 파워 메트릭 차이를 출력하는 단계와;상기 정시점(On-time)에서 샘플링된 파워 메트릭 대비 상기 반칩 이른 시점(Early-time)과 반칩 늦은 시점(late-time) 간의 파워 메트릭 차이의 비율에 따라 베타(β) 값을 산출하는 단계와;상기 베타(β) 값에 따라 상기 오실레이터의 상기 샘플링 클럭을 조정하는 단계를 포함하는 것을 특징으로 하는 레이크 수신 방법.
- 제7항에 있어서, 상기 오실레이터의 샘플링 클럭을 조정하기 위한 상기 베타(β) 값은최대 SNR을 나타내는 정시점(On-time)에서 샘플링이 수행되게끔 결정되는 것을 특징으로 하는 레이크 수신 방법.
- 제9항에 있어서,실제 주파수 오프셋은 0이지만, 스크램블링 코드에 따라 자기 상관이 달라져 타이밍 오프셋에 따라 음(-)의 주파수 오프셋이 존재하는 것으로 확인되는 경우, 상기 x의 값을 더 크게 설정되는 것을 특징으로 하는 레이크 수신 방법.
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KR1020167034960A KR101869638B1 (ko) | 2014-11-27 | 2014-11-27 | 레이크 수신기 및 그 수신 방법 |
EP14906838.9A EP3226427B1 (en) | 2014-11-27 | 2014-11-27 | Rake receiver and receiving method thereof |
US15/322,706 US9793946B2 (en) | 2014-11-27 | 2014-11-27 | Rake receiver and receiving method thereof |
PCT/KR2014/011461 WO2016084998A1 (ko) | 2014-11-27 | 2014-11-27 | 레이크 수신기 및 그 수신 방법 |
JP2016573567A JP6277291B2 (ja) | 2014-11-27 | 2014-11-27 | レーク受信機及びその受信方法 |
CN201480080308.XA CN106664117B (zh) | 2014-11-27 | 2014-11-27 | 耙式接收机及其接收方法 |
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- 2014-11-27 JP JP2016573567A patent/JP6277291B2/ja active Active
- 2014-11-27 US US15/322,706 patent/US9793946B2/en active Active
- 2014-11-27 KR KR1020167034960A patent/KR101869638B1/ko active IP Right Grant
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US20170155422A1 (en) | 2017-06-01 |
EP3226427B1 (en) | 2019-06-26 |
KR20170008791A (ko) | 2017-01-24 |
EP3226427A4 (en) | 2018-08-01 |
JP2017525212A (ja) | 2017-08-31 |
EP3226427A1 (en) | 2017-10-04 |
US9793946B2 (en) | 2017-10-17 |
JP6277291B2 (ja) | 2018-02-07 |
CN106664117A (zh) | 2017-05-10 |
CN106664117B (zh) | 2019-06-14 |
KR101869638B1 (ko) | 2018-06-20 |
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