WO2016080584A1 - Mit device having buffer layer and passivation thin film - Google Patents

Mit device having buffer layer and passivation thin film Download PDF

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Publication number
WO2016080584A1
WO2016080584A1 PCT/KR2014/012548 KR2014012548W WO2016080584A1 WO 2016080584 A1 WO2016080584 A1 WO 2016080584A1 KR 2014012548 W KR2014012548 W KR 2014012548W WO 2016080584 A1 WO2016080584 A1 WO 2016080584A1
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thin film
mit
buffer layer
passivation
mit device
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PCT/KR2014/012548
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French (fr)
Korean (ko)
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이동채
이수영
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주식회사 모브릭
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Priority claimed from KR1020140160655A external-priority patent/KR101684643B1/en
Priority claimed from KR1020140179228A external-priority patent/KR20160071720A/en
Application filed by 주식회사 모브릭 filed Critical 주식회사 모브릭
Publication of WO2016080584A1 publication Critical patent/WO2016080584A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention relates to an MIT device having a buffer layer and a passivation thin film, and more particularly, to fabricate an MIT device after depositing a buffer layer on a substrate, thereby making it possible to manufacture an MIT device having excellent stability and increasing a transition temperature.
  • the present invention relates to an MIT device having a buffer layer and a passivation thin film capable of forming a passivation thin film for preventing a change in characteristics of the MIT thin film due to high temperature generated during the deposition of the passivation thin film and plasma and dry etching processes.
  • MIT Metal-Insulator Transition
  • the characteristics of the MIT device vary depending on the substrate, and the substrate has excellent MIT transition characteristics, which can be identified by the change in resistance at the transition temperature or the transition voltage after the deposition of the MIT thin film, and the heat treatment at high temperature. Because of the advantages that the properties of the device appears stably, a sapphire substrate made of single crystal aluminum oxide (Al 2 O 3) is widely used.
  • the sapphire substrate is melted to a high-purity (99.99%, 4N grade or more) of alumina (Al2O3) powder at a high temperature of more than 2300C and then cooled slowly to harden to produce an ingot, and then sliced to produce a wafer in a large diameter ingot. Since it is difficult to grow, the large area of the substrate is difficult and expensive.
  • alumina Al2O3
  • the sapphire substrate has a Mohs hardness value of 9, it is difficult to process because it is the hardest material after diamond in nature.
  • a silicon on insulator (SOI) substrate which is a substrate on which SiO 2 is deposited or a thermal oxide film is grown on a silicon substrate, is used.
  • the MIT device that experiences the MIT phenomenon according to the temperature, when a constant voltage is applied, when the temperature around the device rises above the threshold temperature, the MIT phenomenon occurs, a large current flows through the MIT device. However, even when the ambient temperature falls below the critical temperature, the MIT device self-heating phenomenon may appear without flowing such a large current. In order to reduce the occurrence frequency of the MIT device self-heating phenomenon, it is desirable to increase the transition temperature of the MIT device.
  • semiconductor devices such as MIT devices are exposed to channels during the process, and due to the incomplete molecular bonding structure on the exposed surface, charge-charged ions floating in the air can stick to the surface, thereby changing the electrical characteristics of the device. And the lifetime of the device is also shortened.
  • a passivation process is necessary to block the exposed surface and the ions floating in the air in order to prevent such a change in the characteristics of the device and increase the life of the device.
  • the conventional passivation process uses a method of depositing a dielectric thin film such as an oxide or nitride thin film by plasma enhanced chemical vapor deposition (PECVD) or sputtering. Since the dielectric thin film deposited in this manner cannot be selectively formed, there is a need for a process of removing an unnecessary portion through an etching process after pattern formation. In the deposition and etching process, device characteristics are deteriorated by a few gas components injected with the plasma, and expensive equipment for depositing and etching the dielectric thin film is required.
  • PECVD plasma enhanced chemical vapor deposition
  • the present invention has been made to solve the above problems is an object of the present invention to provide a structure and manufacturing method of the MIT device showing a stable MIT characteristics even during heat treatment.
  • the MIT device having a buffer layer and a passivation thin film according to the present invention includes a silicon substrate and a thin film having a threshold point at which characteristics and a buffer layer deposited on the substrate change.
  • the thin film having the critical point is an MIT thin film that causes a metal-insulator transition (MIT) phenomenon at a critical temperature determined by the material.
  • MIT metal-insulator transition
  • the passivation thin film made of a photoreactive polymer on the thin film having the critical point is characterized in that it further comprises.
  • the photoreactive polymer is characterized in that the photoreactive polyimide.
  • the MIT thin film is characterized in that the pattern is formed.
  • the buffer layer is characterized in that the aluminum nitride (AlN).
  • the MIT thin film is characterized in that it comprises at least one of the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO.
  • An MIT device having a buffer layer and a passivation thin film includes cleaning a silicon substrate, depositing an AlN buffer layer on one side of the substrate, and depositing an MIT thin film on the buffer layer. .
  • the depositing of the buffer layer may include any one of sputtering, evaporation, e-beam evaporation, chemical vapor deposition, and pulsed laser deposition. It is characterized by depositing in a method.
  • the MIT thin film is characterized in that it comprises at least one of the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO.
  • the step of depositing the MIT thin film physical vapor deposition (PVD, physical vapor deposition) such as sputtering, evaporation, e-beam evaporation, laser deposition (PLD, Pulsed Lase Deposition) Deposition) or chemical vapor deposition (CVD) such as plasma-enhanced CVD (PECVD), atmospheric pressure CVD (APCVP), low pressure CVD (LPCVD), or high density plasma CVD (HDPCVD). It is characterized by depositing using.
  • PVD physical vapor deposition
  • PVD physical vapor deposition
  • PVD physical vapor deposition
  • PVD physical vapor deposition
  • PLD Pulsed Lase Deposition
  • CVD chemical vapor deposition
  • PECVD plasma-enhanced CVD
  • APCVP atmospheric pressure CVD
  • LPCVD low pressure CVD
  • HDPCVD high density plasma CVD
  • the method may further include manufacturing a device by forming a pattern on the MIT thin film.
  • the method may further include coating a photoreactive polymer on the MIT thin film, heating and curing the photoreactive polymer to a first temperature, and exposing ultraviolet rays after contacting a mask having a pattern formed thereon with the cured photoreactive polymer thin film. Transferring the pattern to the polymer thin film, developing the patterned polymer thin film to form a pattern on the polymer thin film, and heating and curing the patterned polymer thin film to a second temperature. It is characterized by.
  • the coating of the photoreactive polymer, the transferring of the pattern, and the forming of the pattern may be performed at or below the critical temperature.
  • the photoreactive polymer is characterized in that the photoreactive polyimide.
  • the first temperature is 130 degrees or less, and the second temperature is 50 degrees or more than the first temperature.
  • an MIT device including a buffer layer and a passivation thin film may improve productivity by providing a method for fabricating an MIT device that is easy to process and that can be large in area.
  • the characteristics of the MIT device can be kept constant even after the heat treatment without being sensitive to heat treatment conditions, thereby facilitating quality control of the MIT devices.
  • the MIT transition temperature by fabricating an MIT device that can be used at a higher temperature, the application range of the MIT device can be widened, and the self-heating phenomenon of the MIT device can be prevented.
  • FIG. 1 is a graph showing the characteristics of MIT
  • FIG. 1A is a graph of MIT characteristics according to temperature
  • FIG. 1B is a graph of MIT characteristics according to voltage.
  • FIG. 2 is a structural diagram of an MIT device according to a preferred embodiment of the present invention.
  • FIG. 3 is a manufacturing process diagram of the MIT device according to a preferred embodiment of the present invention.
  • FIG. 4 is a flow diagram of a passivation process of an MIT device in accordance with a preferred embodiment of the present invention.
  • FIG. 5 is a graph measuring the characteristics of the MIT device according to the material of the passivation thin film of the present invention.
  • FIG. 6 is a graph measuring the characteristics of the MIT device according to the material of the substrate and the buffer layer of the present invention.
  • FIG. 7 is a graph illustrating a change in characteristics of a MIT device in which a material of a buffer layer of the present invention is changed with time of heat treatment at 90 degrees.
  • FIG. 8 is a graph illustrating a change in characteristics of a MIT device in which a material of a buffer layer of the present invention is changed at a temperature of 150 ° C.
  • FIG. 8 is a graph illustrating a change in characteristics of a MIT device in which a material of a buffer layer of the present invention is changed at a temperature of 150 ° C.
  • Figure 1 is a graph showing the characteristics of the MIT
  • Figure 1a is a graph showing the MIT characteristics according to the temperature
  • Figure 1b is a graph showing the MIT characteristics according to the voltage.
  • MIT Metal-Insulator Transition
  • the temperature at which the MIT device causes the metal-insulator transition is referred to as the "transition temperature,” and the voltage causing the metal-insulator transition is referred to as the "transition voltage.”
  • the material having MIT characteristics may be formed of a transition metal oxide, a transition alkali-metal oxide, a lanthanide oxide, or the like. Specifically, it may be formed of at least one material selected from the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO.
  • vanadium dioxide is particularly used as the only material having a transition temperature near room temperature. That is, since most application devices such as sensors, semiconductor devices, and electrical devices operate near room temperature, vanadium dioxide having a transition temperature near room temperature can be used as a particularly useful MIT device.
  • the MIT phenomenon of vanadium dioxide was first discovered by Morin in 1959.
  • the resistance change with temperature of vanadium dioxide is insulator (semiconductor) at room temperature as shown in the graph of FIG. It can be seen that it is rapidly reduced to one hundred thousand. This rapid change in resistance at the transition temperature is one of the representative characteristics of the metal-insulator transition.
  • the current characteristics of vanadium dioxide according to the voltage are semiconductor characteristics having a physical property with a bandgap similar to an insulator at low voltage, and are determined based on the state of devices and materials. Threshold voltage) suddenly shows a high current density. Since the current flows in proportion to the voltage, it exhibits the same characteristics as a metal without a band gap.
  • FIG. 2 is a structural diagram of an MIT device according to a preferred embodiment of the present invention.
  • an MIT device having a buffer layer includes a substrate 210, a buffer layer 230, an MIT thin film 250, and a passivation thin film 270.
  • the substrate 210 may be a silicon substrate having good workability, easy to large area, sufficient supply quantity, and easy to supply raw materials.
  • the silicon substrate has excellent thermal conductivity, it is possible to prevent the deterioration of device characteristics due to heat generated inside the device when voltage is applied to drive the device.
  • the buffer layer 230 is formed to solve the insulation and lattice mismatch between the MIT thin film 250 and the substrate 210.
  • the buffer layer 230 may be formed by physical vapor deposition such as sputtering, evaporation, e-beam evaporation, and laser deposition (PLD) on a substrate such as an oxide or nitride.
  • Chemical Vapor Deposition (CVD) such as PVD, Physical Vapor Deposition (PECVD), Plasma-Enhanced CVD (PECVD), Atmospheric Pressure CVD (APCVP), Low Pressure CVD (LPCVD), or High Density Plasma CVD (HDPCVD). Deposition can be made using one method.
  • an oxide such as SiO 2 is deposited and used as the buffer layer 230, but in this case, a disadvantage arises in that the thermal stability of the MIT device is lowered.
  • MIT materials have different characteristics depending on the crystal structure, they are greatly influenced by the substrate. In other words, the larger the lattice mismatch between the substrate and the MIT material, the more unstable the MIT characteristic is.
  • SiO2 is deposited using the above deposition method, a thin film is formed in an amorphous state, which distorts the crystal structure of the MIT material deposited on SiO2, which is an uncontrollable variable during the process, which makes the characteristics of the MIT device stable. It will cause it not to appear.
  • the characteristics of the MIT device can be stably presented.
  • the MIT thin film 250 refers to a thin film on which a material causing an MIT phenomenon, which suddenly changes from an insulating characteristic (semiconductor characteristic) to a metallic characteristic in an environment corresponding to a specific temperature or a specific electric field, is deposited.
  • the MIT material may be formed of a transition metal oxide, a transition alkali-metal oxide, a lanthanide oxide, or the like. Specifically, it may be formed of at least one material selected from the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO.
  • Passivation thin film 270 is formed by coating a photoreactive polymer on a MIT thin film using a wet coating technique such as spin coating and then heating on an oven or hotplate.
  • a dielectric thin film such as an oxide or nitride
  • PECVD chemical vapor deposition method
  • FIG. 3 is a flowchart illustrating a method for fabricating an MIT device according to a preferred embodiment of the present invention.
  • the MIT device includes preparing a substrate (S310), depositing a buffer layer on one side of the substrate prepared in S310 (S320), and depositing a buffer layer on the buffer layer deposited in S320. Depositing a thin film having MIT characteristics (S330), forming a pattern on the MIT thin film deposited in step S330 to manufacture an MIT device (S340), and forming a passivation thin film on the MIT device formed in step S340 In operation S350 and the substrate on which the MIT device is manufactured, the substrate is fabricated through a dicing or sawing process to fabricate an MIT device chip (S360).
  • Step S310 is a process of pre-processing the silicon substrate used as the substrate of the MIT device.
  • Such pretreatment may include substrate polishing and cleaning processes.
  • Polishing is a process that polishes one side of a wafer to make it look like a mirror. That is, it smoothes the surface of the substrate and removes defects such as scratches that may occur on the surface of the substrate during slicing in the ingot.
  • the polishing process may be omitted when the polished wafer is purchased and used.
  • the cleaning process may use a commonly used RCA substrate cleaning process.
  • the RCA cleaning process includes one or more of Standard Cleaning-1 (SC-1), which cleans surface organic materials using a basic solution, and Standard Cleaning-2 (SC-2), which removes surface metal contaminants using an acidic solution. It may include.
  • SC-1 Standard Cleaning-1
  • SC-2 Standard Cleaning-2
  • Step S320 is a step of depositing a buffer layer on one side of the substrate prepared in step S310. Sputtering, evaporation, e-beam evaporation, chemical vapor deposition, and chemical vapor deposition of AlN as the buffer layer Can be deposited using.
  • Step S330 is a process of forming a MIT thin film by depositing a material having an MIT characteristic on the buffer layer deposited in step S320.
  • MIT material is sputtering or evaporating at least one material selected from the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO ), Physical Vapor Deposition (PVD) or Plasma-Enhanced CVD (PECVD), Atmospheric Pressure CVD (LPC), LPCVD (e-beam evaporation), Laser Deposition (PLD, Pulsed Lase Deposition)
  • the deposition may be carried out using any one of Chemical Vapor Deposition (CVD), such as Low Pressure CVD) and High Density Plasma CVD (HDPCVD).
  • CVD Chemical Vapor Deposition
  • HDPCVD High Density
  • step S340 a pattern is formed on the MIT thin film deposited in step S330 by a pattern forming process using a photolithography process to fabricate an MIT device.
  • a passivation film may be further formed on the MIT device formed in operation S340, and then a passivation film pattern may be formed.
  • the passivation film forming process will be described in detail below.
  • Step S360 is a process of cutting a substrate (silicon wafer) on which an MIT device is manufactured to manufacture an MIT device chip.
  • Blade dicing, laser ablation, or stealth dicing (used for wafer dicing) is performed.
  • Stealth Dicing can be used, and other methods can be cut using known techniques, so detailed descriptions are omitted here.
  • FIG. 4 is a flowchart illustrating a process of forming a passivation film on an MIT device, which describes step S350 of FIG. 3 in more detail.
  • the passivation process includes coating the photoreactive polymer on the MIT device fabricated in step S340 (S410), and removing the photoreactive polymer coated in step S410 on an oven or a hot plate.
  • Forming a photoreactive polymer thin film by heating to a temperature (S420), irradiating ultraviolet rays to the photoreactive polymer thin film formed in step S420 (S430), and developing a pattern formed in step S430 (S440).
  • the photoreactive polymer is coated on the MIT thin film using a wet coating technique such as spin coating, and then heated on an oven or hot plate to form a passivation thin film.
  • a dielectric thin film such as an oxide or nitride
  • PECVD chemical vapor deposition method
  • the plasma thin film is formed at a high temperature of 250C or more, which is a temperature higher than the transition temperature. Diffusion occurs in the MIT device characteristics become unstable, the hysteresis effect of the MIT characteristics occurs when the dielectric thin film is formed and cooled to a temperature below the transition temperature.
  • the cause of the MIT phenomenon is not clear until recently, but it has been found that the MIT phenomenon is caused by a phase transition inside the sample at the critical temperature or the threshold voltage (hereinafter referred to as the 'critical point').
  • the phase of the MIT thin film appears differently based on the critical point, which causes the MIT phenomenon to appear. That is, if a diffusion phenomenon occurs at the thin film interface in the phase of the MIT material at or above the critical temperature, the phase transition is different when the temperature is lower than the critical temperature, thereby changing the characteristics of the MIT material.
  • the diffusion phenomenon between the thin films are more likely to occur as the film formation temperature increases, so to solve this problem, after forming the dielectric thin film at a temperature below the transition temperature, the dielectric thin film is fixed on the MIT thin film. It is desirable to minimize the diffusion phenomenon.
  • MIT materials are composed of oxides, and in the conventional technique of forming a passivation thin film with an oxide such as silica on the MIT thin film, deposition between the MIT thin film and the passivation oxide thin film is better by depositing the same oxide series. This causes a greater deterioration of the characteristics of the MIT device.
  • the photoreactive polymer to be applied to the present invention preferably uses a polyimide-based polymer which is less reactive with an oxide, exhibits excellent heat resistance, chemical resistance, and abrasion resistance, and has excellent electrical properties.
  • Polyimide is a high molecular material having an imide ring and is mainly produced by synthesizing using an aromatic anhydride and diamine.
  • a functional ring capable of reacting with light may be substituted and used to implement a function suitable for a specific purpose.
  • Steps S430 and S440 are developed after forming a pattern on the photoreactive polymer thin film formed in step S420 using a photolithography process.
  • the patterned mask is contacted with the MIT device coated with the photoreactive polymer thin film, and then exposed to UV ultraviolet rays to form a pattern using a developer.
  • any one of negative photosensitive characteristics in which an unexposed part is developed and positive photosensitive in which an exposed part is developed may be applied.
  • the type of photoreactive polymer can be selected from among negative or positive photoreactive properties according to the process characteristics according to the process characteristics.
  • a method of forming a pattern of a passivation thin film by using a photolithography process after depositing an oxide such as silica and then forming a pattern by a photolithography process in the present invention, a pattern of the passivation thin film is formed using only a photolithography process.
  • the chemical reaction becomes more active when the temperature is higher or when light energy such as ultraviolet rays are irradiated from the outside. Therefore, in the photolithography process, the step of forming a pattern in which the MIT thin film is in contact with a chemical such as the ultraviolet light exposure step and the developer is preferably performed at a temperature below the critical temperature in order to prevent the MIT characteristic change.
  • Step S450 is a step of heating at a temperature of 50 degrees or more than the temperature heated in step S420 in order to increase the adhesion and hardness of the pattern passivation thin film.
  • the photoreactive polymer thin film having a pattern formed through the step S440 is fixed to have a clear interface on the MIT thin film, that is, to prevent molecular diffusion at the interface. Therefore, even when heated to a high temperature in step S250, molecular diffusion at the interface does not occur, and even when heated to a high temperature, almost no change in characteristics of the MIT device occurs.
  • This temperature is set in a temperature range of 50 degrees or more than the temperature of step S420, it is preferable to set below the deformation temperature of the photoreactive polymer.
  • the first temperature may be cured by heating at 130 ° C. or more at 180 degrees.
  • FIG. 5 is a graph measuring the characteristics of the MIT device according to the material of the passivation thin film of the present invention.
  • Tables 1 to 3 show that the passivation thin film was deposited using MIT thin film with vanadium dioxide and then silica (Table 1), silicon nitride (Table 2) and photoreactive polyimide (Table 3) on the MIT thin film. After the formation, the resistance value of the MIT thin film was measured.
  • Table 1 shows a case in which silica (SiO 2) is formed as a passivation thin film, and the resistance value after passivation decreases from 32% to 38%.
  • [Table 2] is a case where the silicon nitride (Si3N4) is formed as a passivation thin film, it can be seen that the resistance value after passivation is reduced from 32% to 57%.
  • [Table 3] which is the result of passivation using the photoreactive polyimide among the photoreactive polymers according to the present invention, it can be seen that the resistance change of the MIT thin film after passivation is hardly shown as 5% or less.
  • the photoreactive polymer is deposited by a plasma chemical vapor deposition method and then dry etched to form a pattern on the passivation thin film (Table 1 and Table 2).
  • Table 3 it can be seen that the characteristic change of the MIT thin film before the passivation (BF) and after the passivation (AF) appears less.
  • FIG. 6 is a graph measuring characteristics of an MIT device having a different substrate and a buffer layer.
  • Al2O3 sapphire substrate
  • AlN aluminum nitride
  • Si silicon substrate
  • FIG. 6 It is a graph measuring the MIT characteristics when the MIT material is deposited (dotted line) after depositing the buffer layer.
  • the transition temperature when deposited on the sapphire substrate does not show a significant difference, but the transition temperature increases about 10 degrees.
  • FIG. 7 is a graph illustrating the change in resistance of an MIT thin film according to the time of annealing MIT devices having different buffer layers at 90 degrees based on the resistance of the MIT thin film before heat treatment, and Table 4 summarizes the results of FIG. 7. One result.
  • Comparative Example 1 is a case of depositing an MIT thin film on a sapphire substrate (Al2O3)
  • Comparative Example 2 is a case of depositing an MIT thin film after depositing SiO2 as a buffer layer on a silicon substrate (SiO2-Si)
  • Example is a silicon substrate This is the case where MIT thin film is deposited after AlN is deposited as a buffer layer (AlN-Si).
  • FIG. 8 is a graph illustrating the change in resistance of an MIT thin film according to the time of annealing MIT devices having different buffer layers at 150 degrees based on the resistance of the MIT thin film before heat treatment, and Table 5 summarizes the results of FIG. 8. One result.
  • Comparative Example 1 is a case of depositing an MIT thin film on a sapphire substrate (Al2O3)
  • Comparative Example 2 is a case of depositing an MIT thin film after depositing SiO2 as a buffer layer on a silicon substrate (SiO2-Si)
  • Example is a silicon substrate
  • AlN-Si a buffer layer
  • AlN-Si a silicon substrate
  • an MIT device can be fabricated by depositing a buffer layer on a substrate and then fabricating an MIT device, which is excellent in stability and can increase a transition temperature, and is caused by a high temperature, plasma and dry etching process generated during the deposition of a passivation thin film.
  • the present invention relates to an MIT device having a buffer layer and a passivation thin film capable of forming a passivation thin film for preventing the characteristic change of the MIT thin film.

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Abstract

Provided are a structure of a MIT device having a buffer layer and a passivation thin film and a manufacturing method therefor, the structure enabling: easy processing and enlargement by forming the MIT device on a silicon substrate; stable maintenance of a characteristic of the device even after heat treatment, without sensitively reacting to a heat treatment condition by the insertion of an AlN buffer layer; an increase of transition temperature; and easy manufacturing of a passivation thin film having a pattern through only a single pattern formation operation by using a photoreactive polymer.

Description

버퍼층 및 패시베이션 박막을 구비한 MIT 소자 MIT device with buffer layer and passivation thin film
본 발명은 버퍼층 및 패시베이션 박막을 구비한 MIT 소자에 관한 것으로, 더욱 상세하게는 기판 상에 버퍼층을 증착한 후 MIT 소자를 제작함으로써 안정성이 우수하며 전이온도를 높일 수 있는 MIT 소자를 제작할 수 있으며, 패시베이션 박막의 증착과정에서 발생되는 고온과 플라즈마 및 건식 식각 공정으로 인한 MIT 박막의 특성 변화를 방지하기 위한 패시베이션 박막을 형성할 수 있는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자에 관한 것이다.The present invention relates to an MIT device having a buffer layer and a passivation thin film, and more particularly, to fabricate an MIT device after depositing a buffer layer on a substrate, thereby making it possible to manufacture an MIT device having excellent stability and increasing a transition temperature. The present invention relates to an MIT device having a buffer layer and a passivation thin film capable of forming a passivation thin film for preventing a change in characteristics of the MIT thin film due to high temperature generated during the deposition of the passivation thin film and plasma and dry etching processes.
MIT(Metal-Insulator Transition)는 어떠한 절연물질이 특정 온도 또는 특정 전기장이 되면 절연 특성(반도체적 특성)에서 갑자기 금속 특성으로 변하는 현상을 말하는 것으로 최근 2차 전지 및 인체감지센서등의 개발과 더불어 온도와 관련된 회로에 MIT 소자를 적용하는 연구가 활발히 진행되고 있다.MIT (Metal-Insulator Transition) refers to a phenomenon in which an insulating material suddenly changes from an insulating characteristic (semiconductor characteristic) to a metallic characteristic when a certain temperature or a specific electric field is reached. Research into applying the MIT device to the circuit related to is actively being conducted.
일반적으로 MIT 소자의 특성은 기판에 따라 변화하게 되는데, 기판으로는 MIT 박막을 증착한 후 전이온도 또는 전이전압에서의 저항의 변화정도로 확인할 수 있는 MIT 전이특성이 우수하고, 고온에서 열처리를 하는 경우에도 소자의 특성이 안정적으로 나타난다는 장점 때문에 단결정 산화알루미늄(Al2O3)인 사파이어 기판이 널리 사용되고 있다.In general, the characteristics of the MIT device vary depending on the substrate, and the substrate has excellent MIT transition characteristics, which can be identified by the change in resistance at the transition temperature or the transition voltage after the deposition of the MIT thin film, and the heat treatment at high temperature. Because of the advantages that the properties of the device appears stably, a sapphire substrate made of single crystal aluminum oxide (Al 2 O 3) is widely used.
그러나, 사파이어 기판은 고순도(99.99%, 4N 급 이상)의 알루미나(Al2O3) 분말을 2300C 이상의 고온에서 융융시킨 뒤 서서히 냉각하여 굳혀서 잉곳을 제작한 후 슬라이싱하여 웨이퍼 상태로 제작하게 되는데, 대구경의 잉곳을 성장시키기 힘들기 때문에 기판의 대면적화가 어렵고 가격이 비싸다는 단점이 있다.However, the sapphire substrate is melted to a high-purity (99.99%, 4N grade or more) of alumina (Al2O3) powder at a high temperature of more than 2300C and then cooled slowly to harden to produce an ingot, and then sliced to produce a wafer in a large diameter ingot. Since it is difficult to grow, the large area of the substrate is difficult and expensive.
또한, 사파이어 기판은 모스 경도 수치가 9로 자연계에서 다이아몬드 다음으로 단단한 물질이기 때문에 가공이 힘들다는 단점이 있다.In addition, since the sapphire substrate has a Mohs hardness value of 9, it is difficult to process because it is the hardest material after diamond in nature.
상기 문제점을 해결하기 위하여 가공성이 우수하고, 기판의 대면적화가 용이한 실리콘 기판으로 대체하는 기술 개발이 진행되고 있다.In order to solve the above problems, the development of technology to replace the silicon substrate with excellent processability and easy to large area of the substrate is in progress.
실리콘 기판 상에 MIT 소자를 제작하기 위해서는 기판과 MIT 박막 사이에 절연을 시키고, 격자 불일치(lattice mismatch)를 해소하기 위한 버퍼층을 사용해야 한다. 이러한 버퍼층으로는 SiO2를 증착하거나 실리콘 기판상에 열적 산화막을 성장시킨 기판인 SOI(Silicon on Insulator)기판을 사용하고 있다.In order to fabricate an MIT device on a silicon substrate, it is necessary to insulate between the substrate and the MIT thin film and to use a buffer layer to eliminate lattice mismatch. As the buffer layer, a silicon on insulator (SOI) substrate, which is a substrate on which SiO 2 is deposited or a thermal oxide film is grown on a silicon substrate, is used.
그러나, SiO2 또는 SOI와 같은 실리콘 산화막을 버퍼로 사용하여 MIT 소자를 제작할 경우 열처리 시 열처리 조건에 소자의 특성이 민감하게 반응하고, 열처리 후에 소자의 특성이 큰 폭으로 변화함에 따라 소자의 안정화가 힘들다는 단점이 있다.However, when fabricating an MIT device using a silicon oxide film such as SiO2 or SOI as a buffer, it is difficult to stabilize the device as the device's characteristics are sensitive to heat treatment conditions during heat treatment, and the device's properties greatly change after heat treatment. Has its drawbacks.
또한, 온도에 따라 MIT 현상을 겪는 MIT 소자는 일정 전압을 인가한 상태에서, 소자 주변의 온도가 임계온도 이상으로 올라가면 MIT 현상이 나타나고, 그에 따라 MIT 소자에 대전류가 흐르게 된다. 그런데, 주변 온도가 임계온도 이하로 내려갔을 때에도 이러한 대전류가 감소하지 않고 그대로 흐르는 MIT 소자 자체발열 현상이 나타날 있다. 이러한 MIT 소자 자체발열 현상의 발생 빈도를 줄이기 위해서 MIT 소자의 전이온도를 높이는 것이 바람직하다.In addition, the MIT device that experiences the MIT phenomenon according to the temperature, when a constant voltage is applied, when the temperature around the device rises above the threshold temperature, the MIT phenomenon occurs, a large current flows through the MIT device. However, even when the ambient temperature falls below the critical temperature, the MIT device self-heating phenomenon may appear without flowing such a large current. In order to reduce the occurrence frequency of the MIT device self-heating phenomenon, it is desirable to increase the transition temperature of the MIT device.
따라서, 가공이 쉬우며 대면적화가 용이하고, MIT 전이 온도를 높일 수 있는 MIT 소자 기술 개발이 시급한 실정이다.Therefore, there is an urgent need to develop an MIT device technology that can be easily processed, has a large area, and can increase the MIT transition temperature.
또한, MIT 소자와 같은 반도체 소자는 공정상 채널이 노출되며, 노출되어 있는 표면에 존재하는 불완전한 분자결합구조로 인해 공기 중에 떠도는 전하를 띤 이온들이 표면에 들러붙게 되어 소자의 전기적 특성을 변화시킬 수 있고, 소자의 수명 또한 단축되게 된다. 이러한 소자의 특성 변화를 방지하고 소자의 수명을 증가시키기 위하여 노출된 표면과 공기중에 떠도는 이온들을 차단하기 위하여 패시베이션 공정이 필요하다.In addition, semiconductor devices such as MIT devices are exposed to channels during the process, and due to the incomplete molecular bonding structure on the exposed surface, charge-charged ions floating in the air can stick to the surface, thereby changing the electrical characteristics of the device. And the lifetime of the device is also shortened. A passivation process is necessary to block the exposed surface and the ions floating in the air in order to prevent such a change in the characteristics of the device and increase the life of the device.
종래의 패시베이션 공정은 플라즈마를 이용한 화학기상증착방법(Plasma Enhanced Chemical Vapor Deposition, PECVD) 또는 스퍼터링(Sputtering) 방식으로 산화물 또는 질화물 박막과 같은 유전박막을 증착하는 방법을 사용하고 있다. 이러한 방법으로 증착된 유전 박막은 선택적으로 형성이 불가능하여 패턴 형성 후 식각 공정을 통해 필요하지 않은 부분을 제거하는 공정이 필요하다. 이러한 증착 및 식각 과정에서 Plasma 와 주입되는 소수의 기체 성분에 의해 소자 특성이 저하되는 현상이 나타나며, 유전 박막을 증착하고 식각하기 위한 고가의 장비가 필요하다.The conventional passivation process uses a method of depositing a dielectric thin film such as an oxide or nitride thin film by plasma enhanced chemical vapor deposition (PECVD) or sputtering. Since the dielectric thin film deposited in this manner cannot be selectively formed, there is a need for a process of removing an unnecessary portion through an etching process after pattern formation. In the deposition and etching process, device characteristics are deteriorated by a few gas components injected with the plasma, and expensive equipment for depositing and etching the dielectric thin film is required.
따라서, 이러한 MIT 소자의 신뢰성을 향상시키고, 수명을 증가시키기 위한 패시베이션 박막 형성 기술 개발이 시급한 실정이다.Therefore, there is an urgent need to develop a passivation thin film formation technology for improving the reliability and increasing the lifetime of the MIT device.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로 본 발명의 목적은 열처리시에도 안정적인 MIT 특성을 보이는 MIT 소자의 구조 및 제작방법을 제공하는 것이다.The present invention has been made to solve the above problems is an object of the present invention to provide a structure and manufacturing method of the MIT device showing a stable MIT characteristics even during heat treatment.
본 발명의 부가적인 목적은 MIT 전이 온도를 높일 수 있는 MIT 소자의 구조 및 제작방법을 제공하는 것이다.It is an additional object of the present invention to provide a structure and fabrication method of an MIT device capable of increasing the MIT transition temperature.
본 발명의 부가적인 목적은 광반응성 폴리머를 사용하여 한 번의 패턴 형성으로 패시베이션 박막을 형성함으로써 공정의 단순화 및 저가격화가 가능한 패시베이션 박막을 구비한 MIT 소자의 구조 및 제작방법을 제공하는 것이다.It is an additional object of the present invention to provide a structure and a fabrication method of an MIT device having a passivation thin film which can simplify the process and reduce the cost by forming a passivation thin film in one pattern formation using a photoreactive polymer.
상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 버퍼층 및 패시베이션 박막을 구비한 MIT 소자는, 실리콘 기판과 상기 기판 상에 증착되는 버퍼층과 특성이 변화하는 임계점을 가지는 박막을 포함한다.In order to achieve the above object, the MIT device having a buffer layer and a passivation thin film according to the present invention includes a silicon substrate and a thin film having a threshold point at which characteristics and a buffer layer deposited on the substrate change.
또한, 상기 임계점을 가지는 박막은, 재료에 의해 정해지는 임계온도에서 금속-절연체 전이(MIT) 현상을 일으키는 MIT 박막인 것을 특징으로 한다.In addition, the thin film having the critical point is an MIT thin film that causes a metal-insulator transition (MIT) phenomenon at a critical temperature determined by the material.
또한, 상기 임계점을 가지는 박막 상에 광반응성 폴리머로 이루어지는 패시베이션 박막을 더 포함하는 것을 특징으로 한다.In addition, the passivation thin film made of a photoreactive polymer on the thin film having the critical point is characterized in that it further comprises.
또한, 상기 광반응성 폴리머는, 광반응성 폴리이미드인 것을 특징으로 한다.In addition, the photoreactive polymer is characterized in that the photoreactive polyimide.
또한, 상기 MIT 박막은, 패턴이 형성되는 것을 특징으로 한다.In addition, the MIT thin film is characterized in that the pattern is formed.
또한, 상기 버퍼층은, 질화알루미늄 (AlN) 인 것을 특징으로 한다.In addition, the buffer layer is characterized in that the aluminum nitride (AlN).
또한, 상기 MIT 박막은, KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO로 이루어진 그룹 중 적어도 하나를 포함하는 것을 특징으로 한다.In addition, the MIT thin film is characterized in that it comprises at least one of the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO.
본 발명의 다른 양상에 따른 버퍼층 및 패시베이션 박막을 구비한 MIT 소자는, 실리콘 기판을 세정하는 단계와 상기 기판의 일측면에 AlN 버퍼층을 증착하는 단계와 상기 버퍼층에 MIT 박막을 증착하는 단계를 포함한다.An MIT device having a buffer layer and a passivation thin film according to another aspect of the present invention includes cleaning a silicon substrate, depositing an AlN buffer layer on one side of the substrate, and depositing an MIT thin film on the buffer layer. .
또한, 상기 버퍼층을 증착하는 단계는, 스퍼터링 (sputtering), 증발증착 (Evaporation), 전자빔증착(e-beam evaporation), 화학기상증착 (Chemical Vapor Deposition), 레이저증착 (Pulsed Laser Deposition) 중 어느 하나의 방법으로 증착하는 것을 특징으로 한다.The depositing of the buffer layer may include any one of sputtering, evaporation, e-beam evaporation, chemical vapor deposition, and pulsed laser deposition. It is characterized by depositing in a method.
또한, 상기 MIT 박막은, KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO로 이루어진 그룹 중 적어도 하나를 포함하는 것을 특징으로 한다.In addition, the MIT thin film is characterized in that it comprises at least one of the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO.
또한, 상기 MIT 박막을 증착하는 단계는, 스퍼터링 (sputtering), 증발증착 (Evaporation), 전자빔증착(e-beam evaporation), 레이저증착 (PLD, Pulsed Lase Deposition) 과 같은 물리기상증착 (PVD, Physical Vapor Deposition) 또는 PECVD (Plasma-Enhanced CVD), APCVP (Atmospheric Pressure CVD), LPCVD (Low Pressure CVD), HDPCVD (High Density Plasma CVD)와 같은 화학기상증착 (CVD, Chemical Vapor Deposition) 중 어느 하나의 방법을 사용하여 증착하는 것을 특징으로 한다.In addition, the step of depositing the MIT thin film, physical vapor deposition (PVD, physical vapor deposition) such as sputtering, evaporation, e-beam evaporation, laser deposition (PLD, Pulsed Lase Deposition) Deposition) or chemical vapor deposition (CVD) such as plasma-enhanced CVD (PECVD), atmospheric pressure CVD (APCVP), low pressure CVD (LPCVD), or high density plasma CVD (HDPCVD). It is characterized by depositing using.
또한, 상기 MIT 박막에 패턴을 형성하여 소자를 제작하는 단계를 더 포함하는 것을 특징으로 한다.The method may further include manufacturing a device by forming a pattern on the MIT thin film.
또한, 상기 MIT 박막 상에 광반응성 폴리머를 코팅하는 단계와 상기 광반응성 폴리머를 제1 온도로 가열하여 경화시키는 단계와 상기 경화된 광반응성 폴리머 박막에 패턴이 형성된 마스크를 접촉시킨 후 자외선을 노광하여 상기 패턴을 상기 폴리머 박막에 전사시키는 단계와 상기 패턴이 전사된 폴리머 박막을 현상하여 상기 폴리머 박막에 패턴을 형성하는 단계와 상기 패턴이 형성된 폴리머 박막을 제2 온도로 가열하여 경화시키는 단계를 포함하는 것을 특징으로 한다.The method may further include coating a photoreactive polymer on the MIT thin film, heating and curing the photoreactive polymer to a first temperature, and exposing ultraviolet rays after contacting a mask having a pattern formed thereon with the cured photoreactive polymer thin film. Transferring the pattern to the polymer thin film, developing the patterned polymer thin film to form a pattern on the polymer thin film, and heating and curing the patterned polymer thin film to a second temperature. It is characterized by.
또한, 상기 광반응성 폴리머를 코팅하는 단계 및 상기 패턴을 전사하는 단계 및 상기 패턴을 형성하는 단계는, 상기 임계온도 이하에서 이루어지는 것을 특징으로 한다.The coating of the photoreactive polymer, the transferring of the pattern, and the forming of the pattern may be performed at or below the critical temperature.
또한, 상기 광반응성 폴리머는, 광반응성 폴리이미드 인 것을 특징으로 한다.In addition, the photoreactive polymer is characterized in that the photoreactive polyimide.
또한, 상기 제1온도는, 130도 이하이고, 상기 제2 온도는, 상기 제1 온도보다 50도 이상인 것을 특징으로 한다.The first temperature is 130 degrees or less, and the second temperature is 50 degrees or more than the first temperature.
이상에서 살펴본 바와 같이, 본 발명의 일 실시예에 따른 버퍼층 및 패시베이션 박막을 구비한 MIT 소자는 가공이 용이하고 대면적화가 가능한 MIT 소자 제작 방법을 제공함으로써 생산성을 향상시킬 수 있다.As described above, an MIT device including a buffer layer and a passivation thin film according to an embodiment of the present invention may improve productivity by providing a method for fabricating an MIT device that is easy to process and that can be large in area.
또한, 열처리 조건에 민감하게 반응하지 않고, 열처리 후에도 MIT 소자의 특성을 일정하게 유지할 수 있어 MIT 소자의 품질관리를 용이하게 할 수 있다.In addition, the characteristics of the MIT device can be kept constant even after the heat treatment without being sensitive to heat treatment conditions, thereby facilitating quality control of the MIT devices.
또한, MIT 전이온도를 높임으로써, 보다 고온에서 사용할 수 있는 MIT 소자를 제작함으로써, MIT 소자의 응용범위를 넓힐 수 있으며, MIT 소자의 자체발열 현상을 방지할 수 있다.In addition, by increasing the MIT transition temperature, by fabricating an MIT device that can be used at a higher temperature, the application range of the MIT device can be widened, and the self-heating phenomenon of the MIT device can be prevented.
또한, 종래의 건식 증착, 패턴 형성 및 건식 습각 공정의 3단계 공정으로 진행되는 패시베이션 박막 형성 공정을 광반응성 폴리머를 이용한 패턴 형성 공정만으로 패시베이션 박막을 형성할 수 있도록 함으로써, 생산성을 향상 시킬 수 있다.In addition, by allowing the passivation thin film formation process of the conventional dry deposition, pattern formation, and dry wet processes to be performed using only a pattern formation process using a photoreactive polymer, productivity can be improved.
또한, 종래의 건식 증착 및 건식 습각 공정에서 발생하는 소자의 특성 저하를 방지할 수 있다.In addition, it is possible to prevent the deterioration of the characteristics of the device generated in the conventional dry deposition and dry wet process.
또한, 종래의 건식 증착 공정보다 두꺼운 패시베이션 박막을 형성할 수 있도록 함으로써, 소자의 내구성을 향상시키며 또한 보다 저가에 패시베이션 공정을 진행 시킬 수 있다.In addition, it is possible to form a passivation thin film thicker than the conventional dry deposition process, it is possible to improve the durability of the device and to proceed the passivation process at a lower cost.
도 1은 MIT 의 특성을 나타낸 그래프로, 도 1a는 온도에 따른 MIT 특성 그래프이고, 도 1b는 전압에 따른 MIT 특성 그래프이다.1 is a graph showing the characteristics of MIT, FIG. 1A is a graph of MIT characteristics according to temperature, and FIG. 1B is a graph of MIT characteristics according to voltage.
도 2는 본 발명의 바람직한 실시예에 따른 MIT 소자의 구조도이다.2 is a structural diagram of an MIT device according to a preferred embodiment of the present invention.
도 3은 본 발명의 바람직한 실시예에 따른 MIT 소자의 제작 공정도이다.3 is a manufacturing process diagram of the MIT device according to a preferred embodiment of the present invention.
도 4는 본 발명의 바람직한 실시예에 따른 MIT 소자의 패시베이션 공정 순서도이다.4 is a flow diagram of a passivation process of an MIT device in accordance with a preferred embodiment of the present invention.
도 5는 본 발명의 패시베이션 박막의 물질에 따른 MIT 소자의 특성을 측정한 그래프이다.5 is a graph measuring the characteristics of the MIT device according to the material of the passivation thin film of the present invention.
도 6은 본 발명의 기판 및 버퍼층의 물질에 따른 MIT 소자의 특성을 측정한 그래프이다.6 is a graph measuring the characteristics of the MIT device according to the material of the substrate and the buffer layer of the present invention.
도 7은 본 발명의 버퍼층의 물질을 변경한 MIT 소자를 90도에서 열처리하는 시간에 따른 특성 변화를 측정한 그래프이다.FIG. 7 is a graph illustrating a change in characteristics of a MIT device in which a material of a buffer layer of the present invention is changed with time of heat treatment at 90 degrees.
도 8은 본 발명의 버퍼층의 물질을 변경한 MIT 소자를 150도에서 열처리하는 시간에 따른 특성 변화를 측정한 그래프이다.FIG. 8 is a graph illustrating a change in characteristics of a MIT device in which a material of a buffer layer of the present invention is changed at a temperature of 150 ° C. FIG.
이하, 첨부된 도면을 참조하여 본 발명에 따른 통화 제어 방법 및 장치에 대하여 설명한다.Hereinafter, a call control method and apparatus according to the present invention will be described with reference to the accompanying drawings.
도 1은 MIT의 특성을 나타내는 그래프로, 도 1a는 온도에 따른 MIT 특성을 나타내는 그래프이고, 도 1b는 전압에 따른 MIT 특성을 나타내는 그래프이다.1 is a graph showing the characteristics of the MIT, Figure 1a is a graph showing the MIT characteristics according to the temperature, Figure 1b is a graph showing the MIT characteristics according to the voltage.
금속-절연체 전이(Metal-Insulator Transition, MIT)는 특정 절연 물질이 특정 온도 또는 특정 전기장에 해당하는 환경에서 절연특성(반도체적 특성)에서 갑자기 금속 특성으로 변하는 현상을 말한다.Metal-Insulator Transition (MIT) is a phenomenon in which a certain insulating material suddenly changes from an insulating property (semiconductor property) to a metal property in an environment corresponding to a specific temperature or a specific electric field.
이하에서 MIT 소자가 금속-절연체 전이를 일으키는 온도를 ‘전이 온도’라 하고, 금속-절연체 전이를 일으키는 전압을 ‘전이 전압’이라 한다.Hereinafter, the temperature at which the MIT device causes the metal-insulator transition is referred to as the "transition temperature," and the voltage causing the metal-insulator transition is referred to as the "transition voltage."
MIT 특성을 가지는 물질은 전이금속산화물(transition metal oxide), 전이 알칼리 금속 산화물(transition alkali-metal oxide), 란탄계열 산화물(lanthanide oxide) 등으로 이루어질 수 있다. 구체적으로는 KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO로 이루어진 그룹 중 선택된 적어도 하나의 물질로 형성될 수 있다.The material having MIT characteristics may be formed of a transition metal oxide, a transition alkali-metal oxide, a lanthanide oxide, or the like. Specifically, it may be formed of at least one material selected from the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO.
상기 물질들 중 이산화바나듐(VO2)은 전이 온도가 상온 근처인 유일한 물질로 특히 많이 사용되고 있다. 즉 센서, 반도체 소자, 전기 소자 등 대부분의 응용 소자는 상온 근방에서 동작하므로, 전이 온도가 상온 근처인 이산화바나듐은 특히 유용한 MIT 소자로 사용될 수 있는 것이다.Among these materials, vanadium dioxide (VO2) is particularly used as the only material having a transition temperature near room temperature. That is, since most application devices such as sensors, semiconductor devices, and electrical devices operate near room temperature, vanadium dioxide having a transition temperature near room temperature can be used as a particularly useful MIT device.
이산화바나듐의 MIT 현상은 1959년 Morin 에 의하여 처음으로 발견되었는데, 이산화바나듐의 온도에 따른 저항 변화는 도 1a의 그래프와 같이, 상온에서 절연체(반도체) 상태이다가 340K (67 C) 근처에서 저항이 급격하게 10만분의 1로 감소한다는 사실을 알 수 있다. 이와 같이 전이온도에서의 저항의 급격한 변화는 금속-절연체 전이의 대표적인 특징 중의 하나이다.The MIT phenomenon of vanadium dioxide was first discovered by Morin in 1959. The resistance change with temperature of vanadium dioxide is insulator (semiconductor) at room temperature as shown in the graph of FIG. It can be seen that it is rapidly reduced to one hundred thousand. This rapid change in resistance at the transition temperature is one of the representative characteristics of the metal-insulator transition.
이산화바나듐의 전압에 따른 전류 특성은 도 1b의 그래프에서 볼 수 있듯이, 낮은 전압에서는 절연체와 마찬가지로 밴드 갭이 있는 물리적 특성을 가진 반도체적인 특성을 보이다가 소자와 물질의 상태 등에 기반하여 결정된 특정 전압(임계전압)에서 갑자기 높은 전류 밀도를 보인다. 이후 전압에 비례하여 전류가 흐름으로써 밴드 갭이 없는 금속과 같은 특성을 보인다.As can be seen in the graph of FIG. 1B, the current characteristics of vanadium dioxide according to the voltage are semiconductor characteristics having a physical property with a bandgap similar to an insulator at low voltage, and are determined based on the state of devices and materials. Threshold voltage) suddenly shows a high current density. Since the current flows in proportion to the voltage, it exhibits the same characteristics as a metal without a band gap.
도 2는 본 발명의 바람직한 실시예에 따른 MIT 소자의 구조도이다.2 is a structural diagram of an MIT device according to a preferred embodiment of the present invention.
도 2를 참조하면, 본 발명에 따른 버퍼층을 구비한 MIT 소자는 기판(210), 버퍼층(230), MIT 박막(250) 및 패시베이션박막(270)을 포함한다.Referring to FIG. 2, an MIT device having a buffer layer according to the present invention includes a substrate 210, a buffer layer 230, an MIT thin film 250, and a passivation thin film 270.
기판(210)은 가공성이 좋고 대면적화가 용이하며, 공급 물량이 충분하여 원자재 수급이 용이한 실리콘 기판을 사용하는 것이 바람직하다. 또한, 실리콘 기판은 열전도율이 우수하기 때문에 소자 구동을 위해 전압을 인가할 때 소자 내부에서 발생하는 열로 인한 소자의 특성 저하가 발생하는 것을 방지할 수 있다.The substrate 210 may be a silicon substrate having good workability, easy to large area, sufficient supply quantity, and easy to supply raw materials. In addition, since the silicon substrate has excellent thermal conductivity, it is possible to prevent the deterioration of device characteristics due to heat generated inside the device when voltage is applied to drive the device.
버퍼층(230)은 MIT 박막(250)과 기판(210) 사이의 절연 및 격자 불일치를 해소하기 위하여 형성된다.The buffer layer 230 is formed to solve the insulation and lattice mismatch between the MIT thin film 250 and the substrate 210.
버퍼층(230)은 산화물 또는 질화물과 같은 유전체를 기판 상에 스퍼터링 (sputtering), 증발증착 (Evaporation), 전자빔증착(e-beam evaporation), 레이저증착 (PLD, Pulsed Lase Deposition) 과 같은 물리기상증착 (PVD, Physical Vapor Deposition) 또는 PECVD (Plasma-Enhanced CVD), APCVP (Atmospheric Pressure CVD), LPCVD (Low Pressure CVD), HDPCVD (High Density Plasma CVD)와 같은 화학기상증착 (CVD, Chemical Vapor Deposition) 중 어느 하나의 방법을 사용하여 증착할 수 있다.The buffer layer 230 may be formed by physical vapor deposition such as sputtering, evaporation, e-beam evaporation, and laser deposition (PLD) on a substrate such as an oxide or nitride. Chemical Vapor Deposition (CVD), such as PVD, Physical Vapor Deposition (PECVD), Plasma-Enhanced CVD (PECVD), Atmospheric Pressure CVD (APCVP), Low Pressure CVD (LPCVD), or High Density Plasma CVD (HDPCVD). Deposition can be made using one method.
종래에는 버퍼층(230)으로 SiO2와 같은 산화물을 증착하여 사용하였으나, 이 경우 MIT 소자의 열적 안정성이 저하된다는 단점이 발생한다.Conventionally, an oxide such as SiO 2 is deposited and used as the buffer layer 230, but in this case, a disadvantage arises in that the thermal stability of the MIT device is lowered.
MIT 물질은 결정 구조에 따라 특성이 다르게 나타나므로, 기판의 영향을 크게 받게 된다. 즉, 기판과 MIT 물질의 격자 불일치가 클수록 MIT 특성이 불안정하게 나타나게 되는 것이다. SiO2 를 상기 증착 방법을 사용해서 증착할 경우 비정질 상태로 박막이 형성되어 SiO2 상에 증착되는 MIT 물질의 결정 구조를 왜곡시키게 되는데, 이는 공정 진행 중에 제어할 수 없는 변수로 MIT 소자의 특성이 안정적으로 나타나지 않게 되는 원인이 된다.Since MIT materials have different characteristics depending on the crystal structure, they are greatly influenced by the substrate. In other words, the larger the lattice mismatch between the substrate and the MIT material, the more unstable the MIT characteristic is. When SiO2 is deposited using the above deposition method, a thin film is formed in an amorphous state, which distorts the crystal structure of the MIT material deposited on SiO2, which is an uncontrollable variable during the process, which makes the characteristics of the MIT device stable. It will cause it not to appear.
본 발명에서는 상기와 같은 문제점을 해결하기 위하여 결정형태로 증착되는 질화알루미늄 (AlN) 을 버퍼층으로 사용하여 MIT 물질의 결정 구조가 왜곡되는 현상을 최소화함으로써 MIT 소자의 특성이 안정적으로 나올 수 있도록 한다.In the present invention, to solve the above problems, by using aluminum nitride (AlN) deposited in the crystal form as a buffer layer to minimize the distortion of the crystal structure of the MIT material, the characteristics of the MIT device can be stably presented.
MIT 박막(250)은 특정 온도 또는 특정 전기장에 해당하는 환경에서 절연특성(반도체적 특성)에서 갑자기 금속 특성으로 변하는 현상인 MIT 현상을 일으키는 물질을 증착한 박막을 의미한다.The MIT thin film 250 refers to a thin film on which a material causing an MIT phenomenon, which suddenly changes from an insulating characteristic (semiconductor characteristic) to a metallic characteristic in an environment corresponding to a specific temperature or a specific electric field, is deposited.
이러한 MIT 특성을 보이는 물질은 상기에서 설명한 바와 같이 전이금속산화물 (transition metal oxide), 전이알칼리금속산화물 (transition alkali-metal oxide), 란탄계열 산화물 (lanthanide oxide) 등으로 이루어질 수 있다. 구체적으로는 KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO로 이루어진 그룹 중 선택된 적어도 하나의 물질로 형성될 수 있다.As described above, the MIT material may be formed of a transition metal oxide, a transition alkali-metal oxide, a lanthanide oxide, or the like. Specifically, it may be formed of at least one material selected from the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO.
패시베이션 박막(270)은 광반응성 폴리머를 MIT 박막 상에 스핀 코팅과 같은 습식 코팅 기술을 이용하여 코팅한 후 오븐 또는 핫플레이트 상에서 가열하여 형성된다. 종래의 패시베이션 공정에서는 산화물 또는 질화물과 같은 유전박막을 플라즈마를 이용한 화학기상증착방법(PECVD)으로 약 250C 이상의 고온에서 증착하는 방법으로 얻어지지만, 본 발명에서는 상온에서 습식 코팅 방식으로 코팅 한 후 130C 이하의 온도로 가열함으로써 용이하게 박막을 형성할 수 있다.Passivation thin film 270 is formed by coating a photoreactive polymer on a MIT thin film using a wet coating technique such as spin coating and then heating on an oven or hotplate. In the conventional passivation process, a dielectric thin film, such as an oxide or nitride, is obtained by vapor deposition at a high temperature of about 250C or more by a chemical vapor deposition method (PECVD) using plasma, but in the present invention, after coating by a wet coating method at room temperature, 130C or less The thin film can be easily formed by heating to a temperature of.
도 3은 본 발명의 바람직한 실시예에 따른 MIT 소자 제작방법을 설명하기 위한 공정 순서도이다.3 is a flowchart illustrating a method for fabricating an MIT device according to a preferred embodiment of the present invention.
도 3을 참조하면, 본 발명에 따른 MIT 소자는 기판을 준비하는 단계(S310), 상기 S310 단계에서 준비된 기판의 일측면에 버퍼층을 증착하는 단계(S320), 상기 S320 단계에서 증착된 버퍼층 상에 MIT 특성을 보이는 박막을 증착하는 단계(S330), 상기 S330 단계에서 증착된 MIT 박막에 패턴을 형성하여 MIT 소자를 제작하는 단계(S340), 상기 S340 단계에서 형성된 MIT 소자 상에 패시베이션 박막을 형성하는 단계(S350) 및 상기 MIT 소자가 제작된 기판을 다이싱(dicing) 또는 쏘잉(Sawing) 공정을 통하여 절단하여 MIT 소자 칩을 제작하는 단계(S360)를 통해 제작된다.Referring to FIG. 3, the MIT device according to the present invention includes preparing a substrate (S310), depositing a buffer layer on one side of the substrate prepared in S310 (S320), and depositing a buffer layer on the buffer layer deposited in S320. Depositing a thin film having MIT characteristics (S330), forming a pattern on the MIT thin film deposited in step S330 to manufacture an MIT device (S340), and forming a passivation thin film on the MIT device formed in step S340 In operation S350 and the substrate on which the MIT device is manufactured, the substrate is fabricated through a dicing or sawing process to fabricate an MIT device chip (S360).
이하, 상기 공정단계에 대하여 상세히 설명한다.Hereinafter, the process steps will be described in detail.
S310 단계는 MIT 소자의 기판으로 사용되는 실리콘 기판을 전처리하는 공정이다. 이러한 전처리는 기판 폴리싱(polishing) 및 세정 공정을 포함할 수 있다. 폴리싱 공정은 웨이퍼의 한쪽 면을 연마하여 거울면처럼 만들어주는 공정이다. 즉, 기판을 표면을 평탄하게 하고 잉곳에서 슬라이싱 하는 도중에 기판의 표면에 발생할 수 있는 스크래치와 같은 defect 를 없애주는 역할을 한다. 상기 폴리싱 공정은 폴리싱 완료된 웨이퍼를 구매하여 사용할 경우에는 생략할 수 있다. 세정 공정은 일반적으로 사용되는 RCA 기판 세정 공정을 사용할 수 있다. RCA 세정 공정은 염기성 용액을 사용하여 표면 유기 물질들을 세정하는 SC-1(Standard Cleaning-1)공정과 산성 용액을 사용하여 표면 금속 오염물질을 제거하는 SC-2(Standard Cleaning-2) 중 하나 이상을 포함할 수 있다.Step S310 is a process of pre-processing the silicon substrate used as the substrate of the MIT device. Such pretreatment may include substrate polishing and cleaning processes. Polishing is a process that polishes one side of a wafer to make it look like a mirror. That is, it smoothes the surface of the substrate and removes defects such as scratches that may occur on the surface of the substrate during slicing in the ingot. The polishing process may be omitted when the polished wafer is purchased and used. The cleaning process may use a commonly used RCA substrate cleaning process. The RCA cleaning process includes one or more of Standard Cleaning-1 (SC-1), which cleans surface organic materials using a basic solution, and Standard Cleaning-2 (SC-2), which removes surface metal contaminants using an acidic solution. It may include.
S320 단계는 상기 S310 단계에서 준비한 기판의 일측면 상에 버퍼층을 증착하는 단계이다. 버퍼층으로 질화알루미늄(AlN)을 스퍼터링 (sputtering), 증발증착 (Evaporation), 전자빔증착(e-beam evaporation), 화학기상증착 (Chemical Vapor Deposition), 레이저증착 (Pulsed Laser Deposition) 중 어느 하나의 방법을 사용하여 증착할 수 있다.Step S320 is a step of depositing a buffer layer on one side of the substrate prepared in step S310. Sputtering, evaporation, e-beam evaporation, chemical vapor deposition, and chemical vapor deposition of AlN as the buffer layer Can be deposited using.
S330 단계는 상기 S320 단계에서 증착된 버퍼층 상에 MIT 특성을 가지는 물질을 증착하여 MIT 박막을 형성하는 공정이다. MIT 물질은 KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO로 이루어진 그룹 중 선택된 적어도 하나의 물질을 스퍼터링 (sputtering), 증발증착 (Evaporation), 전자빔증착(e-beam evaporation), 레이저증착 (PLD, Pulsed Lase Deposition) 과 같은 물리기상증착 (PVD, Physical Vapor Deposition) 또는 PECVD (Plasma-Enhanced CVD), APCVP (Atmospheric Pressure CVD), LPCVD (Low Pressure CVD), HDPCVD (High Density Plasma CVD)와 같은 화학기상증착 (CVD, Chemical Vapor Deposition) 중 어느 하나의 방법을 사용하여 증착할 수 있다.Step S330 is a process of forming a MIT thin film by depositing a material having an MIT characteristic on the buffer layer deposited in step S320. MIT material is sputtering or evaporating at least one material selected from the group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO ), Physical Vapor Deposition (PVD) or Plasma-Enhanced CVD (PECVD), Atmospheric Pressure CVD (LPC), LPCVD (e-beam evaporation), Laser Deposition (PLD, Pulsed Lase Deposition) The deposition may be carried out using any one of Chemical Vapor Deposition (CVD), such as Low Pressure CVD) and High Density Plasma CVD (HDPCVD).
S340 단계는 상기 S330 단계에서 증착한 MIT 박막에 포토리소그래피 (photolithography) 공정을 이용한 패턴 형성공정을 통하여 패턴을 형성하여 MIT 소자를 제작하는 공정이다.In step S340, a pattern is formed on the MIT thin film deposited in step S330 by a pattern forming process using a photolithography process to fabricate an MIT device.
S350 단계에서는 상기 S340 단계에서 형성된 MIT 소자상에 광반응성 폴리머로 패시베이션 막을 더 형성한 후 패시베이션 막 패턴을 형성할 수도 있다. 패시베이션 막 형성 공정에 대해서는 하기에서 상세히 설명한다.In operation S350, a passivation film may be further formed on the MIT device formed in operation S340, and then a passivation film pattern may be formed. The passivation film forming process will be described in detail below.
S360 단계는 MIT 소자가 제작된 기판(실리콘 웨이퍼)을 절단하여 MIT 소자 칩을 제작하는 공정으로 웨이퍼 다이싱에 사용되는 블레이드 다이싱 (Blade Dicing) 또는 레이저 아블레이션 (Laser ablation) 또는 스텔스 다이싱 (Stealth Dicing) 중 어느 하나의 방법을 사용할 수 있고 이외에 공지된 기술들을 사용하여 절단할 수 있으므로 여기에서는 상세한 설명을 생략한다.Step S360 is a process of cutting a substrate (silicon wafer) on which an MIT device is manufactured to manufacture an MIT device chip. Blade dicing, laser ablation, or stealth dicing (used for wafer dicing) is performed. Stealth Dicing) can be used, and other methods can be cut using known techniques, so detailed descriptions are omitted here.
도 4는 MIT 소자 상에 패시베이션 막을 형성하는 공정의 순서도로, 도 3의 S350 단계를 보다 상세히 설명한다.4 is a flowchart illustrating a process of forming a passivation film on an MIT device, which describes step S350 of FIG. 3 in more detail.
도 4를 참조하면, 본 발명에 따른 패시베이션 공정은 S340 단계에서 제작된 MIT 소자 상에 광반응성 폴리머를 코팅하는 단계(S410)와, 상기 S410 단계에서 코팅된 광반응성 폴리머를 오븐이나 핫플레이트 상에서 제1온도로 가열함으로써 광반응성 폴리머 박막을 형성하는 단계(S420)와, 상기 S420 단계에서 형성된 광반응성 폴리머 박막에 자외선을 조사하는 단계(S430)와, 상기 S430 단계에서 형성된 패턴을 현상하는 단계(S440)와, 상기 S440 단계에서 형성된 광반응성 폴리머 패턴의 접착력 강화 및 경화를 위하여 오븐이나 핫플레이트 상에서 제2온도로 가열하는 단계(S450)로 이루어진다.Referring to FIG. 4, the passivation process according to the present invention includes coating the photoreactive polymer on the MIT device fabricated in step S340 (S410), and removing the photoreactive polymer coated in step S410 on an oven or a hot plate. Forming a photoreactive polymer thin film by heating to a temperature (S420), irradiating ultraviolet rays to the photoreactive polymer thin film formed in step S420 (S430), and developing a pattern formed in step S430 (S440). ), And heating (S450) to a second temperature on an oven or a hot plate to enhance adhesion and curing of the photoreactive polymer pattern formed in step S440.
S410 단계 및 S420 단계에서는 광반응성 폴리머를 MIT 박막 상에 스핀 코팅과 같은 습식 코팅 기술을 이용하여 코팅한 후 오븐 또는 핫플레이트 상에서 가열하여 패시베이션 박막을 형성한다. 종래의 패시베이션 공정에서는 산화물 또는 질화물과 같은 유전박막을 플라즈마를 이용한 화학기상증착방법(PECVD)으로 약 250C 이상의 고온에서 증착하는 방법으로 얻어지지만, 본 발명에서는 상온에서 습식 코팅 방식으로 코팅 한 후 130C 이하의 온도로 가열함으로써 용이하게 박막을 형성할 수 있다.In steps S410 and S420, the photoreactive polymer is coated on the MIT thin film using a wet coating technique such as spin coating, and then heated on an oven or hot plate to form a passivation thin film. In the conventional passivation process, a dielectric thin film, such as an oxide or nitride, is obtained by vapor deposition at a high temperature of about 250C or more by a chemical vapor deposition method (PECVD) using plasma, but in the present invention, after coating by a wet coating method at room temperature, 130C or less The thin film can be easily formed by heating to a temperature of.
종래의 기술에서는 유전 박막이 증착될 때 전이온도 이상의 온도인 250C 이상의 고온과 Plasma 상태에서 이루어짐으로써 유전 박막이 증착되는 동안 유전 박막과 MIT 박막의 계면에서 유전 박막의 분자들과 MIT 박막의 분자들 사이에 확산이 발생하여 MIT 소자의 특성이 불안정해지고, 유전 박막이 형성된 후 전이 온도 이하의 온도로 냉각되었을 때 MIT 특성의 이력 현상(hysteresis effect)이 발생하게 된다는 문제점이 발생한다.In the prior art, when the dielectric thin film is deposited, the plasma thin film is formed at a high temperature of 250C or more, which is a temperature higher than the transition temperature. Diffusion occurs in the MIT device characteristics become unstable, the hysteresis effect of the MIT characteristics occurs when the dielectric thin film is formed and cooled to a temperature below the transition temperature.
MIT 현상이 발생하는 원인에 대해서는 최근까지도 확실히 밝혀지지는 않았지만, 임계온도 또는 임계전압(이하 ‘임계점’이라 함)에서 시료내부에서 상전이(phase transition)가 일어나서 MIT 현상이 나타난다는 사실을 밝혀졌다. 임계점을 기준으로 하여 MIT 박막의 상(phase)이 다르게 나타나게 되고 이로 인해 MIT 현상이 나타나게 되는 것이다. 즉, 임계온도 이상에서의 MIT 소재의 상(phase)에서 박막 계면에서의 확산 현상이 발생하게 되면 임계온도 이하로 되었을 때 상전이(phase transition)가 다르게 나타나게 되어 MIT 소재의 특성이 변하게 되는 것이다.The cause of the MIT phenomenon is not clear until recently, but it has been found that the MIT phenomenon is caused by a phase transition inside the sample at the critical temperature or the threshold voltage (hereinafter referred to as the 'critical point'). The phase of the MIT thin film appears differently based on the critical point, which causes the MIT phenomenon to appear. That is, if a diffusion phenomenon occurs at the thin film interface in the phase of the MIT material at or above the critical temperature, the phase transition is different when the temperature is lower than the critical temperature, thereby changing the characteristics of the MIT material.
또한, 박막 사이에서의 확산 현상은 박막 형성 온도가 증가할수록 많이 발생하게 되므로 이러한 문제점을 해결하기 위해서는 전이온도 이하의 온도에서 유전 박막을 형성한 후 유전 박막을 MIT 박막 상에 고착시킴으로써 계면에서 발생하는 확산 현상을 최소화하는 것이 바람직하다.In addition, the diffusion phenomenon between the thin films are more likely to occur as the film formation temperature increases, so to solve this problem, after forming the dielectric thin film at a temperature below the transition temperature, the dielectric thin film is fixed on the MIT thin film. It is desirable to minimize the diffusion phenomenon.
또한, 대부분의 MIT 물질들은 산화물로 이루어져 있는바, 상기 MIT 박막 상에 실리카와 같은 산화물로 패시베이션 박막을 형성하는 종래의 기술에서는 동일한 산화물 계열을 증착함으로써 MIT 박막과 패시베이션 산화물 박막 사이에 확산이 보다 잘 발생하게 되어 MIT 소자의 특성 저하가 더 크게 발생하게 된다.In addition, most MIT materials are composed of oxides, and in the conventional technique of forming a passivation thin film with an oxide such as silica on the MIT thin film, deposition between the MIT thin film and the passivation oxide thin film is better by depositing the same oxide series. This causes a greater deterioration of the characteristics of the MIT device.
따라서, 본 발명에 적용되는 광반응성 폴리머는 산화물과 반응이 적고 우수한 내열성, 내화학성, 내마모성을 보이며, 전기적 특성이 우수한 폴리이미드 계열의 고분자를 사용하는 것이 바람직하다.Therefore, the photoreactive polymer to be applied to the present invention preferably uses a polyimide-based polymer which is less reactive with an oxide, exhibits excellent heat resistance, chemical resistance, and abrasion resistance, and has excellent electrical properties.
폴리이미드(Polyimide)는 이미드 고리를 가지는 고분자 물질로 주로 방향족의 무수물 및 디아민을 이용하여 합성하여 제작된다. 이러한 폴리이미드 중 광반응성 폴리이미드(photosensitive polyimide)의 경우 광과 반응할 수 있는 기능 고리가 치환되어 세부 목적에 적합한 기능을 구현하도록 사용될 수 있다.Polyimide is a high molecular material having an imide ring and is mainly produced by synthesizing using an aromatic anhydride and diamine. In the case of photosensitive polyimide of such polyimide, a functional ring capable of reacting with light may be substituted and used to implement a function suitable for a specific purpose.
S430 단계 및 S440 단계는 S420 단계에서 형성된 광반응성 폴리머 박막에 포토리소그래피(photolithography) 공정을 이용하여 패턴을 형성한 후 현상하는 단계이다.Steps S430 and S440 are developed after forming a pattern on the photoreactive polymer thin film formed in step S420 using a photolithography process.
패시베이션 박막이 필요한 부분만을 남기기 위하여 패턴을 형성하는 단계로, 패턴이 형성된 마스크와 광반응성 폴리머 박막이 코팅된 MIT 소자를 접촉시킨 후 UV 자외선에 노출시킨 후 현상액을 이용하여 패턴을 형성하게 된다.In the step of forming a pattern in order to leave only a portion of the passivation thin film, the patterned mask is contacted with the MIT device coated with the photoreactive polymer thin film, and then exposed to UV ultraviolet rays to form a pattern using a developer.
본 발명에 적용되는 광반응성 폴리머의 경우 노광되지 않는 부분이 현상되는 음성 광반응 특성(negative photosensitive)과 노광되는 부분이 현상되는 양성(Positive photosensitive)를 중 어느 하나를 적용할 수 있다.In the case of the photoreactive polymer to be applied to the present invention, any one of negative photosensitive characteristics in which an unexposed part is developed and positive photosensitive in which an exposed part is developed may be applied.
즉, 공정 특성에 따라 광반응성 폴리머의 타입을 공정의 특성에 따라 음성 또는 양성 광반응 특성 중 선택하여 사용할 수 있는 것이다.That is, the type of photoreactive polymer can be selected from among negative or positive photoreactive properties according to the process characteristics according to the process characteristics.
종래의 기술에서는 실리카와 같은 산화물을 증착한 후 포토리소그래피 공정으로 패턴을 형성한 후 건식 식각 공정을 통하여 패시베이션 박막의 패턴을 형성하는 방법을 사용한 반면, 본 발명에서는 포토리소그래피 공정만으로 패시베이션 박막의 패턴을 형성함으로써 건식 식각 공정 중 발생할 수 있는 과잉 식각(overetching)으로 인한 MIT 박막의 손상을 방지할 수 있을 뿐만 아니라, 건식 식각 공정 중에 투입되는 식각가스로 인한 MIT 특성 변화도 방지할 수 있게 된다.In the prior art, a method of forming a pattern of a passivation thin film by using a photolithography process after depositing an oxide such as silica and then forming a pattern by a photolithography process, in the present invention, a pattern of the passivation thin film is formed using only a photolithography process. By forming, it is possible not only to prevent damage to the MIT thin film due to overetching that may occur during the dry etching process, but also to prevent the MIT characteristic change due to the etching gas introduced during the dry etching process.
또한, 화학 반응은 온도가 높을수록 또는 외부에서 자외선과 같은 광에너지가 조사될 때 보다 활성화되게 된다. 따라서, 포토리소그래피 공정에서의 자외선 노광 단계 및 현상액과 같은 화학 물질과 MIT 박막이 접촉하게 되는 패턴 형성 단계는 MIT 특성 변화를 방지하기 위하여 임계온도 이하의 온도에서 진행하는 것이 바람직하다.In addition, the chemical reaction becomes more active when the temperature is higher or when light energy such as ultraviolet rays are irradiated from the outside. Therefore, in the photolithography process, the step of forming a pattern in which the MIT thin film is in contact with a chemical such as the ultraviolet light exposure step and the developer is preferably performed at a temperature below the critical temperature in order to prevent the MIT characteristic change.
S450 단계는 패턴이 현상된 패시베이션 박막의 접착력 및 경도를 증가시키기 위하여 S420 단계에서 가열한 온도보다 50도 이상의 온도에서 가열하는 공정이다.Step S450 is a step of heating at a temperature of 50 degrees or more than the temperature heated in step S420 in order to increase the adhesion and hardness of the pattern passivation thin film.
S440 단계까지 거치면서 패턴이 형성된 광반응성 폴리머 박막은 MIT 박막 상에 명확한 계면을 가지도록, 즉 계면에서의 분자 확산이 일어나지 않도록 고착된 상태가 된다. 따라서, S250 단계에서 고온으로 가열을 한다 하여도 계면에서의 분자 확산이 발생하지 않게 되어 고온으로 가열을 하여도 MIT 소자의 특성 변화가 거의 발생하지 않는다.The photoreactive polymer thin film having a pattern formed through the step S440 is fixed to have a clear interface on the MIT thin film, that is, to prevent molecular diffusion at the interface. Therefore, even when heated to a high temperature in step S250, molecular diffusion at the interface does not occur, and even when heated to a high temperature, almost no change in characteristics of the MIT device occurs.
이러한 온도는 S420 단계의 온도보다 50도 이상의 온도 범위에서 설정하되, 광반응성 폴리머의 변형 온도이하로 설정하는 것이 바람직하다. 일례로, 본 발명에 적용되는 광반응성 폴리머 중 광반응성 폴리이미드의 경우 제1온도는 130C 제2온도는 180도 이상에서 가열하여 경화시킬 수 있다.This temperature is set in a temperature range of 50 degrees or more than the temperature of step S420, it is preferable to set below the deformation temperature of the photoreactive polymer. For example, in the photoreactive polyimide of the photoreactive polymer to be applied to the present invention, the first temperature may be cured by heating at 130 ° C. or more at 180 degrees.
도 5는 본 발명의 패시베이션 박막의 물질에 따른 MIT 소자의 특성을 측정한 그래프이다.5 is a graph measuring the characteristics of the MIT device according to the material of the passivation thin film of the present invention.
도 5의 세로축은 MIT 박막의 저항값을 MΩ 단위로 측정한 결과이고, 가로축은 패시베이션 이전(BF), 패시베이션 이후(AF)를 의미한다.5 is the result of measuring the resistance value of the MIT thin film in MΩ unit, and the horizontal axis means before passivation (BF) and after passivation (AF).
아래의 표1 내지 표3의 결과는 MIT 박막으로 이산화바나듐을 증착한 후 MIT 박막 상에 실리카(표 1), 질화실리콘(표 2) 및 광반응성 폴리이미드(표 3)을 이용하여 패시베이션 박막을 형성한 후 MIT 박막의 저항값을 측정한 결과이다.The results of Tables 1 to 3 below show that the passivation thin film was deposited using MIT thin film with vanadium dioxide and then silica (Table 1), silicon nitride (Table 2) and photoreactive polyimide (Table 3) on the MIT thin film. After the formation, the resistance value of the MIT thin film was measured.
표 1
패시베이션 전 저항값(MΩ) 패시베이션 후 저항값(MΩ) 패시베이션 전후 변화율(%)
8.5 5.3 -38
7.1 4.6 -35
11.6 7.9 -32
6.4 4.3 -33
8.5 5.5 -35
5.1 3.4 -33
Table 1
Resistance value before passivation (MΩ) Resistance after passivation (MΩ) % Change before and after passivation
8.5 5.3 -38
7.1 4.6 -35
11.6 7.9 -32
6.4 4.3 -33
8.5 5.5 -35
5.1 3.4 -33
표 2
패시베이션 전 저항값(MΩ) 패시베이션 후 저항값(MΩ) 패시베이션 전후 변화율(%)
10.5 6.0 -43
9.4 5.4 -43
12.6 5.4 -57
9.9 4.4 -56
8.4 5.7 -32
7.3 4.7 -36
TABLE 2
Resistance value before passivation (MΩ) Resistance after passivation (MΩ) % Change before and after passivation
10.5 6.0 -43
9.4 5.4 -43
12.6 5.4 -57
9.9 4.4 -56
8.4 5.7 -32
7.3 4.7 -36
표 3
패시베이션 전 저항값(MΩ) 패시베이션 후 저항값(MΩ) 패시베이션 전후 변화율(%)
7.9 7.7 -3
12.6 12.7 1
7.5 7.2 -4
11.0 11.3 3
5.1 5.0 -2
8.0 8.2 2
TABLE 3
Resistance value before passivation (MΩ) Resistance after passivation (MΩ) % Change before and after passivation
7.9 7.7 -3
12.6 12.7 One
7.5 7.2 -4
11.0 11.3 3
5.1 5.0 -2
8.0 8.2 2
상기 [표 1]은 실리카(SiO2) 를 패시베이션 박막으로 형성한 경우로서, 패시베이션 후의 저항값이 32% 에서 38% 감소함을 알 수 있다. 또한, 상기 [표 2]는 질화실리콘(Si3N4)을 패시베이션 박막으로 형성한 경우로서, 패시베이션 후의 저항값이 32%에서 57% 감소함을 알 수 있다. 반면 본 발명에 따른 광반응성 폴리머 중 광반응성 폴리이미드를 사용하여 패시베이션을 한 결과인 [표 3]을 참조하면, 패시베이션 후 MIT 박막의 저항 변화가 5% 이하로 거의 나타나지 않음을 알 수 있다.Table 1 shows a case in which silica (SiO 2) is formed as a passivation thin film, and the resistance value after passivation decreases from 32% to 38%. In addition, [Table 2] is a case where the silicon nitride (Si3N4) is formed as a passivation thin film, it can be seen that the resistance value after passivation is reduced from 32% to 57%. On the other hand, referring to [Table 3], which is the result of passivation using the photoreactive polyimide among the photoreactive polymers according to the present invention, it can be seen that the resistance change of the MIT thin film after passivation is hardly shown as 5% or less.
즉, 상기 표 1 내지 표 3 및 도 5를 참조하면, 플라즈마 화학기상방식으로 증착한 후 건식 식각하여 패시베이션 박막에 패턴을 형성한 경우(표 1, 표 2)에 비해 습식 코팅 방식으로 광반응성 폴리머를 코팅한 후 패턴을 형성한 경우(표 3)에 패시베이션 전(BF)과 패시베이션 후(AF)의 MIT 박막의 특성 변화가 더 적게 나타나는 것을 알 수 있다.That is, referring to Tables 1 to 3 and FIG. 5, the photoreactive polymer is deposited by a plasma chemical vapor deposition method and then dry etched to form a pattern on the passivation thin film (Table 1 and Table 2). In the case of forming a pattern after coating (Table 3), it can be seen that the characteristic change of the MIT thin film before the passivation (BF) and after the passivation (AF) appears less.
도 6은 서로 다른 기판 및 버퍼층을 구비한 MIT 소자의 특성을 측정한 그래프로 종래 기술인 사파이어기판(Al2O3) 상에 MIT 물질을 증착한 경우(실선)와 실리콘기판(Si) 상에 질화알루미늄(AlN) 버퍼층을 증착한 후 MIT 물질을 증착한 경우(점선)의 MIT 특성을 측정한 그래프이다.FIG. 6 is a graph measuring characteristics of an MIT device having a different substrate and a buffer layer. In the case of depositing MIT material on a sapphire substrate (Al2O3) of the prior art (solid line) and aluminum nitride (AlN) on a silicon substrate (Si), FIG. ) It is a graph measuring the MIT characteristics when the MIT material is deposited (dotted line) after depositing the buffer layer.
도면에 도시된 바와 같이 실리콘 기판에 버퍼층을 증착한 후 MIT 물질을 증착한 경우에 사파이어 기판에 증착했을 때의 전이특성과 큰 차이를 보이지 않는 반면 전이온도가 약 10도 증가하게 됨을 알 수 있다.As shown in the figure, when the MIT material is deposited after depositing the buffer layer on the silicon substrate, the transition temperature when deposited on the sapphire substrate does not show a significant difference, but the transition temperature increases about 10 degrees.
즉, 기판과 MIT 박막 사이에 버퍼층을 삽입함으로써, 가공성이 우수하고 대면적화가 용이하며 비교적 저가인 실리콘 기판을 사용하여 큰 성능 저하 없이 MIT 소자 제작이 가능하게 되는 것이고, 부가적으로 전이온도를 높임으로써 MIT 소자의 자체발열로 인한 소자의 오작동을 줄일 수 있는 것이다.In other words, by inserting a buffer layer between the substrate and the MIT thin film, it is possible to fabricate the MIT device without significant performance degradation by using a silicon substrate which is excellent in workability, easy to large area and relatively inexpensive, and additionally increases the transition temperature. As a result, malfunction of the device due to self-heating of the MIT device can be reduced.
도 7은 서로 다른 버퍼층을 구비한 MIT 소자를 90도에서 열처리 하는 시간에 따른 MIT 박막의 저항의 변화를 열처리 전 MIT 박막의 저항을 기준으로 측정한 그래프이고, 표 4는 도 7의 결과를 요약한 결과이다.FIG. 7 is a graph illustrating the change in resistance of an MIT thin film according to the time of annealing MIT devices having different buffer layers at 90 degrees based on the resistance of the MIT thin film before heat treatment, and Table 4 summarizes the results of FIG. 7. One result.
비교예 1은 사파이어 기판에 MIT 박막을 증착한 경우이고(Al2O3), 비교예 2는 실리콘 기판에 SiO2 를 버퍼층으로 증착한 후 MIT 박막을 증착한 경우이며(SiO2-Si), 실시예는 실리콘 기판에 AlN 를 버퍼층으로 증착한 후 MIT 박막을 증착한 경우이다(AlN-Si).Comparative Example 1 is a case of depositing an MIT thin film on a sapphire substrate (Al2O3), Comparative Example 2 is a case of depositing an MIT thin film after depositing SiO2 as a buffer layer on a silicon substrate (SiO2-Si), Example is a silicon substrate This is the case where MIT thin film is deposited after AlN is deposited as a buffer layer (AlN-Si).
표 4
3시간 15시간 20시간 25시간 37시간 변화율(%)
비교예 1 94% 90% 86% 86% 89% 8%
비교예 2 118% 123% 120% 122% 129% 11%
실시예 96% 99% 90% 95% 99% 9%
Table 4
3 hours 15 hours 20 hours 25 hours 37 hours % Change
Comparative Example 1 94% 90% 86% 86% 89% 8%
Comparative Example 2 118% 123% 120% 122% 129% 11%
Example 96% 99% 90% 95% 99% 9%
상기 표 4에서 보면, 비교예 1 및 실시예의 경우 열처리 시간에 따른 저항의 변화가 10% 이내로 나타나는 반면, 비교예 2의 경우에는 열처리 시간에 따른 저항의 변화폭이 10%를 초과함을 알 수 있다.In Table 4, in Comparative Example 1 and Example, the change in the resistance according to the heat treatment time appears within 10%, while in Comparative Example 2, it can be seen that the change in the resistance according to the heat treatment time exceeds 10%. .
즉, AlN 을 버퍼층으로 삽입함으로써 실리콘 기판을 이용해도 사파이어 기판을 이용했을 때와 유사한 정도의 안정적인 특성을 보이는 것이다.In other words, by inserting AlN into the buffer layer, even when using a silicon substrate, it exhibits a stable characteristic similar to that when using a sapphire substrate.
도 8은 서로 다른 버퍼층을 구비한 MIT 소자를 150도에서 열처리 하는 시간에 따른 MIT 박막의 저항의 변화를 열처리 전 MIT 박막의 저항을 기준으로 측정한 그래프이고, 표 5는 도 8의 결과를 요약한 결과이다.FIG. 8 is a graph illustrating the change in resistance of an MIT thin film according to the time of annealing MIT devices having different buffer layers at 150 degrees based on the resistance of the MIT thin film before heat treatment, and Table 5 summarizes the results of FIG. 8. One result.
비교예 1은 사파이어 기판에 MIT 박막을 증착한 경우이고(Al2O3), 비교예 2는 실리콘 기판에 SiO2 를 버퍼층으로 증착한 후 MIT 박막을 증착한 경우이며(SiO2-Si), 실시예는 실리콘 기판에 AlN 를 버퍼층으로 증착한 후 MIT 박막을 증착한 경우인 것은(AlN-Si) 도 7의 경우와 같다.Comparative Example 1 is a case of depositing an MIT thin film on a sapphire substrate (Al2O3), Comparative Example 2 is a case of depositing an MIT thin film after depositing SiO2 as a buffer layer on a silicon substrate (SiO2-Si), Example is a silicon substrate In the case of depositing AlN as a buffer layer and then depositing an MIT thin film (AlN-Si) is the same as the case of FIG.
표 5
3시간 15시간 20시간 25시간 37시간 변화율(%)
비교예 1 97% 95% 96% 93% 101% 8%
비교예 2 73% 87% 59% 56% 56% 31%
실시예 87% 93% 87% 88% 94% 7%
Table 5
3 hours 15 hours 20 hours 25 hours 37 hours % Change
Comparative Example 1 97% 95% 96% 93% 101% 8%
Comparative Example 2 73% 87% 59% 56% 56% 31%
Example 87% 93% 87% 88% 94% 7%
상기 표 5에서 보면, 비교예 1 및 실시예의 경우 열처리 시간에 따른 저항의 변화가 10% 이내로 나타나는 반면, 비교예 2의 경우에는 열처리 시간에 따른 저항의 변화폭이 30%를 초과함을 알 수 있다.In Table 5, in Comparative Example 1 and Example, the change in the resistance according to the heat treatment time appears within 10%, while in Comparative Example 2 it can be seen that the change in the resistance according to the heat treatment time exceeds 30%. .
비교예 2의 경우 90도에서 열처리 했을 경우에는 11 %의 변화율을 보였지만, 130도에서 열처리 했을 경우에는 31 %의 변화율을 보이게 된다. 즉, SiO2 를 버퍼층으로 삽입할 경우 고온에서의 안정성이 급격하게 저하됨을 알 수 있다.In Comparative Example 2, when the heat treatment at 90 degrees showed a change of 11%, the heat treatment at 130 degrees showed a change of 31%. That is, when SiO 2 is inserted into the buffer layer, it can be seen that the stability at high temperature is drastically lowered.
반면, 실시예의 경우 90도에서 열처리 했을 경우와 130도에서 열처리 했을 경우 모두 10 % 이내로 저항이 변함을 알 수 있다. 즉, 실리콘 기판을 사용하여도 AlN 버퍼층을 삽입함으로써 사파이어 기판을 사용했을 때와 유사한 정도의 변화만을 가짐을 알 수 있다.On the other hand, in the case of the heat treatment at 90 degrees in the case of the embodiment and 130 degrees can be seen that the resistance changes within 10%. That is, even when using a silicon substrate, it can be seen that by inserting the AlN buffer layer, only a change similar to that when using the sapphire substrate is obtained.
이상에서 설명된 본 발명이 속한 당해 기술 분야에서 통상의 지식을 지닌 자가 본 발명을 용이하게 이해하고 재현할 수 있도록 도면에 도시한 실시예들을 참고로 설명되었으나 이는 예시적인 것에 불과하며, 당해 기술 분야에 통상의 지식을 지닌 자라면 본 발명의 실시 예들로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. 여기서 특정한 용어들이 사용되었으나, 이는 단지 당업자에게 본 발명을 상세히 설명하기 위한 목적에서 사용된 것이지 의미 한정이나 특허청구범위에 기재된 본 발명의 범위를 제한하기 위해 사용된 것이 아니다.The present invention has been described with reference to the embodiments shown in the drawings so that those skilled in the art to which the present invention as described above belongs can easily understand and reproduce the present invention. Those skilled in the art will appreciate that various modifications and equivalent other embodiments are possible from the embodiments of the present invention. Although specific terms have been used herein, they are used only for the purpose of describing the present invention in detail to those skilled in the art, and are not used to limit the scope of the present invention as defined in the meaning or claims.
본 발명은 기판 상에 버퍼층을 증착한 후 MIT 소자를 제작함으로써 안정성이 우수하며 전이온도를 높일 수 있는 MIT 소자를 제작할 수 있으며, 패시베이션 박막의 증착과정에서 발생되는 고온과 플라즈마 및 건식 식각 공정으로 인한 MIT 박막의 특성 변화를 방지하기 위한 패시베이션 박막을 형성할 수 있는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자에 관한 것으로서 산업상 이용 가능성이 존재함.According to the present invention, an MIT device can be fabricated by depositing a buffer layer on a substrate and then fabricating an MIT device, which is excellent in stability and can increase a transition temperature, and is caused by a high temperature, plasma and dry etching process generated during the deposition of a passivation thin film. The present invention relates to an MIT device having a buffer layer and a passivation thin film capable of forming a passivation thin film for preventing the characteristic change of the MIT thin film.

Claims (16)

  1. 실리콘 기판;Silicon substrates;
    상기 기판 상에 증착되는 버퍼층; 및A buffer layer deposited on the substrate; And
    특성이 변화하는 임계점을 가지는 박막;A thin film having a threshold point at which characteristics change;
    을 포함하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.MIT device having a buffer layer and a passivation thin film comprising a.
  2. 청구항 1에 있어서, 상기 임계점을 가지는 박막은,The method according to claim 1, wherein the thin film having a critical point,
    재료에 의해 정해지는 임계온도에서 금속-절연체 전이(MIT) 현상을 일으키는 MIT 박막인 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.An MIT device having a buffer layer and a passivation thin film, characterized in that it is an MIT thin film which causes a metal-insulator transition (MIT) phenomenon at a critical temperature determined by a material.
  3. 청구항 2에 있어서,The method according to claim 2,
    상기 임계점을 가지는 박막 상에 광반응성 폴리머로 이루어지는 패시베이션 박막을 더 포함하는 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.A MIT device having a buffer layer and a passivation thin film, further comprising a passivation thin film made of a photoreactive polymer on the thin film having the critical point.
  4. 청구항 3에 있어서, 상기 광반응성 폴리머는,The method according to claim 3, wherein the photoreactive polymer,
    광반응성 폴리이미드인 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.An MIT device comprising a buffer layer and a passivation thin film, characterized in that the photoreactive polyimide.
  5. 청구항 1 내지 청구항 4중 어느 한 항에 있어서, 상기 MIT 박막은,The method according to any one of claims 1 to 4, wherein the MIT thin film,
    패턴이 형성되는 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.An MIT device having a buffer layer and a passivation thin film, characterized in that the pattern is formed.
  6. 청구항 5에 있어서, 상기 버퍼층은,The method according to claim 5, wherein the buffer layer,
    질화알루미늄 (AlN) 인 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.An MIT device having a buffer layer and a passivation thin film, characterized in that it is aluminum nitride (AlN).
  7. 청구항 5에 있어서, 상기 MIT 박막은,The method according to claim 5, wherein the MIT thin film,
    KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO로 이루어진 그룹 중 적어도 하나를 포함하는 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.MIT device comprising a buffer layer and a passivation thin film comprising at least one of a group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO .
  8. 실리콘 기판을 세정하는 단계;Cleaning the silicon substrate;
    상기 기판의 일측면에 AlN 버퍼층을 증착하는 단계; 및Depositing an AlN buffer layer on one side of the substrate; And
    상기 버퍼층에 MIT 박막을 증착하는 단계;Depositing an MIT thin film on the buffer layer;
    를 포함하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자MIT device having a buffer layer and a passivation thin film comprising a
  9. 청구항 8에 있어서, 상기 버퍼층을 증착하는 단계는,The method of claim 8, wherein depositing the buffer layer comprises:
    스퍼터링 (sputtering), 증발증착 (Evaporation), 전자빔증착(e-beam evaporation), 화학기상증착 (Chemical Vapor Deposition), 레이저증착 (Pulsed Laser Deposition) 중 어느 하나의 방법으로 증착하는 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.Buffer layer characterized in that the deposition by any one of sputtering, evaporation (evaporation), e-beam evaporation (e-beam evaporation), chemical vapor deposition (Pulsed Laser Deposition) and MIT device with passivation thin film.
  10. 청구항 8에 있어서, 상기 MIT 박막은,The method according to claim 8, wherein the MIT thin film,
    KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO로 이루어진 그룹 중 적어도 하나를 포함하는 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.MIT device comprising a buffer layer and a passivation thin film comprising at least one of a group consisting of KTaO3, Na-doped WO3, TiAlO, NiO, V2O3, VO2, TiO2, BaTiO3, ZrO2, Nb2O5, SrTiO3, TiAlO, ZrAlO .
  11. 청구항 8에 있어서, 상기 MIT 박막을 증착하는 단계는,The method of claim 8, wherein the depositing the MIT thin film,
    스퍼터링 (sputtering), 증발증착 (Evaporation), 전자빔증착(e-beam evaporation), 레이저증착 (PLD, Pulsed Lase Deposition) 과 같은 물리기상증착 (PVD, Physical Vapor Deposition) 또는 PECVD (Plasma-Enhanced CVD), APCVP (Atmospheric Pressure CVD), LPCVD (Low Pressure CVD), HDPCVD (High Density Plasma CVD)와 같은 화학기상증착 (CVD, Chemical Vapor Deposition) 중 어느 하나의 방법을 사용하여 증착하는 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.Physical Vapor Deposition (PVD) or Plasma-Enhanced CVD (PECVD), such as sputtering, evaporation, e-beam evaporation, pulsed lase deposition (PLD), Buffer layer and passivation, characterized in that the deposition using any one method of Chemical Vapor Deposition (CVD), such as Atmospheric Pressure CVD (APCVP), Low Pressure CVD (LPCVD), High Density Plasma CVD (HDPCVD) MIT device with a thin film.
  12. 청구항 8에 있어서,The method according to claim 8,
    상기 MIT 박막에 패턴을 형성하여 소자를 제작하는 단계를 더 포함하는 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자MIT device having a buffer layer and a passivation thin film further comprising the step of forming a pattern on the MIT thin film to fabricate the device
  13. 청구항 8에 있어서,The method according to claim 8,
    상기 MIT 박막 상에 광반응성 폴리머를 코팅하는 단계;Coating a photoreactive polymer on the MIT thin film;
    상기 광반응성 폴리머를 제1 온도로 가열하여 경화시키는 단계;Curing the photoreactive polymer by heating to a first temperature;
    상기 경화된 광반응성 폴리머 박막에 패턴이 형성된 마스크를 접촉시킨 후 자외선을 노광하여 상기 패턴을 상기 폴리머 박막에 전사시키는 단계;Contacting the cured photoreactive polymer thin film with a patterned mask and then exposing ultraviolet light to transfer the pattern to the polymer thin film;
    상기 패턴이 전사된 폴리머 박막을 현상하여 상기 폴리머 박막에 패턴을 형성하는 단계; 및Developing the polymer thin film to which the pattern has been transferred to form a pattern on the polymer thin film; And
    상기 패턴이 형성된 폴리머 박막을 제2 온도로 가열하여 경화시키는 단계;Curing the patterned polymer thin film by heating to a second temperature;
    를 포함하는 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.MIT device having a buffer layer and a passivation thin film comprising a.
  14. 청구항 13에 있어서, 상기 광반응성 폴리머를 코팅하는 단계 및 상기 패턴을 전사하는 단계 및 상기 패턴을 형성하는 단계는,The method of claim 13, wherein coating the photoreactive polymer and transferring the pattern and forming the pattern,
    상기 임계온도 이하에서 이루어지는 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.An MIT device having a buffer layer and a passivation thin film, characterized in that it is made below the critical temperature.
  15. 청구항 8 내지 청구항 14 중 어느 한 항에 있어서, 상기 광반응성 폴리머는,The method according to any one of claims 8 to 14, wherein the photoreactive polymer,
    광반응성 폴리이미드 인 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.An MIT device comprising a buffer layer and a passivation thin film, characterized in that the photoreactive polyimide.
  16. 청구항 15에 있어서, 상기 제1온도는,The method of claim 15, wherein the first temperature is,
    130도 이하이고,130 degrees or less,
    상기 제2 온도는,The second temperature is,
    상기 제1 온도보다 50도 이상인 것을 특징으로 하는 버퍼층 및 패시베이션 박막을 구비한 MIT 소자.An MIT device having a buffer layer and a passivation thin film, characterized in that more than 50 degrees above the first temperature.
PCT/KR2014/012548 2014-11-18 2014-12-18 Mit device having buffer layer and passivation thin film WO2016080584A1 (en)

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KR10-2014-0160655 2014-11-18
KR1020140160655A KR101684643B1 (en) 2014-11-18 2014-11-18 Passivation Method of Metal-Insulator Transition(MIT) Thin Film
KR10-2014-0179228 2014-12-12
KR1020140179228A KR20160071720A (en) 2014-12-12 2014-12-12 Metal-insulator transition(MIT) device comprising buffer layer

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