WO2016079406A1 - Integrated circuit with power switching structure - Google Patents

Integrated circuit with power switching structure Download PDF

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Publication number
WO2016079406A1
WO2016079406A1 PCT/FR2015/053090 FR2015053090W WO2016079406A1 WO 2016079406 A1 WO2016079406 A1 WO 2016079406A1 FR 2015053090 W FR2015053090 W FR 2015053090W WO 2016079406 A1 WO2016079406 A1 WO 2016079406A1
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WO
WIPO (PCT)
Prior art keywords
transistors
transistor
integrated circuit
conduction
conduction electrode
Prior art date
Application number
PCT/FR2015/053090
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French (fr)
Inventor
René Escoffier
Anthony BIER
Charlotte Gillot
Jérémy MARTIN
Original Assignee
Commissariat à l'énergie atomique et aux énergies alternatives
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Publication of WO2016079406A1 publication Critical patent/WO2016079406A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV

Definitions

  • the invention relates to power switching and in particular to integrated circuits intended to perform voltage switching or current switching, and comprising at least one bidirectional operation in voltage or current.
  • Such switches require a power switch to be associated with a diode.
  • the switch is generally made in the form of field-effect or junction silicon transistor, depending on the desired current density.
  • the diodes induce considerable voltage drops and energy losses.
  • SiC-type diodes can not be cointegrated with power transistors, which requires the use of two separate components. The combination of two components induces a significant bulk and losses of energy at the connections between these components.
  • US2013 / 002336 discloses a switch using diode connected transistors. Generating gate control voltages from a reference potential can be problematic for such a switch.
  • the invention aims to solve one or more of these disadvantages.
  • the invention further aims to facilitate the design and cointegration of power switches, regardless of its mode of operation, bidirectional current or voltage.
  • FIG 1 is a schematic illustration of an embodiment of a switching integrated circuit according to the invention
  • FIG. 2 is a diagrammatic sectional view of an exemplary HEMT transistor that can be used for an integrated switching circuit according to the invention
  • FIG. 3 is a voltage / current diagram of an example of a transistor
  • FIG. 4 is a top view of a first example of a topography for the switching integrated circuit of FIG. 1;
  • FIG. 5 is a top view of a second example of a topography for the integrated switching circuit of FIG. Figure 1;
  • FIG. 6 is a view from above of a third topography example for the switching integrated circuit of FIG. 1;
  • FIGS. 7 to 9 are partial sectional views of an exemplary HEMT transistor at different stages of an example of a manufacturing method
  • FIGS. 10 to 14 are partial sectional views of an example of an integrated circuit according to FIG. 1, at different stages of an example of a manufacturing method
  • FIGS. 15 and 16 are schematic representations of examples of simplified functions that can be implemented via an integrated switching circuit according to the invention.
  • the invention proposes an integrated circuit comprising a switching circuit.
  • This switching circuit comprises four field effect heterojunction transistors connected in two branches between an input and a power output.
  • a field effect heterojunction transistor of each branch is diode-mounted, the diodes of the two branches being mounted in antiparallel.
  • the invention allows to cointegrate in the same chip a power switch function with a diode to obtain bidirectional operation current and / or voltage. This cointegration makes it possible to limit the losses in the connections, to considerably reduce the size of the switch obtained, and to limit the conduction losses in the diode.
  • the same component structure can be used for different functions, even without using all the transistors of a cell, while still maintaining a small footprint.
  • the use of the same component structure for different functions also makes it easier to design the topographies of integrated circuits from the same standard cell.
  • Such transistors are particularly suitable for power applications, since they have a breakdown voltage. high, with a reduced conduction resistance and a potentially high current density.
  • FIG. 1 is a schematic illustration of an embodiment of an integrated circuit comprising a switching circuit 1.
  • the switching circuit 1 comprises first to fourth field effect heterojunction transistors 1 1 to 14.
  • the transistor 1 1 and the transistor 14 are connected by respective first conduction electrodes at a power connection pad of the switching circuit 1.
  • Transistor 12 and transistor 13 are connected by respective second conduction electrodes at a power connection pad of switching circuit 1.
  • a second conduction electrode of the transistor 1 1 and a first conduction electrode of the transistor 12 are connected.
  • a second conduction electrode of transistor 14 and a first conduction electrode of transistor 13 are connected.
  • the switching circuit 1 thus comprises a first branch including the transistors 1 1 and 12, and a second branch including the transistors 13 and 14. Each branch thus comprises a respective diode, these diodes being connected in anti-parallel.
  • the control gates of the transistors 12 and 14 are electrically connected by the node 17.
  • This electrical connection connects the second electrodes of the transistors 1 1 and 14, as well as the first electrodes of the transistors 12 and 13.
  • This electrical connection makes it possible in particular to obtain a potential reference for the transistors 12 and 14 mounted in diode. In addition, such a connection makes it possible to increase the current density in conduction through the switching circuit 1.
  • the conduction state of transistors 11 and 13 may be controlled by a control circuit not shown. Since the polarization of the control gates of the transistors 1 1 and 13 is effected by relative potentials with respect to the connection node between the transistors 1 1 to 14, this polarization is carried out by an isolated power supply with respect to the potentials applied to the nodes 15 and 16 and with respect to the potential of the node 17, in order to avoid any current flow in the control circuit via this connection node 17. According to a variant, in replacement of the transistor 14, the transistor 13 can be connected so as to form an antiparallel diode of the transistor 12 connected diode.
  • switching circuit 1 may include heterojunction field effect transistors with high hole mobility, the invention advantageously utilizes high electron mobility heterojunction field effect transistors to provide greater current density. .
  • FIG. 2 is a schematic figure of an example of a HEMT transistor 18, that is to say a high electron mobility field effect transistor.
  • the transistor 18 comprises a silicon substrate 181, typically having P-type doping but which can also not be doped.
  • a semiconductor layer 182 made of a nitride of a type III element (for example GaN) is formed above the substrate 181.
  • a semiconductor layer, called a barrier, of a ternary alloy of a nitride of a type III element (for example AIGaN) 183 is formed above the layer 182.
  • a layer of electron gas 184 is intrinsically formed at the interface between the layer 182 and the layer 183.
  • the transistor 18 includes a first conduction electrode 186 and a second conduction electrode 187, between which a current must selectively be established.
  • the electrodes 186 and 187 are formed in a known manner in the form of ion implantation or metal diffusion.
  • the transistor 18 further comprises a control gate 188, the control potential of which defines whether the transistor 18 is on or off.
  • the electrodes 186 and 187 and the gate 188 are formed above the layer 183.
  • the layer 184 comprises a zone 185 in line with the gate 188.
  • the zone 185 is made selectively conductive or insulating according to the applied voltage on the gate 188.
  • the zone 185 makes this transistor is normally open, or normally closed, depending on the insulating or conducting state of the zone 185 in the absence of polarization of the gate 188.
  • the transistor 18 is isolated from other electronic components through insulation trenches not shown.
  • heterojunction transistor of AIGaN type Although a particular case of a heterojunction transistor of AIGaN type has been described, other structures such as GaAlAs / GaAs or GaAlAs (N +) / In GaAs (n.d) / GaAs can of course also be envisaged.
  • Transistors 12 and 14 are of normally open type so that they can be diode connected.
  • FIG. 3 is an example of a voltage / current diagram of such a HEMT type transistor.
  • a transistor type normally open has a positive threshold voltage Vth.
  • this threshold voltage is less than or equal to 1 V in order to limit the switching losses in the switching circuit 1.
  • this threshold voltage is at least equal to 0.2 V, or at least equal to 0.4 V to avoid unwanted conduction in reverse of the diodes formed.
  • heterojunction transistors of normally open type are known per se to those skilled in the art, for example by techniques known as partial or complete etching of the layer 183, ion implantation of fluorine, formation of a p- (AI) GaN gate or the formation of a back gate.
  • FIG. 4 is a view from above of an exemplary topography of the switching circuit 1 of the embodiment of FIG. 1.
  • Transistors 1 1 and 14 are connected by their first conductive electrodes 1 1 1 and 141, referred to herein as their respective drains.
  • the electrodes 11 and 141 are connected to a power connection pad 15.
  • the transistors 12 and 13 are connected by their second conductive electrodes 122 and 132, designated here as their respective drains.
  • the electrodes 122 and 132 are connected to a power connection pad 16.
  • the second conductive electrode of the transistor 1 1 and the first conductive electrode of the transistor 12 are combined, in the form of a common electrode 1 12 designated as their source.
  • the second conductive electrode of the transistor 14 and the first conductive electrode of the transistor 13 are combined in the form of a common electrode 131 designated as their source.
  • a control connection pad 1 14 is connected to the gate 1 13 of the transistor 1 1.
  • a control connection pad 134 is connected to the gate 133 of the transistor 13.
  • the first and second transistors 1 1 and 12 include the same first heterojunction band 171, corresponding to the first branch.
  • the third and fourth transistors 13 and 14 include the same second heterojunction band 172, corresponding to the second branch.
  • the heterojunction bands 171 and 172 are separated by an insulating strip 173.
  • the power connection pads 15 and 16 are positioned from the side with respect to the insulating strip 173 and with respect to the heterojunction strips 171 and 172.
  • the control connection pads 1 and 4 are positioned on the opposite side to the pads. and 16, with respect to the insulating strip 173 and with respect to the heterojunction strips 171 and 172.
  • the electrical connection between the control gates 123 and 143 is made in particular by means of a conductive element 193 extending vertically above the insulating strip 173 and connecting the electrodes 1 12 and 131.
  • This conductive element 193 is here positioned in the middle position between the transistors 1 1 to 14 and therefore only slightly affects the size of the switching circuit 1.
  • a conductive element 191 extends vertically above the insulating strip 173 and connects the electrodes 122 and 132;
  • a conductive element 192 extends vertically above the insulating strip 173 and connects the electrodes 11 1 and 141.
  • the electrode 1 12 is connected to the control gate 123 via a conductive element 194.
  • the conductive element 194 is here offset laterally with respect to the heterojunction band 171, on the same side as the pins of FIG. connection 15 and 16.
  • the electrode 131 is connected to the control gate 143 via a conductive element 195.
  • the conductive element 195 is here offset laterally with respect to the heterojunction band 172, on the same side that the connection pads 1 14 and 134.
  • connection pad 1 14 is connected to the control gate 1 13 via a conductive element 196 extending vertically above the insulating strip 173 and the heterojunction band 172.
  • a stud connection 101 allows to apply a reference potential on the conductive element 194, without being traversed by the current between the connection pads 15 and 16.
  • the conduction state of the transistors 11 and 13 may be controlled by a control circuit 2.
  • This control circuit 2 selectively applies a potential generated by a supply (not shown) isolated from the connection pads 15 and 16.
  • the polarization of the control gates of the transistors 1 1 and 13 is effected by relative potentials with respect to the connection node between the transistors 1 1 to 14 (potential of the connection pad 101). This makes it possible to avoid any passage of power current in the control circuit 2 or the power supply.
  • the illustrated configuration of the switching circuit 1 thus proves to be particularly compact, makes it possible to limit as far as possible the lengths of the connections between the transistors 1 1 to 14, and makes it possible to reduce to only two the number of ohmic contacts between the connection pads 15 and 16, while providing a four-quadrant switching structure.
  • the conductive elements 191 to 196 may advantageously be made by respective metal deposits.
  • the control gates 1 13, 123, 133 and 143 may for example be made directly on the semiconductor (for example on a layer of AIGaN) to form a Schottky gate contact or on an insulator to form a contact of grid type MIS.
  • the control grids 1 13, 123, 133 and 143 may for example have a width of between 0.5 and 2 ⁇ .
  • the dimensions of the electrodes 1 1 1, 141, 122 and 132 are for example fixed as a function of the current density to pass through the circuit switching 1.
  • FIG. 5 illustrates a variant of the topography of the embodiment of FIG. 1 of the switching circuit 1.
  • This variant advantageously makes it possible to use an intermediate node of the branches of the circuit 1 in order to have another power connection pad making it possible to short-circuit certain functions.
  • This variant makes it possible to have a gate reference potential making it possible to drive transistors 1 1 and 13.
  • power connection pads 101 and 102 are respectively connected to conducting elements 194 and 195.
  • a control circuit 2 selectively applies on the pads 1 14 and 134 a potential generated by a power supply (not shown) isolated from the connection pads 15 and 16 and relative to the power connection pads 101 and 102. This makes it possible to avoid any passage of power in the control circuit 2 or the power supply.
  • FIG. 6 illustrates another variant of the topography of the embodiment of FIG. 1 of the switching circuit 1.
  • This variant advantageously makes it possible to increase the integration density of the switching circuit 1. Unlike the other variants, it is not necessary here to provide an insulation strip between two heterojunction strips. This variant is particularly suitable for HEMT transistors.
  • the transistors 1 1 and 14 are connected by a common conductive electrode 1 1 1, designated here as their respective drain.
  • the common electrode 1 1 1 is connected to a power connection pad 15.
  • the transistors 12 and 13 are connected by their second conductive electrodes 122 and 132, designated here as their respective drains.
  • the electrodes 122 and 132 are connected via respective power connection pads 161 and 162 interconnected.
  • the second conductive electrode of the transistor 1 1 and the first conductive electrode of the transistor 12 are combined, in the form of a common electrode 1 12 designated as their source.
  • the second electrode conductive transistor 14 and the first conductive electrode of the transistor 13 are combined, in the form of a common electrode 131 designated as their source.
  • a control connection pad 1 14 is connected to the gate 123 of the transistor 12.
  • a control connection pad 134 is connected to the gate 133 of the transistor 13.
  • a conductive element 197 connects the source 1 12, the gate 143 and the source 131.
  • a connection pad 101 is connected to this conductive element 197.
  • the connection pad 101 makes it possible to apply a reference potential to the conductive element 197, without the current flowing between the connection pads 15 and 16.
  • the first through fourth transistors 11 to 14 include the same heterojunction band 170.
  • the switching circuit 1 can thus have a very high integration density.
  • the power connection pads 15, 161, 162, 14 and 134 are positioned on the same side with respect to the heterojunction band 170.
  • the conduction state of transistors 1 1 and 13 may be controlled by a control circuit 2.
  • This control circuit 2 selectively applies, on pads 1 13 and 134, a potential generated by a power supply (not illustrated) isolated relative to to the connection pads 15, 161 and 162.
  • the polarization of the control gates of the transistors 1 1 and 13 is effected by potentials relative to the potential of the pad 101. This makes it possible to avoid any passage of power current in the control circuit 2 or the power supply.
  • Such a switching circuit 1 can be used for functions known per se of four-quadrant switch. Such a switching circuit 1 can be used even only for part of these functionalities.
  • Such a switching circuit 1 may, for example, be used as a bidirectional current and unidirectional voltage switch, for example corresponding to the block diagram illustrated in FIG. 15.
  • Such a switch is used, for example, in inverter switching cells. voltage for three-phase current.
  • a switching circuit 1 as illustrated in FIG. 1 it is possible, for example, to form the antiparallel diode by means of the transistor 14, to form the switch function via the transistor 11, and to carry out a bidirectional conduction by through the transistor 13 kept closed.
  • Such a switching circuit 1 can also be used as bidirectional switch in voltage and monodirectional in current, corresponding for example to the block diagram illustrated in FIG. 16.
  • Such a switch can also be used in an inverter in order to form a spontaneous blocking blocking a return current from a powered load.
  • a switching circuit 1 as illustrated in FIG. 1 it is possible, for example, to form the antiparallel diode by means of the transistor 14, to form the switch function via the transistor 11, to form the series diode by means of FIG. intermediate of the transistor 12 and keep the transistor 13 open.
  • Figures 7 to 9 are sectional views of a HEMT transistor 1 1 at different stages of an exemplary manufacturing method. Figures 7 to 9 partially illustrate the transistor 1 1 at its gate and its source.
  • a substrate 181 on which a semiconductor layer 182 of binary alloy of a nitride of a type III element (for example GaN ) is spared.
  • a barrier semiconductor layer of ternary alloy of a nitride of a type III element (for example AIGaN) 183 is formed above the layer 182.
  • a layer of electron gas 184 is intrinsically formed. at the interface between the layer 182 and the layer 183.
  • An insulator layer 153 is formed on the layer 183 and has been shaped to have through holes at the source, the drain and the gate of the transistor 1 1.
  • a groove 154 is formed in particular at the level of the grid to be formed.
  • the groove 154 has for example a width between 0.25 and 2 ⁇ .
  • the insulating layer 153 is for example formed of silicon nitride.
  • Metal deposits 151 are shaped and are in contact with the layer 183 at the source and the drain.
  • the metal deposits 151 have for example a thickness of 100 nm and a width of between 4 and 20 ⁇ .
  • the width of the insulating layer 153 between the groove 154 and the metal deposit 151 of the source is for example of the order of 1 ⁇ .
  • a gate oxide layer 152 is deposited full plate.
  • the gate oxide layer 152 may be deposited by an atomic layer deposition (ALD) method.
  • the gate oxide layer 152 is for example made of Al 2 O 3.
  • the gate oxide layer 152 may typically have a thickness of the order of 10 nm.
  • the layer 152 is shaped for example by photolithography, to keep it in the groove 154 and remove it at the other areas.
  • the layer 152 can then be annealed, for example at 650 ° in the presence of dinitrogen. The structure is thus obtained as illustrated in FIG. 8.
  • an interfacial metal deposit is produced, for example of Ti or TiN.
  • This deposit may for example be made on a thickness of 100 nm.
  • This deposit may for example be made by physical vapor deposition;
  • a metal deposit is made for the various electrodes, for example made of tungsten.
  • This deposit may for example be made to a thickness of between 200 and 400 nm.
  • This deposit can for example be made by chemical vapor deposition;
  • the metal deposits are shaped to give them the shape of the different electrodes. This shaping is for example carried out by photolithography. The structure is thus obtained as illustrated in FIG. 9 on which the source 1 12 and the grid 1 13 can be distinguished.
  • Figures 10 to 14 are sectional views of a switching circuit according to the embodiment at different stages of an exemplary manufacturing method. The cut is made here at the electrode 1 12, the electrode 131 and the conductive element 193 of the switching circuit 1 to form.
  • substrate 181 is available here, on which the semiconductor layer 182 made of a nitride of a type III element (for example GaN) is formed.
  • the barrier semiconductor layer of ternary alloy of a nitride of a type III element (for example AIGaN) 183 is formed above the layer 182.
  • the electron gas layer 184 is intrinsically formed at the interface between the layer 182 and the layer 183.
  • the insulating layer 153 is formed on the layer 183.
  • the insulating layer 153 has been shaped to form a through hole 155 to the layer 183.
  • the electrodes 1 12 and 131 have been formed by metal deposits in electrical contact with the layer 183 at the orifice 155. After forming the metal deposits, the electrodes 1 12 and 131 are separated by a throat 156.
  • a deposit of an insulating layer 157 is made to cover the electrodes 1 12 and 131, and to fill the groove 156.
  • An insulating separation 173 is formed between the electrodes 1 12 and 131.
  • the insulating layer 157 has been shaped by photolithography, then a deposit and a shaping of a metal (for example of the AlCu type) have been made, in order to form a conducting element 193 overhanging the separation. insulating 173 and joining the electrodes 1 12 and 131.
  • connection or interconnections of the electrodes 1 12 and 131 has not been illustrated.
  • preliminary steps for etching the AIGaN layer 183 associated or not with a implantation of dopants under zone 185 may be carried out prior to deposition of the gate oxide layer 152.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Engineering & Computer Science (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to an integrated circuit (1) comprising a switching circuit, characterized in that it comprises: - a first branch including first and second transistors (11, 12); - a second branch including third and fourth transistors (13, 14), said first to fourth transistors being field effect heterojunction transistors; - said second and fourth transistors being of the normally-open type, - the first conduction electrode of the second transistor being connected to the second conduction electrode of the fourth transistor, the control gate of the second transistor being connected to the control gate of the fourth transistor, in such a way as to form a diode in the first and second branches, such that the diodes formed in the first and second branches are in anti-parallel; - a power supply insulated from the first conduction electrodes of the first and fourth transistors and from the second conduction electrodes of the second and third transistors; - and a control circuit (2) configured to selectively apply the potential generated by the power supply to the control gates of the first and third transistors (11, 13).

Description

CIRCUIT INTEGRE A STRUCTURE DE COMMUTATION DE  INTEGRATED CIRCUIT WITH SWITCHING STRUCTURE
PUISSANCE  POWER
L'invention concerne la commutation de puissance et en particulier les circuits intégrés destinés à réaliser une commutation en tension ou une commutation en courant, et comportant au moins un fonctionnement bidirectionnel en tension ou en courant.  The invention relates to power switching and in particular to integrated circuits intended to perform voltage switching or current switching, and comprising at least one bidirectional operation in voltage or current.
Pour des raisons de coût, de compacité et de fréquence d'utilisation, de nombreux composants de commutation de puissance sont réalisés à partir de composants semi-conducteurs.  For reasons of cost, compactness and frequency of use, many power switching components are made from semiconductor components.
De nombreuses applications de puissance, par exemple la réalisation d'onduleurs triphasés, font appel à des commutateurs de puissance ayant un fonctionnement bidirectionnel en tension ou en courant, ou bidirectionnel en tension et en courant.  Many power applications, for example the realization of three-phase inverters, use power switches having bi-directional operation in voltage or current, or bidirectional in voltage and current.
De tels commutateurs nécessitent d'associer un interrupteur de puissance à une diode. L'interrupteur est généralement réalisé sous forme de transistor Silicium à effet de champ ou à jonction, en fonction de la densité de courant souhaitée. A haut niveau de puissance et à fréquences de commutation élevées, les diodes induisent des chutes de tension et des déperditions d'énergie considérables. Pour limiter ces pertes, il est usuel d'utiliser des diodes de type SiC. Cependant, des diodes de type SiC ne peuvent pas être cointégrées avec des transistors de puissance, ce qui impose d'utiliser deux composants distincts. La combinaison de deux composants induit un encombrement non négligeable et des déperditions d'énergie au niveau des connexions entre ces composants.  Such switches require a power switch to be associated with a diode. The switch is generally made in the form of field-effect or junction silicon transistor, depending on the desired current density. At high power levels and high switching frequencies, the diodes induce considerable voltage drops and energy losses. To limit these losses, it is customary to use SiC-type diodes. However, SiC-type diodes can not be cointegrated with power transistors, which requires the use of two separate components. The combination of two components induces a significant bulk and losses of energy at the connections between these components.
Le document US2013/002336 décrit un commutateur utilisant des transistors connectés en diode. La génération de tensions de commande de grille à partir d'un potentiel de référence peut s'avérer problématique pour un tel commutateur.  US2013 / 002336 discloses a switch using diode connected transistors. Generating gate control voltages from a reference potential can be problematic for such a switch.
L'invention vise à résoudre un ou plusieurs de ces inconvénients. L'invention vise en outre à faciliter la conception et la cointégration de commutateurs de puissance, quel que soit son mode de fonctionnement, bidirectionnel en courant ou en tension.  The invention aims to solve one or more of these disadvantages. The invention further aims to facilitate the design and cointegration of power switches, regardless of its mode of operation, bidirectional current or voltage.
L'invention porte ainsi sur un circuit intégré comprenant un circuit de commutation, tel que défini dans les revendications annexées. L'homme du métier comprendra que chaque caractéristique des revendications dépendantes peut être combinée indépendamment aux caractéristiques de la revendication 1 sans constituer une généralisation intermédiaire.  The invention thus relates to an integrated circuit comprising a switching circuit, as defined in the appended claims. Those skilled in the art will appreciate that each feature of the dependent claims may be independently combined with the features of claim 1 without constituting an intermediate generalization.
D'autres caractéristiques et avantages de l'invention ressortiront clairement de la description qui en est faite ci-après, à titre indicatif et nullement limitatif, en référence aux dessins annexés, dans lesquels : -la figure 1 est une illustration schématique d'un mode de réalisation d'un circuit intégré de commutation selon l'invention ; Other characteristics and advantages of the invention will emerge clearly from the description which is given hereinafter, by way of indication and in no way limitative, with reference to the appended drawings, in which: FIG 1 is a schematic illustration of an embodiment of a switching integrated circuit according to the invention;
-la figure 2 est une vue en coupe schématique d'un exemple de transistor HEMT utilisable pour un circuit intégré de commutation selon l'invention ;  FIG. 2 is a diagrammatic sectional view of an exemplary HEMT transistor that can be used for an integrated switching circuit according to the invention;
-la figure 3 est un diagramme tension/courant d'un exemple de transistor FIG. 3 is a voltage / current diagram of an example of a transistor
HEMT utilisé pour former une diode ; HEMT used to form a diode;
-la figure 4 est une vue de dessus d'un premier exemple de topographie pour le circuit intégré de commutation de la figure 1 ;-la figure 5 est une vue de dessus d'un deuxième exemple de topographie pour le circuit intégré de commutation de la figure 1 ;  FIG. 4 is a top view of a first example of a topography for the switching integrated circuit of FIG. 1; FIG. 5 is a top view of a second example of a topography for the integrated switching circuit of FIG. Figure 1;
-la figure 6 est une vue de dessus d'un troisième exemple de topographie pour le circuit intégré de commutation de la figure 1 ;  FIG. 6 is a view from above of a third topography example for the switching integrated circuit of FIG. 1;
-les figures 7 à 9 sont des vues en coupe partielle d'un exemple de transistor HEMT à différentes étapes d'un exemple de procédé de fabrication ;  FIGS. 7 to 9 are partial sectional views of an exemplary HEMT transistor at different stages of an example of a manufacturing method;
-les figures 10 à 14 sont des vues en coupe partielle d'un exemple de circuit intégré selon la figure 1 , à différentes étapes d'un exemple de procédé de fabrication ;  FIGS. 10 to 14 are partial sectional views of an example of an integrated circuit according to FIG. 1, at different stages of an example of a manufacturing method;
-les figures 15 et 16 sont des représentations schématiques d'exemples de fonctions simplifiées pouvant être mises en œuvre par l'intermédiaire d'un circuit intégré de commutation selon l'invention.  FIGS. 15 and 16 are schematic representations of examples of simplified functions that can be implemented via an integrated switching circuit according to the invention.
L'invention propose un circuit intégré comprenant un circuit de commutation. Ce circuit de commutation comprend quatre transistors à heterojonction à effet de champ connectés selon deux branches entre une entrée et une sortie de puissance. Un transistor à heterojonction à effet de champ de chaque branche est monté en diode, les diodes des deux branches étant montées en anti parallèle. The invention proposes an integrated circuit comprising a switching circuit. This switching circuit comprises four field effect heterojunction transistors connected in two branches between an input and a power output. A field effect heterojunction transistor of each branch is diode-mounted, the diodes of the two branches being mounted in antiparallel.
L'invention permet de cointégrer dans une même puce une fonction interrupteur de puissance avec une diode pour obtenir un fonctionnement bidirectionnel en courant et/ou en tension. Cette cointégration permet de limiter les pertes dans les connexions, de réduire considérablement l'encombrement du commutateur obtenu, et de limiter les pertes de conduction dans la diode.  The invention allows to cointegrate in the same chip a power switch function with a diode to obtain bidirectional operation current and / or voltage. This cointegration makes it possible to limit the losses in the connections, to considerably reduce the size of the switch obtained, and to limit the conduction losses in the diode.
De plus, une même structure de composant peut être utilisée pour différentes fonctions, même en n'utilisant pas tous les transistors d'une cellule, en conservant malgré tout un encombrement réduit. L'utilisation d'une même structure de composant pour différentes fonctions permet en outre de faciliter la conception des topographies de circuits intégrés à partir d'une même cellule standard.  In addition, the same component structure can be used for different functions, even without using all the transistors of a cell, while still maintaining a small footprint. The use of the same component structure for different functions also makes it easier to design the topographies of integrated circuits from the same standard cell.
En outre, de tels transistors sont particulièrement adaptés pour des applications de puissance, puisqu'ils présentent une tension de claquage élevée, avec une résistance de conduction réduite et une densité de courant potentiellement élevée. In addition, such transistors are particularly suitable for power applications, since they have a breakdown voltage. high, with a reduced conduction resistance and a potentially high current density.
La figure 1 est une illustration schématique d'un mode de réalisation d'un circuit intégré comprenant un circuit de commutation 1 . Le circuit de commutation 1 comprend des premiers à quatrième transistors à heterojonction à effet de champ 1 1 à 14. FIG. 1 is a schematic illustration of an embodiment of an integrated circuit comprising a switching circuit 1. The switching circuit 1 comprises first to fourth field effect heterojunction transistors 1 1 to 14.
Le transistor 1 1 et le transistor 14 sont connectés par des premières électrodes de conduction respectives, au niveau d'un plot de connexion de puissance du circuit de commutation 1 . Le transistor 12 et le transistor 13 sont connectés par des secondes électrodes de conduction respectives, au niveau d'un plot de connexion de puissance du circuit de commutation 1 . Une deuxième électrode de conduction du transistor 1 1 et une première électrode de conduction du transistor 12 sont connectées. Une deuxième électrode de conduction du transistor 14 et une première électrode de conduction du transistor 13 sont connectées.  The transistor 1 1 and the transistor 14 are connected by respective first conduction electrodes at a power connection pad of the switching circuit 1. Transistor 12 and transistor 13 are connected by respective second conduction electrodes at a power connection pad of switching circuit 1. A second conduction electrode of the transistor 1 1 and a first conduction electrode of the transistor 12 are connected. A second conduction electrode of transistor 14 and a first conduction electrode of transistor 13 are connected.
Une des électrodes de conduction du deuxième transistor 12 est connectée à sa grille de commande. Le transistor 12 est connecté de façon à former une diode. Une des électrodes de conduction du transistor 14 est connectée à sa grille de commande. Le transistor 14 est connecté de façon à former une diode. Le circuit de commutation 1 comprend ainsi une première branche incluant les transistors 1 1 et 12, et une deuxième branche incluant les transistors 13 et 14. Chaque branche comprend ainsi une diode respective, ces diodes étant connectées en anti parallèle.  One of the conduction electrodes of the second transistor 12 is connected to its control gate. The transistor 12 is connected to form a diode. One of the conduction electrodes of the transistor 14 is connected to its control gate. Transistor 14 is connected to form a diode. The switching circuit 1 thus comprises a first branch including the transistors 1 1 and 12, and a second branch including the transistors 13 and 14. Each branch thus comprises a respective diode, these diodes being connected in anti-parallel.
Les grilles de commande des transistors 12 et 14 sont connectées électriquement par le nœud 17. Cette connexion électrique raccorde les deuxièmes électrodes des transistors 1 1 et 14, ainsi que les premières électrodes des transistors 12 et 13. Cette connexion électrique permet notamment d'obtenir une référence de potentiel pour les transistors 12 et 14 montés en diode. En outre, une telle connexion permet d'accroître la densité de courant en conduction à travers le circuit de commutation 1 .  The control gates of the transistors 12 and 14 are electrically connected by the node 17. This electrical connection connects the second electrodes of the transistors 1 1 and 14, as well as the first electrodes of the transistors 12 and 13. This electrical connection makes it possible in particular to obtain a potential reference for the transistors 12 and 14 mounted in diode. In addition, such a connection makes it possible to increase the current density in conduction through the switching circuit 1.
L'état de conduction des transistors 1 1 et 13 peut être commandé par un circuit de commande non illustré. Comme la polarisation des grilles de commande des transistors 1 1 et 13 est effectuée par des potentiels relatifs par rapport au nœud de connexion entre les transistors 1 1 à 14, cette polarisation est réalisée par une alimentation isolée par rapport aux potentiels appliqués sur les nœuds 15 et 16 et par rapport au potentiel du nœud 17, afin d'éviter tout passage de courant dans le circuit de commande par l'intermédiaire de ce nœud de connexion 17. Selon une variante, en remplacement du transistor 14, le transistor 13 peut être connecté de façon à former une diode en antiparallèle du transistor 12 connecté en diode. Bien que le circuit de commutation 1 puisse inclure des transistors à effet de champ à hétérojonction à haute mobilité de trous, l'invention utilise avantageusement des transistors à effet de champ à hétérojonction à haute mobilité électronique, afin de fournir une plus grande densité de courant. The conduction state of transistors 11 and 13 may be controlled by a control circuit not shown. Since the polarization of the control gates of the transistors 1 1 and 13 is effected by relative potentials with respect to the connection node between the transistors 1 1 to 14, this polarization is carried out by an isolated power supply with respect to the potentials applied to the nodes 15 and 16 and with respect to the potential of the node 17, in order to avoid any current flow in the control circuit via this connection node 17. According to a variant, in replacement of the transistor 14, the transistor 13 can be connected so as to form an antiparallel diode of the transistor 12 connected diode. Although switching circuit 1 may include heterojunction field effect transistors with high hole mobility, the invention advantageously utilizes high electron mobility heterojunction field effect transistors to provide greater current density. .
La figure 2 est une figure schématique d'un exemple de transistor 18 de type HEMT, c'est-à-dire un transistor à effet de champ à haute mobilité électronique.  FIG. 2 is a schematic figure of an example of a HEMT transistor 18, that is to say a high electron mobility field effect transistor.
Le transistor 18 comporte un substrat de silicium 181 , présentant typiquement dopage de type P mais pouvant aussi ne pas être dopé. Une couche semi-conductrice 182 en alliage binaire d'un nitrure d'un élément de type III (par exemple du GaN) est ménagée au-dessus du substrat 181 . Une couche semi-conductrice dite barrière, d'alliage ternaire d'un nitrure d'un élément de type III (par exemple du AIGaN) 183 est ménagée au-dessus de la couche 182. Une couche de gaz d'électrons 184 est intrinsèquement formée à l'interface entre la couche 182 et la couche 183.  The transistor 18 comprises a silicon substrate 181, typically having P-type doping but which can also not be doped. A semiconductor layer 182 made of a nitride of a type III element (for example GaN) is formed above the substrate 181. A semiconductor layer, called a barrier, of a ternary alloy of a nitride of a type III element (for example AIGaN) 183 is formed above the layer 182. A layer of electron gas 184 is intrinsically formed at the interface between the layer 182 and the layer 183.
Le transistor 18 comporte une première électrode de conduction 186 et une deuxième électrode de conduction 187, entre lesquelles un courant doit sélectivement être établi. Les électrodes 186 et 187 sont formées de façon connue en soit sous forme d'implantation ionique ou de diffusion métallique. Le transistor 18 comporte en outre une grille de commande 188, dont le potentiel de commande définit si le transistor 18 est passant ou bloqué. Les électrodes 186 et 187 et la grille 188 sont ménagées au-dessus de la couche 183. La couche 184 comporte une zone 185 à l'aplomb de la grille 188. La zone 185 est rendue sélectivement conductrice ou isolante en fonction de la tension appliquée sur la grille 188. En fonction de la conception du transistor 18, la zone 185 rend ce transistor soit normalement ouvert, soit normalement fermé, en fonction de l'état isolant ou conducteur de la zone 185 en l'absence de polarisation de la grille 188. Le transistor 18 est isolé d'autres composants électroniques par l'intermédiaire de tranchées d'isolation non illustrées.  The transistor 18 includes a first conduction electrode 186 and a second conduction electrode 187, between which a current must selectively be established. The electrodes 186 and 187 are formed in a known manner in the form of ion implantation or metal diffusion. The transistor 18 further comprises a control gate 188, the control potential of which defines whether the transistor 18 is on or off. The electrodes 186 and 187 and the gate 188 are formed above the layer 183. The layer 184 comprises a zone 185 in line with the gate 188. The zone 185 is made selectively conductive or insulating according to the applied voltage on the gate 188. Depending on the design of the transistor 18, the zone 185 makes this transistor is normally open, or normally closed, depending on the insulating or conducting state of the zone 185 in the absence of polarization of the gate 188. The transistor 18 is isolated from other electronic components through insulation trenches not shown.
Bien qu'on ait décrit un cas particulier de transistor à hétérojonction de type AIGaN, d'autres structures telles que le GaAIAs/GaAs, ou le GaAIAs(N+)/lnGaAs(n.d)/GaAs peuvent bien entendu également être envisagées.  Although a particular case of a heterojunction transistor of AIGaN type has been described, other structures such as GaAlAs / GaAs or GaAlAs (N +) / In GaAs (n.d) / GaAs can of course also be envisaged.
Les transistors 12 et 14 sont de type normalement ouvert, de façon à pouvoir être connectés en diode. La figure 3 est un exemple de diagramme tension/courant d'un tel transistor de type HEMT. Un transistor de type normalement ouvert présente une tension de seuil positive Vth. Avantageusement, cette tension de seuil est inférieure ou égale à 1 V afin de limiter les pertes de commutation dans le circuit de commutation 1 . Avantageusement, cette tension de seuil est au moins égale à 0,2 V, voire au moins égale à 0,4V pour éviter une mise en conduction intempestive en inverse des diodes formées. Transistors 12 and 14 are of normally open type so that they can be diode connected. FIG. 3 is an example of a voltage / current diagram of such a HEMT type transistor. A transistor type normally open has a positive threshold voltage Vth. Advantageously, this threshold voltage is less than or equal to 1 V in order to limit the switching losses in the switching circuit 1. Advantageously, this threshold voltage is at least equal to 0.2 V, or at least equal to 0.4 V to avoid unwanted conduction in reverse of the diodes formed.
Des procédés de formation de transistors à hétérojonction de type normalement ouvert sont connus en soi de l'homme du métier, par exemple par des techniques dites de gravure partielle ou complète de la couche 183, d'implantation ionique de Fluor, de formation d'une grille p-(AI)GaN ou la formation d'une grille arrière.  Processes for forming heterojunction transistors of normally open type are known per se to those skilled in the art, for example by techniques known as partial or complete etching of the layer 183, ion implantation of fluorine, formation of a p- (AI) GaN gate or the formation of a back gate.
La figure 4 est une vue de dessus d'un exemple de topographie du circuit de commutation 1 du mode de réalisation de la figure 1 . Les transistors 1 1 et 14 sont connectés par leurs premières électrodes conductrices 1 1 1 et 141 , désignées ici comme leurs drains respectifs. Les électrodes 1 1 1 et 141 sont connectées à un plot de connexion de puissance 15. Les transistors 12 et 13 sont connectés par leurs deuxièmes électrodes conductrices 122 et 132, désignées ici comme leurs drains respectifs. Les électrodes 122 et 132 sont connectées à un plot de connexion de puissance 16. FIG. 4 is a view from above of an exemplary topography of the switching circuit 1 of the embodiment of FIG. 1. Transistors 1 1 and 14 are connected by their first conductive electrodes 1 1 1 and 141, referred to herein as their respective drains. The electrodes 11 and 141 are connected to a power connection pad 15. The transistors 12 and 13 are connected by their second conductive electrodes 122 and 132, designated here as their respective drains. The electrodes 122 and 132 are connected to a power connection pad 16.
La deuxième électrode conductrice du transistor 1 1 et la première électrode conductrice du transistor 12 sont confondues, sous la forme d'une électrode commune 1 12 désignée comme leur source. La deuxième électrode conductrice du transistor 14 et la première électrode conductrice du transistor 13 sont confondues, sous la forme d'une électrode commune 131 désignée comme leur source.  The second conductive electrode of the transistor 1 1 and the first conductive electrode of the transistor 12 are combined, in the form of a common electrode 1 12 designated as their source. The second conductive electrode of the transistor 14 and the first conductive electrode of the transistor 13 are combined in the form of a common electrode 131 designated as their source.
Un plot de connexion de commande 1 14 est connecté à la grille 1 13 du transistor 1 1 . Un plot de connexion de commande 134 est connecté à la grille 133 du transistor 13.  A control connection pad 1 14 is connected to the gate 1 13 of the transistor 1 1. A control connection pad 134 is connected to the gate 133 of the transistor 13.
Les premier et deuxième transistors 1 1 et 12 incluent une même première bande d'heterojonction 171 , correspondant à la première branche. Les troisième et quatrième transistors 13 et 14 incluent une même deuxième bande d'heterojonction 172, correspondant à la deuxième branche. Les bandes d'heterojonction 171 et 172 sont séparées par une bande d'isolant 173.  The first and second transistors 1 1 and 12 include the same first heterojunction band 171, corresponding to the first branch. The third and fourth transistors 13 and 14 include the same second heterojunction band 172, corresponding to the second branch. The heterojunction bands 171 and 172 are separated by an insulating strip 173.
Les plots de connexion de puissance 15 et 16 sont positionnés de côté par rapport à la bande isolante 173 et par rapport aux bandes d'heterojonction 171 et 172. Les plots de connexion de commande 1 14 et 134 sont positionnés du côté opposé aux plots 15 et 16, par rapport à la bande isolante 173 et par rapport aux bandes d'heterojonction 171 et 172. En positionnant les plots de connexion 1 14 et 134 et les plots de connexion 15 et 16 à l'opposé de la bande isolante 173 notamment, la conception du circuit de commutation 1 peut être particulièrement compacte puisqu'il n'y a pas lieu d'isoler davantage ces plots les uns des autres. The power connection pads 15 and 16 are positioned from the side with respect to the insulating strip 173 and with respect to the heterojunction strips 171 and 172. The control connection pads 1 and 4 are positioned on the opposite side to the pads. and 16, with respect to the insulating strip 173 and with respect to the heterojunction strips 171 and 172. By positioning the connection pads 1 and 14 and the connection pads 15 and 16 opposite the insulating strip 173, in particular , the design of the switching circuit 1 can be particularly compact since it is not necessary to further isolate these pads from each other.
La connexion électrique entre les grilles de commande 123 et 143 est notamment réalisée par l'intermédiaire d'un élément conducteur 193 s'étendant à l'aplomb de la bande d'isolant 173 et connectant les électrodes 1 12 et 131 . Cet élément conducteur 193 est ici positionné en position médiane entre les transistors 1 1 à 14 et n'altère donc que très peu l'encombrement du circuit de commutation 1 .  The electrical connection between the control gates 123 and 143 is made in particular by means of a conductive element 193 extending vertically above the insulating strip 173 and connecting the electrodes 1 12 and 131. This conductive element 193 is here positioned in the middle position between the transistors 1 1 to 14 and therefore only slightly affects the size of the switching circuit 1.
De façon similaire :  In the same way :
-un élément conducteur 191 s'étend à l'aplomb de la bande d'isolant 173 et connecte les électrodes 122 et 132 ;  a conductive element 191 extends vertically above the insulating strip 173 and connects the electrodes 122 and 132;
-un élément conducteur 192 s'étend à l'aplomb de la bande d'isolant 173 et connecte les électrodes 1 1 1 et 141 .  a conductive element 192 extends vertically above the insulating strip 173 and connects the electrodes 11 1 and 141.
L'électrode 1 12 est connectée à la grille de commande 123 par l'intermédiaire d'un élément conducteur 194. L'élément conducteur 194 est ici déporté latéralement par rapport à la bande d'heterojonction 171 , du même côté que les plots de connexion 15 et 16. L'électrode 131 est connectée à la grille de commande 143 par l'intermédiaire d'un élément conducteur 195. L'élément conducteur 195 est ici déporté latéralement par rapport à la bande d'heterojonction 172, du même côté que les plots de connexion 1 14 et 134.  The electrode 1 12 is connected to the control gate 123 via a conductive element 194. The conductive element 194 is here offset laterally with respect to the heterojunction band 171, on the same side as the pins of FIG. connection 15 and 16. The electrode 131 is connected to the control gate 143 via a conductive element 195. The conductive element 195 is here offset laterally with respect to the heterojunction band 172, on the same side that the connection pads 1 14 and 134.
Le plot de connexion 1 14 est connecté à la grille de commande 1 13 par l'intermédiaire d'un élément conducteur 196 s'étendant à l'aplomb de la bande d'isolant 173 et de la bande d'heterojonction 172. Un plot de connexion 101 permet d'appliquer un potentiel de référence sur l'élément conducteur 194, sans être traversé par le courant entre les plots de connexion 15 et 16.  The connection pad 1 14 is connected to the control gate 1 13 via a conductive element 196 extending vertically above the insulating strip 173 and the heterojunction band 172. A stud connection 101 allows to apply a reference potential on the conductive element 194, without being traversed by the current between the connection pads 15 and 16.
L'état de conduction des transistors 1 1 et 13 peut être commandé par un circuit de commande 2. Ce circuit de commande 2 applique sélectivement un potentiel généré par une alimentation (non illustrée) isolée par rapport aux plots de connexion 15 et 16. La polarisation des grilles de commande des transistors 1 1 et 13 est effectuée par des potentiels relatifs par rapport au nœud de connexion entre les transistors 1 1 à 14 (potentiel du plot de connexion 101 ). Ceci permet d'éviter tout passage de courant de puissance dans le circuit de commande 2 ou l'alimentation. La configuration illustrée du circuit de commutation 1 s'avère ainsi particulièrement compacte, permet de limiter au maximum les longueurs des connexions entre les transistors 1 1 à 14, et permet de réduire à seulement deux le nombre de contacts ohmiques entre les plots de connexion 15 et 16, tout en fournissant une structure de commutation quatre quadrants. Les éléments conducteurs 191 à 196 peuvent avantageusement être réalisés par des dépôts métalliques respectifs. The conduction state of the transistors 11 and 13 may be controlled by a control circuit 2. This control circuit 2 selectively applies a potential generated by a supply (not shown) isolated from the connection pads 15 and 16. The polarization of the control gates of the transistors 1 1 and 13 is effected by relative potentials with respect to the connection node between the transistors 1 1 to 14 (potential of the connection pad 101). This makes it possible to avoid any passage of power current in the control circuit 2 or the power supply. The illustrated configuration of the switching circuit 1 thus proves to be particularly compact, makes it possible to limit as far as possible the lengths of the connections between the transistors 1 1 to 14, and makes it possible to reduce to only two the number of ohmic contacts between the connection pads 15 and 16, while providing a four-quadrant switching structure. The conductive elements 191 to 196 may advantageously be made by respective metal deposits.
Les grilles de commande 1 13, 123, 133 et 143 peuvent par exemple être réalisées directement sur le semi-conducteur (par exemple sur une couche d'AIGaN) pour former un contact de grille Schottky ou bien sur un isolant pour former un contact de grille de type MIS. Les grilles de commande 1 13, 123, 133 et 143 peuvent par exemple présenter une largeur comprise entre 0,5 et 2 μιτι.  The control gates 1 13, 123, 133 and 143 may for example be made directly on the semiconductor (for example on a layer of AIGaN) to form a Schottky gate contact or on an insulator to form a contact of grid type MIS. The control grids 1 13, 123, 133 and 143 may for example have a width of between 0.5 and 2 μιτι.
Les dimensions des électrodes 1 1 1 , 141 , 122 et 132 (typiquement leur largeur est définie par leur dimension selon l'axe de la longueur des bandes 171 à 173) sont par exemple fixées en fonction de la densité de courant devant traverser le circuit de commutation 1 .  The dimensions of the electrodes 1 1 1, 141, 122 and 132 (typically their width is defined by their dimension along the axis of the length of the strips 171 to 173) are for example fixed as a function of the current density to pass through the circuit switching 1.
La figure 5 illustre une variante de topographie du mode de réalisation de la figure 1 du circuit de commutation 1 . Cette variante permet avantageusement d'utiliser un nœud intermédiaire des branches du circuit 1 pour disposer d'un autre plot de connexion de puissance permettant de court-circuiter certaines fonctions. Cette variante permet de disposer d'un potentiel de référence de grille permettant de piloter les transistors 1 1 et 13. À cet effet, des plots de connexion de puissance 101 et 102 sont connectés respectivement aux éléments conducteurs 194 et 195. Un circuit de commande 2 applique sélectivement sur les plots 1 14 et 134 un potentiel généré par une alimentation (non illustrée) isolée par rapport aux plots de connexion 15 et 16 et par rapport aux plots de connexion de puissance 101 et 102. Ceci permet d'éviter tout passage de courant de puissance dans le circuit de commande 2 ou l'alimentation. FIG. 5 illustrates a variant of the topography of the embodiment of FIG. 1 of the switching circuit 1. This variant advantageously makes it possible to use an intermediate node of the branches of the circuit 1 in order to have another power connection pad making it possible to short-circuit certain functions. This variant makes it possible to have a gate reference potential making it possible to drive transistors 1 1 and 13. For this purpose, power connection pads 101 and 102 are respectively connected to conducting elements 194 and 195. A control circuit 2 selectively applies on the pads 1 14 and 134 a potential generated by a power supply (not shown) isolated from the connection pads 15 and 16 and relative to the power connection pads 101 and 102. This makes it possible to avoid any passage of power in the control circuit 2 or the power supply.
La figure 6 illustre une autre variante de topographie du mode de réalisation de la figure 1 du circuit de commutation 1 . Cette variante permet avantageusement d'accroître la densité d'intégration du circuit de commutation 1 . Contrairement aux autres variantes, il n'est ici pas nécessaire de prévoir une bande d'isolant entre deux bandes d'hétérojonction. Cette variante est particulièrement adaptée pour des transistors HEMT. FIG. 6 illustrates another variant of the topography of the embodiment of FIG. 1 of the switching circuit 1. This variant advantageously makes it possible to increase the integration density of the switching circuit 1. Unlike the other variants, it is not necessary here to provide an insulation strip between two heterojunction strips. This variant is particularly suitable for HEMT transistors.
Les transistors 1 1 et 14 sont connectés par une électrode conductrice commune 1 1 1 , désignée ici comme leur drain respectif. L'électrode commune 1 1 1 est connectée à un plot de connexion de puissance 15. Les transistors 12 et 13 sont connectés par leurs deuxièmes électrodes conductrices 122 et 132, désignées ici comme leurs drains respectifs. Les électrodes 122 et 132 sont connectées par l'intermédiaire de plots de connexion de puissance respectifs 161 et 162 interconnectés.  The transistors 1 1 and 14 are connected by a common conductive electrode 1 1 1, designated here as their respective drain. The common electrode 1 1 1 is connected to a power connection pad 15. The transistors 12 and 13 are connected by their second conductive electrodes 122 and 132, designated here as their respective drains. The electrodes 122 and 132 are connected via respective power connection pads 161 and 162 interconnected.
La deuxième électrode conductrice du transistor 1 1 et la première électrode conductrice du transistor 12 sont confondues, sous la forme d'une électrode commune 1 12 désignée comme leur source. La deuxième électrode conductrice du transistor 14 et la première électrode conductrice du transistor 13 sont confondues, sous la forme d'une électrode commune 131 désignée comme leur source. The second conductive electrode of the transistor 1 1 and the first conductive electrode of the transistor 12 are combined, in the form of a common electrode 1 12 designated as their source. The second electrode conductive transistor 14 and the first conductive electrode of the transistor 13 are combined, in the form of a common electrode 131 designated as their source.
Un plot de connexion de commande 1 14 est connecté à la grille 123 du transistor 12. Un plot de connexion de commande 134 est connecté à la grille 133 du transistor 13.  A control connection pad 1 14 is connected to the gate 123 of the transistor 12. A control connection pad 134 is connected to the gate 133 of the transistor 13.
Un élément conducteur 197 connecte la source 1 12, la grille 143 et la source 131 . Un plot de connexion 101 est connecté à cet élément conducteur 197. Le plot de connexion 101 permet d'appliquer un potentiel de référence sur l'élément conducteur 197, sans être traversé par le courant entre les plots de connexion 15 et 16.  A conductive element 197 connects the source 1 12, the gate 143 and the source 131. A connection pad 101 is connected to this conductive element 197. The connection pad 101 makes it possible to apply a reference potential to the conductive element 197, without the current flowing between the connection pads 15 and 16.
Les premier à quatrième transistors 1 1 à 14 incluent une même bande d'hétérojonction 170. Le circuit de commutation 1 peut ainsi présenter une densité d'intégration très élevée.  The first through fourth transistors 11 to 14 include the same heterojunction band 170. The switching circuit 1 can thus have a very high integration density.
Les plots de connexion de puissance 15, 161 , 162, 1 14 et 134 sont positionnés d'un même côté par rapport à la bande d'hétérojonction 170.  The power connection pads 15, 161, 162, 14 and 134 are positioned on the same side with respect to the heterojunction band 170.
L'état de conduction des transistors 1 1 et 13 peut être commandé par un circuit de commande 2. Ce circuit de commande 2 applique sélectivement, sur les plots 1 13 et 134, un potentiel généré par une alimentation (non illustrée) isolée par rapport aux plots de connexion 15, 161 et 162. La polarisation des grilles de commande des transistors 1 1 et 13 est effectuée par des potentiels relatifs au potentiel du plot 101 . Ceci permet d'éviter tout passage de courant de puissance dans le circuit de commande 2 ou l'alimentation. The conduction state of transistors 1 1 and 13 may be controlled by a control circuit 2. This control circuit 2 selectively applies, on pads 1 13 and 134, a potential generated by a power supply (not illustrated) isolated relative to to the connection pads 15, 161 and 162. The polarization of the control gates of the transistors 1 1 and 13 is effected by potentials relative to the potential of the pad 101. This makes it possible to avoid any passage of power current in the control circuit 2 or the power supply.
Un tel circuit de commutation 1 peut être utilisé pour des fonctions connues en soi d'interrupteur quatre quadrants. Un tel circuit de commutation 1 peut être utilisé même seulement pour une partie de ces fonctionnalités. Such a switching circuit 1 can be used for functions known per se of four-quadrant switch. Such a switching circuit 1 can be used even only for part of these functionalities.
Un tel circuit de commutation 1 peut par exemple être utilisé comme interrupteur bidirectionnel en courant et unidirectionnel en tension, correspondant par exemple au schéma de principe illustré à la figure 15. Un tel interrupteur est par exemple utilisé dans des cellules de commutation d'onduleurs de tension pour courant triphasé. Avec un circuit de commutation 1 tel qu'illustré à la figure 1 , on peut par exemple former la diode antiparallèle par l'intermédiaire du transistor 14, former la fonction interrupteur par l'intermédiaire du transistor 1 1 , et réaliser une conduction bidirectionnelle par l'intermédiaire du transistor 13 maintenu fermé.  Such a switching circuit 1 may, for example, be used as a bidirectional current and unidirectional voltage switch, for example corresponding to the block diagram illustrated in FIG. 15. Such a switch is used, for example, in inverter switching cells. voltage for three-phase current. With a switching circuit 1 as illustrated in FIG. 1, it is possible, for example, to form the antiparallel diode by means of the transistor 14, to form the switch function via the transistor 11, and to carry out a bidirectional conduction by through the transistor 13 kept closed.
Un tel circuit de commutation 1 peut également être utilisé comme interrupteur bidirectionnel en tension et monodirectionnel en courant, correspondant par exemple au schéma de principe illustré à la figure 16. Un tel interrupteur peut également être utilisé dans un onduleur en vue de former un blocage spontané bloquant un courant de retour provenant d'une charge alimentée. Avec un circuit de commutation 1 tel qu'illustré à la figure 1 , on peut par exemple former la diode antiparallèle par l'intermédiaire du transistor 14, former la fonction interrupteur par l'intermédiaire du transistor 1 1 , former la diode série par l'intermédiaire du transistor 12 et maintenir le transistor 13 ouvert. Such a switching circuit 1 can also be used as bidirectional switch in voltage and monodirectional in current, corresponding for example to the block diagram illustrated in FIG. 16. Such a switch can also be used in an inverter in order to form a spontaneous blocking blocking a return current from a powered load. With a switching circuit 1 as illustrated in FIG. 1, it is possible, for example, to form the antiparallel diode by means of the transistor 14, to form the switch function via the transistor 11, to form the series diode by means of FIG. intermediate of the transistor 12 and keep the transistor 13 open.
Les figures 7 à 9 sont des vues en coupe d'un transistor HEMT 1 1 à différentes étapes d'un exemple de procédé de fabrication. Les figures 7 à 9 illustrent partiellement le transistor 1 1 au niveau de sa grille et de sa source. Figures 7 to 9 are sectional views of a HEMT transistor 1 1 at different stages of an exemplary manufacturing method. Figures 7 to 9 partially illustrate the transistor 1 1 at its gate and its source.
Pour le circuit intégré en cours de formation illustré à la figure 7, on dispose ici d'un substrat 181 , sur lequel une couche semi-conductrice 182 en alliage binaire d'un nitrure d'un élément de type III (par exemple du GaN) est ménagée. Une couche semi-conductrice barrière, d'alliage ternaire d'un nitrure d'un élément de type III (par exemple du AIGaN) 183 est ménagée au-dessus de la couche 182. Une couche de gaz d'électrons 184 est intrinsèquement formée à l'interface entre la couche 182 et la couche 183.  For the integrated circuit being formed illustrated in Figure 7, there is here a substrate 181, on which a semiconductor layer 182 of binary alloy of a nitride of a type III element (for example GaN ) is spared. A barrier semiconductor layer of ternary alloy of a nitride of a type III element (for example AIGaN) 183 is formed above the layer 182. A layer of electron gas 184 is intrinsically formed. at the interface between the layer 182 and the layer 183.
Une couche d'isolant 153 est formée sur la couche 183 et a été mise en forme pour présenter des orifices traversants au niveau de la source, du drain et de la grille du transistor 1 1 . Une gorge 154 est notamment ménagée au niveau de la grille à former. La gorge 154 présente par exemple une largeur comprise entre 0,25 et 2 μιτι. La couche d'isolant 153 est par exemple formée en nitrure de silicium. Des dépôts métalliques 151 sont mis en forme et sont en contact avec la couche 183 au niveau de la source et du drain. Les dépôts métalliques 151 présentent par exemple une épaisseur de 100 nm et une largeur comprise entre 4 et 20 μιτι. La largeur de la couche d'isolant 153 entre la gorge 154 et le dépôt métallique 151 de la source est par exemple de l'ordre de 1 μιτι.  An insulator layer 153 is formed on the layer 183 and has been shaped to have through holes at the source, the drain and the gate of the transistor 1 1. A groove 154 is formed in particular at the level of the grid to be formed. The groove 154 has for example a width between 0.25 and 2 μιτι. The insulating layer 153 is for example formed of silicon nitride. Metal deposits 151 are shaped and are in contact with the layer 183 at the source and the drain. The metal deposits 151 have for example a thickness of 100 nm and a width of between 4 and 20 μιτι. The width of the insulating layer 153 between the groove 154 and the metal deposit 151 of the source is for example of the order of 1 μιτι.
Une couche d'oxyde de grille 152 est déposée pleine plaque. La couche d'oxyde de grille 152 peut être déposée par un procédé de dépôt de couche atomique (ALD). La couche d'oxyde de grille 152 est par exemple réalisée en AI2O3. La couche d'oxyde de grille 152 peut typiquement présenter une épaisseur de l'ordre de 10 nm.  A gate oxide layer 152 is deposited full plate. The gate oxide layer 152 may be deposited by an atomic layer deposition (ALD) method. The gate oxide layer 152 is for example made of Al 2 O 3. The gate oxide layer 152 may typically have a thickness of the order of 10 nm.
Lors d'étapes ultérieures, la couche 152 est mise en forme par exemple par photolithographie, pour la conserver dans la gorge 154 et la retirer au niveau des autres zones. La couche 152 peut alors faire l'objet d'un recuit, par exemple à 650° en présence de diazote. On obtient alors la structure telle qu'illustrée à la figure 8.  In subsequent steps, the layer 152 is shaped for example by photolithography, to keep it in the groove 154 and remove it at the other areas. The layer 152 can then be annealed, for example at 650 ° in the presence of dinitrogen. The structure is thus obtained as illustrated in FIG. 8.
Lors d'étapes ultérieures :  In later stages:
-on réalise avantageusement un dépôt métallique interfacial par exemple de Ti ou de TiN. Ce dépôt peut par exemple être réalisé sur une épaisseur de 100 nm. Ce dépôt peut par exemple être réalisé par dépôt physique en phase vapeur ; Advantageously, an interfacial metal deposit is produced, for example of Ti or TiN. This deposit may for example be made on a thickness of 100 nm. This deposit may for example be made by physical vapor deposition;
-on réalise un dépôt métallique pour les différentes électrodes, par exemple en tungstène. Ce dépôt peut par exemple être réalisé sur une épaisseur comprise entre 200 à 400 nm. Ce dépôt peut par exemple être réalisé par dépôt chimique en phase vapeur ;  a metal deposit is made for the various electrodes, for example made of tungsten. This deposit may for example be made to a thickness of between 200 and 400 nm. This deposit can for example be made by chemical vapor deposition;
-on réalise une mise en forme des dépôts métalliques pour leur donner la forme des différentes électrodes. Cette mise en forme est par exemple réalisée par photolithographie. On obtient alors la structure telle qu'illustrée à la figure 9 sur laquelle on peut distinguer la source 1 12 et la grille 1 13.  the metal deposits are shaped to give them the shape of the different electrodes. This shaping is for example carried out by photolithography. The structure is thus obtained as illustrated in FIG. 9 on which the source 1 12 and the grid 1 13 can be distinguished.
Les figures 10 à 14 sont des vues en coupe d'un circuit de commutation selon le mode de réalisation à différentes étapes d'un exemple de procédé de fabrication. La coupe est ici réalisée au niveau de l'électrode 1 12, de l'électrode 131 et de l'élément conducteur 193 du circuit de commutation 1 à former. Figures 10 to 14 are sectional views of a switching circuit according to the embodiment at different stages of an exemplary manufacturing method. The cut is made here at the electrode 1 12, the electrode 131 and the conductive element 193 of the switching circuit 1 to form.
Pour le circuit intégré en cours de formation illustré à la figure 10, on dispose ici du substrat 181 , sur lequel la couche semi-conductrice 182 en alliage binaire d'un nitrure d'un élément de type III (par exemple du GaN) est ménagée. La couche semi-conductrice barrière, d'alliage ternaire d'un nitrure d'un élément de type III (par exemple du AIGaN) 183 est ménagée au-dessus de la couche 182. La couche de gaz d'électrons 184 est intrinsèquement formée à l'interface entre la couche 182 et la couche 183. La couche d'isolant 153 est formée sur la couche 183.  For the integrated circuit being formed illustrated in FIG. 10, substrate 181 is available here, on which the semiconductor layer 182 made of a nitride of a type III element (for example GaN) is formed. The barrier semiconductor layer of ternary alloy of a nitride of a type III element (for example AIGaN) 183 is formed above the layer 182. The electron gas layer 184 is intrinsically formed at the interface between the layer 182 and the layer 183. The insulating layer 153 is formed on the layer 183.
A la figure 1 1 , la couche d'isolant 153 a été mise en forme pour former un orifice traversant 155 jusqu'à la couche 183.  In Figure 1 1, the insulating layer 153 has been shaped to form a through hole 155 to the layer 183.
A la figure 12, les électrodes 1 12 et 131 ont été formées par des dépôts métalliques en contact électrique avec la couche 183 au niveau de l'orifice 155. Après mise en forme des dépôts métalliques, les électrodes 1 12 et 131 sont séparées par une gorge 156.  In FIG. 12, the electrodes 1 12 and 131 have been formed by metal deposits in electrical contact with the layer 183 at the orifice 155. After forming the metal deposits, the electrodes 1 12 and 131 are separated by a throat 156.
A la figure 13, un dépôt d'une couche isolante 157 est effectué pour recouvrir les électrodes 1 12 et 131 , et remplir la gorge 156. Une séparation isolante 173 est formée entre les électrodes 1 12 et 131 .  In FIG. 13, a deposit of an insulating layer 157 is made to cover the electrodes 1 12 and 131, and to fill the groove 156. An insulating separation 173 is formed between the electrodes 1 12 and 131.
A la figure 14, on a mis en forme la couche isolante 157 par photolithographie, puis on a réalisé un dépôt et une mise en forme d'un métal (par exemple de type AlCu), afin de former un élément conducteur 193 surplombant la séparation isolante 173 et joignant les électrodes 1 12 et 131 .  In FIG. 14, the insulating layer 157 has been shaped by photolithography, then a deposit and a shaping of a metal (for example of the AlCu type) have been made, in order to form a conducting element 193 overhanging the separation. insulating 173 and joining the electrodes 1 12 and 131.
Dans le procédé de fabrication illustré, on n'a pas illustré la formation des connexions ou interconnexions des électrodes 1 12 et 131 . Pour la formation d'un transistor HEMT de type normalement ouvert, des étapes préalables de gravure de la couche d'AIGaN 183 associée ou non à une implantation de dopants sous la zone 185 peuvent être réalisées préalablement au dépôt de la couche d'oxyde de grille 152. In the manufacturing method illustrated, the formation of the connections or interconnections of the electrodes 1 12 and 131 has not been illustrated. For the formation of a normally open type HEMT transistor, preliminary steps for etching the AIGaN layer 183 associated or not with a implantation of dopants under zone 185 may be carried out prior to deposition of the gate oxide layer 152.
La plupart des étapes des procédés de fabrication des transistors de conduction et des transistors destinés à former des diodes sont communes. Par conséquent, les différentes grilles peuvent aisément être alignées les unes par rapport aux autres ce qui limite des dispersions de fabrication et permet d'obtenir une bonne symétrie du fonctionnement d'un circuit de commutation 1 tel qu'illustré à la figure 4.  Most of the steps of manufacturing methods of conduction transistors and transistors for forming diodes are common. Consequently, the different grids can easily be aligned relative to one another, which limits manufacturing dispersions and makes it possible to obtain a good symmetry of the operation of a switching circuit 1 as illustrated in FIG. 4.

Claims

REVENDICATIONS
1 . Circuit intégré (1 ) comprenant un circuit de commutation, caractérisé en ce qu'il comprend :  1. Integrated circuit (1) comprising a switching circuit, characterized in that it comprises:
-une première branche incluant des premier et deuxième transistors (1 1 , 12) ; -une deuxième branche incluant des troisième et quatrième transistors (13, 14), lesdits premier à quatrième transistors étant des transistors à hétérojonction à effet de champ comportant chacun des première et deuxième électrodes de conduction et une grille de commande ;  a first branch including first and second transistors (1 1, 12); a second branch including third and fourth transistors (13, 14), said first to fourth transistors being field effect heterojunction transistors each comprising first and second conduction electrodes and a control gate;
-la première électrode (1 1 1 ) de conduction du premier transistor (1 1 ) étant connectée à la première électrode de conduction (141 ) du quatrième transistor (14) ;  the first conduction electrode (1 1 1) of the first transistor (1 1) being connected to the first conduction electrode (141) of the fourth transistor (14);
-la deuxième électrode de conduction (122) du deuxième transistor (12) étant connectée à la deuxième électrode de conduction (132) du troisième transistor (13) ;  the second conduction electrode (122) of the second transistor (12) being connected to the second conduction electrode (132) of the third transistor (13);
-la deuxième électrode de conduction (1 12) du premier transistor (1 1 ) étant connectée à la première électrode de conduction du deuxième transistor the second conduction electrode (1 12) of the first transistor (1 1) being connected to the first conduction electrode of the second transistor
(12) ; (12);
-la deuxième électrode de conduction du quatrième transistor (14) étant connectée à la première électrode de conduction (131 ) du troisième transistor the second conduction electrode of the fourth transistor (14) being connected to the first conduction electrode (131) of the third transistor
(13) ; (13);
-lesdits deuxième et quatrième transistors étant de type normalement ouvert, -la première électrode de conduction du deuxième transistor étant connectée à la deuxième électrode de conduction du quatrième transistor, la grille de commande du deuxième transistor (12) étant connectée à la grille de commande du quatrième transistor (14) de façon à former une diode dans les première et deuxième branches, de sorte que les diodes formées dans les première et deuxième branches sont en antiparallèle ;  said second and fourth transistors being of normally open type, the first conduction electrode of the second transistor being connected to the second conduction electrode of the fourth transistor, the control gate of the second transistor being connected to the control gate; the fourth transistor (14) so as to form a diode in the first and second branches, so that the diodes formed in the first and second branches are anti-parallel;
-une alimentation isolée par rapport aux premières électrodes de conduction des premier et quatrième transistors et par rapport aux deuxièmes électrodes de conduction des deuxième et troisième transistors ;  an isolated supply with respect to the first conduction electrodes of the first and fourth transistors and with respect to the second conduction electrodes of the second and third transistors;
-un circuit de commande (2) configuré pour appliquer sélectivement le potentiel généré par l'alimentation sur les grilles de commande des premier et troisième transistors (1 1 , 13).  a control circuit (2) configured to selectively apply the potential generated by the power supply to the control gates of the first and third transistors (1 1, 13).
2. Circuit intégré (1 ) selon l'une quelconque des revendications précédentes, dans lequel lesdits premier à quatrième transistors sont des transistors à haute mobilité électronique. An integrated circuit (1) according to any one of the preceding claims, wherein said first through fourth transistors are high electron mobility transistors.
3. Circuit intégré (1 ) selon l'une quelconque des revendications précédentes, dans lequel lesdits premier et deuxième transistors (1 1 ,12) incluent une même première bande d'hétéronjonction (171 ) et dans lequel lesdits An integrated circuit (1) according to any one of the preceding claims, wherein said first and second transistors (11, 12) include the same first heteronjunction band (171) and wherein said
ICG 10962 PCT Depot Texte.doc troisième et quatrième transistors (13,14) incluent une même deuxième bande d'hétéronjonction (172), les première et deuxième bandes d'hétérojonction étant séparées par une bande d'isolant (173). ICG 10962 PCT Depot Text.doc third and fourth transistors (13, 14) include the same second heteronjunction band (172), the first and second heterojunction bands being separated by an insulating strip (173).
4. Circuit intégré (1 ) selon la revendication 3, dans lequel un élément conducteur (193) s'étend à l'aplomb de la bande d'isolant (173) et connecte les grilles de commande (123,143) des deuxième et quatrième transistors. 4. Integrated circuit (1) according to claim 3, wherein a conductive element (193) extends vertically above the insulating strip (173) and connects the control gates (123,143) of the second and fourth transistors. .
5. Circuit intégré selon la revendication 4, dans lequel ledit élément conducteur (193) est disposé dans une position médiane par rapport aux premier à quatrième transistors. An integrated circuit according to claim 4, wherein said conductive element (193) is disposed in a median position relative to the first through fourth transistors.
6. Circuit intégré (1 ) selon la revendication 4 ou 5, dans lequel des premier et deuxième plots d'interconnexion (15,16) sont connectés respectivement à la première électrode de conduction du premier transistor et à la deuxième électrode de conduction du deuxième transistor, et dans lequel des troisième et quatrième plots d'interconnexion (1 14,134) sont connectés respectivement aux grilles de commande des premier et troisième transistors (1 1 ,13), et dans lequel lesdits premier et deuxième plots d'interconnexion sont positionnés d'un premier côté par rapport à ladite bande d'isolant (173), lesdits troisième et quatrième plots d'interconnexion étant positionnés d'un deuxième côté opposé au premier par rapport à ladite bande d'isolant. 6. Integrated circuit (1) according to claim 4 or 5, wherein first and second interconnection pads (15,16) are respectively connected to the first conduction electrode of the first transistor and the second conduction electrode of the second transistor, and wherein third and fourth interconnection pads (1 14, 134) are respectively connected to the control gates of the first and third transistors (1 1, 13), and wherein said first and second interconnection pads are positioned in a first side with respect to said insulating strip (173), said third and fourth interconnection pads being positioned with a second opposite side to the first with respect to said insulating strip.
7. Circuit intégré selon la revendication 1 ou 2, dans lequel lesdits premier à quatrième transistors (1 1 , 12, 13 ,14) incluent une même bande d'hétérojonction (170). The integrated circuit of claim 1 or 2, wherein said first through fourth transistors (11, 12, 13, 14) include the same heterojunction band (170).
8. Circuit intégré (1 ) selon l'une quelconque des revendications précédentes, dans lequel la tension de seuil des deuxième et quatrième transistors est comprise entre 0 et 1 V. 8. Integrated circuit (1) according to any one of the preceding claims, wherein the threshold voltage of the second and fourth transistors is between 0 and 1 V.
PCT/FR2015/053090 2014-11-17 2015-11-16 Integrated circuit with power switching structure WO2016079406A1 (en)

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