WO2016078312A1 - 单板测试方法及装置 - Google Patents

单板测试方法及装置 Download PDF

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Publication number
WO2016078312A1
WO2016078312A1 PCT/CN2015/076807 CN2015076807W WO2016078312A1 WO 2016078312 A1 WO2016078312 A1 WO 2016078312A1 CN 2015076807 W CN2015076807 W CN 2015076807W WO 2016078312 A1 WO2016078312 A1 WO 2016078312A1
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test
switching device
packet
network processor
test packet
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PCT/CN2015/076807
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English (en)
French (fr)
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姜海明
朱延灵
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中兴通讯股份有限公司
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Publication of WO2016078312A1 publication Critical patent/WO2016078312A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks

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  • the present invention relates to the field of communications, and in particular, to a board testing method and apparatus.
  • ASICs Application Specific Integrated Circuits
  • NPs Network Processors
  • the mainstream routing switching product framework is shown in Figure 1.
  • the line card consists of an interface card, an ASIC or NP, a switching chip, and a Central Processing Unit (CPU).
  • CPU Central Processing Unit
  • a single-line card is sufficient; if it is a distributed system, it consists of multiple line cards plus a central processing card, and the central control processing card is responsible for completing the cross-board forwarding between the multi-line cards.
  • the message passes through the interface card, ASIC/NP, switching system, and the links between the modules (such as Serial Peripheral Interface (SPI), INTERLAKEN, etc.)
  • SPI Serial Peripheral Interface
  • INTERLAKEN INTERLAKEN
  • the usual test system is shown in Figure 2.
  • the tester sends out the package and goes back to the tester after passing through the whole system.
  • the receiver end of the tester visually observes whether there is any packet loss.
  • the cause of the problem may be resistance, capacitor soldering, and peripheral DDR3.
  • the biggest drawback of the test system in the related art is that it needs to occupy valuable tester resources.
  • panel ports which may be Ethernet ports or narrow band ports.
  • the Ethernet ports may be GE, XG, 40G and 100G, and the narrow band may be POS, E1, etc., 100G optical modules are very expensive to borrow, and the panel may have dozens of ports, so the traversal test consumes resources and is inefficient.
  • test device that is different from the conventional method has also been proposed in the related art.
  • a specially designed test board is inserted into the rack and sent to the board to be tested through the test board.
  • it requires an additional design of the test board, which takes up a separate slot for testing, which is troublesome.
  • the embodiment of the invention provides a method and a device for testing a single board, so as to at least solve the problem that the related technology is inefficient in testing the board.
  • a method for testing a board includes: generating, by a network processor, a test packet, and sending the test packet to a switching device in a switching network; After the test packet of the switching device is verified, the verification result is used as the test result of the board.
  • sending the test packet to the switching device includes: calculating, by the network processor, the microcode of the network processor according to an exchange header format of the switching device and an out port of the network processor a queue ID of the switching device; the queue ID is encapsulated in the test packet and sent to the switching device.
  • the network processor performs verification on the test packet that passes the switching device, and the network processor compares the test packet passing the switching device with the test packet by using a microcode. If the comparison result is consistent, the test result indicates that the board is normal; if the comparison result is inconsistent, the test result indicates that the board is abnormal.
  • the network processor uses the microcode to count the error bytes, and sends the statistical result to the central processing unit and/or discards the test message passing through the switching chip.
  • the generating, by the network processor, the test packet includes: when the current test packet transmission rate is less than a predetermined threshold, the network processor copies the current test packet to obtain the test packet.
  • a single board testing apparatus is further provided, which is applied to a network processor, the apparatus comprising: a generating module, configured to generate a test message, and send the test message to The switching device in the switching network is configured to verify the test packet passing the switching device, and the verification result is used as a test result of the board.
  • the generating module includes: a calculating unit, configured to calculate, according to a switching header format of the switching device and an egress port of the network processor, a microcode of the network processor to calculate the switching device a queue ID, the sending unit, configured to encapsulate the queue ID in the test packet and send the packet to the switching device.
  • the verification module is further configured to compare the test packet passing the switching device with the test packet by using a microcode, and if the comparison result is consistent, the test result indicates the board Normal; if the comparison result is inconsistent, the test result indicates that the board is abnormal.
  • the verification module is further configured to use the microcode to count the error bytes when the comparison result is inconsistent, and send the statistical result to the central processing unit and/or discard the test report passing through the switching chip. Text.
  • the generating module is further configured to: when the current test packet transmission rate is less than a predetermined threshold, copy the current test packet to obtain the test packet.
  • the network processor is used to generate the test packet, and the test packet is sent to the switching device in the switching network.
  • the network processor verifies the test packet of the switching device, and the verification result is used as a pair.
  • the test results of the board The problem of inefficient testing of the board in the related art is solved, thereby effectively testing the board and improving the testing efficiency.
  • FIG. 1 is a schematic structural diagram of a network route switching product in the related art
  • FIG. 2 is a schematic structural diagram of a board integrity test method in the related art
  • FIG. 3 is a flowchart of a board testing method according to an embodiment of the present invention.
  • FIG. 4 is a structural block diagram of a single board testing apparatus according to an embodiment of the present invention.
  • FIG. 5 is a structural block diagram 1 of a single board testing apparatus according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a single board level test method according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a whole-machine test method according to an embodiment of the present invention.
  • FIG. 8 is a flow chart of a single board test according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a method for testing a single board according to an embodiment of the present invention. As shown in FIG. 3, the process includes the following steps:
  • Step S302 the network processor generates a test packet, and sends the test packet to the switching device in the switching network.
  • step S304 the network processor verifies the test packet of the switching device, and the verification result is used as a test result of the board.
  • the test packet is generated by using the internal resources of the network processor, and the test packet is sent to the switching device, and the test packet of the switching device is verified to complete the test on the board, compared with the related technology.
  • the test of the board requires the use of the tester or the addition of the test board.
  • step S302 involves the network processor sending the test packet to the switching device. It should be noted that the switching device needs to meet certain conditions to implement packet forwarding.
  • the network processor is configured according to the switching device. The switch header format and the egress port of the network processor calculate the queue ID of the switching device through the microcode of the network processor; the queue ID is encapsulated in the test packet and sent to the switching device.
  • the foregoing step S304 involves the network processor verifying the test packet of the switching device, and the network processor can verify the test packet in multiple manners.
  • the network processor utilizes the microcode.
  • the test packet of the switching device is compared with the preset test packet. If the comparison result is consistent, the test result indicates that the board is normal. If the comparison result is inconsistent, the test result indicates that the board is abnormal. Therefore, the test of the board is implemented by verifying the test packet.
  • the network processor uses the microcode to count the error bytes and sends the statistics to the central processor.
  • the test packets passing through the switch chip are discarded.
  • the test packet generated by the network processor needs to reach a certain speed.
  • the network processor copies the current test packet to obtain a test report.
  • the generated test message reaches a certain speed.
  • a single-board test device is also provided in the embodiment, and the device is configured to implement the foregoing embodiments and preferred embodiments, and details are not described herein.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 4 is a structural block diagram of a single board testing apparatus according to an embodiment of the present invention.
  • the apparatus is applied to a network processor.
  • the apparatus includes: a generating module 42 configured to generate a test packet and test the packet.
  • the verification module 44 is configured to check the test packet of the switching device, and the verification result is used as a test result of the board.
  • FIG. 5 is a structural block diagram of a single board testing apparatus according to an embodiment of the present invention.
  • the generating module 42 includes: a calculating unit 422 configured to be in accordance with a switching header format of the switching device and an out port of the network processor.
  • the queue ID of the switching device is calculated by using the microcode of the network processor.
  • the sending unit 424 is configured to encapsulate the queue identifier ID in the test packet and send it to the switching device.
  • the verification module 44 is further configured to compare the test packet of the switching device with the test packet by using the microcode. If the comparison result is consistent, the test result indicates that the board is normal; the comparison result is inconsistent. In the case, the test result indicates that the board is abnormal.
  • the verification module 44 uses the microcode to count the error bytes, and sends the statistics to the central processor and/or discards the test message passing through the switch chip.
  • the generating module 42 is further configured to: when the current test packet transmission rate is less than a predetermined threshold, copy the current test packet to obtain a test packet.
  • each of the foregoing modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the above modules are respectively located.
  • the first processor, the second processor, and the third processor In the first processor, the second processor, and the third processor.
  • the optional embodiment uses the packet generator of the network processor to periodically generate a message, and performs integrity testing of the board and the whole machine by means of the flexible processing performance of the network processor.
  • the network processor In order to support the operation, management, and maintenance (OAM) detection, the network processor generally has a packet generator that can periodically send packets according to a specified time interval.
  • This alternative embodiment utilizes the characteristics of a network processor, and the configuration packet generator periodically sends Send the packet, assemble the switching header by the microcode, go back to the NP after the switching system, perform packet verification by the egress direction microcode, and perform statistics on the verification failure, and put related information (such as index and read). The result is carried in the message and sent to the Central Processing Unit (CPU).
  • CPU Central Processing Unit
  • PTN packet transfer network
  • BFD OAM/Bidirectional Forwarding Detection
  • Another feature of network processors is programming flexibility. Internal microcode can implement a variety of business logic as needed.
  • This alternative embodiment combines the above two NP characteristics to generate a message through the packet generator.
  • the rate of the packet generator is controllable. If the required test rate exceeds the bandwidth of the packet generator, such as testing the processing performance of 100G, it can be solved by configuring multiple packet generators, or by using the NP packet replication function. Reach the required rate.
  • the packet generator can be configured with different packet content templates and generated packet lengths. It can control the sending of different packet contents and packet lengths for board and machine testing.
  • FIG. 6 is a schematic structural diagram of a board level test method according to an embodiment of the present invention. As shown in FIG. 6, the method includes:
  • the CPU is responsible for the initialization of each chip on the board, which is the core of the entire control plane. In this patent, it is mainly responsible for packet generator, counter configuration, microcode download and error message processing.
  • Configure the packet generator Configure the interval for sending scanned packets.
  • the delivery interval is set according to the required test bandwidth.
  • Sending packet processing When the microcode verification fails, the CPU is interrupted and the CPU is responsible for processing the request, and the error address Idx is read from the packet.
  • the packet generator is a unit that is set by the network processor to periodically generate a message, and is generally used to implement OAM detection.
  • the packet generator can periodically generate packets according to the packet interval configured by the CPU.
  • the copy unit is the network processor base unit. Optional in this patent. In the case that the packet generator has insufficient bandwidth, the packet can be copied to achieve the desired bandwidth.
  • the switch chip needs to implement packet forwarding.
  • the packet must be queued in the switch chip, and the packet is stored in the peripheral DDR3.
  • the premise of the queue entry is that the network processor carries the switch header, and the switch header contains the queue ID of the switch chip. Therefore, the network processor microcode must calculate the corresponding queue ID according to the egress port, and encapsulate the queue ID into the packet header and carry it to the switch chip according to the exchange header format defined by the switch chip.
  • the function implemented by the network processor in the direction of microcode is implemented by means of microcode instructions.
  • the message received from the switching side is compared with the expected message. If the exchange network modifies a bit or byte in the message, the check unit can discover it and count it by the 306 unit, and send the message to the 301 CPU unit for processing.
  • the counter is set to 305 to check the statistical count of the message after it has been modified.
  • the packet In the inbound direction, the packet is queued according to the queue ID in the switching header carried by the NP. The packet is buffered in the external DDR3. After the scheduler is authorized, the chip is sliced into cells and the cell is dispatched to the corresponding egress switch chip. Unit; the egress switch unit reassembles the cells into packets and sends the direction to the network processor
  • DDR3 memory (308):
  • the DDR3 memory is an external memory attached to the switch chip and used to buffer messages.
  • FIG. 7 is a schematic structural diagram of a whole-machine test method according to an embodiment of the present invention. As shown in Figure 7, the difference from Figure 6 is the centralized scheduling process of a central switching chip (406) such that the test system covers the central switching chip unit (406).
  • FIG. 8 is a flowchart of a board test according to an embodiment of the present invention. As shown in FIG. 8, the process includes the following steps:
  • Step S804 configuring a packet generator and a counter, configuring a sending interval of the counting scan packet, and configuring the content and length of the packet as needed;
  • Step S806 the copy unit is copied. This step is optional.
  • the copy unit of the network processor is used to perform packet copying to achieve a desired bandwidth.
  • Step S808 the inbound direction microcode processing, according to the switching header format of the switching chip, and the outbound port encapsulation switching header;
  • Step S810 The switching network processes, and the switching network unit forwards the packet according to the format of the switching header.
  • the switching chip implements local switching, and the whole-level testing needs to involve cross-board switching.
  • step S812 the outbound direction microcode processing is performed, and the microcode compares the packet received from the switching network with the expected packet byte by byte. If the inconsistency is found, the process is performed in step S814 and discarded; otherwise, the packet is directly discarded;
  • step S814 the error count is counted and reported, and the verification fails in step S812, and the error message is sent to the CPU, so that the control layer can sense the error count and the offset position of the specific message modification;
  • the optional embodiment of the present invention utilizes the current network processor internal packet generator to generate a message, and utilizes the flexible characteristics of the network processor microcode to perform exchange header encapsulation, message copying, verification, and counting statistics. It effectively solves the problem of low cost and low efficiency of test method resources in related technologies, low cost and high promotion value.
  • a storage medium is further provided, wherein the software includes the above-mentioned software, including but not limited to: an optical disk, a floppy disk, a hard disk, an erasable memory, and the like.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. Perform the steps shown or described, or separate them into individual integrated circuit modules, or Multiple of these modules or steps are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.
  • the single board testing method and apparatus provided by the embodiments of the present invention have the following beneficial effects: compared with the testing methods provided in the related art, the utility model can effectively reduce resource consumption, improve testing efficiency, and reduce cost. High promotion value.

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Abstract

本发明公开了单板测试方法及装置，其中，该方法包括：网络处理器产生测试报文，并将测试报文发送至交换网络中的交换设备；网络处理器对经过交换设备的测试报文进行校验，将校验结果作为对单板的测试结果。通过本发明解决了相关技术中对单板进行测试效率低下的问题，进而实现了对单板的有效测试，提高了测试效率。

Description

单板测试方法及装置 技术领域
本发明涉及通信领域，具体而言，涉及单板测试方法及装置。
背景技术
现今网络发展速度惊人，网络流量的增长及新业务的出现，需要网络设备具有线速和灵活的处理能力。目前网络芯片包括专用集成电路(Application Specific Integrated Circuits，简称为ASIC)和网络处理器(Network Processor，简称为NP)两大类。网络处理器凭借其高速处理及灵活的可编程性，已成为当今网络中数据处理的有效解决方案。
如今主流的路由交换产品框架如图1所示，线卡上由接口卡、ASIC或NP，交换芯片以及中央处理器(Central Processing Unit，简称为CPU)组成。如果是集中式***，单块线卡就够了；如果是分布式***，则由多个线卡加***处理卡组成，中央控制处理卡负责完成多线卡间的跨板转发。
报文从进入***，到转发出***，会经过接口卡、ASIC/NP、交换***，并且各个模块间的链路(如串行外设接口(Serial Peripheral Interface，简称为SPI)、INTERLAKEN等)也会可能存在问题，因此在产品转产测试过程中，会对线卡进行转发测试，保证各个芯片及链路的完整性。
通常的测试***如图2所示，由测试仪发包，经过整个***后回到测试仪，测试仪接收端肉眼观察是否存在丢包。
测试发现，NP及交换网之间的高速serdes链路，非常容易出问题，另外交换芯片内部也会存在修改报文的问题，出问题的原因可能是电阻、电容虚焊，***DDR3问题等。
相关技术中的测试***最大的弊端是需要占用宝贵的测试仪资源，另外面板端口类型多种多样，可能是以太口或者窄带口，以太口有可能是GE、XG、40G及100G，窄带可能是POS、E1等，100G光模块很贵很难借到，而且面板可能出几十个端口，这样遍历测试耗费资源，效率低下。
相关技术中还提出了一种区别于传统方式的测试装置。机架上***一块特别设计的陪测单板，通过陪测单板发包到被测单板。但是其需要额外设计陪测单板，占用一个单独槽位进行测试，比较麻烦。
针对相关技术中，对单板进行测试效率低下的问题，还未提出有效的解决方案。
发明内容
本发明实施例提供了一种单板测试方法及装置，以至少解决相关技术对单板进行测试效率低下的问题。
根据本发明实施例的一个方面，提供了一种单板测试方法，包括：网络处理器产生测试报文，并将所述测试报文发送至交换网络中的交换设备；所述网络处理器对经过所述交换设备的测试报文进行校验，将校验结果作为对单板的测试结果。
进一步地，将所述测试报文发送至交换设备包括：所述网络处理器根据所述交换设备的交换头格式以及所述网络处理器的出端口，通过所述网络处理器的微码计算出所述交换设备的队列ID；将所述队列ID封装在所述测试报文中发送至所述交换设备。
进一步地，所述网络处理器对经过所述交换设备的测试报文进行校验包括：所述网络处理器利用微码将经过所述交换设备的测试报文与所述测试报文进行比较，在比较结果一致的情况下，所述测试结果指示所述单板正常；在比较结果不一致的情况下，所述测试结果指示所述单板异常。
进一步地，在比较结果不一致的情况下，所述网络处理器利用微码对错误字节进行统计，并将统计结果发送至中央处理器和/或丢弃经过所述交换芯片的测试报文。
进一步地，网络处理器产生测试报文包括：在当前测试报文传输速率小于预定阈值的情况下，所述网络处理器对所述当前测试报文进行复制，得到所述测试报文。
根据本发明实施例的另一方面，还提供了一种单板测试装置，应用于网络处理器，所述装置包括：产生模块，设置为产生测试报文，并将所述测试报文发送至交换网络中的交换设备；校验模块，设置为对经过所述交换设备的测试报文进行校验，将校验结果作为对单板的测试结果。
进一步地，所述产生模块包括：计算单元，设置为根据所述交换设备的交换头格式以及所述网络处理器的出端口，通过所述网络处理器的微码计算出所述交换设备的 队列ID；发送单元，设置为将所述队列ID封装在所述测试报文中发送至所述交换设备。
进一步地，所述校验模块还设置为利用微码将经过所述交换设备的测试报文与所述测试报文进行比较，在比较结果一致的情况下，所述测试结果指示所述单板正常；在比较结果不一致的情况下，所述测试结果指示所述单板异常。
进一步地，所述校验模块还设置为在比较结果不一致的情况下，利用微码对错误字节进行统计，并将统计结果发送至中央处理器和/或丢弃经过所述交换芯片的测试报文。
进一步地，所述产生模块还设置为在当前测试报文传输速率小于预定阈值的情况下，对所述当前测试报文进行复制，得到所述测试报文。
通过本发明实施例，采用网络处理器产生测试报文，并将测试报文发送至交换网络中的交换设备；网络处理器对经过交换设备的测试报文进行校验，将校验结果作为对单板的测试结果。解决了相关技术中对单板进行测试效率低下的问题，进而实现了对单板的有效测试，提高了测试效率。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是相关技术中网络路由交换产品结构示意图；
图2是相关技术中单板完整性测试方法结构示意图；
图3是根据本发明实施例的单板测试方法的流程图；
图4是根据本发明实施例的单板测试装置的结构框图；
图5是根据本发明实施例的单板测试装置的结构框图一；
图6是根据本发明实施例的单板级测试方法结构示意图；
图7是根据本发明实施例的整机级测试方法结构示意图；
图8是根据本发明实施例的单板测试流程图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
在本实施例中提供了一种单板测试方法，图3是根据本发明实施例的单板测试方法的流程图，如图3所示，该流程包括如下步骤：
步骤S302，网络处理器产生测试报文，并将测试报文发送至交换网络中的交换设备；
步骤S304，网络处理器对经过交换设备的测试报文进行校验，将校验结果作为对单板的测试结果。
通过上述步骤，利用网络处理器内部资源产生测试报文，并将测试报文发送至交换设备，对经过交换设备的测试报文进行校验，来完成对单板的测试，相比于相关技术中对单板的测试需要占用测试仪或者添加陪测单板，上述步骤解决了相关技术中对单板进行测试效率低下的问题，进而实现了对单板的有效测试，提高了测试效率。
上述步骤S302涉及到网络处理器将测试报文发送至交换设备，需要说明的是，交换设备要实现报文转发需要满足一定的条件，在一个可选实施例中，网络处理器根据交换设备的交换头格式以及网络处理器的出端口，通过网络处理器的微码计算出交换设备的队列标识ID；将队列ID封装在测试报文中发送至交换设备。
上述步骤S304涉及到网络处理器对经过交换设备的测试报文进行校验，网络处理器可以通过多种方式对测试报文进行校验，在一个可选实施例中，网络处理器利用微码将经过交换设备的测试报文与预设的测试报文进行比较，在比较结果一致的情况下，测试结果指示单板正常；在比较结果不一致的情况下，测试结果指示单板异常。从而，通过对测试报文的校验实现了对单板的测试。
在一个可选实施例中，在比较结果不一致的情况下，网络处理器利用微码对错误字节进行统计，并将统计结果发送至中央处理器，在另一可选实施例中，在比较结果不一致的情况下，丢弃经过交换芯片的测试报文。
网络处理器产生的测试报文需要达到一定的速度，在一个可选实施例中，在当前测试报文传输速率小于预定阈值的情况下，网络处理器对当前测试报文进行复制，得到测试报文，从而通过对当前测试报文的复制，使得产生的测试报文达到一定的速度。
在本实施例中还提供了一种单板测试装置，该装置设置为实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图4是根据本发明实施例的单板测试装置的结构框图，该应用于网络处理器，如图4所示，该装置包括：产生模块42，设置为产生测试报文，并将测试报文发送至交换网络中的交换设备；校验模块44，设置为对经过交换设备的测试报文进行校验，将校验结果作为对单板的测试结果。
图5是根据本发明实施例的单板测试装置的结构框图一，如图5所示，产生模块42包括：计算单元422，设置为根据交换设备的交换头格式以及该网络处理器的出端口，通过网络处理器的微码计算出交换设备的队列标识ID；发送单元424，设置为将队列标识ID封装在测试报文中发送至交换设备。
可选地，校验模块44还设置为利用微码将经过交换设备的测试报文与测试报文进行比较，在比较结果一致的情况下，测试结果指示该单板正常；在比较结果不一致的情况下，测试结果指示单板异常。
可选地，在比较结果不一致的情况下，校验模块44利用微码对错误字节进行统计，并将统计结果发送至中央处理器和/或丢弃经过该交换芯片的测试报文。
可选地，产生模块42还设置为在当前测试报文传输速率小于预定阈值的情况下，对当前测试报文进行复制，得到测试报文。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述各模块均位于同一处理器中；或者，上述各模块分别位于第一处理器、第二处理器和第三处理器…中。
针对相关技术中存在的上述问题，下面结合可选实施例进行说明，本可选实施例结合了上述实施例及其可选实施方式。
本可选实施例利用网络处理器的包产生器周期性地产生报文，借助于网络处理器灵活的处理性能，进行单板及整机的完整性测试。
目前网络处理器为了支持运行、管理和维护(Operation Administration and Maintenance，简称为OAM)检测，内部一般都有包产生器，可以根据指定时间间隔周期性发送报文。本可选实施例利用了网络处理器这一特性，配置包产生器周期性发 送报文，由微码组装交换头，经过交换***后再回到NP，由egress方向微码进行报文校验，并对校验失败的情况进行统计，并把相关信息(比如索引、读出来的结果)携带在报文中上送中央处理器(Central Processing Unit，简称为CPU)。
如果校验成功，证明整个链路没有问题；如果有校验失败的情况，需要对交换网芯片及中间的链路进行排查，找到问题。
分组传送网(Packet Transfer Network，简称为PTN)设备目前的一个重要功能就是链路检测，比如OAM/双向转发检测(Bidirectional Forwarding Detection，简称为BFD)等，因此目前主流NP内部都会有包产生器，可以设置包产生器报文间隔周期性发送检测报文。
网络处理器的另一个特征是编程灵活性。内部微码可以根据需要实现各种业务逻辑。
本可选实施例将如上两个NP特性结合起来，通过包产生器产生报文。包产生器速率可控，如果需要的测试速率超过了包产生器的带宽，比如测试100G的处理性能，可以通过配置多个包产生器的方法解决，或者利用NP的报文复制功能，通过复制达到需要的速率。
包产生器通常可以配置不同的报文内容模板及产生的包长，可以控制发送不同的报文内容及包长，进行单板及整机测试。
图6是根据本发明实施例的单板级测试方法结构示意图，如图6所示，包括：
CPU模块(301)：
CPU负责单板上各个芯片的初始化，是整个控制层面的核心，在本专利中主要负责包产生器、计数器配置，微码下载及错误情况的上送报文处理。
配置包产生器：配置扫描报文发送间隔。发包间隔根据需要的测试带宽设置。
上送报文处理：当微码校验失败，会中断上报CPU，CPU负责处理该请求，从报文中读取错误地址Idx。
包产生器(302)：
包产生器为网络处理器设置为周期性产生报文的单元，通常用于实现OAM检测。包产生器可以按照CPU配置的报文间隔时间周期性产生报文。
复制单元(303)：
复制单元为网络处理器基本单元。在本专利中可选。在包产生器带宽不够情况下，可以通过报文复制，达到期望的带宽。
交换头封装(304)：
交换芯片要实现报文转发，报文必须在交换芯片入队列，而报文是存储在***的DDR3中，入队列的前提是网络处理器携带交换头，交换头中包含交换芯片的队列ID。因此网络处理器微码必须根据出端口计算出相应的队列ID，按照交换芯片定义的交换头格式把队列ID封装到报文头中携带给交换芯片。
校验单元(305)：
由网络处理器出方向微码实现的功能，借助微码指令实现。将从交换侧接收到的报文，和预期的报文进行对比。如果交换网上修改了报文中的某个bit或byte，校验单元能够发现，并由306单元进行计数，并将报文上送301CPU单元处理。
计数器(306)：
该计数器设置为305校验单元检查到报文被修改后的统计计数。
交换芯片(307)：
入方向根据NP携带过来的交换头中的队列ID，将报文入队列，报文会缓存在外部DDR3中，当得到调度器授权后，芯片切片成信元后调度信元到相应出***换芯片单元；出***换单元将信元重组成报文并发给出方向的网络处理器
DDR3存储器(308)：
DDR3存储器为挂接于交换芯片的外部存储器，用来缓存报文。
图7是根据本发明实施例的整机级测试方法结构示意图。如图7所示，与图6区别是多了一个中央交换芯片(406)的集中式调度处理，这样测试***覆盖到了中央交换芯片单元(406)。
图8是根据本发明实施例的单板测试流程图，如图8所示，该流程包括如下步骤：
步骤S802，开始；
步骤S804，配置包产生器及计数器，配置计数扫描报文的发送间隔，报文内容及长度根据需要配置；
步骤S806，复制单元复制，本步骤为可选项，在包产生器产生报文速率不够情况下，利用网络处理器的复制单元进行报文复制以达到期望的带宽；
步骤S808，入方向微码处理，根据交换芯片的交换头格式，以及出端口封装交换头；
步骤S810，交换网处理，交换网单元根据交换头格式，对报文进行转发，对于单板级测试，交换芯片实现本地交换，整机级测试需要涉及跨板交换；
步骤S812，出方向微码处理，微码将从交换网收到的报文与预期的报文进行逐字节的对比，如果发现不一致则用步骤S814进行统计并丢弃；否则直接丢弃；
步骤S814，错误计数统计及上报，对于步骤S812中校验失败的情况进行统计计数，并且将错误报文上送CPU，这样控制层面能感知到错误计数以及具体报文修改的偏移位置；
步骤S816，结束。
综上所述，本发明可选实施例利用了目前网络处理器内部包产生器产生报文，同时利用网络处理器微码灵活的特性进行交换头封装、报文复制、校验及计数统计。有效解决了相关技术中测试方法资源耗费、效率低下的问题，成本低，具有很高的推广价值。
在另外一个实施例中，还提供了一种软件，该软件用于执行上述实施例及优选实施方式中描述的技术方案。
在另外一个实施例中，还提供了一种存储介质，该存储介质中存储有上述软件，该存储介质包括但不限于：光盘、软盘、硬盘、可擦写存储器等。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将 它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
如上所述，本发明实施例提供的一种单板测试方法及装置具有以下有益效果：与相关技术中所提供的测试方法相比，能够有效地降低资源耗费、提高测试效率、减少成本，具有很高的推广价值。

Claims (10)

  1. 一种单板测试方法，包括：
    网络处理器产生测试报文，并将所述测试报文发送至交换网络中的交换设备；
    所述网络处理器对经过所述交换设备的测试报文进行校验，将校验结果作为对单板的测试结果。
  2. 根据权利要求1所述的方法，其中，将所述测试报文发送至交换设备包括：
    所述网络处理器根据所述交换设备的交换头格式以及所述网络处理器的出端口，通过所述网络处理器的微码计算出所述交换设备的队列标识ID；
    将所述队列标识ID封装在所述测试报文中发送至所述交换设备。
  3. 根据权利要求1所述的方法，其中，所述网络处理器对经过所述交换设备的测试报文进行校验包括：
    所述网络处理器利用微码将经过所述交换设备的测试报文与所述测试报文进行比较，在比较结果一致的情况下，所述测试结果指示所述单板正常；在比较结果不一致的情况下，所述测试结果指示所述单板异常。
  4. 根据权利要求3所述的方法，其中，在比较结果不一致的情况下，所述网络处理器利用微码对错误字节进行统计，并将统计结果发送至中央处理器和/或丢弃经过所述交换芯片的测试报文。
  5. 根据权利要求1至4中任一项所述的方法，其中，网络处理器产生测试报文包括：
    在当前测试报文传输速率小于预定阈值的情况下，所述网络处理器对所述当前测试报文进行复制，得到所述测试报文。
  6. 一种单板测试装置，应用于网络处理器，所述装置包括：
    产生模块，设置为产生测试报文，并将所述测试报文发送至交换网络中的交换设备；
    校验模块，设置为对经过所述交换设备的测试报文进行校验，将校验结果作为对单板的测试结果。
  7. 根据权利要求6所述的装置，其中，所述产生模块包括：
    计算单元，设置为根据所述交换设备的交换头格式以及所述网络处理器的出端口，通过所述网络处理器的微码计算出所述交换设备的队列标识ID；
    发送单元，设置为将所述队列标识ID封装在所述测试报文中发送至所述交换设备。
  8. 根据权利要求6所述的装置，其中，所述校验模块还设置为利用微码将经过所述交换设备的测试报文与所述测试报文进行比较，在比较结果一致的情况下，所述测试结果指示所述单板正常；在比较结果不一致的情况下，所述测试结果指示所述单板异常。
  9. 根据权利要求8述的装置，其中，所述校验模块还设置为在比较结果不一致的情况下，利用微码对错误字节进行统计，并将统计结果发送至中央处理器和/或丢弃经过所述交换芯片的测试报文。
  10. 根据权利要求6至9中任一项所述的装置，其中，所述产生模块还设置为在当前测试报文传输速率小于预定阈值的情况下，对所述当前测试报文进行复制，得到所述测试报文。
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CN101854648A (zh) * 2010-04-14 2010-10-06 华为技术有限公司 通信设备单板的测试方法、设备和测试***
CN102143014A (zh) * 2010-11-03 2011-08-03 华为数字技术有限公司 一种检测单板故障的方法、单板和路由器
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CN110601801B (zh) * 2019-08-23 2021-11-05 深圳震有科技股份有限公司 一种tdm背板总线测试方法、测试装置及存储介质
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