WO2016078213A1 - 一种阵列基板和液晶显示面板及其驱动方法 - Google Patents
一种阵列基板和液晶显示面板及其驱动方法 Download PDFInfo
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Definitions
- the present invention relates to liquid crystal display technology, and more particularly to an array substrate and a liquid crystal display panel capable of improving the difference in brightness between left and right eyes and a driving method thereof.
- three-dimensional stereo imaging technology can provide more vivid stereoscopic images, and thus has become the mainstream direction of current display technology development. Due to its slimness, low power consumption and no radiation pollution, the liquid crystal display device has become the mainstream configuration of various industries and even home entertainment displays. Therefore, the three-dimensional stereoscopic imaging liquid crystal display device developed on the basis of the original two-dimensional planar display technology has also become a new development hot spot.
- the more common three-dimensional imaging technology is shutter glasses technology.
- the technology adopts the time division effect, so that the left lens and the right lens of the 3D glasses are sequentially switched in turn: when the right lens is opened, the liquid crystal display device simultaneously outputs the image provided to the right eye; when the left lens is opened, the liquid crystal The display device simultaneously outputs the image provided to the left eye, and then by the difference in the angles of the left and right eye angles, the image viewer superimposes the images of the left and right eyes into a three-dimensional image with depth of field and layering in the brain.
- the liquid crystal display device generally drives the liquid crystal molecules to rotate by alternating current, and realizes different gray scale image display by changing the rotation angle of the liquid crystal molecules. This is because if the liquid crystal molecules are driven to rotate by the direct current mode, the moving ions in the liquid crystal molecules will move in the same direction, thereby generating another electric field and affecting the steering of the liquid crystal molecules, that is, the DC residual phenomenon occurs. In order to prevent such a DC residual phenomenon from affecting the display quality of the picture, the liquid crystal display generally changes the voltage applied to the pixel electrode of the pixel unit periodically by changing the positive and negative polarities of the image information data signal.
- a light-transmissive bright picture (a white picture of 255 steps) is recorded as L255, and a dark picture (a black picture of 0th order) which is opaque is recorded as L0.
- the positive and negative driving voltages of the white screen are 7V and 5V, respectively, and the positive and negative driving voltages of the black screen are 1V and 11V, respectively, and the common electrode voltage is 6V.
- the voltage on the panel and the difference between the voltage and the common electrode voltage are as shown in Table 1 below.
- the voltage difference across the pixel electrode relative to the common electrode will vary between 1V and 5V. That is, the voltage applied to the liquid crystal during the positive polarity driving period was 1 V; and the voltage applied to the liquid crystal during the negative polarity driving period was 5V. Since the voltages acting on the liquid crystal during the positive and negative driving periods are too large and always positive, they cannot cancel each other out. Therefore, after a long time of operation, the point will have a residual charge similar to DC residual, thereby causing three-dimensional image sticking. .
- the dual-frame image polarity inversion driving method is often used in the prior art to change the positive and negative polarities of the image information data signal. Since the polarity of the data signal is inverted every two frames, the voltage on the pixel electrode and the difference between the voltage and the common electrode voltage are shown in Table 2 below.
- the voltage difference with respect to the common electrode on the pixel electrode is repeatedly cycled between 1V ⁇ -5V ⁇ -1V ⁇ 5V. That is, the voltage applied to the liquid crystal during the positive polarity driving period was 1 V and -5 V; and the voltage applied to the liquid crystal during the negative polarity driving period was -1 V and 5 V.
- the voltage difference on the pixel electrode with respect to the common electrode during the positive and negative polarity driving is mutually compensated, so that the image sticking phenomenon does not occur.
- the problem of uneven brightness of the left and right eyes is derived. This phenomenon is particularly prominent for liquid crystal display panels that use charge sharing technology (LCS) to improve color shift.
- LCD charge sharing technology
- the pixel electrode of the pixel unit in the liquid crystal display panel is usually divided into two parts of a main area (Main) and a sub-area (Sub), and a sharing capacitor is set to be in the control signal.
- Main main area
- Sub sub-area
- the charge on the primary and secondary regions is redistributed, and the voltage on the primary and secondary regions is changed.
- the shared capacitor has a function of storing the charge, when the shared capacitor obtains the same polarity during the new frame image as the charge stored during the previous frame image, the new frame image will be relatively more due to the charge accumulation effect.
- the shared capacitor acquires a charge that is opposite to the charge stored during the previous frame, the new frame will be relatively dark because the charges cancel each other out. Therefore, when the same data signal is input (for example, the input signal L255 in Table 3 below), the brightness of the left-eye image output by the liquid crystal display panel operating in the dual-frame image polarity inversion driving mode is always lower than that of the right-eye image. .
- the inventors of the present invention have proposed a new array substrate and liquid crystal display panel capable of improving the difference in brightness between left and right eyes and a driving method thereof through repeated experiments and explorations.
- an object of the present invention is to provide a new array substrate and liquid crystal display panel and Drive method.
- the array substrate and the liquid crystal display panel can overcome the large-view character deviation phenomenon in the two-dimensional scanning mode, and can improve the left and right eye brightness difference problems in the three-dimensional mode.
- the invention provides an array substrate comprising:
- a plurality of pixel units disposed in an array of the plurality of scan lines and the plurality of data lines, each of the pixel units corresponding to the scan line and the data line, and comprising:
- a main area electrode connected to the corresponding data line through a main area control switch, wherein the control end of the main area control switch is connected to the corresponding scan line to receive the data signal on the data line when there is a scan signal on the scan line Has a main zone voltage;
- sub-area electrode connected to the corresponding data line through the sub-area control switch, wherein the control end of the sub-area control switch is connected to the corresponding scan line to receive the data signal on the data line when there is a scan signal on the scan line Has a sub-region voltage;
- Sharing a capacitor which is connected to the sub-area electrode through a sharing control switch, and the control end of the sharing control switch is connected to a scan line corresponding to the Nth pixel unit arranged in the scanning direction from the pixel unit through a control switch;
- control switch is configured to be turned on in a two-dimensional scanning mode according to the received control signal at least on a scan line connected thereto, thereby having a charge sharing function, and in the three-dimensional scanning mode, at least The charge sharing function is turned off when there is a scan signal on the connected scan line.
- control switches corresponding to the pixel units corresponding to each of the N-1 scan lines are grouped into one group in the scanning direction; wherein the control end of the odd array control switch is connected to a first switch control line. Receiving the first switch control signal and turning on or off under the action thereof, and the control end of the even array control switch is connected to a second switch control line, receiving the second switch control signal, and being turned on or off under the action thereof; among them,
- the first switch control signal and the second switch control signal are continuous high level signals
- the first switch control signal is synchronized with the second switch control signal, which is an odd pulse sequence signal and an even pulse sequence signal, respectively, and the odd/even pulse sequence signal has a pulse width equal to the scan signal. N-1 times the duration.
- control end of the control switch corresponding to the pixel unit corresponding to the odd scan line is connected to a first switch control line, receives the first switch control signal, and is guided by the action Turning on or off, the control end of the control switch corresponding to the pixel unit corresponding to the even scan line is connected to a second switch control line, receiving the second switch control signal, and being turned on or off under the action thereof;
- the first switch control signal and the second switch control signal are continuous high level signals
- the first switch control signal and the second switch control signal are synchronized but opposite polarity pulse sequence signals, and the pulse sequence signal has a pulse width equal to the duration of the scan signal; N is an odd number, the first switch control signal is an even pulse sequence signal, and if N is an even number, the first switch control signal is an odd pulse sequence signal.
- an auxiliary line corresponding to the scan line is further disposed on the array substrate, and a control end of the sharing control switch in each of the pixel units is connected to the corresponding control by the auxiliary line. switch.
- control switch may be arranged in a fan-out zone.
- the main zone control switch, the secondary zone control switch, the share control switch, and the control switch are all thin film switching transistors.
- the present invention also provides a liquid crystal display panel, including:
- the array substrate, the color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate are provided.
- the present invention also provides a driving method of the above liquid crystal display panel, including a two-dimensional scanning driving step and a three-dimensional scanning driving step;
- the two-dimensional scan driving step includes:
- Scanning signals are sequentially input to the respective scanning lines along the scanning direction;
- the main area control switch and the sub-area control switch in the pixel unit corresponding to the scan line are turned on, so that the data signals of the main area electrode and the sub-area electrode on the data line are activated.
- the same voltage is provided under the control; at the same time, the control switch connected to the scan line is turned on, so that the sharing control switch connected to the control switch is turned on, thereby enabling the pixel unit where the sharing control switch is located to implement a charge sharing function;
- the three-dimensional scan driving step includes:
- Scanning signals are sequentially input to the respective scanning lines along the scanning direction;
- the main area control switch and the sub-area control switch in the pixel unit corresponding to the scan line are turned on, so that the data signals of the main area electrode and the sub-area electrode on the data line are activated.
- the lower voltage has the same voltage; at the same time, the control switch connected to the scan line is controlled to be turned off.
- the control switches corresponding to the pixel units corresponding to each N-1 scanning lines are grouped into one group, and the first switch control signal is applied to the control switch of the odd array, the dual array
- the control switch applies a second switch control signal
- the first switch control signal and the second switch control signal are both continuous high level signals
- the first switch control signal is synchronized with the second switch control signal, which is an odd pulse sequence signal and an even pulse sequence signal, respectively, and the odd/even pulse sequence signal has a pulse width equal to the scan signal. N-1 times the duration.
- control end of the control switch corresponding to the pixel unit corresponding to the odd scan line is applied with the first switch control signal, and the control end of the control switch corresponding to the pixel unit corresponding to the even scan line is applied. Controlling the signal with a second switch; wherein
- the first switch control signal and the second switch control signal are both continuous high level signals
- the first switch control signal and the second switch control signal are synchronized but opposite polarity pulse sequence signals, and the pulse sequence signal has a pulse width equal to the duration of the scan signal; if N is an odd number, Then, the first switch control signal is an even pulse sequence signal, and if N is an even number, the first switch control signal is an odd pulse sequence signal.
- 1 is a partial equivalent circuit diagram of an array substrate of the present invention
- FIG. 2A is a timing control signal diagram in a two-dimensional scanning mode according to Embodiment 1 of the present invention.
- FIG. 2B is a timing control signal diagram in a three-dimensional scanning mode according to Embodiment 1 of the present invention.
- 3A is a timing control signal diagram in a two-dimensional scanning mode according to Embodiment 2 of the present invention.
- 3B is a timing control signal diagram in a three-dimensional scan mode when N is an odd number in the second embodiment of the present invention
- 3C is a timing control signal diagram in a three-dimensional scanning mode when N is an even number in the second embodiment of the present invention.
- the present invention proposes a new array substrate and liquid crystal display panel and a driving method thereof.
- the array substrate comprises:
- a plurality of pixel units arranged in an array of a plurality of scan lines and a plurality of data lines, each of the pixel units corresponding to a scan line and a data line, and comprising:
- the main area electrode is connected to the corresponding data line through the main area control switch, and the control end of the main area control switch is connected to the corresponding scan line for receiving the data signal on the data line when there is a scan signal on the scan line Main area voltage
- the sub-area electrode is connected to the corresponding data line through the sub-area control switch, and the control end of the sub-area control switch is connected to the corresponding scan line for receiving the data signal on the data line when there is a scan signal on the scan line Secondary zone voltage
- Sharing a capacitor which is connected to the sub-area electrode through a sharing control switch, and the control end of the sharing control switch is connected to a scan line corresponding to the Nth pixel unit arranged in the scanning direction from the pixel unit through a control switch;
- control switch is configured to be turned on in the two-dimensional scanning mode according to the received control signal at least when there is a scanning signal on the connected scanning line thereof, thereby having a charge sharing function, and in the three-dimensional scanning mode, at least when The charge sharing function is turned off when the connected scan line is turned off when there is a scan signal.
- the array substrate includes an image display area AA and a fan-out area Fanout (not shown).
- the image display area AA includes a plurality of pixel units arranged in a pixel array in which a plurality of common electrodes, a plurality of scan lines, and a plurality of data lines are interleaved by a plurality of scan lines and a plurality of data lines.
- Each pixel unit has the same structure, corresponding to one scan line and one data line, and includes a main area electrode (Main) and a sub-area electrode (Sub), and a sharing capacitor Cshare for charge sharing.
- the pixel unit structure of the array substrate of the present invention will be described in detail below by taking the pixel unit P 1M corresponding to the first scanning line Gate_1 and the Mth data line Data_M as an example.
- the main area electrode (Main) is configured with a main area control switch TFT_A.
- the first end of the main area control switch TFT_A is connected to the corresponding data line Data_M, the second end is connected to the main area electrode, and the control end is connected to the corresponding scan line Gate_1.
- the control end of the main area control switch TFT_A receives the scan drive from the scan line Gate_1
- the first end and the second end of the main area control switch TFT_A are turned on, thereby transmitting the data signal from the data driving circuit on the data line Data_M to the main area electrode.
- the main area liquid crystal capacitor Clc_A formed by coupling between the main area electrode and the common electrode CF_com of the color filter substrate, and the main area storage capacitor Cst_A formed by coupling between the main area electrode and the common electrode A_com of the array substrate will be in the data.
- the charging is started under the action of the signal, so that the main area electrode has and maintains a certain main area voltage.
- the sub-area electrode (Sub) is provided with a sub-area control switch TFT_B.
- the first end of the sub-area control switch TFT_B is connected to the corresponding data line Data_M, the second end is connected to the sub-area electrode, and the control end is connected to the corresponding first scan line Gate_1.
- the control end of the sub-region control switch TFT_B receives the scan signal from the scan driving circuit through the scan line Gate_1, the first end and the second end of the sub-region control switch TFT_B are turned on, thereby bringing the data line Data_M from the data driving circuit.
- the data signal is passed to the secondary electrode.
- the sub-region liquid crystal capacitor Clc_B formed by coupling between the sub-region electrode and the common electrode CF_com of the color filter substrate, and the sub-region storage capacitor Cst_B formed by coupling between the sub-region electrode and the common electrode A_com of the array substrate, will be in the data.
- the charging is started under the action of the signal, so that the secondary region electrode has and maintains a certain sub-region voltage.
- Sharing capacitor Cshare configuration has a shared control switch TFT_C.
- the first end of the sharing control switch TFT_C is connected to the secondary electrode, the second end is connected to one electrode of the sharing capacitor Cshare, and the other electrode of the sharing capacitor Cshare is connected to the common electrode A_com of the array substrate.
- the control terminal of the sharing control switch TFT_C connects the scan line Gate_N corresponding to the Nth pixel unit arranged in the scanning direction from the pixel unit through a control switch TFT_1.
- the number of control switches disposed on the array substrate is consistent with the number of scan lines, that is, each control switch corresponds to one row of pixel units.
- all of the control switches in this embodiment are preferably arranged at the fan-out area of the array substrate.
- an auxiliary line corresponding to the scan line is preferably arranged on the array substrate.
- the array substrate is arranged with auxiliary lines Gate_Share_1, Gate_Share_2, Gate_Share_3, etc. corresponding to the scan lines Gate_1, Gate_2, Gate_3, ...
- the control end of the sharing control switch in the pixel unit is connected to the first auxiliary line Gate_Share_1, one end of the control switch TFT_1 is connected to the first auxiliary line Gate_Share_1, the other end is connected to the Nth scanning line Gate_N;
- the second scanning line Gate_2 corresponds to The control end of the sharing control switch in the pixel unit is connected to the second auxiliary line Gate_Share_2, one end of the control switch TFT_2 is connected to the second auxiliary line Gate_Share_2, and the other end is connected to the N+1th scanning line Gate_N+1;
- the control terminal of the sharing control switch in the pixel unit corresponding to the scan line Gate_3 is connected to the third auxiliary On the helper Gate_Share_3, one end of the control switch TFT_3 is connected to the third auxiliary line Gate_Share_3, the other end is connected to the N+2th scanning line Gate_N+2... and so on.
- the main area control switch, the sub area control switch, the sharing control switch, and the control switch may all be thin film switching transistors.
- the present invention proposes:
- each control switch is turned on at least when there is a scan signal on the connected scan line;
- each control switch is turned off at least when there is a scan signal on its connected scan line.
- the inventors of the present invention have proposed an embodiment. That is, in the scanning direction, the control switches corresponding to the pixel units corresponding to each (N-1) scanning lines are grouped. Wherein: the control end of the odd-array control switch is connected to the first switch control line to receive the first switch control signal, and is turned on or off under its action; the control end of the even-array control switch is connected to the second switch control line to receive the first The two switch control signals are turned on or off under their action.
- N 3 as an example for explanation.
- each of the two control switches is grouped into one group: the control switches TFT_1 and TFT_2 are the first group, the control switches TFT_3 and TFT_4 are the second group, the control switches TFT_5 and TFT_6 are the third group, and the control switches TFT_7 and TFT_8 are controlled.
- the fourth group ... and so on.
- the first group, the third group, the fifth group the control end of the odd array control switch is connected to the first switch control line Line_1, and receives the first switch control signal SW1;
- the second group, the fourth group, the sixth group The control terminal of the even array of control switches is connected to the second switch control line Line_2 and receives the second switch control signal SW2.
- the first switch control signal SW1 and the second switch control signal SW2 are both continuous high level signals, so that all the control switches maintain a continuous conduction state during the scan.
- the above-described operating conditions of "at least when the scan signal is input on the scan line to which it is connected" are satisfied. Therefore, in the two-dimensional scanning mode, when there is a scan signal on a scan line, the main area control switch and the sub-area control switch in the pixel unit corresponding to the scan line are turned on, so that the main area electrode and the sub-area electrode are The data signal on the data line has the same voltage under the action of the data signal.
- the control switch connected to the scan line since the control switch connected to the scan line remains turned on, the scan signal on the scan line can be transmitted to the corresponding pixel unit.
- the control terminal of the control switch is shared, so that the corresponding pixel unit can implement the charge sharing function and improve the color shift phenomenon.
- the first switch control signal SW1 is synchronized with the second switch control signal SW2, which is an odd pulse sequence signal and an even pulse sequence signal, respectively, and the pulse width of the pulse sequence signal is equal to (N-1) times the duration of the scan signal.
- the pulse width is 2T
- T is the duration of the scan signal.
- SW1 is at a low level, so that the control switch TFT_1 is turned off; when a high-level scan signal is input to the fourth scan line Gate_4, the first control received by the control terminal of the control switch TFT_2 connected to the fourth scan line Gate_4
- the signal SW1 is at a low level, so that the control switch TFT_2 is turned off; when a high-level scan signal is input to the fifth scan line Gate_5, the control terminal of the control switch TFT_3 connected to the fifth scan line Gate_5 receives the second
- the control signal SW2 is at a low level, so the control switch TFT_5 is turned off, and so on.
- the control switch connected thereto is low-powered by the control terminal.
- the flat control signal (SW1 or SW2) is turned off, and satisfies the aforementioned operating condition of "cutting off at least when there is a scan signal on the scan line to which it is connected". Therefore, in the three-dimensional scanning mode: when there is a scanning signal on a scanning line, only the main area control switch and the sub-area control switch in the pixel unit corresponding to the scanning line are turned on, so that the main area electrode and the sub-area electrode are in the data.
- the data signals on the line have the same voltage.
- the control switches are divided into two groups: the control switches corresponding to the pixel units corresponding to the odd scan lines are a group, referred to as an odd array; the control switches corresponding to the pixel units corresponding to the even scan lines are another group, referred to as Even array.
- the control terminal of the odd-array control switch is connected to the first switch control line to receive the first switch control signal, and is turned on or off under the action of the switch; the control end of the even-array control switch is connected to the second switch control line. Up to receive the second switch control signal and turn on or off under its action.
- the control terminals of the control switches TFT_1, TFT_3, TFT_5, ... corresponding to the pixel units corresponding to the odd scan lines Gate_1, Gate_3, Gate_5, . . . are connected to the first switch control line Line_1, and receive the first a switch control signal SW1 is turned on or off under its action; the control terminals of the control switches TFT_2, TFT_4, TFT_6, ... corresponding to the pixel units of the even scan lines Gate_2, Gate_4, Gate_6, ... are connected in parallel
- the second switch control line Line_2 receives the second switch control The signal SW2 is made and turned on or off under its action.
- the first switch control signal SW1 and the second switch control signal SW2 are both continuous high level signals, so all the control switches are in The continuous conduction state can be maintained during the scanning, that is, the aforementioned "on at least when there is a scanning signal on the connected scanning line".
- the first switch control signal SW1 and the second switch control signal SW2 are synchronized but opposite polarity pulse sequence signals, and the pulse sequence signal has a pulse width equal to that of the scan signal. duration. Further, if N is an odd number, the first switch control signal SW1 is an even pulse sequence signal, and the second switch control signal SW2 is an odd pulse sequence signal; if N is an even number, the first switch control signal SW1 is an odd pulse sequence The signal, the second switch control signal SW2 is an even pulse sequence signal.
- the first switch control signal SW1 is an even pulse sequence signal
- the second switch control signal SW2 is an odd pulse sequence signal.
- the control switch TFT_1 is turned off; when a high-level scan signal is input to the fourth scan line Gate_4, the second control signal SW2 received by the control terminal of the control switch TFT_2 connected to the fourth scan line Gate_4 is at a low level. Therefore, the control switch TFT_2 is turned off, and so on.
- the control switch connected thereto receives a low level control signal (SW1 or SW2) due to the control terminal. And cut off, satisfying the aforementioned operating condition that "the control switch is turned off at least when there is a scan signal on the scan line to which it is connected".
- the first switch control signal SW1 is an odd pulse sequence signal
- the second switch control signal SW2 is an even pulse sequence signal.
- the first control signal SW1 received by the control terminal of the control switch TFT_1 connected to the fourth scan line Gate_4 is at a low level. Therefore, the control switch TFT_1 is turned off; when a high-level scan signal is input to the fifth scan line Gate_5, the second control signal SW2 received by the control terminal of the control switch TFT_2 connected to the fifth scan line Gate_5 is at a low level. Therefore, the control switch TFT_2 is turned off, and so on.
- the control switch connected thereto receives a low level control signal (SW1 or SW2) due to the control terminal. And cut off, satisfying the aforementioned operating condition that "the control switch is turned off at least when there is a scan signal on the scan line to which it is connected".
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Abstract
Description
Claims (19)
- 一种阵列基板,其中包括:多条扫描线和多条数据线;配置在由所述多条扫描线和多条数据线交错而成的阵列中的多个像素单元,每一所述像素单元对应一所述扫描线和一所述数据线,并包括:主区电极,其通过主区控制开关连接对应的数据线,所述主区控制开关的控制端连接对应的扫描线,以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有主区电压;次区电极,其通过次区控制开关连接对应的数据线,所述次区控制开关的控制端连接对应的扫描线,以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有次区电压;分享电容,其通过分享控制开关连接所述次区电极,所述分享控制开关的控制端通过一控制开关与从本像素单元起沿扫描方向排列的第N个像素单元对应的扫描线连接;其中,所述控制开关配置成根据接收的控制信号,在二维扫描模式下,至少当其连接的扫描线上有扫描信号时导通,以及在三维扫描模式下,至少当其连接的扫描线上有扫描信号时截止。
- 如权利要求1所述的阵列基板,其中包括:沿扫描方向,将每N-1条扫描线对应的像素单元所对应的控制开关归为一组;其中,奇数组控制开关的控制端连接一第一开关控制线,接收第一开关控制信号,并在其作用下导通或者截止,偶数组控制开关的控制端连接一第二开关控制线,接收第二开关控制信号,并在其作用下导通或者截止;其中,在二维扫描模式下,所述第一开关控制信号与第二开关控制信号均为持续的高电平信号;在三维扫描模式下,所述第一开关控制信号与第二开关控制信号同步,分别为奇脉冲序列信号和偶脉冲序列信号,且所述奇/偶脉冲序列信号的脉冲宽度等于所述扫描信号时长的N-1倍。
- 如权利要求1所述的阵列基板,其中包括:与奇数扫描线对应的像素单元所对应的控制开关的控制端并接在一第一开关控制线上,接收第一开关控制信号,并在其作用下导通或者截止,与偶数扫描 线对应的像素单元所对应的控制开关的控制端并接在一第二开关控制线上,接收第二开关控制信号,并在其作用下导通或者截止;其中,在二维扫描模式下,所述第一开关控制信号与第二开关控制信号均为持续的高电平信号;在三维扫描模式下,所述第一开关控制信号与第二开关控制信号为同步但极性相反的脉冲序列信号,且所述脉冲序列信号的脉冲宽度等于所述扫描信号的时长;同时,若N为奇数/偶数,所述第一开关控制信号为偶/奇脉冲序列信号。
- 如权利要求2所述的阵列基板,其中包括:所述阵列基板上还设置有与所述扫描线一一对应的辅助线,各所述像素单元中的分享控制开关的控制端通过所述辅助线连接其对应的控制开关。
- 如权利要求3所述的阵列基板,其中包括:所述阵列基板上还设置有与所述扫描线一一对应的辅助线,各所述像素单元中的分享控制开关的控制端通过所述辅助线连接其对应的控制开关。
- 如权利要求4所述的阵列基板,其中包括:所述控制开关设置在扇出区。
- 如权利要求5所述的阵列基板,其中包括:所述控制开关设置在扇出区。
- 如权利要求2所述的阵列基板,其中包括:所述主区控制开关、次区控制开关、分享控制开关以及所述控制开关均为薄膜开关晶体管。
- 如权利要求3所述的阵列基板,其中包括:所述主区控制开关、次区控制开关、分享控制开关以及所述控制开关均为薄膜开关晶体管。
- 一种液晶显示面板,包括阵列基板,其中包括:多条扫描线和多条数据线;配置在由所述多条扫描线和多条数据线交错而成的阵列中的多个像素单元,每一所述像素单元对应一所述扫描线和一所述数据线,并包括:主区电极,其通过主区控制开关连接对应的数据线,所述主区控制开关的控制端连接对应的扫描线,以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有主区电压;次区电极,其通过次区控制开关连接对应的数据线,所述次区控制开关的控制端连接对应的扫描线,以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有次区电压;分享电容,其通过分享控制开关连接所述次区电极,所述分享控制开关的控制端通过一控制开关与从本像素单元起沿扫描方向排列的第N个像素单元对应的扫描线连接;其中,所述控制开关配置成根据接收的控制信号,在二维扫描模式下,至少当其连接的扫描线上有扫描信号时导通,以及在三维扫描模式下,至少当其连接的扫描线上有扫描信号时截止。
- 如权利要求10所述的液晶显示面板,其中包括:沿扫描方向,将每N-1条扫描线对应的像素单元所对应的控制开关归为一组;其中,奇数组控制开关的控制端连接一第一开关控制线,接收第一开关控制信号,并在其作用下导通或者截止,偶数组控制开关的控制端连接一第二开关控制线,接收第二开关控制信号,并在其作用下导通或者截止;其中,在二维扫描模式下,所述第一开关控制信号与第二开关控制信号均为持续的高电平信号;在三维扫描模式下,所述第一开关控制信号与第二开关控制信号同步,分别为奇脉冲序列信号和偶脉冲序列信号,且所述奇/偶脉冲序列信号的脉冲宽度等于所述扫描信号时长的N-1倍。
- 如权利要求10所述的液晶显示面板,其中包括:与奇数扫描线对应的像素单元所对应的控制开关的控制端并接在一第一开关控制线上,接收第一开关控制信号,并在其作用下导通或者截止,与偶数扫描线对应的像素单元所对应的控制开关的控制端并接在一第二开关控制线上,接收第二开关控制信号,并在其作用下导通或者截止;其中,在二维扫描模式下,所述第一开关控制信号与第二开关控制信号均为持续的高电平信号;在三维扫描模式下,所述第一开关控制信号与第二开关控制信号为同步但极性相反的脉冲序列信号,且所述脉冲序列信号的脉冲宽度等于所述扫描信号的时长;同时,若N为奇数/偶数,所述第一开关控制信号为偶/奇脉冲序列信号。
- 如权利要求11所述的液晶显示面板,其中包括:所述阵列基板上还设置有与所述扫描线一一对应的辅助线,各所述像素单元中的分享控制开关的控制端通过所述辅助线连接其对应的控制开关。
- 如权利要求12所述的液晶显示面板,其中包括:所述阵列基板上还设置有与所述扫描线一一对应的辅助线,各所述像素单元中的分享控制开关的控制端通过所述辅助线连接其对应的控制开关。
- 如权利要求11所述的液晶显示面板,其中包括:所述控制开关设置在扇出区。
- 如权利要求12所述的液晶显示面板,其中包括:所述控制开关设置在扇出区。
- 一种液晶显示面板的驱动方法,包括二维扫描驱动步骤和三维扫描驱动步骤;其中,所述二维扫描驱动步骤包括:沿扫描方向依次向各扫描线输入扫描信号;当一扫描线上有扫描信号时,使该扫描线对应的像素单元中的主区控制开关和次区控制开关导通,从而使主区电极和次区电极在数据线上的数据信号的作用下具有相同的电压;同时控制与该扫描线连接的控制开关导通,从而使与该控制开关连接的分享控制开关导通,进而使该分享控制开关所在的像素单元实现电荷分享功能;所述三维扫描驱动步骤包括:沿扫描方向依次向各扫描线输入扫描信号;当一扫描线上有扫描信号时,使该扫描线对应的像素单元中的主区控制开关和次区控制开关导通,从而使主区电极和次区电极在数据线上的数据信号的作用下具有相同的电压;同时控制与该扫描线连接的控制开关截止。
- 如权利要求17所述的驱动方法,其中:沿扫描方向,将每N-1条扫描线对应的像素单元所对应的控制开关归为一组,对奇数组的控制开关施以第一开关控制信号,对偶数组的控制开关施以第二开关控制信号;其中,在二维扫描模式下,第一开关控制信号与第二开关控制信号均为持续的高电平信号;在三维扫描模式下,所述第一开关控制信号与第二开关控制信号同步,分别为奇脉冲序列信号和偶脉冲序列信号,且所述奇/偶脉冲序列信号的脉冲宽度等于所述扫描信号时长的N-1倍。
- 如权利要求17所述的驱动方法,其中:与奇数扫描线对应的像素单元所对应的控制开关的控制端施以第一开关控制信号,与偶数扫描线对应的像素单元所对应的控制开关的控制端施以第二开关控制信号;其中,在二维扫描模式下,第一开关控制信号与第二开关控制信号均为持续的高电平信号;在三维扫描模式下,第一开关控制信号与第二开关控制信号为同步但极性相反的脉冲序列信号,且所述脉冲序列信号的脉冲宽度等于所述扫描信号的时长;若N为奇数/偶数,则第一开关控制信号为偶/奇脉冲序列信号。
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