WO2016032193A1 - Diode électroluminescente et son procédé de fabrication - Google Patents

Diode électroluminescente et son procédé de fabrication Download PDF

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WO2016032193A1
WO2016032193A1 PCT/KR2015/008840 KR2015008840W WO2016032193A1 WO 2016032193 A1 WO2016032193 A1 WO 2016032193A1 KR 2015008840 W KR2015008840 W KR 2015008840W WO 2016032193 A1 WO2016032193 A1 WO 2016032193A1
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Prior art keywords
layer
light emitting
electrode
semiconductor layer
ohmic contact
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PCT/KR2015/008840
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English (en)
Korean (ko)
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이소라
윤여진
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서울바이오시스 주식회사
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Priority claimed from KR1020150116046A external-priority patent/KR20160025455A/ko
Application filed by 서울바이오시스 주식회사 filed Critical 서울바이오시스 주식회사
Priority to US15/056,702 priority Critical patent/US9847458B2/en
Publication of WO2016032193A1 publication Critical patent/WO2016032193A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes

Definitions

  • the present invention relates to a light emitting device and a method for manufacturing the same, and more particularly, to a light emitting device having improved electrical conductivity and reliability and a method for manufacturing the same.
  • a light emitting diode is a device that makes a small number of carriers (electrons or holes) injected by using a pn junction structure of a semiconductor and emits a predetermined light by recombination thereof.
  • GaAs, AlGaAs, GaN, InGaN Various colors can be realized by configuring a light emitting source by changing a compound semiconductor material such as AlGaInP.
  • Such a light emitting diode has a smaller power consumption and a longer life than conventional light bulbs or fluorescent lamps, can be installed in a narrow space, and exhibits strong vibration resistance.
  • the light emitting diode is used as a display element and a backlight, and has excellent characteristics in terms of power consumption reduction and durability, applications have recently been extended to general lighting, large LCD-TV backlights, automotive headlights, and general lighting.
  • a light emitting diode is manufactured by sequentially forming an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and a reflective layer on a predetermined substrate.
  • the light emitting diode structure uses silver (Ag), silver oxide (Ag 2 O), or aluminum (Al) having high reflection efficiency as a material of the reflective layer, and these metals are difficult to form ohmic contacts, and thus, device operation is unstable. In operation, there is a problem that the device life is shortened by causing heat generation due to high driving voltage. Accordingly, many studies have been conducted on ohmic contact layers having low specific contact resistance and high reflectance.
  • an object of the present invention is to provide a light emitting device having improved electrical conductivity and reliability.
  • Another object of the present invention is to provide a method of manufacturing a light emitting device having improved electrical conductivity and reliability.
  • a light emitting device includes: an n-type semiconductor layer formed on a substrate; A p-type semiconductor layer formed on a portion of the n-type semiconductor layer; An active layer formed between the n-type semiconductor layer and the p-type semiconductor layer to generate light through recombination of electrons and holes; An ohmic contact layer formed on the p-type semiconductor layer and including an indium tin oxide (ITO) layer doped with a metal; A transparent conductor layer formed on the ohmic contact layer to a different thickness from the ohmic contact layer and including an undoped ITO layer; And a reflective layer formed on the transparent conductor layer and including an oxide layer.
  • ITO indium tin oxide
  • the ohmic contact layer silver (Ag), indium (In), tin (Sn), zinc (Zn), cadmium (Cd), gallium (Ga), aluminum (Al), magnesium ( Mg), titanium (Ti), molybdenum (Mo), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), iridium (Ir), ruthenium (Ru), and palladium ( May be doped with at least one metal of Pd).
  • the transparent conductor layer may be an ITO layer relatively thicker than the ohmic contact layer.
  • the reflective layer may be formed of a non-conductive material.
  • the reflective layer is silver (Ag), indium (In), tin (Sn), zinc (Zn), cadmium (Cd), gallium (Ga), aluminum (Al), magnesium (Mg) , Titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), iridium (Ir), ruthenium (Ru) And palladium (Pd) at least one conductive material.
  • the reflective layer may form a distributed Bragg reflector (DBR).
  • DBR distributed Bragg reflector
  • the distribution Bragg reflector may include a first oxide layer including silicon oxide (SiO x ); And a second oxide layer including titanium oxide (TiO x ).
  • the reflective layer may further include a dielectric film formed on the ohmic contact layer.
  • the reflective layer may be formed of a plurality of oxide layers having different refractive indices.
  • the reflective layer In an embodiment of the invention, the reflective layer, the first oxide layer; And a second oxide layer having a refractive index different from that of the first oxide layer.
  • a light emitting device in another embodiment, includes a first conductive semiconductor layer, a second conductive semiconductor layer positioned on the first conductive semiconductor layer, and the first and second conductive semiconductor layers.
  • a light emitting structure including an active layer interposed therebetween and at least one hole penetrating the second conductive semiconductor layer and the active layer to expose the first conductive semiconductor layer;
  • a current spreading layer disposed on the second conductive semiconductor layer, ohmic contacting the second conductive semiconductor layer, and including a lower current spreading layer and an upper current spreading layer on the lower current spreading layer;
  • An insulating layer covering the light emitting structure and the current spreading layer and including openings partially exposing the first and second electrodes; And a first pad and a second pad on the insulating layer and electrically connected to the first and second electrodes, respectively, wherein the upper current spreading layer and the lower current spreading layer
  • the light emitting device may further include a current blocking layer positioned below the current spreading layer, and the current blocking layer may be positioned below the second electrode in correspondence with the position of the second electrode. .
  • the upper current spreading layer may have a lower electrical conductivity than the lower current spreading layer.
  • the first electrode may include a first ohmic contact electrode disposed under the first pad and in ohmic contact with the first conductive semiconductor layer through the first hole; And an extension electrode extending from the main electrode and extending from the main electrode to a lower portion of the region between the first pad and the second pad, through the second hole. And a second ohmic contact electrode in ohmic contact with the first conductive semiconductor layer.
  • An extension electrode of the second ohmic contact electrode may further extend to a lower portion of the second pad.
  • An extension electrode of the second ohmic contact electrode may be covered by the insulating layer.
  • the second electrode may include a first connection electrode positioned below the second pad; And a second connection electrode including a main electrode positioned below the second pad, and an extension electrode extending from the main electrode and extending to a lower portion of a region between the first pad and the second pad. .
  • the extension electrode of the second connection electrode may further extend to the bottom of the first pad.
  • the lower insulating layer may have a thicker thickness than the upper insulating layer, and the upper insulating layer may include a distributed Bragg reflector.
  • the current spreading layer may include a conductive oxide doped with a metallic dopant.
  • the current spreading layer may include a transparent conductive oxide doped with at least one of Ga, Al, and In.
  • the upper current spreading layer and the lower current spreading layer may have different refractive indices.
  • the upper insulating layer may include two or more distributed Bragg reflectors having different reflecting wavelength bands.
  • the p-type ohmic contact layer is formed of ITO, it is possible to improve the efficiency of the light emitting device by improving ohmic contact characteristics and improving transmittance.
  • ITO can be deposited thin during the process, thereby stabilizing the manufacturing process of the light emitting device.
  • the ITO may be doped with a metal such as silver (Ag) to improve electrical conductivity, improve current dispersion, and improve driving voltage characteristics.
  • the ohmic contact layer may be formed to a minimum thickness, thereby improving current spreading and light transmission.
  • the reflective layer is formed of a distributed Bragg reflector (DBR) using two or more oxide layers having a large difference in refractive index
  • the reflective layer may be designed to reflect at all wavelengths of light, thereby improving reflectivity. Accordingly, it is possible to provide a light emitting device having improved reliability.
  • DBR distributed Bragg reflector
  • a light emitting device having electrodes including extending portions extending into a region between the first and second pads by providing a light emitting device having electrodes including extending portions extending into a region between the first and second pads, a light emitting device having improved current dispersion efficiency can be provided.
  • FIG. 1 is a cross-sectional view of a light emitting device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a light emitting device according to another embodiment of the present invention.
  • 3A to 3G are cross-sectional views illustrating a method of manufacturing a light emitting device according to the present invention.
  • FIGS. 4 and 5 are plan views illustrating a light emitting device according to an embodiment of the present invention.
  • 6 to 9 are cross-sectional views for describing a light emitting device according to an embodiment of the present invention.
  • 10 to 17 are plan views and cross-sectional views illustrating a method of manufacturing a light emitting device according to another embodiment of the present invention.
  • FIG. 18 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.
  • 19 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
  • FIG. 20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
  • 21 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.
  • FIG. 1 is a cross-sectional view of a light emitting device according to an embodiment of the present invention.
  • the ohmic contact layer 60 formed on the p-type semiconductor layer 50 is formed of indium tin oxide (ITO) doped with a metal such as silver (Ag) to improve ohmic contact characteristics. Improve the transmittance, stabilize the device fabrication process and enable thin deposition.
  • ITO doped with a metal such as silver (Ag) improves current dispersion and improves driving voltage characteristics, it is possible to provide stable reliability of the light emitting device 1 and extend the life of the device.
  • the undoped transparent conductor layer 65 on the ohmic contact layer 60 the ohmic contact layer 60 may be formed to a minimum thickness, thereby improving current spreading and light transmission.
  • the reflective layer 70 is formed of a distributed Bragg reflector (DBR) using a plurality of oxide layers having a large refractive index difference, and is designed to reflect at the full wavelength of light (400 to 700 nm). Accordingly, the reflectivity of the reflective layer 70 can be improved, and the light efficiency of the light emitting element 1 can be improved.
  • DBR distributed Bragg reflector
  • the light emitting device 1 includes an n-type semiconductor layer 30, an active layer 40, a p-type semiconductor layer 50, and an ohmic contact layer sequentially formed on a substrate 10. 60, a transparent conductor layer 65 and a reflective layer 70.
  • the light emitting device 1 may further include electrodes 80 and 90 and a sub-mount substrate that is flip chip bonded to the substrate 10.
  • the substrate 10 refers to a conventional wafer for fabricating the light emitting device 1, and is a transparent substrate such as sapphire (Al 2 O 3 ), zinc oxide (ZnO), or lithium-alumina (LiAl 2 O 3 ). Can be used.
  • the substrate 10 may use a sapphire substrate, and the substrate 10 may be finally removed.
  • the electrodes 80 and 90 may be formed on the n-type semiconductor layer 30 or the conductive substrate from which the substrate 10 is removed.
  • a buffer layer 20 including aluminum nitride (AlN) or gallium nitride (GaN) is further formed to reduce lattice mismatch with the sapphire substrate. You may.
  • the n-type semiconductor layer 30 may be formed of gallium nitride (GaN) implanted with n-type impurities as the electron generation layer.
  • the n-type semiconductor layer 30 may be formed of a material layer having various semiconductor properties.
  • an n-type semiconductor layer 30 including n-type Al x Ga 1 - x N (0 ⁇ x ⁇ 1 ) is formed.
  • the p-type semiconductor layer 50 may be a layer in which holes are formed, and may use gallium nitride (GaN) implanted with p-type impurities, but is not limited thereto and may be formed of a material layer having various semiconductor properties.
  • GaN gallium nitride
  • a p-type semiconductor layer 50 including p-type Al x Ga 1 - x N (0 ⁇ x ⁇ 1 ) is formed.
  • indium gallium nitrogen may be used as the n-type semiconductor layer 30 and the p-type semiconductor layer 50.
  • the n-type semiconductor layer 30 and the p-type semiconductor layer 50 may be formed in a different position, each layer may be formed in multiple layers, additional layers may be formed.
  • the active layer 40 has a predetermined band gap and is a region where quantum wells are made to recombine electrons and holes to generate light.
  • the active layer 40 may include indium gallium nitrogen (InGaN). Since the emission wavelength generated by the combination of electrons and holes is changed according to the type of material constituting the active layer 40, the semiconductor material included in the active layer 40 may be adjusted according to the target wavelength.
  • the active layer 40 may be configured in various ways such as a single layer, a multi quantum well (MQW), a multi quantum dot / wire, or a layer in which quantum dots / lines and wells are mixed. Can be.
  • MQW multi quantum well
  • wire a layer in which quantum dots / lines and wells are mixed.
  • the layer in which the n-type semiconductor layer 30, the active layer 40, and the p-type semiconductor layer 50 are stacked may be referred to as a light emitting layer.
  • the electrodes 80 and 90 include an n-type electrode 80 for supplying electrons to the n-type semiconductor layer 30 and a p-type electrode 90 for supplying holes to the p-type semiconductor layer 50.
  • a contact 95 for electrical connection may be formed between the p-type semiconductor layer 50 and the p-type electrode 90.
  • the electrodes 80 and 90 are described as being deposited lower than the package. In this case, a separate bump or solder may be used to combine with the package (sub mount substrate). Alternatively, however, the electrodes 80 and 90 may be formed of metal bumps having a height coupled with the package.
  • the p-type electrode 90 of the reflective layer 70 on the p-type semiconductor layer 50 in terms of helping to reflect light from the active layer 40 to the substrate 10 side or the n-type semiconductor layer 30 side. It is preferable that it is a conductive reflecting film which covers all or almost all. In this case, a metal having high reflectance such as aluminum (Al) or gold (Ag) may be used.
  • Ni nickel (Ni) / gold (Au), silver (Ag) / gold (Au), titanium (Ti) / gold (Au), nickel (Ni) / gold (Au), palladium (Pd) / gold (Au ), Or a layer structure in which chromium (Cr) / gold (Au) and the like are sequentially stacked.
  • the ohmic contact layer 60 is formed of indium tin oxide (ITO) doped with a metal to reduce contact resistance of the p-type semiconductor layer 50.
  • Metals doped in the ohmic contact layer 60 may include silver (Ag), indium (In), tin (Sn), zinc (Zn), cadmium (Cd), gallium (Ga), aluminum (Al), and magnesium (Mg). ), Titanium (Ti), molybdenum (Mo), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), iridium (Ir), ruthenium (Ru), and palladium (Pd) It may be at least one of).
  • the ohmic contact layer 60 may be formed to a thickness of about 10 to 1000 ⁇ .
  • the doping range of the metal in the ohmic contact layer 60 may be about 0.01% to about 40%, preferably about 0.01% to about 20%.
  • the reflective layer 70 is formed on the ohmic contact layer 60 formed of indium tin oxide (ITO) doped with metal
  • ITO indium tin oxide
  • the ITO is easily deposited to a thin thickness, thereby improving ohmic characteristics and increasing transmittance.
  • ITO has a lower current spreading-resistance during a high output operation than metals, ITO can increase the light output to increase the efficiency of the light emitting device 1.
  • the metal may be doped with ITO to improve electrical conductivity, improve current dispersion, and improve driving characteristics.
  • the transparent conductor layer 65 is formed of an undoped ITO layer on the ohmic contact layer 60.
  • the transparent conductor layer 65 may have a thickness different from that of the ohmic contact layer 60 and may be relatively thicker than the thickness of the ohmic contact layer 60.
  • an undoped transparent conductor layer 65 is formed on the ohmic contact layer 60 formed of the metal doped ITO, and the current spreading is formed while forming the ohmic contact layer 60 to a minimum thickness. Improvement and light transmission can be improved.
  • the reflective layer 70 reflects the light from the ohmic contact layer 60 and the transparent conductor layer 65 toward the substrate 10 or the n-type semiconductor layer 30 from which the substrate 10 has been removed. Formed on layer 65.
  • the reflective layer 70 may be formed on a portion of the n-type semiconductor layer 30 and the electrode 80 that are etched and exposed. However, the reflective layer 70 does not necessarily cover all regions on the semiconductor layers 30 and 50 opposite to the substrate 10.
  • an oxide layer is used as a material of the reflective layer 70 instead of a conventional metal layer. Accordingly, the adhesive force between the ohmic contact layer 60 and the transparent conductor layer 65 is strengthened as compared with the related art, thereby ensuring stable driving reliability when the light emitting device 1 operates. In addition, since a separate metal layer is not required, improvement in luminous efficiency can be expected by preventing absorption of light.
  • the reflective layer 70 may be formed of a plurality of oxide layers having different refractive indices.
  • the reflective layer 70 may be formed of a first oxide layer and a second oxide layer having a refractive index different from that of the first oxide layer.
  • the oxide layer may be a nonconductive or conductive material.
  • the reflective layer 70 is formed of a conductive material, silver (Ag), indium (In), tin (Sn), zinc (Zn), cadmium (Cd), gallium (Ga), aluminum (Al), magnesium ( Mg), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), iridium (Ir), ruthenium ( Metals such as Ru) and palladium (Pd).
  • the reflective layer 70 functions as a reflective film, but is preferably made of a light-transmissive material to prevent absorption of light.
  • a light-transmissive material for example, silicon oxide (SiO x ), titanium oxide (TiO x ), and tantalum oxide (Ta 2 O 5). It may be composed of an oxide such as).
  • the reflective layer 70 is made of silicon oxide (SiO x )
  • the reflective layer 70 has a lower refractive index than that of the p-type semiconductor layer 50 (eg, GaN)
  • the light having a critical angle or more is partially directed toward the light emitting layer 30, 40, 50. It can be reflected.
  • the reflective layer 70 is made of a distributed Bragg reflector (DBR), it is possible to increase the light efficiency by reflecting a greater amount of light toward the light emitting layer (30, 40, 50).
  • DBR distributed Bragg reflector
  • the reflective layer 70 may be formed of a plurality of oxide layers having different refractive indices to reflect the light at all wavelengths (400 to 700 nm) of light.
  • the distribution Bragg reflector DBR may include a first oxide layer including silicon oxide (SiO 2 ) and a second oxide layer including titanium oxide (TiO 2 ).
  • the p-type ohmic contact layer is formed of ITO, the ohmic contact property is improved, the transmittance is improved, and the device fabrication process is stabilized to enable thin deposition.
  • the ITO may be doped with a metal such as silver (Ag) to improve electrical conductivity, and the ITO may improve current distribution and drive voltage characteristics.
  • the reflective layer may be configured to reflect light at all wavelengths (400 to 700 nm) by using a distributed Bragg reflector (DBR) using two or more oxides having a large refractive index difference, thereby improving reflectivity while replacing the conventional metal reflective layer. .
  • DBR distributed Bragg reflector
  • FIG. 2 is a cross-sectional view of a light emitting device according to another embodiment of the present invention.
  • the light emitting element 3 has a configuration substantially the same as the light emitting element 1 of FIG. 1 except for the reflective layer. Therefore, the same components as those of the light emitting element 1 of FIG. 1 are given the same reference numerals, and repeated descriptions are omitted.
  • the reflective layers 70a and 70b of the light emitting element 3 may have a dual structure of a distribution Bragg reflector 70a and a dielectric film 70b having a lower refractive index than the p-type semiconductor layer 50. have.
  • the dielectric film 70b having a predetermined thickness Prior to the deposition of the distributed Bragg reflector 70a, which requires precision, the dielectric film 70b having a predetermined thickness is formed so that the heterogeneous and heterogeneous deposits 50 on the light emitting layers 30, 40, and 50 are formed. Despite the 60, 80, and 90, it is possible to stably manufacture the distributed Bragg reflector 70a, and may also help to reflect light.
  • the material of the dielectric film 70b may use silicon oxide (SiO 2 ), and may have a thickness of about 0.2 ⁇ m to 1.0 ⁇ m.
  • each layer when composed of a combination of titanium oxide (TiO 2 ) / silicon oxide (SiO 2 ), each layer is designed to have an optical thickness of 1/4 of a given wavelength and the number of combinations May be formed in 4 to 20 pairs. Too thin a thickness can cause an increase in operating voltage.
  • the p-type ohmic contact layer is formed of ITO, the ohmic contact property is improved, the transmittance is improved, and the device fabrication process is stabilized to enable thin deposition.
  • a dielectric film under the distribution Bragg reflector a more stable manufacturing process may be performed, and the reliability of the product may be improved even after manufacturing the light emitting device.
  • the present invention can be applied to not only flip chip type light emitting devices as shown in FIGS. 1 and 2 but also other modified flip chip types.
  • the present invention is not limited to the flip chip type, and may be applied to any type of light emitting device such as a top-emitting light emitting diode (TELED) type and a vertical LED (VLED).
  • TELED top-emitting light emitting diode
  • VLED vertical LED
  • 3A to 3G are cross-sectional views illustrating a method of manufacturing a light emitting device according to the present invention.
  • This embodiment provides a light emitting device that can be used for lighting and can be driven by an AC power source by reducing the size of the device by driving a plurality of light emitting cells in series, parallel or series-parallel at the wafer level, and driving at an appropriate voltage and current. do.
  • a light emitting layer that is, an n-type semiconductor layer 30, an active layer 40, and a p-type semiconductor layer 50 are sequentially formed on the substrate 10.
  • the substrate 10 refers to a conventional wafer for fabricating a light emitting device, and may use a transparent substrate such as sapphire (Al 2 O 3 ), zinc oxide (ZnO), or lithium-alumina (LiAl 2 O 3 ). have.
  • the substrate 10 may use a sapphire substrate, and the substrate 10 may be finally removed.
  • a buffer layer (not shown) including AlN or GaN may be further formed to reduce the lattice mismatch with the sapphire substrate before the n-type semiconductor layer 30 is formed on the substrate 10. have.
  • the n-type semiconductor layer 30 may be formed of gallium nitride (GaN) implanted with n-type impurities as the electron generation layer.
  • the n-type semiconductor layer 30 may be formed of a material layer having various semiconductor properties.
  • an n-type semiconductor layer 30 including n-type Al x Ga 1 - x N (0 ⁇ x ⁇ 1 ) is formed.
  • the p-type semiconductor layer 50 may be a layer in which holes are formed, and may use gallium nitride (GaN) implanted with p-type impurities, but is not limited thereto and may be formed of a material layer having various semiconductor properties.
  • GaN gallium nitride
  • a p-type semiconductor layer 50 including p-type Al x Ga 1 - x N (0 ⁇ x ⁇ 1 ) is formed.
  • indium gallium nitrogen may be used as the n-type semiconductor layer 30 and the p-type semiconductor layer 50.
  • the n-type semiconductor layer 30 and the p-type semiconductor layer 50 may be formed by changing positions, each layer may be formed in a multi-layer, additional layers may be formed.
  • the active layer 40 has a predetermined band gap and is a region where quantum wells are made to recombine electrons and holes to generate light.
  • the active layer 40 may include indium gallium nitrogen (InGaN). According to the type of material constituting the active layer 40, the emission wavelength generated by the combination of electrons and holes is changed. Therefore, the semiconductor material included in the active layer 40 can be adjusted according to the target wavelength.
  • the above-described material layers may include metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma chemical vapor deposition (PCVD), molecular beam growth (MBE), and molecular beam growth (MBE). It can be formed through a variety of deposition and growth methods, including Beam Epitaxy), Hydride Vapor Phase Epitaxy (HVPE).
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • PCVD plasma chemical vapor deposition
  • MBE molecular beam growth
  • MBE molecular beam growth
  • MBE molecular beam growth
  • portions of the p-type semiconductor layer 50, the active layer 40, and the n-type semiconductor layer 30 are removed to separate the light emitting cells.
  • a predetermined mask pattern is formed on the p-type semiconductor layer 50, and then the p-type semiconductor layer 50, the active layer 40, and the n-type semiconductor layer 30 in the region exposed by the mask pattern are removed. Etching may electrically separate the plurality of light emitting cells.
  • a portion of the n-type semiconductor layer 30 is exposed by removing a portion of the p-type semiconductor layer 50 and the active layer 40 through a predetermined etching process.
  • a predetermined etching mask pattern is formed on the p-type semiconductor layer 50, and then, a dry / wet etching process is performed to remove the n-type semiconductor layer by removing the p-type semiconductor layer 50 and the active layer 40. Expose (30).
  • n-type semiconductor layer 30 is exposed by removing a portion of the p-type semiconductor layer 50 and the active layer 40 through a predetermined etching process, and a plurality of light emitting cells are disposed on the substrate 10.
  • the predetermined region of the n-type semiconductor layer 30 exposed to form may be removed to expose the substrate 10.
  • the ohmic contact layer 60 and the dopant are not doped with indium tin oxide (ITO) doped with metal to reduce contact resistance of the p-type semiconductor layer 50 on the p-type semiconductor layer 50.
  • the transparent conductor layer 65 is formed of ITO.
  • ITO Indium tin oxide
  • ITO is first deposited on the p-type semiconductor layer 50 to form the ohmic contact layer 60.
  • ITO may be processed into a spattering target to obtain a transparent conductive film, a transparent conductive film may be obtained by dissolving and spraying ITO, or depositing a substrate in a solution.
  • a transparent conductive film coated with ITO may be attached to a film such as polyethylene, and various processes may be applied as necessary.
  • ITO may be formed to a thickness of about 10-1000 kPa.
  • the metal is doped.
  • the metal is silver (Ag), indium (In), tin (Sn), zinc (Zn), cadmium (Cd), gallium (Ga), aluminum (Al), magnesium (Mg), titanium (Ti), molybdenum ( Mo, nickel (Ni), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), iridium (Ir), ruthenium (Ru) and palladium (Pd).
  • the doping range of the metal may be about 0.01% to about 40%, preferably about 0.01% to about 20%.
  • the transparent conductor layer 65 is formed by forming ITO, which is the same material as the ohmic contact layer 60, on the formed ohmic contact layer 60. However, the transparent conductor layer 65 is formed of undoped ITO. The transparent conductor layer 65 may be deposited to have a thickness different from that of the ohmic contact layer 60, and may be deposited relatively thicker than the thickness of the ohmic contact layer 60.
  • an undoped transparent conductor layer 65 is formed on the ohmic contact layer 60 formed of the metal doped ITO, and the current spreading is formed while forming the ohmic contact layer 60 to a minimum thickness. Improvement and light transmission can be improved.
  • a reflective layer 70 for reflecting light is formed on the transparent conductor layer 65.
  • an oxide layer is used instead of a conventional metal layer.
  • the oxide layer may be a nonconductive or conductive material.
  • the reflective layer 70 is formed of a conductive material, silver (Ag), indium (In), tin (Sn), zinc (Zn), cadmium (Cd), gallium (Ga), aluminum (Al), magnesium ( Mg), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), iridium (Ir), ruthenium ( Metals such as Ru) and palladium (Pd).
  • the reflective layer 70 is formed on the ohmic contact layer 60 formed of indium tin oxide (ITO) doped with a metal such as silver (Ag) and the transparent conductor layer 65 formed of ITO.
  • ITO indium tin oxide
  • the ohmic contact layer 60 can be easily deposited to a thin thickness, thereby improving ohmic characteristics and increasing transmittance.
  • the ohmic contact layer 60 may be doped with a metal such as silver (Ag) to improve electrical conductivity, improve current dispersion, and improve driving characteristics.
  • the adhesion between the ohmic contact layer 60, the transparent conductor layer 65, and the reflective layer 70 is enhanced, compared to the related art, thereby ensuring stable driving reliability during operation of the light emitting device.
  • improvement in luminous efficiency can be expected by preventing absorption of light.
  • the reflective layer 70 may be formed of a plurality of oxide layers having different refractive indices.
  • the reflective layer 70 may be formed of a first oxide layer and a second oxide layer having a refractive index different from that of the first oxide layer.
  • the reflective layer 70 functions as a reflective film, but is preferably made of a light-transmissive material to prevent absorption of light.
  • a light-transmissive material for example, silicon oxide (SiO x ), titanium oxide (TiO x ), and tantalum oxide (Ta 2 O 5). It may be composed of an oxide such as).
  • the reflective layer 70 is made of silicon oxide (SiO x )
  • the reflective layer 70 has a lower refractive index than that of the p-type semiconductor layer 50 (eg, GaN)
  • the light having a critical angle or more is partially directed toward the light emitting layers 30, 40, and 50. It can be reflected.
  • the reflective layer 70 is made of a distributed Bragg reflector (DBR), it is possible to increase the light efficiency by reflecting a greater amount of light toward the light emitting layer (30, 40, 50).
  • DBR distributed Bragg reflector
  • the reflective layer 70 may be formed of a plurality of oxide layers having different refractive indices to reflect at the full wavelength of light (400 to 700 nm).
  • the distribution Bragg reflector DBR may include a first oxide layer including silicon oxide (SiO 2 ) and a second oxide layer including titanium oxide (TiO 2 ).
  • the deposition temperature applied to form the reflective layer 70 is in the range of 20 degrees to 1500 degrees
  • the pressure in the evaporator may be performed at atmospheric pressure to 10 to 12 torr (torr).
  • annealing may be performed after the reflective layer 70 is formed.
  • the heat treatment may be performed for 10 seconds to 3 hours in a vacuum or gas atmosphere at a temperature of 100 to 800 degrees in the reactor.
  • At least one gas of nitrogen, argon, helium, oxygen, hydrogen, or air may be applied to the gas introduced into the reactor during the heat treatment.
  • the reflective layer 70 reflects light from the active layer 40 to the substrate 10 side used for growth or to the n-type semiconductor layer 30 side when the substrate 10 is removed. ) Is formed on.
  • the reflective layer 70 may be formed on a portion of the n-type semiconductor layer 30 and the electrode 80 which are etched and exposed.
  • the reflective layer 70 does not necessarily cover all regions on the semiconductor layers 30 and 50 opposite to the substrate 10.
  • the reflective layer may have a double structure of a dielectric film 70b having a refractive index lower than that of the distribution Bragg reflector 70a and the p-type semiconductor layer 50. have.
  • the dielectric film 70b may be deposited with silicon oxide (SiO 2 ) at about 0.2 ⁇ m to 1.0 ⁇ m.
  • the distribution Bragg reflector 70a can be formed by a combination of titanium oxide (TiO 2 ) / silicon oxide (SiO 2 ), each layer being designed to have an optical thickness of 1/4 of a given wavelength, and the combination The number of can be formed in 4 to 20 pairs.
  • the n-type semiconductor layer 30 and the p-type semiconductor layer 50 between adjacent light emitting cells are connected through a predetermined wiring forming process. That is, the exposed n-type semiconductor layer 30 of one light emitting cell and the p-type semiconductor layer 50 of another light emitting cell adjacent thereto are connected to the wiring 85.
  • the bridge process described above is also referred to as an air bridge process, by using a photo process between the chips to be connected to each other by using a photo process to form a photoresist pattern, and then forming a material such as metal on the first thin film by a method such as vacuum deposition, Again, a conductive material containing gold is applied to a predetermined thickness by a method such as electroplating, electroplating or metal deposition. Subsequently, when the photoresist pattern is removed with a solution such as a solvent, the lower portion of the conductive material is removed and only the bridge-shaped conductive material is formed in the space.
  • the step cover process uses a photo process between the chips to be connected to each other using a photo process, and develops, leaving only the portions to be connected to each other, and covering the other portions with a photoresist pattern, and on top of it by electroplating, electroless plating or metal deposition. Applying a conductive material containing a predetermined thickness. Subsequently, when the photoresist pattern is removed with a solution such as a solvent, all portions other than the conductive material are covered and only the covered portions remain to electrically connect the chips to be connected.
  • the wiring 85 all materials having conductivity as well as metal may be used. For example, gold (Au), silver (Ag), nickel (Ni), chromium (Cr), platinum (Pt), palladium (Pd), titanium (Ti), tungsten (W), tantalum (Ta) or its It can be formed from an alloy.
  • the p-type metal bumps 90 and the n-type metal bumps 80 are formed on the p-type semiconductor layer 50 located at one edge of the light emitting cell and the n-type semiconductor layer 30 located at the other edge thereof, respectively.
  • the p-type and n-type metal bumps 80 and 90 may include palladium (Pd), tin (Sn), gold (Au), germanium (Ge), copper (Cu), bismuth (Bi), cadmium (Cd), and zinc. At least one of (Zn), silver (Ag), nickel (Ni) and titanium (Ti) can be used, and these alloys can be used.
  • the metal bumps 80 and 90 may be deposited to form a low electrode, and may further form a separate bump or solder.
  • the light emitting cell block 100 is electrically connected to the plurality of light emitting cells by the conductive wiring 85.
  • the manufacturing process of the light emitting cell block 100 is not limited to the above-described method, and various modifications and various material films may be further added.
  • the n-type semiconductor layer 30, the active layer 40, and the p-type semiconductor layer 50 are formed on the substrate 10, and the ohmic contact layer 60 and the transparent conductor are formed on the upper surface thereof.
  • an etching process for separating between the light emitting cells and exposing the n-type semiconductor layer 30 may be performed.
  • an additional ohmic metal layer including chromium (Cr), gold (Au), or the like may be further formed on the exposed n-type semiconductor layer 30 to smoothly supply current.
  • the sub-mount substrate 200 includes a substrate 210, a plurality of bonding layers 230 formed on the substrate, a p-type bonding pad 220 located at one edge, and an n-type bonding pad located at the other edge ( 225).
  • silicon carbide (SiC), silicon (Si), germanium (Ge), silicon germanium (SiGe), aluminum nitride (AlN), metal, and the like having excellent thermal conductivity may be used as the substrate 210.
  • aluminum nitride (AlN) having excellent thermal conductivity and insulating properties is used.
  • the present invention is not limited thereto, and a metallic material having high thermal conductivity and excellent electrical conductivity may be used.
  • the bonding layer 230, the n-type bonding pad 225, and the p-type bonding pad 220 use a metal having excellent electrical conductivity. This may be formed by a screen printing method or through a deposition process using a predetermined mask pattern.
  • the light emitting cell block 100 and the sub-mount substrate 200 are flip-chip bonded to manufacture a light emitting device.
  • the light emitting device of the present invention flip-bonds the light emitting cell block 100 and the sub-mount substrate 200, and is bonded by metal bumps 80 and 90 formed on the light emitting cell.
  • the p-type metal bump 90 located at one edge of the light emitting cell block 100 is connected to the p-type bonding pad 220 of the sub-mount substrate 200
  • the n-type metal bump 80 located at the other edge of the light emitting cell block 100 is connected to the sub type. It is connected to the n-type bonding pad 225 of the mount substrate 200.
  • the bonding may be performed using heat or ultrasonic waves, or simultaneously using heat and ultrasonic waves. Bonding of the light emitting cell block 100 and the sub-mount substrate 200 is not limited to the above-described method, and may be flip chip bonded by various bonding methods.
  • the position of the metal bumps 80 and 90 is not limited thereto, and may be formed at another suitable position that does not affect flip chip bonding if it does not disturb the electrical flow of the bridge wiring 85.
  • the metal bumps 80 and 90 may not be formed in the light emitting cells in the light emitting cell block 100, but the metal bumps 80 and 90 may be formed in the sub-mount substrate 200.
  • the manufacturing process of the light emitting device of the present invention described above is not limited thereto, and various processes and manufacturing methods may be changed or added according to the characteristics of the device and the convenience of the process.
  • the n-type semiconductor layer 30 and the p-type semiconductor layer 50 of adjacent light-emitting cells are formed through a bridge process or a step cover process in manufacturing the light-emitting cell block 100.
  • the sub-mount substrate 200 was flip-chip bonded to manufacture a light emitting device.
  • the present invention is not limited thereto, and the n-type semiconductor layer 30 and the p-type semiconductor layer 50 of adjacent light emitting cells may be electrically connected to each other using metal bumps during flip chip bonding of the light emitting cell block 100 and the sub-mount substrate 200. It can also be connected.
  • a light emitting device in which a plurality of light emitting cells in a flip chip form is arranged on a sub-mount substrate may be manufactured.
  • the light emitting cells may be variously connected in series, in parallel, or in parallel and according to a desired purpose.
  • the light emitting device of the present invention reduces the resistance of the p-type semiconductor layer through the ohmic contact layer on the p-type semiconductor layer, and has a stable power-voltage driving characteristic due to the enhanced adhesion between the ohmic contact layer and the reflective layer and the reliability of the light emitting device. It can improve the and can extend the life of the light emitting device.
  • a reflective layer including an oxide instead of a separate metal layer, which has been conventionally formed, it is possible to prevent the absorption of light and smoothly reflect the light, thereby obtaining improved light efficiency.
  • FIGS. 4 and 5 are plan views illustrating light emitting devices according to embodiments of the present invention
  • FIGS. 6 to 9 are cross-sectional views illustrating light emitting devices according to embodiments of the present invention.
  • FIG. 4 and 5 respectively show a plane of the light emitting element.
  • FIG. 5 illustrates a plan view of the light emitting device, and for convenience of description, the first pad 181, the second pad 183, and the insulating layer 170 are omitted.
  • FIG. 6 shows a cross section of a portion corresponding to the line AA ′ of FIG. 5
  • FIG. 7 shows a cross section of a portion corresponding to the line B-B ′ of FIG. 5
  • FIG. 8 is a C- line of FIG. 5.
  • the cross section of the part corresponding to the C 'line is shown
  • FIG. 9 shows the cross section of the part corresponding to the D-D' line of FIG.
  • the light emitting device includes a light emitting structure 120, a current spreading layer 130, a first electrode 140, a second electrode 160, and an insulating layer 170.
  • the light emitting device may further include a substrate 110, a current blocking layer 150, a first pad 181, and a second pad 183.
  • the light emitting device may have a rectangular planar shape.
  • the light emitting device may have a generally square planar shape, and the third side surface 103 positioned opposite to the first side surface 101, the second side surface 102, and the first side surface 101. , And a fourth side 104 positioned opposite the second side 102.
  • the present invention is not limited thereto.
  • the substrate 110 is not limited as long as it can grow the light emitting structure 120, and may be, for example, a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, or the like.
  • the substrate 110 may be a patterned sapphire substrate (PSS).
  • PSS patterned sapphire substrate
  • the substrate 110 may be omitted.
  • the substrate 110 may be separated and removed from the light emitting structure 120 using a known technique.
  • the substrate 110 may be a support substrate supporting the light emitting structure 120 grown on a separate growth substrate.
  • the light emitting structure 120 includes a first conductive semiconductor layer 121, an active layer 123 positioned on the first conductive semiconductor layer 121, and a second conductive semiconductor layer disposed on the active layer 123 ( 125).
  • the first conductive semiconductor layer 121, the active layer 123, and the second conductive semiconductor layer 125 may include a III-V series compound semiconductor, and include, for example, (Al, Ga, In) N and The same nitride-based semiconductor may be included.
  • the first conductivity-type semiconductor layer 121 may include n-type impurities (eg, Si), and the second conductivity-type semiconductor layer 125 may include p-type impurities (eg, Mg). have. It may also be the reverse.
  • the active layer 123 may include a multi-quantum well structure (MQW).
  • the light emitting structure 120 may include a region in which the first conductive semiconductor layer 121 is partially exposed through the second conductive semiconductor layer 125 and the active layer 123.
  • the light emitting structure 120 may include at least one hole 127a through the second conductive semiconductor layer 125 and the active layer 123 to expose a portion of the first conductive semiconductor layer 121. 127b).
  • At least one hole 127a and 127b may include a first hole 127a and a second hole 127b.
  • the first hole 127a may have a generally circular or polygonal planar shape.
  • the second hole 127b may have a shape extending longer in an arbitrary direction than the first hole 127a.
  • the second hole 127b may include a portion having a relatively large width and a portion having a relatively small width.
  • the first hole 127a has a circular planar shape and may be formed in plural.
  • the second hole 127b may be formed to extend from the first side surface 101 toward the third side surface 103 and may be formed in plurality.
  • the shape of the second hole 127b may be a shape extending from the portion having a relatively large width toward the third side surface 103, and the portion extending toward the third side surface 103 may be relatively small. It may have a width.
  • a portion having a relatively large width of the second hole 127b may be formed to have substantially the same width and shape as the first hole 127a.
  • the plurality of second holes 127b may be disposed to be substantially spaced apart at regular intervals. In one second hole 127b, a part of the second hole 127b may be located under the first pad 181, and another part of the second hole 127b may be the second pad 183. It may be located at the bottom of the). That is, at least one of the second holes 127b may be formed to extend from the bottom of the first pad 181 to the bottom of the second pad 183.
  • the current blocking layer 150 is partially positioned on the light emitting structure 120, particularly on the second conductivity type semiconductor layer 125.
  • the current blocking layer 150 may be located corresponding to the portion where the second electrode 160 is located.
  • the current blocking layer 150 may include a first current blocking layer 151 and a second current blocking layer 153, and the first and second current blocking layers 151 and 153 may respectively include the second electrode 160.
  • the second current blocking layer 153 includes a main current blocking layer 153a and a negative current blocking corresponding to positions of the main electrode 163a and the extension electrode 163b of the second connection electrode 163, respectively. Layer 153b.
  • the current blocking layer 150 directly conducts the current supplied to the second electrode 160 to the second conductivity type semiconductor layer 125 to prevent the current from being concentrated on the lower portion of the second electrode 160.
  • the current blocking layer 150 may be electrically insulating, may include an insulating material, and may be formed of a single layer or multiple layers.
  • the current blocking layer 130 is SiO x or SiN x Or the like, or may include a distributed Bragg reflector in which layers of insulating materials having different refractive indices are stacked.
  • the current blocking layer 150 may have light transmittance, may have light reflectivity, or may have selective light reflectivity.
  • the current blocking layer 150 may have a larger area than the second electrode 160 formed thereon. Accordingly, the second electrode 160 may be located in the region where the current blocking layer 150 is formed.
  • the current spreading layer 130 may be located on the second conductive semiconductor layer 125. In addition, the current spreading layer 130 may cover the current blocking layer 150 and include at least one opening exposing at least one hole 127a and 127b. The current spreading layer 130 may be electrically connected to the second conductive semiconductor layer 125 and form an ohmic contact with the second conductive semiconductor layer 125. The current spreading layer 130 may cover the entire upper surface of the light emitting structure 120 as a whole, and may be formed along the outer edge of the upper surface of the light emitting structure 120 as shown. In addition, the current spreading layer 130 may be formed along the edge of the at least one hole 127a and 127b to expose the at least one hole 127a and 127b.
  • the current injected through the current spreading layer 130 may be evenly distributed in the horizontal direction on the upper portion of the light emitting structure 120, so that the current spreading of the light emitting device may be improved.
  • the current spreading layer 130 may be formed of a conductive material such as a metal or a conductive oxide.
  • the current spreading layer 130 may include a conductive oxide such as ITO, ZnO, IZO, GZO, AZO, a light-transmitting metal layer such as Ni / Au, and Ni, Pt, Pd, Rh, W, Ti, Al, Mg And metals such as Ag, Cr, Au, and the like.
  • the current spreading layer 130 may have a multi-layer structure, and includes a lower current spreading layer 131 and a lower current spreading layer (131) disposed on the second conductivity type semiconductor layer 125.
  • the upper current spreading layer 133 may be disposed on the 131.
  • the lower current spreading layer 131 and the upper current spreading layer 133 may have different electrical conductivity.
  • the lower current spreading layer 131 and the upper current spreading layer 133 may have different refractive indices.
  • the lower current spreading layer 131 may be in ohmic contact with the second conductive semiconductor layer 125.
  • the lower current spreading layer 131 may be formed of a conductive oxide doped with a predetermined dopant, and thus, the contact resistance at the interface between the lower current spreading layer 131 and the second conductivity-type semiconductor layer 125. Can be reduced.
  • the lower current spreading layer 131 may include ITO, ZnO, or the like doped with dopants, and the dopants may include silver (Ag), indium (In), tin (Sn), zinc (Zn), and cadmium.
  • current spreading layer 130 may comprise a transparent conductive oxide doped with at least one of Ga, Al, and In.
  • the lower current spreading layer 131 may be formed of a transparent conductive oxide doped with at least one of Ga, Al, and In.
  • the lower current spreading layer 131 may have a thickness of about 10 to 1000 kHz.
  • the doping concentration of the dopant for the lower current spreading layer 131 may be about 0.01 at% to about 40 at%, preferably about 0.01 at% to about 20 at%.
  • the upper current spreading layer 133 may be located on the lower current spreading layer 131.
  • the upper current spreading layer 133 may have higher transmittance and lower sheet resistance than the lower current spreading layer 233.
  • the lower current spreading layer 131 is formed of ITO or ZnO doped with a dopant
  • the upper current spreading layer 133 has a thicker thickness than the lower current spreading layer 131 and is undoped ITO or ZnO. It can be formed as.
  • Undoped conductive oxides have a higher light transmittance than doped conductive oxides and have a relatively low horizontal resistance, ie sheet resistance, by having a relatively thick thickness.
  • the total thickness of the current spreading layer 130 is not limited, but may be, for example, about 10000 kPa or less, and further, about 5000 kPa to 9000 kPa, and may be formed to a thickness of about 6000 kPa or about 8000 kPa.
  • each of the lower and upper current spreading layers 131 and 133 is shown in FIG. 1. It may be similar to each of the ohmic contact layer 60 and the transparent conductor layer 65 in the embodiment described with reference.
  • the lower current dispersion layer 131 having a relatively thin thickness and formed of ITO, ZnO, or the like doped with a metallic dopant forms electrical contact with the second conductivity-type semiconductor layer 125, thereby distributing the lower current.
  • the light transmittance in the layer 131 may be high and the ohmic characteristics may be improved.
  • the upper current spreading layer 133 by forming the upper current spreading layer 133 with a relatively thick thickness and undoped ITO, ZnO, etc., it is possible to improve the current dispersion efficiency in the horizontal direction.
  • the light emitting device includes a current spreading layer 130 having a multilayer structure of lower and upper current spreading layers 131 and 133, thereby improving ohmic characteristics and current spreading efficiency,
  • the forward voltage Vf may be reduced, and light emission efficiency of the light emitting device may be improved by improving light transmittance.
  • current spreading layer 130 may be formed of a single layer.
  • the single-layer current spreading layer 130 may include a transparent conductive oxide having improved ohmic characteristics and light transmittance.
  • the current spreading layer 130 may include a single layer formed of ZnO having a higher light transmittance than that of ITO.
  • the insulating layer 170 may cover openings of the light emitting structure 120 and the current spreading layer 130, and include openings exposing the positions of the first and second electrodes 140 and 160.
  • the insulating layer 170 may include a lower insulating layer 171 and an upper insulating layer 173.
  • the lower insulating layer 171 and the upper insulating layer 173 will be described separately, but the present invention is not limited thereto.
  • the lower insulating layer 171 may include side surfaces and top surfaces of the light emitting structure 120 and openings covering the current spreading layer 130 and exposing a portion of the current spreading layer 130.
  • the lower insulating layer 171 may cover side surfaces of the at least one hole 127a and 127b and partially cover the first conductive semiconductor layer 121 exposed to the lower portion of the at least one hole 127a and 127b. It may include openings to expose to. Portions exposed by the openings of the lower insulating layer 171 may correspond to the positions of the first and second electrodes 140 and 160.
  • a portion of the first conductivity type semiconductor layer 121 exposed through the first hole 127a and the second hole 127b may be exposed by the openings.
  • side surfaces of the first and second holes 127a and 127b may be at least partially covered by the lower insulating layer 171.
  • portions of the current spreading layer 130 exposed by the openings of the lower insulating layer 171 may be portions positioned above the current blocking layer 150.
  • the lower insulating layer 171 may include an insulating material, and may include, for example, SiO 2 , SiN x , MgF 2, or the like. In some embodiments, the lower insulating layer 171 may serve as a basal layer for other layers formed on the lower insulating layer 171. For example, when the upper insulating layer 173 includes a distributed Bragg reflector, the lower insulating layer 171 may serve as a base layer to stably form the distributed Bragg reflector. When the distribution Bragg reflector has a structure of alternately stacked TiO 2 layer / SiO 2 layer, the lower insulating layer 171 may be formed of a SiO 2 layer having a thickness of a predetermined thickness or more. For example, the predetermined thickness may be about 0.2 ⁇ m to 1.0 ⁇ m.
  • the distribution Bragg reflector can be stably manufactured on the lower insulating layer 171 by forming the lower insulating layer 171 with a thickness greater than or equal to a predetermined thickness.
  • the first electrode 140 is electrically connected to the first conductivity type semiconductor layer 121.
  • the first electrode 140 may be positioned on the exposed portion of the first conductivity type semiconductor layer 121 and may make ohmic contact with the first conductivity type semiconductor layer 121.
  • the first electrode 140 may be in ohmic contact with the first conductivity-type semiconductor layer 121 through at least one hole 127a and 127b.
  • the first electrode 140 is electrically connected to the first pad 181.
  • the first electrode 140 may include at least one first ohmic contact electrode 141 and a second ohmic contact electrode 143.
  • the first ohmic contact electrode 141 may be located in at least some of the first holes 127a and may be formed of a first conductivity type through an opening of the lower insulating layer 171 partially exposing the first holes 127a.
  • the semiconductor layer 121 may be in ohmic contact.
  • the first ohmic contact electrode 141 may be located in the plurality of first holes 127a.
  • the first ohmic contact electrode 141 may be positioned to overlap the region where the first pad 181 is formed in the vertical direction. That is, the first ohmic contact electrode 141 may be positioned under the first pad 181, and further, may be located within an area where the first pad 181 is formed. Therefore, the first ohmic contact electrode 141 may be in contact with the first pad 181.
  • the second ohmic contact electrode 143 may be located in the main contact hole 127a and the sub contact hole 127b.
  • the second ohmic contact electrode 143 may be located in at least some of the second holes 127b, and may have a first conductivity type through an opening of the lower insulating layer 171 partially exposing the first holes 127a.
  • the semiconductor layer 121 may be in ohmic contact.
  • the second ohmic contact electrode 143 may be located in the plurality of second holes 127b.
  • the second ohmic contact electrode 143 may be formed to extend in the direction in which the second hole 127b extends.
  • the second ohmic contact electrode 143 may have a shape extending from the first side surface 101 toward the third side surface 103.
  • the second ohmic contact electrode 143 extends from the main electrode 143a positioned below the first pad 181 and the main electrode 143a to extend the first pad 181 and the second pad 183. It may include an extension electrode (143b) located under the region between. Accordingly, the main electrode 143a may contact the first pad 181, but the extension electrode 143b may extend toward the second pad 183. In addition, the extension electrode 143b may further extend to the bottom of the second pad 183. Accordingly, electrons injected through the main electrode 143a in contact with the first pad 181 may be easily dispersed by the extension electrode 143b.
  • the width of the main electrode 143a may be larger than the width of the extension electrode 143b, so that a current may be smoothly injected into the second ohmic contact electrode 143 through the main electrode 143a.
  • the second electrode 160 is positioned on the current spreading layer 130 and can be electrically connected to the current spreading layer 130.
  • the second electrode 160 may be positioned above the current blocking layer 150, so that the current spreading layer 130 is partially disposed between the second electrode 160 and the current blocking layer 150. It may be interposed.
  • the second electrode 160 may be electrically connected to the second pad 183, and the current spreading layer 130 and the second pad 183 may be electrically connected through the second electrode 160.
  • the second electrode 160 may include at least one first connection electrode 161 and at least one second connection electrode 163.
  • the first connection electrode 161 may contact the current spreading layer 130 through the openings of the lower insulating layer 171.
  • the first connection electrode 161 may be positioned to overlap the region where the second pad 183 is formed in the vertical direction. That is, the first connection electrode 161 may be located under the second pad 183, and further, may be located in an area where the second pad 183 is formed. Therefore, the first connection electrode 161 may be in contact with the second pad 183.
  • the plurality of first connection electrodes 161 may be spaced apart from each other.
  • the present invention is not limited thereto, and the plurality of first connection electrodes 161 may be connected to each other.
  • the second connection electrode 163 may be positioned to overlap the region where the second pad 183 is formed in the vertical direction.
  • the second connection electrode 163 may include a main electrode 163a positioned below the second pad 183 and contacting the second pad 183 and an extension electrode 163b extending from the main electrode 163a. Can be.
  • the extension electrode 163b may extend from the second pad 183 in a direction closer to the first pad 181.
  • the extension electrode 163b may extend from the third side surface 103 toward the first side surface 101.
  • the extension electrode 163b may extend below the region between the first pad 181 and the second pad 183, and may further extend to the bottom of the first pad 181.
  • a portion of the extension electrode 163b extending to the bottom of the first pad 181 is electrically insulated from the first pad 181 by the upper insulating layer 173 described later.
  • the second connection electrode 163 includes the extension electrode 163b extending to the lower portion of the first pad 181, the lower and first portions of the region between the first and second pads 161 and 163 are formed.
  • Current can be smoothly distributed to a portion of the second conductivity-type semiconductor layer 125 located below the pad 181, and the second conductivity-type semiconductor layer 125 located below the main electrode 163a. Concentration of current can be prevented.
  • the extension electrode 163b may have a narrower width than the main electrode 163a. Accordingly, the current may be smoothly injected from the second pad 183 through the main electrode 163a to the second connection electrode 163, and the injected current may be smoothly distributed through the extension electrode 163b.
  • first electrode 140 may be disposed between the plurality of second electrodes 160, and at least a portion of the second electrode 160 is disposed between the plurality of first electrodes 140.
  • at least a part of the first electrodes 140 may be positioned between the extension electrodes 163b.
  • the first and second ohmic contact electrodes 141 and 143 may be positioned between the two second electrodes 160.
  • the current can be distributed more efficiently.
  • first electrode 140 and the second electrode 160 may be formed to further cover the upper surface of the lower insulating layer 171. That is, at least some of the first and second electrodes 140 and 160 may fill the openings of the lower insulating layer 171, and may further cover the upper surface of the lower insulating layer 171 around the opening.
  • the upper insulating layer 173 covers the lower insulating layer 171 and partially covers the first electrode 140 and the second electrode 160.
  • the upper insulating layer 173 has openings that at least partially expose each of the first electrode 140 and the second electrode 160.
  • the first ohmic contact electrode 141 and the second ohmic contact electrode 143 of the first electrode 140 are exposed to the openings of the upper insulating layer 173, and the first pad is formed through the openings. 181 may be in electrical contact.
  • at least a portion of the main electrode 143a of the second ohmic contact electrode 143 is exposed to the opening of the upper insulating layer 173, and the extension electrode 143b of the second ohmic contact electrode 143 is the upper insulating layer. (173).
  • the extension electrode 143b disposed below the second pad 183 is insulated from the second pad 183 through the upper insulating layer 173.
  • At least a portion of the first connection electrode 161 of the second electrode 160 may be exposed to the openings of the upper insulating layer 173 and may be in electrical contact with the second pad 183 through the openings.
  • a portion of the second connection electrode 163 of the second electrode 160 may be exposed to the openings of the upper insulating layer 173, and a portion of the second connection electrode 163 may be covered by the upper insulating layer 173.
  • at least a part of the main electrode 163a of the second connection electrode 163 is exposed to the opening of the upper insulating layer 173, and the extension electrode 163b is covered by the upper insulating layer 173. Accordingly, the extension electrode 163b disposed below the first pad 181 is insulated from the first pad 181 through the upper insulating layer 173.
  • portions of the first and second electrodes 240 and 250 positioned below the region between the first and second pads 161 and 163 are covered and insulated by the upper insulating layer 173, thereby providing the first and second pads.
  • electrical shorts due to solder or impurities may be prevented.
  • the upper insulating layer 173, the lower insulating layer 171 may include an insulating material, for example, may include SiO 2 , SiN x , MgF 2 .
  • the upper insulating layer 173 may include a distributed Bragg reflector.
  • the distributed Bragg reflector may be formed by repeatedly stacking dielectric layers having different refractive indices, for example, the dielectric layers may include TiO 2 , SiO 2 , HfO 2 , ZrO 2 , Nb 2 O 5 , and the like.
  • the upper insulating layer 173 may have a structure of alternately stacked TiO 2 layers / SiO 2 layers.
  • Each layer of the distributed Bragg reflector may have an optical thickness of 1/4 of a particular wavelength and may be formed in 4 to 20 pairs. However, the present invention is not limited thereto.
  • the upper insulating layer 173 is formed of multiple layers, the uppermost layer of the upper insulating layer 173 may be formed of SiN x .
  • the layer formed of SiN x is excellent in moisture resistance and can protect the light emitting element from moisture.
  • the lower insulating layer 171 may serve as a base layer or an interfacial layer capable of improving the film quality of the distributed Bragg reflector.
  • the lower insulating layer 171 may be formed of SiO 2 having a thickness of about 0.2 ⁇ m to 1.0 ⁇ m
  • the upper insulating layer 173 may be formed of a distributed Bragg reflector in which a TiO 2 layer / SiO 2 layer is repeatedly stacked at a predetermined period. have.
  • a layer in contact with the lower insulating layer 171 among the layers of the upper insulating layer 173 may be a TiO 2 layer.
  • the distributed Bragg reflector may have a reflectance for relatively high visible light.
  • the distributed Bragg reflector may be designed to have a reflectance of 90% or more for light having an incident angle of 0 to 60 ° and a wavelength of 400 to 700 nm.
  • the distributed Bragg reflector having the reflectivity described above may be provided by controlling the type, thickness, lamination period, etc. of the plurality of dielectric layers forming the distributed Bragg reflector. Accordingly, it is possible to form a distributed Bragg reflector having a high reflectance for relatively long wavelength light (eg, 550 nm to 700 nm) and relatively short wavelength light (eg 400 nm to 550 nm).
  • the distributed Bragg reflector may comprise a multi-layered structure such that the Distributed Bragg reflector has a high reflectance for light in a wide wavelength range. That is, the distributed Bragg reflector may include a first stacked structure in which dielectric layers having a first thickness are stacked and a second stacked structure in which dielectric layers having a second thickness are stacked.
  • the distributed Bragg reflector includes a first stacked structure in which dielectric layers having a thickness less than 1/4 optical thickness for light having a center wavelength of visible light (about 550 nm), and a center wavelength of visible light (about 550 nm) And a second stacked structure in which dielectric layers having a thickness thicker than an optical thickness of 1/4 for the light of the stacked structure are stacked.
  • the distributed Bragg reflector may include a dielectric layer having a thickness thicker than 1/4 optical thickness for light having a central wavelength of visible light (about 550 nm) and a dielectric layer having a thickness thinner than 1/4 optical thickness for the light. It may further comprise a third stacked structure laminated repeatedly.
  • the luminous efficiency of the light emitting device can be improved.
  • the current spreading layer 130 may be formed in multiple layers and may have a relatively high light transmittance, the ratio of the light absorbed by the distributed Bragg reflector to be absorbed and lost by the current spreading layer 130 may be reduced. It can be reduced, the luminous efficiency of the light emitting device can be improved.
  • the upper insulating layer 173 may partially cover the top surfaces of the first electrode 140 and the second electrode 160. As illustrated in FIGS. 6 to 9, at least some of the first electrode 140 and the second electrode 160 may further cover the top surface of the lower insulating layer 171, and the upper insulating layer 173 may be formed. Top surfaces of at least some of the first electrode 140 and the second electrode 160 may be further covered. Accordingly, at least some of the first electrode 140 and the second electrode 160 may be interposed between the lower insulating layer 171 and the upper insulating layer 173. Accordingly, the first electrode 140 and the second electrode 160 may be stably fixed, thereby preventing the occurrence of a forward voltage increase and a change in the light emission pattern due to the exfoliation of the electrodes 140 and 160. Accordingly, it is possible to improve the electrical and optical reliability of the light emitting device.
  • the insulating layer 170 has been described as including a lower insulating layer 171 and an upper insulating layer 173, but the present invention is not limited thereto.
  • the insulating layer 170 is not formed separately, but may be formed of one layer consisting of a single layer or multiple layers. In this case, the electrodes 140 and 160 may not have a portion sandwiched between the insulating layers 170.
  • the first pad 181 and the second pad 183 are disposed on the upper insulating layer 173.
  • the first pad 181 and the second pad 183 are electrically connected to the first electrode 140 and the second electrode 160, respectively.
  • the first pad 181 may be in contact with a portion of the first ohmic contact electrode 141 and the second ohmic contact electrode 143
  • the second pad 183 may be a part of the second connection electrode 163.
  • And may be in contact with the first connection electrode 161.
  • the light emitting device may further include a heat radiation pad (not shown).
  • the heat dissipation pad may be positioned on the insulating layer 170 to be electrically insulated from the first and second electrodes 140 and 160.
  • 10 to 17 are plan views and cross-sectional views illustrating a method of manufacturing a light emitting device according to still another embodiment of the present invention.
  • the light emitting structure 120 including the first conductive semiconductor layer 121, the active layer 123, and the second conductive semiconductor layer 125 is formed on the growth substrate 110.
  • the growth substrate 110 is not limited as long as it is a substrate capable of growing the light emitting structure 120.
  • the growth substrate 110 may be a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, or the like.
  • the light emitting structure 120 may be formed using a method such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam deposition (MBE). Can be grown.
  • MOCVD metal-organic chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • MBE molecular beam deposition
  • the present embodiment also uses a wafer in which the light emitting structure 120 is grown on the growth substrate 110.
  • the same may be applied in general. In this case, a plurality of light emitting devices can be manufactured from the wafer.
  • At least one hole 127a and 127b is formed by partially removing the light emitting structure 120.
  • the at least one hole 127a and 127b may be formed through a patterning process, for example, by partially removing the second conductivity-type semiconductor layer 125 and the active layer 123 through a photolithography and etching process. . Forming the at least one hole 127a, 127b may include forming the first hole 127a and the second hole 127b. At least one hole 127a or 127b may correspond to an area where the first electrode 140 is formed. Therefore, the arrangement of the at least one hole 127a and 127b may be variously modified in consideration of current dispersion of the light emitting device.
  • a current blocking layer 150 is formed on the second conductive semiconductor layer 125.
  • the current blocking layer 150 may be formed to correspond to a region in which the second electrode 160 to be formed in a process to be described later will be formed.
  • the second connection electrode current blocking layer 153 may include a main electrode current blocking layer 153a and an extension electrode current blocking layer 153b.
  • the current blocking layer 150 may include an insulating material, and may be formed on the second conductive semiconductor layer 125 by a known method.
  • a current blocking layer 150 is formed on the entire surface of the light emitting structure 120 through sputtering, electron beam deposition, or coating and curing, and the current blocking layer 150 as shown through a patterning process using wet or dry etching. ) May be provided.
  • the present invention is not limited thereto, and the current blocking layer 150 may be formed through a lift-off process of first forming a mask formed of a photoresist, depositing the current blocking layer 150, and then removing the photoresist. ) May be formed.
  • a current spreading layer 130 covering the current blocking layer 150 is formed on the second conductive semiconductor layer 125.
  • the current spreading layer 130 may include a conductive oxide, and may include, for example, ITO, ZnO, or the like.
  • forming the current spreading layer 130 may include forming the lower current spreading layer 131 and the upper current spreading layer 133.
  • the lower and upper current spreading layers 131 and 133 may be sequentially formed through separate processes, or may be formed through different processes.
  • the lower current spreading layer 131 may be formed of ITO doped with a dopant including a metal
  • the upper current spreading layer 133 may be formed of undoped ITO.
  • the lower and upper current spreading layers 231 and 233 may be formed by electron beam deposition or sputtering, or may be formed through different methods.
  • the current spreading layer 130 including the conductive oxide may be patterned through an etching process.
  • the present invention is not limited thereto, and when the current spreading layer 130 is formed of a metal, the current spreading layer 130 may be formed by plating, deposition, or the like, and may be formed through a lift-off process. Can be patterned.
  • the present embodiment it is described that at least one hole 127a and 127b is formed, the current blocking layer 150 is formed, and then the current dispersion layer 130 is formed, but the present invention is not limited thereto. .
  • the current blocking layer 150 is formed, the current spreading layer 130 is formed, and the current spreading layer 130 and the light emitting structure 120 are etched in the same process to at least one hole 127a and 127b. ) May be formed.
  • a lower insulating layer 171 partially covering the light emitting structure 120 and the current spreading layer 130 is formed.
  • the lower insulating layer 171 may be formed by depositing an insulating material such as SiO 2 on the front surface of the light emitting structure 120 and the current spreading layer 130, and forming the first and second openings 171a and 171b through a patterning process. May comprise).
  • the first opening 171a may expose at least some of the first and second holes 127a and 127b, and the second opening 171b may partially expose the current spreading layer 130.
  • the first and second openings 171a and 173b may correspond to the positions at which the first electrode 140 and the second electrode 160 are formed, respectively.
  • first and second electrodes 140 and 160 are formed to at least partially fill the first and second openings 171a and 173b of the lower insulating layer 171.
  • the first and second electrodes 140 and 160 may be formed through the same process, and may be formed through a deposition and lift-off process. When the first and second electrodes 140 and 160 are formed through the same process and have a multilayer structure, the first and second electrodes 140 and 160 may have the same multilayer structure.
  • the present invention is not limited thereto, and the first and second electrodes 140 and 160 may be formed of different materials and different layers. In this case, the first and second electrodes 140 and 160 may be formed. It may be formed through a separate process.
  • the first electrode 140 and the second electrode 160 may further cover the upper surface of the lower insulating layer 171 around the first and second openings 171a and 171b, respectively.
  • the lower insulating layer 171 is first formed, and then the first and second electrodes 140 and 160 are formed, but the present invention is not limited thereto.
  • the first and second electrodes 140 and 160 may be formed, and then the lower insulating layer 171 may be formed to partially cover the light emitting structure 120 and the current spreading layer 130.
  • the lower insulating layer 171 may be spaced apart from the side surfaces of the first and second electrodes 140 and 160, and may at least partially cover the side surfaces of the first and second electrodes 140 and 160.
  • the top surfaces of the first and second electrodes 140 and 160 may be partially covered.
  • an upper insulating layer 173 partially covering the first and second electrodes 140 and 160 is formed on the lower insulating layer 171.
  • the upper insulating layer 173 may be formed of a distributed Bragg reflector in which materials having different refractive indices are alternately stacked.
  • the lower insulating layer 171 may serve as an interface layer or a base layer of the distributed Bragg reflector.
  • the upper insulating layer 173 may be formed through a known deposition and etching process.
  • the upper insulating layer 173 may include third and fourth openings 173a and 173b, and the first and second electrodes 140 and 273b may be formed through the third and fourth openings 173a and 173b, respectively. 160 may be exposed respectively.
  • the first pad 181 and the second pad 183 may be further formed on the upper insulating layer 173. Accordingly, the light emitting device as shown in FIGS. 4 to 9 may be provided.
  • the first pad 181 may be in contact with the first electrode 140 through the third opening 173a of the upper insulating layer 173.
  • the second pad 183 may be in contact with the second electrode 160 through the fourth opening 173b of the upper insulating layer 173.
  • the first and second pads 161 and 163 may be formed together in the same process, for example, using photo and etching techniques or lift off techniques.
  • the light emitting device manufacturing method may further include separating the substrate 110 from the light emitting structure 120.
  • the substrate 110 may be separated or removed through physical and / or chemical methods.
  • the present invention provides a light emitting device having improved electrical conductivity and reliability, thereby improving lifetime and reliability of a product using the light emitting device.
  • TELED top-emitting light emitting diode
  • VLED vertical type
  • the present invention may be variously applied to a light receiving device, an organic light emitting diode (OLED), a cell, an LCD, a semiconductor process, and the like.
  • FIG. 18 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.
  • the lighting apparatus includes a diffusion cover 1010, a light emitting device module 1020, and a body portion 1030.
  • the body portion 1030 may accommodate the light emitting device module 1020, and the diffusion cover 1010 may be disposed on the body portion 1030 to cover the upper portion of the light emitting device module 1020.
  • the body portion 1030 is not limited as long as it can receive and support the light emitting device module 1020 and supply electric power to the light emitting device module 1020.
  • the body portion 1030 may include a body case 1031, a power supply device 1033, a power case 1035, and a power connection portion 1037.
  • the power supply device 1033 is accommodated in the power case 1035 and electrically connected to the light emitting device module 1020, and may include at least one IC chip.
  • the IC chip may adjust, convert, or control the characteristics of the power supplied to the light emitting device module 1020.
  • the power case 1035 may receive and support the power supply 1033, and the power case 1035 to which the power supply 1033 is fixed may be located inside the body case 1031. .
  • the power connection unit 115 may be disposed at a lower end of the power case 1035 and may be coupled to the power case 1035. Accordingly, the power connection unit 1037 may be electrically connected to the power supply device 1033 inside the power case 1035 to serve as a path through which external power may be supplied to the power supply device 1033.
  • the light emitting device module 1020 includes a substrate 1023 and a light emitting device 1021 disposed on the substrate 1023.
  • the light emitting device module 1020 may be disposed on the body case 1031 and electrically connected to the power supply device 1033.
  • the substrate 1023 is not limited as long as it can support the light emitting device 1021.
  • the substrate 1023 may be a printed circuit board including wiring.
  • the substrate 1023 may have a shape corresponding to the fixing portion of the upper portion of the body case 1031 so as to be stably fixed to the body case 1031.
  • the light emitting device 1021 may include at least one of the light emitting devices according to the embodiments of the present invention described above.
  • the diffusion cover 1010 may be disposed on the light emitting device 1021, and may be fixed to the body case 1031 to cover the light emitting device 1021.
  • the diffusion cover 1010 may have a translucent material and may adjust the directivity of the lighting device by adjusting the shape and the light transmittance of the diffusion cover 1010. Therefore, the diffusion cover 1010 may be modified in various forms according to the purpose of use of the lighting device and the application aspect.
  • 19 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
  • the display device includes a display panel 2110, a backlight unit providing light to the display panel 2110, and a panel guide supporting a lower edge of the display panel 2110.
  • the display panel 2110 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer.
  • a gate driving PCB for supplying a driving signal to the gate line may be further located at the edge of the display panel 2110.
  • the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate.
  • the backlight unit includes a light source module including at least one substrate and a plurality of light emitting devices 2160.
  • the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130.
  • the bottom cover 2180 may be opened upward to accommodate the substrate, the light emitting device 2160, the reflective sheet 2170, the diffusion plate 2131, and the optical sheets 2130.
  • the bottom cover 2180 may be combined with the panel guide.
  • the substrate may be disposed under the reflective sheet 2170 and be surrounded by the reflective sheet 2170.
  • the present invention is not limited thereto, and when the reflective material is coated on the surface, the reflective material may be positioned on the reflective sheet 2170.
  • a plurality of substrates may be formed, and the plurality of substrates may be arranged in a side-by-side arrangement, but is not limited thereto and may be formed of a single substrate.
  • the light emitting device 2160 may include at least one of the light emitting devices according to the embodiments of the present invention described above.
  • the light emitting devices 2160 may be regularly arranged in a predetermined pattern on the substrate.
  • a lens 2210 may be disposed on each light emitting device 2160 to improve uniformity of light emitted from the plurality of light emitting devices 2160.
  • the diffusion plate 2131 and the optical sheets 2130 are positioned on the light emitting device 2160. Light emitted from the light emitting device 2160 may be supplied to the display panel 2110 in the form of a surface light source through the diffusion plate 2131 and the optical sheets 2130.
  • the light emitting device according to the embodiments of the present invention may be applied to the direct type display device as the present embodiment.
  • 20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment is applied to a display device.
  • the display device including the backlight unit includes a display panel 3210 on which an image is displayed and a backlight unit disposed on a rear surface of the display panel 3210 to irradiate light.
  • the display apparatus includes a frame 240 that supports the display panel 3210 and accommodates the backlight unit, and covers 3240 and 3280 that surround the display panel 3210.
  • the display panel 3210 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer.
  • a gate driving PCB for supplying a driving signal to the gate line may be further located at an edge of the display panel 3210.
  • the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate.
  • the display panel 3210 may be fixed by covers 3240 and 3280 positioned at upper and lower portions thereof, and the cover 3280 positioned at lower portions thereof may be coupled to the backlight unit.
  • the backlight unit for providing light to the display panel 3210 may include a lower cover 3270 having a portion of an upper surface thereof, a light source module disposed on one side of the lower cover 3270, and positioned in parallel with the light source module to provide point light. And a light guide plate 3250 for converting to surface light.
  • the backlight unit according to the present exemplary embodiment is disposed on the light guide plate 3250 and is disposed below the light guide plate 3250 and the optical sheets 3230 for diffusing and condensing light.
  • the display apparatus may further include a reflective sheet 3260 reflecting in the direction of the display panel 3210.
  • the light source module includes a substrate 3220 and a plurality of light emitting devices 3110 spaced apart from each other by a predetermined interval on one surface of the substrate 3220.
  • the substrate 3220 is not limited as long as it supports the light emitting device 3110 and is electrically connected to the light emitting device 3110.
  • the substrate 3220 may be a printed circuit board.
  • the light emitting device 3110 may include at least one light emitting device according to the embodiments of the present invention described above. Light emitted from the light source module is incident to the light guide plate 3250 and is supplied to the display panel 3210 through the optical sheets 3230. Through the light guide plate 3250 and the optical sheets 3230, the point light sources emitted from the light emitting devices 3110 may be transformed into surface light sources.
  • the light emitting device according to the embodiments of the present invention may be applied to the edge type display device as the present embodiment.
  • 21 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.
  • the head lamp includes a lamp body 4070, a substrate 4020, a light emitting device 4010, and a cover lens 4050. Furthermore, the head lamp may further include a heat dissipation unit 4030, a support rack 4060, and a connection member 4040.
  • the substrate 4020 is fixed by the support rack 4060 and spaced apart from the lamp body 4070.
  • the substrate 4020 is not limited as long as it is a substrate capable of supporting the light emitting device 4010.
  • the substrate 4020 may be a substrate having a conductive pattern such as a printed circuit board.
  • the light emitting device 4010 is positioned on the substrate 4020 and may be supported and fixed by the substrate 4020.
  • the light emitting device 4010 may be electrically connected to an external power source through the conductive pattern of the substrate 4020.
  • the light emitting device 4010 may include at least one light emitting device according to the embodiments of the present invention described above.
  • the cover lens 4050 is positioned on a path along which light emitted from the light emitting element 4010 travels.
  • the cover lens 4050 may be disposed spaced apart from the light emitting element 4010 by the connecting member 4040, and may be disposed in a direction to provide light emitted from the light emitting element 4010. Can be.
  • the connection member 4040 may fix the cover lens 4050 with the substrate 4020 and may be disposed to surround the light emitting device 4010 to serve as a light guide for providing the light emitting path 4045.
  • connection member 4040 may be formed of a light reflective material or coated with a light reflective material.
  • the heat dissipation unit 4030 may include a heat dissipation fin 4031 and / or a heat dissipation fan 4033, and emits heat generated when the light emitting device 4010 is driven to the outside.
  • the light emitting device may be applied to the head lamp, in particular, a vehicle head lamp as in the present embodiment.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

L'invention concerne une diode électroluminescente qui comprend : une couche semiconductrice de type N formée sur un substrat ; une couche semiconductrice de type P formée sur une partie de la couche semiconductrice de type N ; une couche active, qui est formée entre la couche semiconductrice de type N et la couche semiconductrice de type P, pour générer de la lumière par la recombinaison d'électrons et de trous ; une couche de contact ohmique qui est formée sur la couche semiconductrice de type P et qui comprend une couche d'oxyde d'étain dopé à l'indium (ITO) dopée avec du métal ; une couche conductrice transparente qui est formée sur la couche de contact ohmique de manière à avoir une épaisseur différente de celle de la couche de contact ohmique et qui comprend une couche d'ITO non dopée ; et une couche réfléchissante qui est formée sur la couche conductrice transparente et qui comprend une couche d'oxyde. En conséquence, il est possible de fournir une diode électroluminescente, qui a de meilleures caractéristiques courant-tension par l'amélioration de la fiabilité et de la conductivité électrique de la couche ohmique ainsi qu'une meilleure efficacité électroluminescente par l'utilisation d'une couche réfléchissante utilisant des oxydes.
PCT/KR2015/008840 2014-08-27 2015-08-24 Diode électroluminescente et son procédé de fabrication WO2016032193A1 (fr)

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CN107527976A (zh) * 2016-06-21 2017-12-29 三星电子株式会社 半导体发光装置及其制造方法
CN107527976B (zh) * 2016-06-21 2022-02-25 三星电子株式会社 半导体发光装置及其制造方法
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CN110036483B (zh) * 2016-11-30 2024-04-12 首尔伟傲世有限公司 具有多个发光单元的发光二极管
CN109004076A (zh) * 2017-06-21 2018-12-14 佛山市国星半导体技术有限公司 一种倒装led芯片及其制作方法
CN109148662A (zh) * 2018-10-17 2019-01-04 河北工业大学 具有均匀电极电场分布的发光二极管及其制备方法
CN112951954A (zh) * 2021-01-28 2021-06-11 湘能华磊光电股份有限公司 一种发光二极管芯片及其制作工艺
CN114038969A (zh) * 2021-11-09 2022-02-11 天津三安光电有限公司 一种led外延结构及led芯片
CN114038969B (zh) * 2021-11-09 2023-10-20 天津三安光电有限公司 一种led外延结构及led芯片
CN114420817A (zh) * 2022-01-20 2022-04-29 京东方科技集团股份有限公司 发光器件及其制备方法、显示面板
CN115763666A (zh) * 2022-11-17 2023-03-07 马鞍山杰生半导体有限公司 一种紫外发光二极管芯片
CN116825924A (zh) * 2023-08-24 2023-09-29 山西中科潞安紫外光电科技有限公司 一种深紫外led倒装芯片及其制备方法
CN116825924B (zh) * 2023-08-24 2023-12-19 山西中科潞安紫外光电科技有限公司 一种深紫外led倒装芯片及其制备方法

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