WO2016024676A1 - Synaptic device and method for manufacturing same - Google Patents

Synaptic device and method for manufacturing same Download PDF

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Publication number
WO2016024676A1
WO2016024676A1 PCT/KR2014/012656 KR2014012656W WO2016024676A1 WO 2016024676 A1 WO2016024676 A1 WO 2016024676A1 KR 2014012656 W KR2014012656 W KR 2014012656W WO 2016024676 A1 WO2016024676 A1 WO 2016024676A1
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active layer
synaptic
poly
gate
mimic device
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PCT/KR2014/012656
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French (fr)
Korean (ko)
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이태우
서문도
민성용
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포항공과대학교 산학협력단
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Publication of WO2016024676A1 publication Critical patent/WO2016024676A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

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  • the present invention relates to a device and more particularly to a synaptic mimic device and a method of manufacturing the same.
  • Humans can understand visual information about their surroundings and distinguish various objects more efficiently than any existing computer. This is possible through the human brain, which consists of a network of 10 12 neurons connected by 10 15 synapses. Neurons are composed of dendrites and axons, and they are structured to transmit information through synapses. Synapses are characterized by reinforcing their formation upon repeated learning. Recently, efforts have been made to develop a synaptic mimic device by developing a neural chip having a learning function.
  • synaptic mimic devices include floating gate silicon devices, nanoparticle organic devices, resistive switching devices, memristors, phase change memory, carbon nanotube devices, etc. There is this.
  • these synaptic mimic devices are mostly metal-insulator-metal two terminals, and have two characteristics, signal transmission and self-learning, which are sequentially performed. In other words, both functions of signal transmission and self-learning do not occur simultaneously.
  • synaptic devices mapstic device
  • synaptic devices that can perform a signal transmission and self-learning at the same time to more realistic synaptic imitation.
  • synaptic devices that can simultaneously perform signal transmission and self-learning. Therefore, there is an urgent need to develop a synaptic device capable of simultaneously performing signal transmission and self-learning.
  • the present invention has been conceived to solve the above problems, and it is an object of the present invention to provide a novel synaptic mimic device and a method for manufacturing the same, which can simultaneously perform signal transmission and self-learning.
  • Another object of the present invention is to provide a method for manufacturing a synaptic mimic device capable of large area alignment and high integration of an active layer.
  • the synaptic mimic device includes a gate electrode, an active layer, an ion gel gate insulating layer disposed between the gate electrode and the active layer, the insulating gel and an ionic material, and a source electrode and a drain electrode electrically connected to the active layer.
  • the gate electrode or active layer is supported on the substrate.
  • the synaptic mimic device may have a top-gate / bottom-contact, top-gate / top-contact, bottom-gate / bottom-contact, or bottom-gate / top-contact structure.
  • the active layer may be a one-dimensional nano-semiconductor material, and the one-dimensional nano-semiconductor material may include at least one selected from the group consisting of nanowires, nanoribbons, nanotubes, nanorods, and nanofilms.
  • the active layer may include at least one selected from the group consisting of a low molecular organic semiconductor, an organic semiconductor, a conductive polymer, an inorganic semiconductor, an oxide semiconductor, a two-dimensional semiconductor, and a quantum dot, and the active layer includes TIPS pentacene (6, 13).
  • the insulating polymer may include at least one selected from the group consisting of an insulating single polymer, a block copolymer, a polymer-monomeric mixture, and a crosslinkable polymer, and the insulating polymer may be made of poly (9-vinylcarba).
  • PS-PEO-PS polyvinylchloride poly (styrene-ethylene oxide-styrene)
  • the ionic material is lithium-bis (trifluoromethylsulfonyl) imide (LiTFSI), lithium poly (styrene sulfonate) (LiPSS), 1-ethyl-3-methylimidazolium bis (trifluoromethylsul Ponyl) imide ([EMIM] [TFSI]), 1-butyl-3-methylimidazolium hexafluorophosphate ([BMIM] [PF 6 ]), and 1-ethyl-3-methylimidazolium n- Octylsulfate ([EMIM] [OctOSO 3 ]) may comprise at least one selected from the group consisting of.
  • Another aspect of the present invention provides a method of manufacturing a synaptic mimic device.
  • the manufacturing method includes forming an active layer on a substrate, and forming source and drain electrodes electrically connected to the active layer at one end and the other end of the active layer, respectively;
  • an ion gel gate insulating layer including an insulating polymer and an ionic material on the active layer Forming an ion gel gate insulating layer including an insulating polymer and an ionic material on the active layer, and forming a gate electrode on the ion gel gate insulating layer.
  • the active layer may be a nanowire pattern, a nanoribbon pattern, a nanotube pattern, or a nanorod pattern, and the forming of the active layer may use an electric field inkjet printing process.
  • the forming of the ion gel gate insulating layer may use a drop casting method.
  • synaptic mimic device of the present invention and a method of manufacturing the same, it is possible to perform signal transmission and self-learning at the same time, and provide a novel synaptic mimic device.
  • the manufacturing method of the synaptic mimic device of the present invention has the effect of large-area alignment and high integration.
  • FIGS. 1A-1D are cross-sectional views of various synaptic mimic devices in accordance with one embodiment of the present invention.
  • FIG. 2 is a process flowchart of a method of manufacturing a synaptic mimic device according to an embodiment of the present invention.
  • a layer is referred to herein as "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween.
  • the directional expression of the upper part, the upper part, and the upper part may be understood as meanings of the lower part, the lower part, the lower part, and the like according to the criteria. That is, the expression of the spatial direction should be understood as a relative direction and should not be construed as limiting the absolute direction.
  • the synaptic mimic device of the present invention is disposed between a gate electrode, an active layer, the gate electrode and the active layer, an ion gel gate insulating layer containing an insulating polymer and an ionic material, and a source electrode and a drain electrode electrically connected to the active layer.
  • the gate electrode or the active layer is supported on a substrate.
  • the gate electrode described above may use at least one metal material selected from the group consisting of aluminum, copper, nickel, iron, chromium, titanium, zinc, lead, gold, and silver, and may be poly (3,4-ethylenedioxy Thiophene): conductive polymer material such as polystyrene sulfonate (PEDOT: PSS), or doped polymer material may be used, but is not limited thereto.
  • the gate electrode described above may use a metal probe.
  • the thickness of the above-described gate electrode may be 0.5nm to 50mm, more specifically 1nm to 1mm.
  • the active layer described above may be a one-dimensional nano-semiconductor material.
  • the one-dimensional nano-semiconductor material described above may include at least one selected from the group consisting of nanowire patterns, nanoribbon patterns, nanotube patterns, nanorod patterns, and nanofilms. In this case, the large area and high integration of the device can be achieved.
  • the active layer described above may include at least one selected from the group consisting of a low molecular organic semiconductor, an organic semiconductor, a conductive polymer, an inorganic semiconductor, an oxide semiconductor, a two-dimensional semiconductor, and a quantum dot.
  • the low molecular organic semiconductor described above is at least selected from the group consisting of TIPS pentacene (6,13-bis (triisopropylsilylethynyl) pentacene), TES ADT (Triethylsilylethynyl anthradithiophene) and PCBM ([6,6] -Phenyl C61 butyric acid methyl ester)
  • the organic semiconductor or conductive polymer described above may include one of P3HT (Poly (3-hexylthiophene)), PEDOT (Poly (3,4-ethylenedioxythiophene)), PVK (Poly (9-vinylcarbazole)), and poly (p -Phenylene vinylene) (poly (p-phenylene vinylene)), polyfluorene (polyfluorene) (polyfluorene) (polyaniline), and may include at least one selected from the group consisting of polypyrrole (polypyrrole), the in
  • Molybdenum (MoS2), tungsten sulfide (WS2), molybdenum selenide (MoSe2), tungsten selenide (WSe2), boron nitride (h-BN), and fluoro-graphene It may comprise at least one, and the above-described quantum dots may include at least one selected from the group consisting of cadmium selenide, cadmium telluride, and cadmium sulfide.
  • the ion gel gate insulating layer includes an insulating polymer and an ionic material.
  • the ion gel gate insulating layer described above has synaptic properties as it includes an ionic material. Electrical synaptic stimulation spikes move ions toward the active layer and produce excitatory post-synaptic currents (drain currents). As a result, the ions moved to the active layer attract and accumulate electric charges. Thereafter, when the above-described synaptic stimulus spike ends, the above-described late synaptic reaction current gradually decreases, and at the same time, the above-mentioned ions gradually return to the equilibrium level of the ion gel of the above-described ion gel gate insulating layer and exhibit synaptic characteristics. .
  • the insulating polymer described above may include at least one selected from the group consisting of a flexible single polymer material, a block copolymer, a polymer-monomeric mixture, and a crosslinkable polymer.
  • the single polymer materials described above are poly (9-vinylcarbazole), poly (p-phenylenevinylene), polyfluorene, polyaniline, polypyrrole, polyethylene oxide, polystyrene, polycaprolactone, polyacrylonitrile, poly (methyl Methacrylate), polyimide, poly (vinylidene fluoride), and polyvinylchloride; and at least one selected from the group consisting of poly (styrene-ethyleneoxide-styrene) ( PS-PEO-PS), and may be a polymer-monomeric mixture or a crosslinkable polymer.
  • the aforementioned ionic materials include lithium-bis (trifluoromethylsulfonyl) imide (LiTFSI), lithium poly (styrene sulfonate) (LiPSS), 1-ethyl-3-methylimidazolium bis (trifluoromethyl Sulfonyl) imide ([EMIM] [TFSI]), 1-butyl-3-methylimidazolium hexafluorophosphate ([BMIM] [PF 6 ]), and 1-ethyl-3-methylimidazolium n -Octyl sulfate ([EMIM] [OctOSO 3 ]) and at least one selected from the group consisting of.
  • LiTFSI lithium-bis (trifluoromethylsulfonyl) imide
  • LiPSS lithium poly (styrene sulfonate)
  • EMIM] [TFSI] 1-butyl-3-methylimidazolium hexaflu
  • the aforementioned source electrode and drain electrode may comprise at least one metal material selected from the group consisting of aluminum, copper, nickel, iron, chromium, titanium, zinc, lead, gold, and silver, and poly (3,4) -Ethylenedioxythiophene): conductive polymer material such as polystyrene sulfonate (PEDOT: PSS), and may comprise a doped polymer material.
  • metal material selected from the group consisting of aluminum, copper, nickel, iron, chromium, titanium, zinc, lead, gold, and silver, and poly (3,4) -Ethylenedioxythiophene): conductive polymer material such as polystyrene sulfonate (PEDOT: PSS), and may comprise a doped polymer material.
  • the thickness of the above-described source electrode and drain electrode may be 0.5nm to 50mm, more specifically 1nm to 1mm.
  • the substrate 10 described above may include at least one selected from the group consisting of an insulating material, a metal material, a carbon material, a semiconductor, and a composite material of a conductor and an insulating film, but is not limited thereto.
  • the aforementioned synaptic mimic device may be a top-gate / bottom-contact, top-gate / top-contact, bottom-gate / bottom-contact, or bottom-gate / top-contact structure.
  • FIGS. 1A-1D are cross-sectional views of various synaptic mimic devices in accordance with one embodiment of the present invention.
  • FIG. 1A is a cross-sectional view of a synaptic mimic device having a top-gate / bottom-contact structure according to an embodiment of the present invention.
  • a synaptic mimic device having a top-gate / bottom-contact structure may have a source electrode 30a and a drain electrode 30b disposed at one end and the other end of a substrate 10, respectively. ), The active layer 20 disposed on the source electrode 30a and the drain electrode 30b described above, the ion gel gate insulating layer 40 disposed on the active layer 20 described above, and the aforementioned ion gel gate insulation
  • the gate electrode 50 may be disposed on the layer 40.
  • FIG. 1B is a cross-sectional view of a synaptic mimic device having a top-gate / top-contact structure according to an embodiment of the present invention.
  • a synaptic mimic device having a top-gate / top-contact structure may include an active layer 20 disposed on a substrate 10, one end of the active layer 20 described above, and The source electrode 30a and the drain electrode 30b disposed at the other end, the ion gel gate insulating layer 40 disposed on the active layer 20 described above, and the ion gel gate insulating layer 40 described above.
  • the gate electrode 50 may be included.
  • 1C is a cross-sectional view of a synaptic mimic device having a bottom-gate / bottom-contact structure according to an embodiment of the present invention.
  • a synaptic mimic device having a bottom-gate / bottom-contact structure may be disposed on a gate electrode 50 disposed on a substrate 10, and the gate electrode 50 described above.
  • the ion gel gate insulating layer 40 disposed on the first side, the source electrode 30a and the drain electrode 30b disposed on one end and the other end of the ion gel gate insulating layer 40 described above, the source electrode 30a described above, and
  • the active layer 20 may be disposed on the drain electrode 30b.
  • 1D is a cross-sectional view of a synaptic mimic device having a bottom-gate / top-contact structure according to an embodiment of the present invention.
  • a synaptic mimic device having a bottom-gate / top-contact structure may be disposed on a gate electrode 50 disposed on a substrate 10, and the gate electrode 50 described above.
  • a drain electrode 30b disposed on one end and the other end of the active layer 20 described above.
  • FIG. 2 is a process flowchart of a method of manufacturing a synaptic mimic device according to an embodiment of the present invention.
  • the synaptic mimic device first forms the active layer 20 on the substrate 10 (S100).
  • the material used to form the substrate 10 or the active layer 20 described above will be referred to the description of the 'synaptic mimic device' described above.
  • a deposition process for forming the above-described active layer 20 on the substrate 10 described above may include physical vapor deposition (PVD), chemical vapor deposition (CVD), and sputtering.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • sputtering Pulsed laser deposition (PLD), thermal evaporation, electron beam evaporation, atomic layer deposition (ALD) and molecular beam epitaxy (MBE) Etc.
  • PLD physical vapor deposition
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • the active layer 20 described above may be formed using an electric field inkjet printing process.
  • the above-described active layer 20 may be formed of a nanowire pattern, a nanoribbon pattern, a nanotube pattern, or a nanorod pattern, so that a large area of the device may be highly integrated.
  • an electric field assisted robotic nozzle printer may be used, but is not limited thereto.
  • source and drain electrodes 30a and 30b which are electrically connected to the active layer described above are formed at one end and the other end of the above-described active layer 20, respectively (S200).
  • the material used to form the source electrode 30a and the drain electrode 30b described above will be referred to the description of the 'synaptic mimic device' described above.
  • Deposition processes for forming the source source electrode 30a and the drain electrode 30b described above include physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, pulse Pulsed laser deposition (PLD), thermal evaporation, electron beam evaporation, atomic layer deposition (ALD) and molecular beam epitaxy (MBE) It is available.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • PLD pulse Pulsed laser deposition
  • thermal evaporation thermal evaporation
  • electron beam evaporation electron beam evaporation
  • ALD atomic layer deposition
  • MBE molecular beam epitaxy
  • the source electrode 30a and the drain electrode 30b described above may be patterned through a shadow mask or a dry etching process so as to be formed at one end and the other end of the active layer 20 described above, respectively.
  • the ion gel gate insulating layer 40 including the insulating polymer and the ionic material is formed on the active layer 20 described above (S300).
  • the ion gel gate insulating layer 40 described above has synaptic properties as it includes an ionic material.
  • the electrical synaptic stimulus spikes move ions toward the active layer 20 and generate an excitatory post-synaptic current (drain current).
  • drain current excitatory post-synaptic current
  • the ions moved to the active layer 20 attract and accumulate charge.
  • the above-mentioned ions gradually return to the equilibrium level of the ion gel of the above-described ion gel gate insulating layer 40 and the synapse Characteristics.
  • the ion gel gate insulating layer 40 described above is preferably formed to be electrically connected to the source electrode 30a and the drain electrode 30b.
  • the ion gel gate insulating layer In forming the ion gel gate insulating layer, it is preferable to use a drop casting method. In the case of using the drop casting method, the surface curvature of the ion gel gate insulating layer 40 in the form of a gel is least formed, thereby improving the performance of the device.
  • the gate electrode 50 is formed on the ion gel gate insulating layer 40 described above (S400).
  • the material used to form the above-described gate electrode 50 will be referred to the description of the 'synaptic mimic device' described above.
  • Deposition processes for forming the above-described gate electrode 50 include physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, pulsed laser deposition; PLD), thermal evaporation, electron beam evaporation, atomic layer deposition (ALD), molecular beam epitaxy (MBE), and the like.
  • zinc oxide precursor / PVA solution prepared by distilled water.
  • concentration of the zinc oxide precursor / PVA solution was 10 wt%.
  • the prepared zinc oxide precursor / PVA solution was placed in a syringe of an electric field assisted robotic nozzle printer, and the zinc oxide precursor / PVA solution was discharged from the nozzle while applying a voltage of about 2.0 kV to the nozzle.
  • a zinc oxide precursor / PVA composite nanowire pattern was formed on the collector's substrate moved by the robot stage.
  • the diameter of the nozzle used was 100 ⁇ m, and the distance between the nozzle and the collector was kept constant at 5 mm.
  • the moving distance in the Y-axis direction of the robot stage was 50 ⁇ m, and the moving distance in the X-axis direction was 15 cm.
  • the collector was 20 cm ⁇ 20 cm in size, and a silicon wafer coated with a 300 nm thick silicon oxide film (SiO 2 ) was used as a substrate. At this time, the size of the substrate was 2.5cm ⁇ 2.5cm.
  • the aligned zinc oxide precursor / PVA nanowire patterns were heated in a furnace at 500 ° C. for 4 hours to form aligned zinc oxide nanowire patterns.
  • the prepared P3HT solution was placed in a syringe of an electric field assisted robotic nozzle printer, and the P3HT solution was discharged from the nozzle while applying a voltage of about 1.5 kV to the nozzle.
  • An P3HT nanowire pattern was formed on the collector's substrate moved by the robot stage.
  • the diameter of the nozzle used was 100 micrometers, and the distance between a nozzle and a collector was kept constant at 5.5 mm.
  • the moving distance in the Y-axis direction of the robot stage was 50 ⁇ m, and the moving distance in the X-axis direction was 15 cm.
  • the collector was 20 cm ⁇ 20 cm in size, and a silicon wafer coated with a 300 nm thick silicon oxide film (SiO 2 ) was used as a substrate. At this time, the size of the substrate was 2.5cm ⁇ 2.5cm.
  • P3HT nanowire-based synaptic mimic device was manufactured by using a metal probe as the gate electrode in the above-described gate insulating layer.
  • the graphene active layer was prepared according to the method described below.
  • Copper foil (Cu foil, purity 99.8%) having a thickness of 25 ⁇ m was placed in a quartz tube and heated at 1000 ° C. At this time, the pressure inside the quartz tube was 0.1 Torr. Then, 16 sccm of hydrogen gas was flowed for 30 minutes, and 26 sccm / 15 sccm of methane / hydrogen mixed gas was flowed for 30 minutes.
  • Graphene produced on copper foil was cooled to room temperature. The cooled graphene was spin-coated with polymethyl methacrylate (PMMA) / chlorobenzene solution (4 wt%) and dried at room temperature for 1 hour.
  • PMMA polymethyl methacrylate
  • the copper foil was removed by floating in 1.4 wt% aqueous solution of ammonium persulfate (APS) and transferred onto a silicon wafer coated with a silicon oxide film (SiO 2) to a thickness of 300 nm.
  • APS ammonium persulfate
  • SiO 2 silicon oxide film
  • PVK polyvinylcarbazole
  • PVK was dissolved in styrene to prepare PVK / styrene solution (3.77 wt%).
  • the prepared PVK / styrene solution was placed in a syringe of an electric field assisted robotic nozzle printer, and the PVK / styrene solution was discharged from the nozzle while applying a voltage of about 3.6 kV to the nozzle.
  • the substrate on which the graphene active layer was transferred was placed on the collector moved by the robot stage, and an aligned PVK nanowire pattern was formed thereon.
  • the diameter of the nozzle used was 100 ⁇ m and the distance between the nozzle and the collector was kept constant at 2.5 mm.
  • the moving distance in the Y-axis direction of the robot stage was 50 ⁇ m, and the moving distance in the X-axis direction was 15 cm.
  • the size of the collector was 20 cm x 20 cm, and the size of the substrate was 2.5 cm x 2.5 cm.
  • Source and drain electrodes were formed by sequentially depositing 3 nm thick titanium and 60 nm thick gold on the PVK nanowire patterns. Graphene regions not covered by PVK nanowires are removed via oxygen plasma etching (30 W, 10 seconds), and PVK nanowires are removed by sonication in chloroform. Graphene nanoribbons were produced through the above process.
  • the active layer is formed in the form of nanowires.
  • the diameter of the nanowire described above is 118 nm.
  • a large area highly integrated device can be manufactured by performing an electric field inkjet printing process.
  • Preparation Example 1 may confirm current characteristics of a zinc oxide nanowire-based synaptic mimic device that mimics a latent synaptic response current (drain current) with respect to an electrical synaptic stimulation voltage.
  • the electric synaptic stimulation voltage gate voltage pulse
  • the late synaptic response current is intensified.
  • the late synaptic response current then slowly decreases to the resting current level.
  • the synaptic mimic device according to an embodiment of the present invention exhibits synaptic properties.
  • the active layer is formed in the form of nanowires. It can also be seen that the diameter of the nanowires described above is 329 nm.
  • a large area highly integrated device can be manufactured by performing an electric field inkjet printing process.
  • Preparation Example 2 exhibits biosynaptic properties.
  • the synaptic mimic device according to an embodiment of the present invention exhibits biosynaptic properties.
  • the active layer is formed in the form of nanoribbons.
  • the width of the above-described nanoribbons is 31.2nm.
  • a large area highly integrated device can be manufactured by performing an electric field inkjet printing process.
  • Preparation Example 3 exhibits biosynaptic properties.
  • the synaptic mimic device according to an embodiment of the present invention exhibits biosynaptic properties.

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Abstract

Provided are a synaptic device and a method for manufacturing the same. The synaptic device comprises: a gate electrode; an active layer; an ion-gel gate insulating layer comprising an insulative polymer and an ionic material, arranged between the gate electrode and the active layer; and a source electrode and a drain electrode which are electrically connected to the active layer, wherein the gate electrode or the active layer is supported on a substrate. As such, the present invention can provide a new synaptic device which can simultaneously perform signal transmission and self-learning.

Description

시냅스 모방 소자 및 이의 제조방법Synaptic mimic device and its manufacturing method
본 발명은 소자에 관한 것으로 더욱 상세하게는 시냅스 모방 소자 및 이의 제조방법에 관한 것이다.The present invention relates to a device and more particularly to a synaptic mimic device and a method of manufacturing the same.
인간은 현존하는 어떠한 컴퓨터보다 효율적으로 주위 환경들에 대한 시각적 정보들을 이해하고 다양한 물체를 구별할 수 있다. 이는 1015 개의 시냅스로 연결된 1012 개의 뉴런의 네트워크로 이루어진 인간의 두뇌를 통해 가능한 일이다. 뉴런은 수상돌기(dendrite) 와 축색돌기(axon) 로 이루어져 있으며, 시냅스를 통해 정보가 전달되는 구조로 이루어져 있다. 시냅스는 반복 학습에 따라 그 형성이 강화되는 특징이 있다. 이에 최근에는 학습 기능을 갖는 신경 칩을 개발하여 시냅스 모방 소자를 제조하고자 하는 노력이 계속되고 있다.Humans can understand visual information about their surroundings and distinguish various objects more efficiently than any existing computer. This is possible through the human brain, which consists of a network of 10 12 neurons connected by 10 15 synapses. Neurons are composed of dendrites and axons, and they are structured to transmit information through synapses. Synapses are characterized by reinforcing their formation upon repeated learning. Recently, efforts have been made to develop a synaptic mimic device by developing a neural chip having a learning function.
기존의 시냅스 모방 소자로는 플로팅 게이트형 (floating gate) 실리콘 소자, 나노입자 유기 소자, 저항성 스위칭 (resistive switching) 소자, 멤리스터 (memristor), 상변화 메모리 (phase change memory), 탄소나노튜브 소자 등이 있다. 하지만 이와 같은 시냅스 모방 소자들은 대부분 금속-절연체-금속 형태의 2 단자(two terminal)로써, 신호 전달과 자가 학습의 두 기능이 동시에 일어나지 않고 순차적으로 이루어지는 특성이 있다. 즉, 신호 전달과 자가 학습의 두 기능이 동시에 일어나지 않는 단점이 있다.Conventional synaptic mimic devices include floating gate silicon devices, nanoparticle organic devices, resistive switching devices, memristors, phase change memory, carbon nanotube devices, etc. There is this. However, these synaptic mimic devices are mostly metal-insulator-metal two terminals, and have two characteristics, signal transmission and self-learning, which are sequentially performed. In other words, both functions of signal transmission and self-learning do not occur simultaneously.
이에, 최근에는 신호 전달과 자가 학습을 동시에 수행하여 보다 실제와 같은 시냅스 모방이 가능한 시냅스 소자(synaptic device)에 대한 관심이 높아지고 있다. 하지만, 신호 전달과 자가학습을 동시에 수행할 수 있는 시냅스 소자에 대한 연구가 미미한 실정이다. 이에, 신호 전달과 자가학습을 동시에 수행할 수 있는 시냅스 소자 개발이 시급한 실정이다.Therefore, in recent years, interest in synaptic devices (simaptic device) that can perform a signal transmission and self-learning at the same time to more realistic synaptic imitation has been increasing. However, there is little research on synaptic devices that can simultaneously perform signal transmission and self-learning. Therefore, there is an urgent need to develop a synaptic device capable of simultaneously performing signal transmission and self-learning.
이에 본 발명은 상기의 문제점을 해결하기 위하여 착안된 것으로서, 신호 전달과 자가학습을 동시에 수행할 수 있고, 시냅스 모방 특성을 나타내는 신규한 시냅스 모방 소자 및 이의 제조방법를 제공하는 데 그 목적이 있다.Accordingly, the present invention has been conceived to solve the above problems, and it is an object of the present invention to provide a novel synaptic mimic device and a method for manufacturing the same, which can simultaneously perform signal transmission and self-learning.
또한, 활성층의 대면적 정렬 및 고집적이 가능한 시냅스 모방 소자의 제조방법을 제공하는 데 다른 목적이 있다.Another object of the present invention is to provide a method for manufacturing a synaptic mimic device capable of large area alignment and high integration of an active layer.
본 발명의 일 측면은 시냅스 모방 소자를 제공한다. 상기 시냅스 모방 소자는 게이트 전극, 활성층, 상기 게이트 전극 및 활성층 사이에 배치되고, 절연성 고분자 및 이온성 물질을 포함하는 이온젤 게이트 절연층, 및 상기 활성층과 전기적으로 접속하는 소스 전극 및 드레인 전극을 포함하고, 상기 게이트 전극 또는 활성층은 기판에 지지된다.One aspect of the invention provides a synaptic mimic device. The synaptic mimic device includes a gate electrode, an active layer, an ion gel gate insulating layer disposed between the gate electrode and the active layer, the insulating gel and an ionic material, and a source electrode and a drain electrode electrically connected to the active layer. The gate electrode or active layer is supported on the substrate.
상기 시냅스 모방 소자는 탑-게이트/바텀-컨텍, 탑-게이트/탑-컨텍, 바텀-게이트/바텀-컨텍, 또는 바텀-게이트/탑-컨텍 구조이 수 있다.The synaptic mimic device may have a top-gate / bottom-contact, top-gate / top-contact, bottom-gate / bottom-contact, or bottom-gate / top-contact structure.
상기 활성층은 1차원 나노 반도체 소재이 수 있고, 상기 1차원 나노 반도체 소재는 나노 와이어, 나노리본, 나노튜브, 나노로드, 및 나노필름으로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있다. 또한, 상기 활성층은 저분자 유기 반도체, 유기반도체, 전도성 고분자, 무기 반도체, 산화물 반도체, 이차원 반도체, 및 양자점으로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있고, 상기 활성층은 TIPS 펜타센(6,13-bis(triisopropylsilylethynyl) pentacene), TES ADT(Triethylsilylethynyl anthradithiophene), PCBM([6,6]-Phenyl C61 butyric acid methyl ester), P3HT(Poly(3-hexylthiophene)), PEDOT(Poly(3,4-ethylenedioxythiophene)), PVK(Poly(9-vinylcarbazole)), 폴리(p-페닐렌 비닐렌)(poly(p-phenylene vinylene)), 폴리플루오렌(polyfluorene), 폴리아닐린(polyaniline), 폴리피롤(polypyrrole), 실리콘, 게르마늄, 갈륨아세나이드, 카본 나노튜브 (CNT), 환원된 산화 그래핀, 그래핀, 그래핀 양자점, 흑연, 산화아연, 산화주석, 산화인듐, 산화아연주석 (ZTO), 산화인듐아연(IZO), 산화인듐아연갈륨(IGZO), 황화몰리브덴 (MoS2), 황화텅스텐(WS2), 몰리브데넘셀레나이드(MoSe2), 텅스텐셀레나이드(WSe2), 질화붕소(h-BN), 불화 그래핀(fluoro-graphene), 카드뮴 셀레나이드, 카드뮴 텔룰라이드, 및 황화카드뮴으로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있다.The active layer may be a one-dimensional nano-semiconductor material, and the one-dimensional nano-semiconductor material may include at least one selected from the group consisting of nanowires, nanoribbons, nanotubes, nanorods, and nanofilms. In addition, the active layer may include at least one selected from the group consisting of a low molecular organic semiconductor, an organic semiconductor, a conductive polymer, an inorganic semiconductor, an oxide semiconductor, a two-dimensional semiconductor, and a quantum dot, and the active layer includes TIPS pentacene (6, 13). -bis (triisopropylsilylethynyl) pentacene), Triethylsilylethynyl anthradithiophene (TES ADT), PCBM ([6,6] -Phenyl C61 butyric acid methyl ester), P3HT (Poly (3-hexylthiophene)), PEDOT (Poly (3,4-ethylenedioxythiophene) )), Poly (9-vinylcarbazole) (PVK), poly (p-phenylene vinylene), polyfluorene, polyaniline, polypyrrole, silicone , Germanium, gallium arsenide, carbon nanotubes (CNT), reduced graphene oxide, graphene, graphene quantum dots, graphite, zinc oxide, tin oxide, indium oxide, zinc tin oxide (ZTO), indium zinc oxide (IZO ), Indium zinc gallium oxide (IGZO), molybdenum sulfide (MoS2), tungsten sulfide ( WS2), molybdenum selenide (MoSe2), tungsten selenide (WSe2), boron nitride (h-BN), fluoro-graphene, cadmium selenide, cadmium telluride, and cadmium sulfide It may include at least one selected from.
상기 절연성 고분자는 절연성을 갖는 단일 고분자, 블록 공중합체, 고분자-단분자 혼합물, 및 가교성 고분자로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있고, 상기 절연성 고분자는 재료는 폴리(9-비닐카바졸), 폴리(p-페닐렌비닐렌), 폴리플루오렌, 폴리아닐린, 폴리피롤, 폴리에틸렌옥사이드, 폴리스티렌, 폴리카프로락톤, 폴리아크릴로니트릴, 폴리(메틸메타크릴레이트), 폴리이미드, 폴리(비닐리덴 플로라이드), 및 폴리비닐클로라이드폴리(스티렌-에틸렌옥사이드-스티렌) (PS-PEO-PS)d로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있다.The insulating polymer may include at least one selected from the group consisting of an insulating single polymer, a block copolymer, a polymer-monomeric mixture, and a crosslinkable polymer, and the insulating polymer may be made of poly (9-vinylcarba). Sol), poly (p-phenylenevinylene), polyfluorene, polyaniline, polypyrrole, polyethylene oxide, polystyrene, polycaprolactone, polyacrylonitrile, poly (methyl methacrylate), polyimide, poly (vinylidene) Fluoride), and at least one selected from the group consisting of polyvinylchloride poly (styrene-ethylene oxide-styrene) (PS-PEO-PS) d.
상기 이온성 물질은 리튬-비스(트리플루오로메틸설포닐)이미드 (LiTFSI), 리튬폴리(스티렌 설포네이트) (LiPSS), 1-에틸-3-메틸이미다졸리움 비스(트리플루오로메틸설포닐)이미드 ([EMIM][TFSI]), 1-부틸-3-메틸이미다졸리움 헥사플루오로포스페이트 ([BMIM][PF6]), 및 1-에틸-3-메틸이미다졸리움 n-옥틸설페이트 ([EMIM][OctOSO3])로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있다.The ionic material is lithium-bis (trifluoromethylsulfonyl) imide (LiTFSI), lithium poly (styrene sulfonate) (LiPSS), 1-ethyl-3-methylimidazolium bis (trifluoromethylsul Ponyl) imide ([EMIM] [TFSI]), 1-butyl-3-methylimidazolium hexafluorophosphate ([BMIM] [PF 6 ]), and 1-ethyl-3-methylimidazolium n- Octylsulfate ([EMIM] [OctOSO 3 ]) may comprise at least one selected from the group consisting of.
본 발명의 다른 측면은 시냅스 모방 소자의 제조방법을 제공한다. 상기 제조방법은 기판 상에 활성층을 형성하는 단계, 상기 활성층 상의 일단 및 타단에 각각 상기 활성층과 전기적으로 접속하는 소스 전극 및 드레인 전극을 형성하는 단계;Another aspect of the present invention provides a method of manufacturing a synaptic mimic device. The manufacturing method includes forming an active layer on a substrate, and forming source and drain electrodes electrically connected to the active layer at one end and the other end of the active layer, respectively;
상기 활성층 상에 절연성 고분자 및 이온성 물질을 포함하는 이온젤 게이트 절연층을 형성하는 단계, 및 상기 이온젤 게이트 절연층 상에 게이트 전극을 형성하는 단계를 포함한다. Forming an ion gel gate insulating layer including an insulating polymer and an ionic material on the active layer, and forming a gate electrode on the ion gel gate insulating layer.
상기 활성층은 나노 와이어 패턴, 나노리본 패턴, 나노튜브 패턴, 또는 나노로드 패턴이 수 있고, 상기 활성층을 형성하는 단계는 전기장 잉크젯 프린팅 공정을 사용할 수 있다. 또한, 상기 이온젤 게이트 절연층을 형성하는 단계는 드롭 캐스팅 방법을 사용할 수 있다.The active layer may be a nanowire pattern, a nanoribbon pattern, a nanotube pattern, or a nanorod pattern, and the forming of the active layer may use an electric field inkjet printing process. In addition, the forming of the ion gel gate insulating layer may use a drop casting method.
본 발명의 시냅스 모방 소자 및 이의 제조방법을 따르면 신호 전달과 자가학습을 동시에 수행할 수 있고 신규한 시냅스 모방 소자를 제공할 수 있다.According to the synaptic mimic device of the present invention and a method of manufacturing the same, it is possible to perform signal transmission and self-learning at the same time, and provide a novel synaptic mimic device.
또한, 본 발명의 시냅스 모방 소자의 제조방법을 따르면 대면적 정렬 및 고집적할 수 있는 효과가 있다.In addition, according to the manufacturing method of the synaptic mimic device of the present invention has the effect of large-area alignment and high integration.
도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 다양한 시냅스 모방 소자의 단면도들이다.1A-1D are cross-sectional views of various synaptic mimic devices in accordance with one embodiment of the present invention.
도 2은 본 발명의 일 실시예에 따른 시냅스 모방 소자의 제조방법의 공정흐름도이다.2 is a process flowchart of a method of manufacturing a synaptic mimic device according to an embodiment of the present invention.
도 3는 본 발명의 제조예 1의 산화아연 나노와이어의 SEM 이미지이다.3 is an SEM image of the zinc oxide nanowires of Preparation Example 1 of the present invention.
도 4은 본 발명의 제조예 1의 전류-전압 특성을 나타낸 그래프이다.4 is a graph showing the current-voltage characteristics of Preparation Example 1 of the present invention.
도 5는 본 발명의 제조예 2의 P3HT 나노와이어의 SEM 이미지이다.5 is an SEM image of P3HT nanowires of Preparation Example 2 of the present invention.
도 6는 본 발명의 제조예 2의 전류-전압 특성을 나타낸 그래프이다.6 is a graph showing the current-voltage characteristics of Preparation Example 2 of the present invention.
도 7은 본 발명의 제조예 3의 그래핀 나노리본의 SEM 이미지이다.7 is an SEM image of the graphene nanoribbons of Preparation Example 3 of the present invention.
도 8은 본 발명의 제조예 3의 전류-전압 특성을 나타낸 그래프이다.8 is a graph showing the current-voltage characteristics of Preparation Example 3 of the present invention.
이하, 첨부한 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명한다. 그러나, 본 발명은 여기서 설명되는 실시예들에 한정되지 않고 다른 형태로 구체화될 수 있으며, 본 발명의 사상 및 기술 범위에 포함되는 모든 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms and should be understood to include all equivalents and substitutes included in the spirit and scope of the present invention.
또한, 본 명세서에서 층이 다른 층 또는 기판 "상"에 있다고 언급되는 경우에 그것은 다른 층 또는 기판 상에 직접 형성될 수 있거나, 그들 사이에 제3의 층이 개재될 수도 있다. 또한, 본 명세서에서 위쪽, 상(부), 상면 등의 방향적인 표현은 그 기준에 따라 아래쪽, 하(부), 하면 등의 의미로 이해될 수 있다. 즉, 공간적인 방향의 표현은 상대적인 방향으로 이해되어야 하며 절대적인 방향을 의미하는 것으로 한정 해석되어서는 안된다.In addition, where a layer is referred to herein as "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. In addition, in the present specification, the directional expression of the upper part, the upper part, and the upper part may be understood as meanings of the lower part, the lower part, the lower part, and the like according to the criteria. That is, the expression of the spatial direction should be understood as a relative direction and should not be construed as limiting the absolute direction.
도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장 또는 축소된 것일 수 있다. 명세서 전체에 걸쳐서 동일한 참조번호들은 동일한 구성 요소들을 나타낸다.In the drawings, the thicknesses of layers and regions may be exaggerated or reduced for clarity. Like numbers refer to like elements throughout.
또한, 하기에서 본 발명을 설명함에 있어 관련된 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명은 생략할 것이다.In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.
시냅스 모방 소자Synaptic mimics
본 발명의 시냅스 모방 소자는 게이트 전극, 활성층, 상기 게이트 전극 및 활성층 사이에 배치되고, 절연성 고분자 및 이온성 물질을 포함하는 이온젤 게이트 절연층, 및 상기 활성층과 전기적으로 접속하는 소스 전극 및 드레인 전극을 포함하고, 상기 게이트 전극 또는 활성층은 기판에 지지된다.The synaptic mimic device of the present invention is disposed between a gate electrode, an active layer, the gate electrode and the active layer, an ion gel gate insulating layer containing an insulating polymer and an ionic material, and a source electrode and a drain electrode electrically connected to the active layer. The gate electrode or the active layer is supported on a substrate.
전술된 게이트 전극은 알루미늄, 구리, 니켈, 철, 크롬, 티타늄, 아연, 납, 금, 및 은으로 이루어진 군으로부터 선택되는 적어도 하나의 금속 재료를 사용할 수 있고, 폴리(3,4-에틸렌디옥시싸이오펜):폴리스티렌 설포네이트 (PEDOT:PSS)와 같은 전도성 고분자 재료, 또는 도핑된 고분자 재료를 사용할 수 있으나 이에 한정되지 않는다. 또한, 전술된 게이트 전극은 금속 프루브를 사용할 수 있다. The gate electrode described above may use at least one metal material selected from the group consisting of aluminum, copper, nickel, iron, chromium, titanium, zinc, lead, gold, and silver, and may be poly (3,4-ethylenedioxy Thiophene): conductive polymer material such as polystyrene sulfonate (PEDOT: PSS), or doped polymer material may be used, but is not limited thereto. In addition, the gate electrode described above may use a metal probe.
또한, 전술된 게이트 전극의 두께는 0.5nm 내지 50mm일 수 있고, 더욱 상세하게는 1nm 내지 1mm일 수 있다.In addition, the thickness of the above-described gate electrode may be 0.5nm to 50mm, more specifically 1nm to 1mm.
전술된 활성층은 1차원 나노 반도체 소재일 수 있다. 전술된 1차원 나노 반도체 소재는 나노 와이어 패턴, 나노리본 패턴, 나노튜브 패턴, 나노로드 패턴, 및 나노필름으로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있다. 이 경우, 소자의 대면적화 및 고집적화가 가능한 효과가 있다. The active layer described above may be a one-dimensional nano-semiconductor material. The one-dimensional nano-semiconductor material described above may include at least one selected from the group consisting of nanowire patterns, nanoribbon patterns, nanotube patterns, nanorod patterns, and nanofilms. In this case, the large area and high integration of the device can be achieved.
또한, 전술된 활성층은 저분자 유기 반도체, 유기반도체, 전도성 고분자, 무기 반도체, 산화물 반도체, 이차원 반도체, 및 양자점으로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있다.In addition, the active layer described above may include at least one selected from the group consisting of a low molecular organic semiconductor, an organic semiconductor, a conductive polymer, an inorganic semiconductor, an oxide semiconductor, a two-dimensional semiconductor, and a quantum dot.
전술된 저분자 유기 반도체는 TIPS 펜타센(6,13-bis(triisopropylsilylethynyl) pentacene), TES ADT(Triethylsilylethynyl anthradithiophene) 및 PCBM([6,6]-Phenyl C61 butyric acid methyl ester)로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있고, 전술된 유기반도체 또는 전도성 고분자는 P3HT(Poly(3-hexylthiophene)), PEDOT(Poly(3,4-ethylenedioxythiophene)), PVK(Poly(9-vinylcarbazole)), 폴리(p-페닐렌 비닐렌)(poly(p-phenylene vinylene)), 폴리플루오렌(polyfluorene), 폴리아닐린(polyaniline), 및 폴리피롤(polypyrrole)로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있으며, 전술된 무기 반도체는 실리콘, 게르마늄, 갈륨아세나이드, 카본 나노튜브 (CNT), 환원된 산화 그래핀, 그래핀, 그래핀 양자점, 및 흑연으로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있고, 전술된 산화물 반도체는 산화아연, 산화주석, 산화인듐, 산화아연주석 (ZTO), 산화인듐아연(IZO), 및 산화인듐아연갈륨(IGZO)으로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있으며, 전술된 이차원 반도체 재료는 황화몰리브덴 (MoS2), 황화텅스텐(WS2), 몰리브데넘셀레나이드(MoSe2), 텅스텐셀레나이드(WSe2), 질화붕소(h-BN), 및 불화 그래핀(fluoro-graphene)으로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있고, 전술된 양자점은 카드뮴 셀레나이드, 카드뮴 텔룰라이드, 및 황화카드뮴으로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있다.The low molecular organic semiconductor described above is at least selected from the group consisting of TIPS pentacene (6,13-bis (triisopropylsilylethynyl) pentacene), TES ADT (Triethylsilylethynyl anthradithiophene) and PCBM ([6,6] -Phenyl C61 butyric acid methyl ester) The organic semiconductor or conductive polymer described above may include one of P3HT (Poly (3-hexylthiophene)), PEDOT (Poly (3,4-ethylenedioxythiophene)), PVK (Poly (9-vinylcarbazole)), and poly (p -Phenylene vinylene) (poly (p-phenylene vinylene)), polyfluorene (polyfluorene) (polyfluorene) (polyaniline), and may include at least one selected from the group consisting of polypyrrole (polypyrrole), the inorganic The semiconductor may comprise at least one selected from the group consisting of silicon, germanium, gallium arsenide, carbon nanotubes (CNT), reduced graphene oxide, graphene, graphene quantum dots, and graphite, the oxide semiconductors described above Zinc oxide , Tin oxide, indium oxide, zinc tin oxide (ZTO), indium zinc oxide (IZO), and indium zinc gallium oxide (IGZO), and the two-dimensional semiconductor material described above may be sulfided. Molybdenum (MoS2), tungsten sulfide (WS2), molybdenum selenide (MoSe2), tungsten selenide (WSe2), boron nitride (h-BN), and fluoro-graphene It may comprise at least one, and the above-described quantum dots may include at least one selected from the group consisting of cadmium selenide, cadmium telluride, and cadmium sulfide.
이온젤 게이트 절연층은 절연성 고분자 및 이온성 물질을 포함한다.The ion gel gate insulating layer includes an insulating polymer and an ionic material.
전술된 이온젤 게이트 절연층은 이온성 물질을 포함함에 따라 시냅스 특성을 갖는다. 전기 시냅스 자극 스파이크(spike)는 활성층을 향해 이온을 이동시키고, 후기 시냅스 반응 전류(excitatory post-synaptic current, 드레인 전류)가 발생한다. 이에, 활성층으로 이동한 이온은 전하를 끌어당기고 축적한다. 이 후, 전술된 시냅스 자극 스파이크가 끝나면, 전술된 후기 시냅스 반응 전류가 서서히 감소함과 동시에, 전술된 이온들은 점차적으로 전술된 이온젤 게이트 절연층의 이온젤의 평형수준으로 되돌아 오며 시냅스 특성을 나타낸다.The ion gel gate insulating layer described above has synaptic properties as it includes an ionic material. Electrical synaptic stimulation spikes move ions toward the active layer and produce excitatory post-synaptic currents (drain currents). As a result, the ions moved to the active layer attract and accumulate electric charges. Thereafter, when the above-described synaptic stimulus spike ends, the above-described late synaptic reaction current gradually decreases, and at the same time, the above-mentioned ions gradually return to the equilibrium level of the ion gel of the above-described ion gel gate insulating layer and exhibit synaptic characteristics. .
전술된 절연성 고분자는 연성을 갖는 단일 고분자 재료, 블록 공중합체, 고분자-단분자 혼합물, 및 가교성 고분자로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있다.The insulating polymer described above may include at least one selected from the group consisting of a flexible single polymer material, a block copolymer, a polymer-monomeric mixture, and a crosslinkable polymer.
전술된 단일 고분자 재료는 폴리(9-비닐카바졸), 폴리(p-페닐렌비닐렌), 폴리플루오렌, 폴리아닐린, 폴리피롤, 폴리에틸렌옥사이드, 폴리스티렌, 폴리카프로락톤, 폴리아크릴로니트릴, 폴리(메틸메타크릴레이트), 폴리이미드, 폴리(비닐리덴 플로라이드), 및 폴리비닐클로라이드로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있고, 전술된 블록 공중합체는 폴리(스티렌-에틸렌옥사이드-스티렌) (PS-PEO-PS)일 수 있으며, 고분자-단분자 혼합물 또는 가교성 고분자일 수 있다.The single polymer materials described above are poly (9-vinylcarbazole), poly (p-phenylenevinylene), polyfluorene, polyaniline, polypyrrole, polyethylene oxide, polystyrene, polycaprolactone, polyacrylonitrile, poly (methyl Methacrylate), polyimide, poly (vinylidene fluoride), and polyvinylchloride; and at least one selected from the group consisting of poly (styrene-ethyleneoxide-styrene) ( PS-PEO-PS), and may be a polymer-monomeric mixture or a crosslinkable polymer.
전술된 이온성 물질은 리튬-비스(트리플루오로메틸설포닐)이미드 (LiTFSI), 리튬폴리(스티렌 설포네이트) (LiPSS), 1-에틸-3-메틸이미다졸리움 비스(트리플루오로메틸설포닐)이미드 ([EMIM][TFSI]), 1-부틸-3-메틸이미다졸리움 헥사플루오로포스페이트 ([BMIM][PF6]), 및 1-에틸-3-메틸이미다졸리움 n-옥틸설페이트 ([EMIM][OctOSO3])로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있다.The aforementioned ionic materials include lithium-bis (trifluoromethylsulfonyl) imide (LiTFSI), lithium poly (styrene sulfonate) (LiPSS), 1-ethyl-3-methylimidazolium bis (trifluoromethyl Sulfonyl) imide ([EMIM] [TFSI]), 1-butyl-3-methylimidazolium hexafluorophosphate ([BMIM] [PF 6 ]), and 1-ethyl-3-methylimidazolium n -Octyl sulfate ([EMIM] [OctOSO 3 ]) and at least one selected from the group consisting of.
전술된 소스 전극 및 드레인 전극은 알루미늄, 구리, 니켈, 철, 크롬, 티타늄, 아연, 납, 금, 및 은을 이루어진 군으로부터 선택되는 적어도 하나의 금속 재료를 포함할 수 있고, 폴리(3,4-에틸렌디옥시싸이오펜):폴리스티렌 설포네이트 (PEDOT:PSS)와 같은 전도성 고분자 재료를 포함할 수 있으며, 도핑된 고분자 재료를 포함할 수 있다.The aforementioned source electrode and drain electrode may comprise at least one metal material selected from the group consisting of aluminum, copper, nickel, iron, chromium, titanium, zinc, lead, gold, and silver, and poly (3,4) -Ethylenedioxythiophene): conductive polymer material such as polystyrene sulfonate (PEDOT: PSS), and may comprise a doped polymer material.
전술된 소스 전극 및 드레인 전극의 두께는 0.5nm 내지 50mm일 수 있고, 더욱 상세하게는 1nm 내지 1mm일 수 있다.The thickness of the above-described source electrode and drain electrode may be 0.5nm to 50mm, more specifically 1nm to 1mm.
전술된 기판(10)은 절연재료, 금속재료, 탄소재료, 반도체, 및 전도체와 절연막의 복합재료로 이루어진 군으로부터 선택되는 적어도 하나를 포함할 수 있으나, 이에 제한되지 않는다.The substrate 10 described above may include at least one selected from the group consisting of an insulating material, a metal material, a carbon material, a semiconductor, and a composite material of a conductor and an insulating film, but is not limited thereto.
전술된 시냅스 모방 소자는 탑-게이트/바텀-컨텍, 탑-게이트/탑-컨텍, 바텀-게이트/바텀-컨텍, 또는 바텀-게이트/탑-컨텍 구조일 수 있다.The aforementioned synaptic mimic device may be a top-gate / bottom-contact, top-gate / top-contact, bottom-gate / bottom-contact, or bottom-gate / top-contact structure.
도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 다양한 시냅스 모방 소자의 단면도들이다.1A-1D are cross-sectional views of various synaptic mimic devices in accordance with one embodiment of the present invention.
도 1a는 본 발명의 일 실시예에 따른 탑-게이트/바텀-컨텍 구조를 갖는 시냅스 모방 소자의 단면도이다.1A is a cross-sectional view of a synaptic mimic device having a top-gate / bottom-contact structure according to an embodiment of the present invention.
도 1a를 참조하면, 본 발명의 일 실시예에 따른 탑-게이트/바텀-컨텍 구조를 갖는 시냅스 모방 소자는 기판(10) 상의 일단 및 타단에 각각 배치된 소스 전극(30a) 및 드레인 전극(30b), 전술된 소스 전극(30a) 및 드레인 전극(30b) 상에 배치된 활성층(20), 전술된 활성층(20) 상에 배치된 이온젤 게이트 절연층(40), 및 전술된 이온젤 게이트 절연층(40) 상에 배치된 게이트 전극(50)을 포함할 수 있다.Referring to FIG. 1A, a synaptic mimic device having a top-gate / bottom-contact structure according to an embodiment of the present invention may have a source electrode 30a and a drain electrode 30b disposed at one end and the other end of a substrate 10, respectively. ), The active layer 20 disposed on the source electrode 30a and the drain electrode 30b described above, the ion gel gate insulating layer 40 disposed on the active layer 20 described above, and the aforementioned ion gel gate insulation The gate electrode 50 may be disposed on the layer 40.
도 1b는 본 발명의 일 실시예에 따른 탑-게이트/탑-컨텍 구조를 갖는 시냅스 모방 소자의 단면도이다.1B is a cross-sectional view of a synaptic mimic device having a top-gate / top-contact structure according to an embodiment of the present invention.
도 1b를 참조하면, 본 발명의 일 실시예에 따른 탑-게이트/탑-컨텍 구조를 갖는 시냅스 모방 소자는 기판(10) 상에 배치된 활성층(20), 전술된 활성층(20) 상의 일단 및 타단에 각각 배치된 소스 전극(30a) 및 드레인 전극(30b), 전술된 활성층(20) 상에 배치되는 이온젤 게이트 절연층(40), 전술된 이온젤 게이트 절연층(40) 상에 배치된 게이트 전극(50)을 포함할 수 있다.1B, a synaptic mimic device having a top-gate / top-contact structure according to an embodiment of the present invention may include an active layer 20 disposed on a substrate 10, one end of the active layer 20 described above, and The source electrode 30a and the drain electrode 30b disposed at the other end, the ion gel gate insulating layer 40 disposed on the active layer 20 described above, and the ion gel gate insulating layer 40 described above. The gate electrode 50 may be included.
도 1c는 본 발명의 일 실시예에 따른 바텀-게이트/바텀-컨텍 구조를 갖는 시냅스 모방 소자의 단면도이다.1C is a cross-sectional view of a synaptic mimic device having a bottom-gate / bottom-contact structure according to an embodiment of the present invention.
도 1c를 참조하면, 본 발명의 일 실시예에 따른 바텀-게이트/바텀-컨텍 구조를 갖는 시냅스 모방 소자는 기판(10) 상에 배치된 게이트 전극(50), 전술된 게이트 전극(50) 상에 배치된 이온젤 게이트 절연층(40), 전술된 이온젤 게이트 절연층(40) 상의 일단 및 타단에 각각 배치된 소스 전극(30a) 및 드레인 전극(30b), 전술된 소스 전극(30a) 및 드레인 전극(30b) 상에 배치된 활성층(20)을 포함할 수 있다.Referring to FIG. 1C, a synaptic mimic device having a bottom-gate / bottom-contact structure according to an embodiment of the present invention may be disposed on a gate electrode 50 disposed on a substrate 10, and the gate electrode 50 described above. The ion gel gate insulating layer 40 disposed on the first side, the source electrode 30a and the drain electrode 30b disposed on one end and the other end of the ion gel gate insulating layer 40 described above, the source electrode 30a described above, and The active layer 20 may be disposed on the drain electrode 30b.
도 1d는 본 발명의 일 실시예에 따른 바텀-게이트/탑-컨텍 구조를 갖는 시냅스 모방 소자의 단면도이다.1D is a cross-sectional view of a synaptic mimic device having a bottom-gate / top-contact structure according to an embodiment of the present invention.
도 1d를 참조하면, 본 발명의 일 실시예에 따른 바텀-게이트/탑-컨텍 구조를 갖는 시냅스 모방 소자는 기판(10) 상에 배치된 게이트 전극(50), 전술된 게이트 전극(50) 상에 배치된 이온젤 게이트 절연층(40), 전술된 이온젤 게이트 절연층(40) 상에 배치된 활성층(20), 전술된 활성층 (20)상의 일단 및 타단에 각각 배치된 소스 전극(30a) 및 드레인 전극(30b)을 포함할 수 있다.Referring to FIG. 1D, a synaptic mimic device having a bottom-gate / top-contact structure according to an embodiment of the present invention may be disposed on a gate electrode 50 disposed on a substrate 10, and the gate electrode 50 described above. The ion gel gate insulating layer 40 disposed on the active layer 20 disposed on the ion gel gate insulating layer 40 described above, the source electrode 30a disposed on one end and the other end of the active layer 20 described above, respectively. And a drain electrode 30b.
시냅스 모방 소자의 제조방법Manufacturing method of synaptic mimic device
도 2은 본 발명의 일 실시예에 따른 시냅스 모방 소자의 제조방법의 공정흐름도이다.2 is a process flowchart of a method of manufacturing a synaptic mimic device according to an embodiment of the present invention.
본 발명의 일 실시예에 따른 시냅스 모방 소자는 먼저, 기판(10) 상에 활성층(20)을 형성한다(S100).The synaptic mimic device according to an embodiment of the present invention first forms the active layer 20 on the substrate 10 (S100).
전술된 기판(10) 또는 활성층(20) 형성을 위해 사용되는 물질은 전술된 '시냅스 모방 소자'의 설명을 참고하기로 한다. The material used to form the substrate 10 or the active layer 20 described above will be referred to the description of the 'synaptic mimic device' described above.
또한, 전술된 기판(10) 상에 전술된 활성층(20)을 형성하기 위한 증착 공정으로는 물리적 기상 증착(physical vapor deposition; PVD), 화학적 기상 증착(chemical vapor deposition; CVD), 스퍼터링(sputtering), 펄스 레이저 증착(pulsed laser deposition; PLD), 증발법(thermal evaporation), 전자빔 증발법(electron beam evaporation), 원자층 증착(atomic layer deposition; ALD) 및 분자선 에피택시 증착(molecular beam epitaxy; MBE) 등을 이용할 수 있다.In addition, a deposition process for forming the above-described active layer 20 on the substrate 10 described above may include physical vapor deposition (PVD), chemical vapor deposition (CVD), and sputtering. Pulsed laser deposition (PLD), thermal evaporation, electron beam evaporation, atomic layer deposition (ALD) and molecular beam epitaxy (MBE) Etc. can be used.
또한, 전술된 활성층(20)은 전기장 잉크젯 프린팅 공정을 사용하여 형성될 수 있다. 이 경우, 전술된 활성층(20)은 나노 와이어 패턴, 나노리본 패턴, 나노튜브 패턴, 또는 나노로드 패턴으로 형성될 수 있어, 소자의 대면적 고집적화가 가능한 장점이 있다. 전기장 잉크젯 프린팅의 일 예로, 전기장 보조 로보틱 노즐 프린터를 사용할 수 있으나 이에 한정되지 않는다. In addition, the active layer 20 described above may be formed using an electric field inkjet printing process. In this case, the above-described active layer 20 may be formed of a nanowire pattern, a nanoribbon pattern, a nanotube pattern, or a nanorod pattern, so that a large area of the device may be highly integrated. As an example of electric field inkjet printing, an electric field assisted robotic nozzle printer may be used, but is not limited thereto.
이 후, 전술된 활성층(20) 상의 일단 및 타단에 각각 전술된 활성층과 전기적으로 접속하는 소스 전극(30a) 및 드레인 전극(30b)을 형성한다(S200).Thereafter, source and drain electrodes 30a and 30b which are electrically connected to the active layer described above are formed at one end and the other end of the above-described active layer 20, respectively (S200).
전술된 소스 전극(30a) 및 드레인 전극(30b) 형성을 위해 사용되는 물질은 전술된 '시냅스 모방 소자'의 설명을 참고하기로 한다.The material used to form the source electrode 30a and the drain electrode 30b described above will be referred to the description of the 'synaptic mimic device' described above.
전술된 소스 소스 전극(30a) 및 드레인 전극(30b)을 형성하기 위한 증착 공정으로는 물리적 기상 증착(physical vapor deposition; PVD), 화학적 기상 증착(chemical vapor deposition; CVD), 스퍼터링(sputtering), 펄스 레이저 증착(pulsed laser deposition; PLD), 증발법(thermal evaporation), 전자빔 증발법(electron beam evaporation), 원자층 증착(atomic layer deposition; ALD) 및 분자선 에피택시 증착(molecular beam epitaxy; MBE) 등을 이용할 수 있다. 그리고, 전술된 소스 전극(30a) 및 드레인 전극(30b)이 전술된 활성층(20)의 일단 및 타단에 각각 형성되도록 쉐도우 마스크 또는 드라이 에칭 공정을 통해 패터닝될 수 있다.Deposition processes for forming the source source electrode 30a and the drain electrode 30b described above include physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, pulse Pulsed laser deposition (PLD), thermal evaporation, electron beam evaporation, atomic layer deposition (ALD) and molecular beam epitaxy (MBE) It is available. In addition, the source electrode 30a and the drain electrode 30b described above may be patterned through a shadow mask or a dry etching process so as to be formed at one end and the other end of the active layer 20 described above, respectively.
이 후, 전술된 활성층(20) 상에 절연성 고분자 및 이온성 물질을 포함하는 이온젤 게이트 절연층(40)을 형성한다(S300).Thereafter, the ion gel gate insulating layer 40 including the insulating polymer and the ionic material is formed on the active layer 20 described above (S300).
전술된 이온젤 게이트 절연층(40)은 이온성 물질을 포함함에 따라 시냅스 특성을 갖는다. 전기 시냅스 자극 스파이크(spike)는 활성층(20)을 향해 이온을 이동시키고, 후기 시냅스 반응 전류(excitatory post-synaptic current, 드레인 전류)가 발생한다. 이에, 활성층(20)으로 이동한 이온은 전하를 끌어당기고 축적한다. 이 후, 전술된 시냅스 자극 스파이크가 끝나면, 전술된 후기 시냅스 반응 전류가 서서히 감소함과 동시에, 전술된 이온들은 점차적으로 전술된 이온젤 게이트 절연층(40)의 이온젤의 평형수준으로 되돌아 오며 시냅스 특성을 나타낸다.The ion gel gate insulating layer 40 described above has synaptic properties as it includes an ionic material. The electrical synaptic stimulus spikes move ions toward the active layer 20 and generate an excitatory post-synaptic current (drain current). As a result, the ions moved to the active layer 20 attract and accumulate charge. Thereafter, when the above-described synaptic stimulus spike ends, the aforementioned late synaptic reaction current gradually decreases, and at the same time, the above-mentioned ions gradually return to the equilibrium level of the ion gel of the above-described ion gel gate insulating layer 40 and the synapse Characteristics.
이 때, 전술된 이온젤 게이트 절연층(40)은 전술된 소스 전극(30a) 및 드레인 전극(30b)과 전기적으로 접속될 수 있게 형성되는 것이 바람직하다.In this case, the ion gel gate insulating layer 40 described above is preferably formed to be electrically connected to the source electrode 30a and the drain electrode 30b.
이온젤 게이트 절연층을 형성시, 드롭 캐스팅(drop casting) 방법을 사용하는 것이 바람직하다. 드롭 캐스팅 방법을 사용할 경우, 젤(gel) 형태인 이온젤 게이트 절연층(40)의 표면 굴곡을 가장 적게 형성시켜 소자의 성능을 향상시키는 효과가 있다.In forming the ion gel gate insulating layer, it is preferable to use a drop casting method. In the case of using the drop casting method, the surface curvature of the ion gel gate insulating layer 40 in the form of a gel is least formed, thereby improving the performance of the device.
마지막으로, 전술된 이온젤 게이트 절연층(40) 상에 게이트 전극(50)을 형성한다(S400).Finally, the gate electrode 50 is formed on the ion gel gate insulating layer 40 described above (S400).
전술된 게이트 전극(50) 형성을 위해 사용되는 물질은 전술된 '시냅스 모방 소자'의 설명을 참고하기로 한다.The material used to form the above-described gate electrode 50 will be referred to the description of the 'synaptic mimic device' described above.
전술된 게이트 전극(50)을 형성하기 위한 증착 공정으로는 물리적 기상 증착(physical vapor deposition; PVD), 화학적 기상 증착(chemical vapor deposition; CVD), 스퍼터링(sputtering), 펄스 레이저 증착(pulsed laser deposition; PLD), 증발법(thermal evaporation), 전자빔 증발법(electron beam evaporation), 원자층 증착(atomic layer deposition; ALD) 및 분자선 에피택시 증착(molecular beam epitaxy; MBE) 등을 이용할 수 있다.Deposition processes for forming the above-described gate electrode 50 include physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, pulsed laser deposition; PLD), thermal evaporation, electron beam evaporation, atomic layer deposition (ALD), molecular beam epitaxy (MBE), and the like.
이하, 본 발명의 이해를 돕기 위하여 바람직한 실험예(example)를 제시한다. 다만, 하기의 실험예는 본 발명의 이해를 돕기 위한 것일 뿐, 본 발명이 하기의 실험예에 의해 한정되는 것은 아니다.Hereinafter, preferred examples are provided to aid the understanding of the present invention. However, the following experimental examples are only for helping understanding of the present invention, and the present invention is not limited to the following experimental examples.
<제조예 1><Manufacture example 1>
먼저, 아세트산 아연 이수화물(Zn(CH3(COO)2·2H2O)) (80 wt%)과 폴리비닐 알코올(PVA) (20 wt%)을 증류수에 용해시켜 산화아연 전구체/PVA 용액을 제조하였다. 상기 산화아연 전구체/PVA 용액의 농도는 10 wt%이었다. 제조된 산화아연 전구체/PVA 용액을 전기장 보조 로보틱 노즐 프린터의 시린지에 담고, 노즐에 약 2.0 kV의 전압을 인가 하면서, 산화아연 전구체/PVA 용액을 노즐로부터 토출하였다. 로봇 스테이지에 의하여 이동되는 콜렉터의 기판 위에 정렬된 산화아연 전구체/PVA 복합체 나노와이어 패턴이 형성되었다.First, zinc acetate dihydrate (Zn (CH 3 (COO) 2 .2H 2 O)) (80 wt%) and polyvinyl alcohol (PVA) (20 wt%) were dissolved in distilled water to prepare a zinc oxide precursor / PVA solution. Prepared. The concentration of the zinc oxide precursor / PVA solution was 10 wt%. The prepared zinc oxide precursor / PVA solution was placed in a syringe of an electric field assisted robotic nozzle printer, and the zinc oxide precursor / PVA solution was discharged from the nozzle while applying a voltage of about 2.0 kV to the nozzle. A zinc oxide precursor / PVA composite nanowire pattern was formed on the collector's substrate moved by the robot stage.
이때, 사용한 노즐의 직경은 100 ㎛이고, 노즐과 콜렉터 사이의 거리를 5 mm로 일정하게 유지하였다. 로봇 스테이지의 Y축 방향의 이동 간격은 50 ㎛이고, X축 방향의 이동 거리는 15 cm이었다. 콜렉터의 크기는 20cm × 20cm이고, 실리콘 산화막 (SiO2)이 300nm 두께로 코팅된 실리콘 웨이퍼를 기판으로 사용하였다. 이때 기판의 크기는 2.5cm × 2.5cm 이었다. 정렬된 산화아연 전구체/PVA 나노와이어 패턴을 퍼니스에서 500 ℃로 각각 4 시간 동안 가열하여 정렬된 산화아연 나노와이어 패턴을 형성하였다.At this time, the diameter of the nozzle used was 100 µm, and the distance between the nozzle and the collector was kept constant at 5 mm. The moving distance in the Y-axis direction of the robot stage was 50 µm, and the moving distance in the X-axis direction was 15 cm. The collector was 20 cm × 20 cm in size, and a silicon wafer coated with a 300 nm thick silicon oxide film (SiO 2 ) was used as a substrate. At this time, the size of the substrate was 2.5cm × 2.5cm. The aligned zinc oxide precursor / PVA nanowire patterns were heated in a furnace at 500 ° C. for 4 hours to form aligned zinc oxide nanowire patterns.
형성된 산화아연 나노와이어 패턴 위에 열증착을 통해서 100nm 두께의 금을 증착하여 소스 및 드레인 전극을 형성 하였다. 이후 폴리(스티렌-산화에틸렌-스티렌) (PS-PEO-PS) (7wt%) 삼중블럭 공중합체와 1-에틸-3-메틸이미다졸륨 비스(트리플루오로메틸설포닐)아마이드 ([EMIM][TFSI]) 의 혼합물로 이루어진 이온젤 용액을 드롭 캐스팅(drop casting) 방법으로 산화아연 나노와이어 활성층 위에 도포하였다. 이후, 기판을 진공 상에서 3시간 동안 건조하여 이온젤 게이트 절연층을 형성하였다. 전술된 게이트 절연층에 금속 프로브를 게이트 전극으로 사용하여 산화아연 나노와이어 기반 시냅스 모방 소자를 제조하였다.100 nm thick gold was deposited on the formed zinc oxide nanowire pattern to form a source and a drain electrode. Then poly (styrene-ethylene oxide-styrene) (PS-PEO-PS) (7wt%) triple block copolymer and 1-ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) amide ([EMIM] An ion gel solution consisting of a mixture of [TFSI]) was applied onto the zinc oxide nanowire active layer by a drop casting method. Thereafter, the substrate was dried under vacuum for 3 hours to form an ion gel gate insulating layer. A zinc oxide nanowire-based synaptic mimic device was fabricated using a metal probe as a gate electrode in the gate insulating layer described above.
<제조예 2><Manufacture example 2>
먼저, P3HT(2.6 wt%)와 PEO(1.6 wt%)를 클로로벤젠:트리클로로에틸렌 = 2:1 중량비의 혼합 용액에 용해시켜서 P3HT 용액을 제조하였다. 제조된 P3HT 용액을 전기장 보조 로보틱 노즐 프린터의 시린지에 담고, 노즐에 약 1.5 kV의 전압을 인가 하면서, P3HT 용액을 노즐로부터 토출하였다. 로봇 스테이지에 의하여 이동되는 콜렉터의 기판 위에 정렬된 P3HT 나노와이어 패턴이 형성되었다.First, P3HT (2.6 wt%) and PEO (1.6 wt%) were dissolved in a mixed solution of chlorobenzene: trichloroethylene = 2: 1 weight ratio to prepare a P3HT solution. The prepared P3HT solution was placed in a syringe of an electric field assisted robotic nozzle printer, and the P3HT solution was discharged from the nozzle while applying a voltage of about 1.5 kV to the nozzle. An P3HT nanowire pattern was formed on the collector's substrate moved by the robot stage.
이때, 사용한 노즐의 직경은 100 ㎛이고, 노즐과 콜렉터 사이의 거리를 5.5 mm 로 일정하게 유지하였다. 로봇 스테이지의 Y축 방향의 이동 간격은 50 ㎛이고, X축 방향의 이동 거리는 15 cm이었다. 콜렉터의 크기는 20cm × 20cm이고, 실리콘 산화막 (SiO2)이 300nm 두께로 코팅된 실리콘 웨이퍼를 기판으로 사용하였다. 이때 기판의 크기는 2.5cm × 2.5cm 이었다.At this time, the diameter of the nozzle used was 100 micrometers, and the distance between a nozzle and a collector was kept constant at 5.5 mm. The moving distance in the Y-axis direction of the robot stage was 50 µm, and the moving distance in the X-axis direction was 15 cm. The collector was 20 cm × 20 cm in size, and a silicon wafer coated with a 300 nm thick silicon oxide film (SiO 2 ) was used as a substrate. At this time, the size of the substrate was 2.5cm × 2.5cm.
형성된 P3HT 나노와이어 패턴 위에 열증착을 통해서 100nm 두께의 금을 증착하여 소스 및 드레인 전극을 형성 하였다. 이후 폴리(스티렌-산화에틸렌-스티렌) (PS-PEO-PS) (7wt%) 삼중블럭 공중합체와 1-에틸-3-메틸이미다졸륨 비스(트리플루오로메틸설포닐)아마이드 ([EMIM][TFSI]) 의 혼합물로 이루어진 이온젤 용액을 드롭 캐스팅(drop casting) 방법으로 P3HT 나노와이어 활성층 위에 도포하였다. 이후, 기판을 진공 상에서 3시간 동안 건조하여 이온젤 게이트 절연층을 형성하였다. 전술된 게이트 절연층에 금속 프로브를 게이트 전극으로 사용하여 P3HT 나노와이어 기반 시냅스 모방 소자를 제조하였다.100 nm thick gold was deposited on the formed P3HT nanowire pattern to form a source and a drain electrode. Then poly (styrene-ethylene oxide-styrene) (PS-PEO-PS) (7wt%) triple block copolymer and 1-ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) amide ([EMIM] An ion gel solution consisting of a mixture of [TFSI]) was applied onto the P3HT nanowire active layer by a drop casting method. Thereafter, the substrate was dried under vacuum for 3 hours to form an ion gel gate insulating layer. The P3HT nanowire-based synaptic mimic device was manufactured by using a metal probe as the gate electrode in the above-described gate insulating layer.
<제조예 3><Manufacture example 3>
먼저, 하기에 기재된 방법에 따라 그래핀 활성층을 제조 하였다.First, the graphene active layer was prepared according to the method described below.
두께가 25 ㎛ 인 구리호일 (Cu foil, 순도 99.8 %)을 석영관 내부에 넣은 후 1000 ℃에서 가열 하였다. 이때 석영관 내부의 기압은 0.1 Torr 이었다. 그리고 16 sccm의 수소가스를 30 분 동안, 26 sccm/15 sccm 인 메탄/수소 혼합가스를 30 분 동안 흘려 주었다. 구리호일 상에 생성된 그래핀은 상온에서 냉각 되었다. 냉각된 그래핀은 폴리메틸메타크릴레이트(PMMA) /클로로벤젠 용액(4 wt%)으로 스핀코팅 처리한 후 1 시간동안 상온 건조처리 하였다. 구리호일은 1.4 wt%의 암모늄 퍼설페이트(APS) 수용액에 띄워서 제거하고, 실리콘 산화막 (SiO2) 이 300 nm 의 두께로 코팅된 실리콘 웨이퍼 위에 전사하였다. 전사된 그래핀 위에 코팅된 PMMA 는 아세톤 용액에 15분 내지 20분 동안 담궈서 제거하였다.Copper foil (Cu foil, purity 99.8%) having a thickness of 25 μm was placed in a quartz tube and heated at 1000 ° C. At this time, the pressure inside the quartz tube was 0.1 Torr. Then, 16 sccm of hydrogen gas was flowed for 30 minutes, and 26 sccm / 15 sccm of methane / hydrogen mixed gas was flowed for 30 minutes. Graphene produced on copper foil was cooled to room temperature. The cooled graphene was spin-coated with polymethyl methacrylate (PMMA) / chlorobenzene solution (4 wt%) and dried at room temperature for 1 hour. The copper foil was removed by floating in 1.4 wt% aqueous solution of ammonium persulfate (APS) and transferred onto a silicon wafer coated with a silicon oxide film (SiO 2) to a thickness of 300 nm. PMMA coated on the transferred graphene was removed by soaking in acetone solution for 15-20 minutes.
이어서, 하기에 기재된 방법에 따라 폴리비닐카바졸(PVK) 나노와이어 패턴을 상기 그래핀 활성층 상에 프린팅 하였다.Subsequently, a polyvinylcarbazole (PVK) nanowire pattern was printed on the graphene active layer according to the method described below.
먼저, PVK 를 스티렌에 용해시켜 PVK/스티렌 용액 (3.77 wt%) 을 제조 하였다. 제조된 PVK/스티렌 용액을 전기장 보조 로보틱 노즐 프린터의 시린지에 담고, 노즐에 약 3.6 kV의 전압을 인가 하면서, PVK/스티렌 용액을 노즐로부터 토출하였다. 로봇 스테이지에 의하여 이동되는 콜렉터 위에 그래핀 활성층이 전사된 기판을 놓고, 그 위에 정렬된 PVK 나노와이어 패턴을 형성하였다.First, PVK was dissolved in styrene to prepare PVK / styrene solution (3.77 wt%). The prepared PVK / styrene solution was placed in a syringe of an electric field assisted robotic nozzle printer, and the PVK / styrene solution was discharged from the nozzle while applying a voltage of about 3.6 kV to the nozzle. The substrate on which the graphene active layer was transferred was placed on the collector moved by the robot stage, and an aligned PVK nanowire pattern was formed thereon.
이때, 사용한 노즐의 직경은 100 ㎛이고 노즐과 콜렉터 사이의 거리를 2.5 mm로 일정하게 유지하였다. 로봇 스테이지의 Y축 방향의 이동 간격은 50 ㎛이고, X축 방향의 이동 거리는 15 cm이었다. 콜렉터의 크기는 20cm × 20cm이고, 기판의 크기는 2.5cm × 2.5cm 이었다. 형성된 PVK 나노와이어 패턴 위에 열증착을 통해서 3nm 두께의 티타늄과 60nm 두께의 금을 순서대로 증착하여 소스 및 드레인 전극을 형성 하였다. PVK 나노와이어에 의해 가려지지 않은 그래핀 영역은 산소 플라즈마 식각 (30 W, 10 초)을 통해 제거하고, PVK 나노와이어는 클로로포름 안에서 초음파 처리하여 제거한다. 상기 과정을 통해 그래핀 나노리본을 제작하였다.At this time, the diameter of the nozzle used was 100 µm and the distance between the nozzle and the collector was kept constant at 2.5 mm. The moving distance in the Y-axis direction of the robot stage was 50 µm, and the moving distance in the X-axis direction was 15 cm. The size of the collector was 20 cm x 20 cm, and the size of the substrate was 2.5 cm x 2.5 cm. Source and drain electrodes were formed by sequentially depositing 3 nm thick titanium and 60 nm thick gold on the PVK nanowire patterns. Graphene regions not covered by PVK nanowires are removed via oxygen plasma etching (30 W, 10 seconds), and PVK nanowires are removed by sonication in chloroform. Graphene nanoribbons were produced through the above process.
이어서, 폴리(스티렌-산화에틸렌-스티렌) (PS-PEO-PS) (7wt%) 삼중블럭 공중합체와 1-에틸-3-메틸이미다졸륨 비스(트리플루오로메틸설포닐)아마이드 ([EMIM][TFSI]) 의 혼합물로 이루어진 이온젤 용액을 드롭 캐스팅(drop casting) 방법으로 그래핀 나노리본 활성층 위에 도포하였다. 이후, 기판을 진공 상에서 3시간 동안 건조하여 이온젤 게이트 절연층을 형성하였다. 전술된 게이트 절연층에 금속 프로브를 게이트 전극으로 사용하여 그래핀 나노리본 기반 시냅스 모방 소자를 제조하였다.Subsequently, poly (styrene-ethylene oxide-styrene) (PS-PEO-PS) (7 wt%) triple block copolymer and 1-ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) amide ([EMIM ] [TFSI]) was applied onto the graphene nanoribbon active layer by drop casting. Thereafter, the substrate was dried under vacuum for 3 hours to form an ion gel gate insulating layer. A graphene nanoribbon-based synaptic mimic device was fabricated using a metal probe as a gate electrode in the above-described gate insulating layer.
도 3는 본 발명의 제조예 1의 산화아연 나노와이어의 SEM 이미지이다.3 is an SEM image of the zinc oxide nanowires of Preparation Example 1 of the present invention.
도 3을 참조하면, 활성층이 나노와이어 형태로 형성되었음을 알 수 있다. 또한, 전술된 나노와이어의 직경이 118nm인 것을 알 수 있다.Referring to Figure 3, it can be seen that the active layer is formed in the form of nanowires. In addition, it can be seen that the diameter of the nanowire described above is 118 nm.
결론적으로, 본 발명의 경우, 전기장 잉크젯 프린팅 공정을 함에 따라 대면적 고집적된 소자를 제조할 수 있음을 알 수 있다.In conclusion, in the case of the present invention, it can be seen that a large area highly integrated device can be manufactured by performing an electric field inkjet printing process.
도 4은 본 발명의 제조예 1의 전류-전압 특성을 나타낸 그래프이다.4 is a graph showing the current-voltage characteristics of Preparation Example 1 of the present invention.
도 4를 참조하면, 제조예 1은 전기 시냅스 자극 전압에 대한 후기 시냅스 반응 전류(excitatory post-synaptic current, 드레인 전류)를 모방하는 산화아연 나노와이어 기반 시냅스 모방 소자의 전류 특성을 확인할 수 있다. 또한 전기 시냅스 자극 전압 (게이트 전압 펄스) 이 계속적으로 입력되면, 후기 시냅스 반응 전류가 강화된다. 그리고 후기 시냅스 반응 전류는 휴지 전류 수준으로 천천히 감소한다.Referring to FIG. 4, Preparation Example 1 may confirm current characteristics of a zinc oxide nanowire-based synaptic mimic device that mimics a latent synaptic response current (drain current) with respect to an electrical synaptic stimulation voltage. In addition, when the electric synaptic stimulation voltage (gate voltage pulse) is continuously input, the late synaptic response current is intensified. The late synaptic response current then slowly decreases to the resting current level.
결과적으로, 본 발명의 일 실시예에 따른 시냅스 모방 소자는 시냅스 특성을 나타냄을 알 수 있다.As a result, it can be seen that the synaptic mimic device according to an embodiment of the present invention exhibits synaptic properties.
도 5는 본 발명의 제조예 2의 P3HT 나노와이어의 SEM 이미지이다.5 is an SEM image of P3HT nanowires of Preparation Example 2 of the present invention.
도 5를 참조하면, 활성층이 나노와이어 형태로 형성되었음을 알 수 있다. 또한, 전술된 나노와이어의 직경이 329nm인 것을 알 수 있다.Referring to Figure 5, it can be seen that the active layer is formed in the form of nanowires. It can also be seen that the diameter of the nanowires described above is 329 nm.
결론적으로, 본 발명의 경우, 전기장 잉크젯 프린팅 공정을 함에 따라 대면적 고집적된 소자를 제조할 수 있음을 알 수 있다.In conclusion, in the case of the present invention, it can be seen that a large area highly integrated device can be manufactured by performing an electric field inkjet printing process.
도 6는 본 발명의 제조예 2의 전류-전압 특성을 나타낸 그래프이다.6 is a graph showing the current-voltage characteristics of Preparation Example 2 of the present invention.
도 6을 참조하면, 제조예 2은 생체 시냅스 특성을 나타냄을 알 수 있다.Referring to Figure 6, it can be seen that Preparation Example 2 exhibits biosynaptic properties.
결론적으로, 본 발명의 일 실시예에 따른 시냅스 모방 소자는 생체 시냅스 특성을 나타냄을 알 수 있다.In conclusion, it can be seen that the synaptic mimic device according to an embodiment of the present invention exhibits biosynaptic properties.
도 7은 본 발명의 제조예 3의 그래핀 나노리본의 SEM 이미지이다.7 is an SEM image of the graphene nanoribbons of Preparation Example 3 of the present invention.
도 7을 참조하면, 활성층이 나노리본 형태로 형성되었음을 알 수 있다. 또한, 전술된 나노리본의 너비가 31.2nm인 것을 알 수 있다.Referring to Figure 7, it can be seen that the active layer is formed in the form of nanoribbons. In addition, it can be seen that the width of the above-described nanoribbons is 31.2nm.
결론적으로, 본 발명의 경우, 전기장 잉크젯 프린팅 공정을 함에 따라 대면적 고집적된 소자를 제조할 수 있음을 알 수 있다.In conclusion, in the case of the present invention, it can be seen that a large area highly integrated device can be manufactured by performing an electric field inkjet printing process.
도 8은 본 발명의 제조예 3의 전류-전압 특성을 나타낸 그래프이다.8 is a graph showing the current-voltage characteristics of Preparation Example 3 of the present invention.
도 8을 참조하면, 제조예 3은 생체 시냅스 특성을 나타냄을 알 수 있다.Referring to FIG. 8, it can be seen that Preparation Example 3 exhibits biosynaptic properties.
결론적으로, 본 발명의 일 실시예에 따른 시냅스 모방 소자는 생체 시냅스 특성을 나타냄을 알 수 있다.In conclusion, it can be seen that the synaptic mimic device according to an embodiment of the present invention exhibits biosynaptic properties.
이상, 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 사상 및 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형 및 변경이 가능하다.In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention. Changes are possible.
[부호의 설명][Description of the code]
10 : 기판 20 : 활성층10 substrate 20 active layer
30a : 소스 전극 30b : 드레인 전극30a: source electrode 30b: drain electrode
40 : 이온젤 게이트 절연층 50 : 게이트 전극40 ion gel gate insulating layer 50 gate electrode

Claims (13)

  1. 게이트 전극;Gate electrodes;
    활성층;Active layer;
    상기 게이트 전극 및 활성층 사이에 배치되고, 절연성 고분자 및 이온성 물질을 포함하는 이온젤 게이트 절연층; 및An ion gel gate insulating layer disposed between the gate electrode and the active layer and including an insulating polymer and an ionic material; And
    상기 활성층과 전기적으로 접속하는 소스 전극 및 드레인 전극을 포함하고,A source electrode and a drain electrode electrically connected to the active layer;
    상기 게이트 전극 또는 활성층은 기판에 지지되는 시냅스 모방 소자.The gate electrode or the active layer is a synaptic mimic device that is supported on a substrate.
  2. 제1항에 있어서, The method of claim 1,
    상기 시냅스 모방 소자는 탑-게이트/바텀-컨텍, 탑-게이트/탑-컨텍, 바텀-게이트/바텀-컨텍, 또는 바텀-게이트/탑-컨텍 구조인 것을 특징으로 하는 시냅스 모방 소자.The synaptic mimic device is a synaptic mimic device, characterized in that the top-gate / bottom-contact, top-gate / top-contact, bottom-gate / bottom-contact, or bottom-gate / top-contact structure.
  3. 제1항에 있어서,The method of claim 1,
    상기 활성층은 1차원 나노 반도체 소재인 것을 특징으로 하는 시냅스 모방 소자.The active layer is a synaptic mimic device, characterized in that the one-dimensional nano-semiconductor material.
  4. 제3항에 있어서,The method of claim 3,
    상기 1차원 나노 반도체 소재는 나노 와이어, 나노리본, 나노튜브, 나노로드, 및 나노필름으로 이루어진 군으로부터 선택되는 적어도 하나를 포함하는 시냅스 모방 소자.The one-dimensional nano-semiconductor material is a synaptic mimic device comprising at least one selected from the group consisting of nanowires, nanoribbons, nanotubes, nanorods, and nanofilms.
  5. 제1항에 있어서,The method of claim 1,
    상기 활성층은 저분자 유기 반도체, 유기반도체, 전도성 고분자, 무기 반도체, 산화물 반도체, 이차원 반도체, 및 양자점으로 이루어진 군으로부터 선택되는 적어도 하나를 포함하는 시냅스 모방 소자.The active layer is a synaptic mimic device comprising at least one selected from the group consisting of a low molecular organic semiconductor, an organic semiconductor, a conductive polymer, an inorganic semiconductor, an oxide semiconductor, a two-dimensional semiconductor, and a quantum dot.
  6. 제1항에 있어서,The method of claim 1,
    상기 활성층은 TIPS 펜타센(6,13-bis(triisopropylsilylethynyl) pentacene), TES ADT(Triethylsilylethynyl anthradithiophene), PCBM([6,6]-Phenyl C61 butyric acid methyl ester), P3HT(Poly(3-hexylthiophene)), PEDOT(Poly(3,4-ethylenedioxythiophene)), PVK(Poly(9-vinylcarbazole)), 폴리(p-페닐렌 비닐렌)(poly(p-phenylene vinylene)), 폴리플루오렌(polyfluorene), 폴리아닐린(polyaniline), 폴리피롤(polypyrrole), 실리콘, 게르마늄, 갈륨아세나이드, 카본 나노튜브 (CNT), 환원된 산화 그래핀, 그래핀, 그래핀 양자점, 흑연, 산화아연, 산화주석, 산화인듐, 산화아연주석 (ZTO), 산화인듐아연(IZO), 산화인듐아연갈륨(IGZO), 황화몰리브덴 (MoS2), 황화텅스텐(WS2), 몰리브데넘셀레나이드(MoSe2), 텅스텐셀레나이드(WSe2), 질화붕소(h-BN), 불화 그래핀(fluoro-graphene), 카드뮴 셀레나이드, 카드뮴 텔룰라이드, 및 황화카드뮴으로 이루어진 군으로부터 선택되는 적어도 하나를 포함하는 시냅스 모방 소자.The active layer is TIPS pentacene (6,13-bis (triisopropylsilylethynyl) pentacene), TES ADT (Triethylsilylethynyl anthradithiophene), PCBM ([6,6] -Phenyl C61 butyric acid methyl ester), P3HT (Poly (3-hexylthiophene)) , PEDOT (Poly (3,4-ethylenedioxythiophene)), PVK (Poly (9-vinylcarbazole)), poly (p-phenylene vinylene), polyfluorene, polyaniline (polyaniline), polypyrrole, silicon, germanium, gallium arsenide, carbon nanotubes (CNT), reduced graphene oxide, graphene, graphene quantum dots, graphite, zinc oxide, tin oxide, indium oxide, zinc oxide Tin (ZTO), indium zinc oxide (IZO), indium zinc gallium oxide (IGZO), molybdenum sulfide (MoS2), tungsten sulfide (WS2), molybdenum selenide (MoSe2), tungsten selenide (WSe2), boron nitride (h-BN), a graphene selected from the group consisting of fluoro-graphene, cadmium selenide, cadmium telluride, and cadmium sulfide FIG synaptic imitation element comprises one.
  7. 제1항에 있어서,The method of claim 1,
    상기 절연성 고분자는 절연성을 갖는 단일 고분자, 블록 공중합체, 고분자-단분자 혼합물, 및 가교성 고분자로 이루어진 군으로부터 선택되는 적어도 하나를 포함하는 시냅스 모방 소자.The insulating polymer is a synaptic mimic device comprising at least one selected from the group consisting of insulating single polymer, block copolymer, polymer-monomeric mixture, and crosslinkable polymer.
  8. 제1항에 있어서,The method of claim 1,
    상기 절연성 고분자는 재료는 폴리(9-비닐카바졸), 폴리(p-페닐렌비닐렌), 폴리플루오렌, 폴리아닐린, 폴리피롤, 폴리에틸렌옥사이드, 폴리스티렌, 폴리카프로락톤, 폴리아크릴로니트릴, 폴리(메틸메타크릴레이트), 폴리이미드, 폴리(비닐리덴 플로라이드), 및 폴리비닐클로라이드폴리(스티렌-에틸렌옥사이드-스티렌) (PS-PEO-PS)d로 이루어진 군으로부터 선택되는 적어도 하나를 포함하는 시냅스 모방 소자.The insulating polymer is poly (9-vinylcarbazole), poly (p-phenylenevinylene), polyfluorene, polyaniline, polypyrrole, polyethylene oxide, polystyrene, polycaprolactone, polyacrylonitrile, poly (methyl Methacrylate), polyimide, poly (vinylidene fluoride), and polyvinylchloride poly (styrene-ethyleneoxide-styrene) (PS-PEO-PS) d including synaptic mimics device.
  9. 제1항에 있어서,The method of claim 1,
    상기 이온성 물질은 리튬-비스(트리플루오로메틸설포닐)이미드 (LiTFSI), 리튬폴리(스티렌 설포네이트) (LiPSS), 1-에틸-3-메틸이미다졸리움 비스(트리플루오로메틸설포닐)이미드 ([EMIM][TFSI]), 1-부틸-3-메틸이미다졸리움 헥사플루오로포스페이트 ([BMIM][PF6]), 및 1-에틸-3-메틸이미다졸리움 n-옥틸설페이트 ([EMIM][OctOSO3])로 이루어진 군으로부터 선택되는 적어도 하나를 포함하는 시냅스 모방 소자.The ionic material is lithium-bis (trifluoromethylsulfonyl) imide (LiTFSI), lithium poly (styrene sulfonate) (LiPSS), 1-ethyl-3-methylimidazolium bis (trifluoromethylsul Ponyl) imide ([EMIM] [TFSI]), 1-butyl-3-methylimidazolium hexafluorophosphate ([BMIM] [PF 6 ]), and 1-ethyl-3-methylimidazolium n- A synaptic mimetic device comprising at least one selected from the group consisting of octyl sulfate ([EMIM] [OctOSO 3 ]).
  10. 기판 상에 활성층을 형성하는 단계;Forming an active layer on the substrate;
    상기 활성층 상의 일단 및 타단에 각각 상기 활성층과 전기적으로 접속하는 소스 전극 및 드레인 전극을 형성하는 단계;Forming source and drain electrodes electrically connected to the active layer at one end and the other end of the active layer, respectively;
    상기 활성층 상에 절연성 고분자 및 이온성 물질을 포함하는 이온젤 게이트 절연층을 형성하는 단계; 및Forming an ion gel gate insulating layer including an insulating polymer and an ionic material on the active layer; And
    상기 이온젤 게이트 절연층 상에 게이트 전극을 형성하는 단계를 포함하는 시냅스 모방 소자의 제조방법.A method of manufacturing a synaptic mimic device comprising forming a gate electrode on the ion gel gate insulating layer.
  11. 제10항에 있어서,The method of claim 10,
    상기 활성층은 나노 와이어 패턴, 나노리본 패턴, 나노튜브 패턴, 또는 나노로드 패턴인 것을 특징으로 하는 시냅스 모방 소자.The active layer is a synaptic mimic device, characterized in that the nanowire pattern, nanoribbon pattern, nanotube pattern, or nanorod pattern.
  12. 제11항에 있어서,The method of claim 11,
    상기 활성층을 형성하는 단계는 전기장 잉크젯 프린팅 공정을 사용하는 것을 특징으로 하는 시냅스 모방 소자의 제조방법.Forming the active layer is a method for manufacturing a synaptic mimic device, characterized in that using an electric field inkjet printing process.
  13. 제10항에 있어서,The method of claim 10,
    상기 이온젤 게이트 절연층을 형성하는 단계는 드롭 캐스팅 방법을 사용하는 것을 특징으로 하는 시냅스 모방 소자의 제조방법.Forming the ion gel gate insulating layer is a method of manufacturing a synaptic mimic device, characterized in that using the drop casting method.
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