WO2016024483A1 - Analog/digital conversion circuit - Google Patents
Analog/digital conversion circuit Download PDFInfo
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- WO2016024483A1 WO2016024483A1 PCT/JP2015/071756 JP2015071756W WO2016024483A1 WO 2016024483 A1 WO2016024483 A1 WO 2016024483A1 JP 2015071756 W JP2015071756 W JP 2015071756W WO 2016024483 A1 WO2016024483 A1 WO 2016024483A1
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- analog
- digital conversion
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Definitions
- the present invention relates to an analog / digital conversion circuit.
- Instrumentation equipment such as a temperature controller provided in a plant or building air conditioner, etc. monitors the state of the controlled device, and includes a heater or a heater provided in the controlled device so that the controlled device is in a target state. Controls valves and the like.
- Patent Document 1 discloses a temperature regulator that controls a control target device so as to reach a target temperature.
- This temperature controller is an analog / digital conversion circuit (hereinafter referred to as “A / D”) that periodically converts the detection result (analog signal) of the temperature of the control target device detected by the temperature sensor into a digital signal.
- a data processing unit processor such as a CPU
- PID Proportional Integral Derivative
- Instrumentation equipment such as a temperature controller needs to accurately grasp the change in the state of the controlled device and perform appropriate control according to the change in the state. Therefore, an instrumentation device such as a temperature controller must periodically A / D convert the detection result of the sensor and transmit the continuous A / D conversion result to a data processing unit such as a CPU without omission. If there is missing measurement data on the data processing unit side, the continuity of the measurement data is lost. When the data processing unit performs a PID operation such as a differential operation in a state where the continuity of the measurement data is lost, the operation amount calculated by the operation suddenly changes to an unintended value, and the control result is not good. There is a risk of becoming stable.
- a PID operation such as a differential operation in a state where the continuity of the measurement data is lost
- the data processing unit determines whether or not the continuity of the acquired data is maintained, and uses the acquired data for the PID calculation only when the continuity of the data is maintained. It is possible to avoid abnormalities such as a sudden change in the operation amount due to the control and to maintain control stability.
- the data processing unit cannot determine whether the continuity of the acquired A / D conversion result is maintained.
- an A / D conversion circuit and a data processing unit such as a CPU are configured by separate semiconductor chips. If these chips cannot be arranged close to each other, the same clock signal may not be supplied from two oscillator chips from a single oscillator. In such a case, it is necessary to provide an oscillator for each semiconductor chip.
- the oscillators are individually provided, by using the clocks of the respective oscillators, the A / D conversion process is executed and the A / D conversion result read period coincides with the A / D conversion result readout period. Even if the conversion circuit and the data processing unit are operated, an error based on an individual difference of oscillators or a difference in performance actually occurs in both operation cycles.
- the data processing unit may acquire the same A / D conversion result twice from the A / D conversion circuit. If the data processing unit acquires the same A / D conversion result twice, the data processing unit only needs to look at the acquired data twice to obtain the A / D conversion result in one A / D conversion cycle. It was not possible to determine whether each A / D conversion result in the two consecutive A / D conversion periods had the same value because the input value was stable or it happened to be acquired.
- the on / off state of the port of the semiconductor chip on which the A / D conversion circuit is formed is switched according to whether the A / D conversion process is completed, and the data processing unit A method is also conceivable in which the on / off state switching is detected by polling or interrupt processing, and the A / D conversion result read processing is executed based on the detection result.
- the A / D conversion result read process executed after the polling determination process or the interrupt process is delayed, the A / D conversion result of the target A / D conversion cycle cannot be acquired. There is a possibility of acquiring an A / D conversion result of the next A / D conversion cycle.
- the data processing unit misses the A / D conversion result of the target A / D conversion cycle, does the data processing unit miss the A / D conversion result for one cycle only by looking at the acquired data? It was not possible to judge whether or not.
- the timing for executing the A / D conversion process and the timing for reading the A / D conversion result can be strictly defined. There is a problem that the time restriction of the processing on the side increases and the design of the data processing unit becomes complicated.
- An object of the present invention is to provide a continuity of a plurality of acquired A / D conversion results in a circuit that continuously acquires a plurality of A / D conversion results from an A / D conversion circuit that periodically performs A / D conversion. It is to be able to determine whether or not the above is maintained.
- An analog / digital conversion circuit includes an analog / digital conversion unit that periodically executes an analog / digital conversion process for converting an input analog signal into a digital signal, a storage unit, and the analog / digital conversion unit.
- a controller that writes an analog / digital conversion result by the analog / digital conversion process and identification data associated with the analog / digital conversion result to the storage unit each time the analog / digital conversion process is executed;
- an output unit that reads out and outputs the analog / digital conversion result written in the storage unit and the corresponding identification data.
- a circuit that continuously acquires a plurality of A / D conversion results from an A / D conversion circuit that periodically performs A / D conversion can be obtained by using the acquired A / D conversion results. It can be determined whether or not the continuity of the D conversion result is maintained.
- FIG. 1 is a diagram showing a configuration of a temperature control system including a temperature controller including an A / D conversion circuit according to the first embodiment.
- FIG. 2 is a diagram illustrating a configuration of a temperature controller including the A / D converter according to the first embodiment.
- FIG. 3A is a diagram illustrating an example when data based on the number of executions of the A / D conversion process is used as identification data.
- FIG. 3B is a diagram illustrating an example when data based on the execution time of the A / D conversion process is used as identification data.
- FIG. 3C is a diagram illustrating an example in which identification data is 1-bit data whose logic level is inverted each time an A / D conversion process is performed.
- FIG. 4A is a diagram illustrating an example of a format of a transmission message of a data read request in the temperature controller including the A / D converter according to the first embodiment.
- 4B is a diagram showing an example of a response message format related to a data read request in the temperature controller including the A / D converter according to Embodiment 1.
- FIG. FIG. 5 is a diagram illustrating a configuration of a temperature regulator including an A / D conversion circuit according to the second embodiment.
- FIG. 6 is a diagram illustrating an example of assignment of addresses of the A / D conversion processing register and the identification data register.
- FIG. 7A is a diagram illustrating an example of a format of a transmission message of a data read request in the temperature controller including the A / D converter according to the second embodiment.
- FIG. 7B is a diagram illustrating an example of a response message format related to a data read request in the temperature controller including the A / D converter according to the second embodiment.
- FIG. 8 is a diagram illustrating an example of assignment of addresses of A / D conversion processing registers and identification data registers in an A / D conversion circuit including a plurality of A / D conversion units.
- An analog / digital conversion circuit includes an analog / digital conversion unit that periodically executes an analog / digital conversion process for converting an input analog signal into a digital signal, a storage unit, and the analog / digital conversion unit.
- a controller that writes an analog / digital conversion result by the analog / digital conversion process and identification data associated with the analog / digital conversion result to the storage unit each time the analog / digital conversion process is executed;
- an output unit that reads out and outputs the analog / digital conversion result written in the storage unit and the corresponding identification data.
- control unit performs the storage unit by the output unit until writing of both the analog / digital conversion result and the identification data by the analog / digital conversion unit to the storage unit is completed. May not be allowed to be read.
- the identification data may be data indicating the number of executions of the analog / digital conversion processing by the analog / digital conversion unit.
- the identification data may be data indicating a time when the analog / digital conversion processing is executed by the analog / digital conversion unit.
- the identification data may be 1-bit data whose logic level is inverted every time the analog / digital conversion process is executed by the analog / digital conversion unit.
- the identification data may be data based on a count value of a free-run counter.
- the storage unit is a register including a first register that stores the analog / digital conversion result obtained by the analog / digital conversion process and a second register that stores the identification data.
- the control unit sequentially stores the analog / digital conversion result of the executed analog / digital conversion process and the identification data in the register pair.
- the writing and the output unit read the analog / digital conversion result and the identification data related to the analog / digital conversion processing for a plurality of times from the plurality of register pairs. May be.
- FIG. 1 is a diagram showing a configuration of a temperature control system including a temperature controller including an A / D conversion circuit according to the first embodiment.
- a temperature control system 300 shown in the figure includes a temperature controller 1, a control target device 2, a temperature sensor 3, an operation unit 4, and a heater 5.
- the temperature sensor 3 detects the temperature of the control target device 2 and outputs an analog detection signal (hereinafter also referred to as “analog signal”) VA.
- the heater 5 is, for example, a device that is provided inside the control target device 2 and heats the control target device 2.
- the operation unit 4 is a device that adjusts the heating temperature of the heater 5. For example, the operation unit 4 adjusts the heating temperature of the heater 5 by changing the current or voltage supplied to the heater 5 based on the control signal CNT supplied from the temperature controller 2.
- the temperature controller 1 periodically converts the analog signal VA output from the temperature sensor 3 into a digital signal, and performs a PID operation using the converted digital signal (measurement data), so that the control target device 2 can perform the target operation.
- the control signal CNT is generated so that the temperature becomes.
- FIG. 2 is a diagram illustrating a configuration of the temperature regulator 1 including the A / D conversion circuit according to the first embodiment. As shown in FIG. 2, the temperature controller 1 includes an A / D conversion circuit 10, a data processing control unit 11, and other power supply circuits and external input / output interface circuits not shown.
- the A / D conversion circuit 10 is a circuit that converts the analog signal VIN output from the temperature sensor 3 into a digital signal.
- the A / D conversion circuit 10 not only outputs the A / D conversion result but also has a function of outputting the identification data associated with the A / D conversion result to the data processing control unit 11 at the subsequent stage. Yes.
- the A / D conversion circuit 10 includes an A / D conversion unit 101, a control unit 102, a storage unit 103, and a communication circuit 106.
- the A / D conversion circuit 10 is, for example, a one-chip semiconductor device in which an A / D conversion unit 101, a control unit 102, a storage unit 103, and a communication circuit 106 are formed on one semiconductor substrate by a known CMOS manufacturing process. It is realized as.
- the A / D converter 101 periodically executes A / D conversion processing for converting the analog signal VIN output from the temperature sensor 3 into a digital signal.
- the A / D conversion unit 101 converts the analog signal VIN into the digital signal DOUT and outputs it at a constant cycle (for example, every 10 ms).
- the A / D converter 101 is, for example, a ⁇ type A / D converter.
- the digital signal DOUT converted by the A / D conversion unit 10 is also referred to as an A / D conversion result DOUT.
- the control unit 102 writes the A / D conversion result DOUT of the completed A / D conversion process in the storage unit 103 and also performs the A / D conversion.
- the identification data DID associated with the result DOUT is written in the storage unit 103.
- the identification data DID is data for identifying a conversion result by an A / D conversion process executed at a certain timing and a conversion result by an A / D conversion process executed at a timing before and after that. Details of the identification data DID will be described later.
- control unit 102 outputs an enable signal EN instructing permission / non-permission of data reading from the storage unit 103 by the communication circuit 106 described later.
- the control unit 102 stores the A / D conversion result DOUT and the enable signal EN in an invalid state until the writing of the identification data DIN corresponding to the A / D conversion result DOUT to the storage unit 103 is completed.
- the enable signal EN is set to a valid state, whereby the data from the storage unit 103 is read. Allow reading.
- the storage unit 103 includes a circuit having a storage area for storing data, and stores the A / D conversion result DOUT and the identification data DID.
- the storage unit 103 includes an A / D conversion result register 104 as a storage circuit for storing the A / D conversion result DOUT, and an identification data register 105 as a storage circuit for storing the identification data DID. Have.
- the A / D conversion result register 104 and the identification data register 105 can be rewritten by the control unit 102 and read by the communication circuit 106. For example, every time the A / D conversion process by the A / D conversion unit 10 is completed, the control unit 102 displays the A / D conversion result OUT of the completed A / D conversion process and the identification data DID corresponding thereto as A / D By writing to the D conversion result register 104 and the identification data register 105, the values of the A / D conversion result register 104 and the identification data register 105 are updated.
- the A / D conversion result DOUT and the identification data DID stored in the A / D conversion result register 104 and the identification data register 105 are periodically read by the communication circuit 106.
- the communication circuit 106 functions as an output unit that reads and outputs data from the storage unit 103. Specifically, in response to a data read request from the data processing control unit 11, the communication circuit 106 reads the A / D conversion result DOUT and the identification data DID written in the storage unit 103, and reads the two read Data is transmitted to the data processing control unit 11. More specifically, when the communication circuit 106 receives a data read request from the data processing control unit 11 and the enable signal EN is in a valid state, the communication circuit 106 receives the A / D conversion result DOUT from the storage unit 103. The identification data DID is read and transmitted to the data processing control unit 11, and when the enable signal EN is in an invalid state, the process waits until the enable signal EN is in an effective state. When the enable signal EN becomes valid, the A / D conversion result DOUT and the identification data DID are read from the storage unit 103 and transmitted to the data processing control unit 11.
- the data processing control unit 11 is a microcontroller, for example, and includes a CPU 111, a storage device 112, a communication circuit 113, an external interface circuit (not shown), and the like.
- the data processing control unit 11 may be configured as a one-chip microcontroller in which the CPU 111, the storage device 112, the communication circuit 113, and the like are formed on one semiconductor substrate, or the CPU 111, the storage device 112, and
- the communication circuit 113 or the like may be configured as a multi-chip microcontroller formed on separate semiconductor chips.
- the communication circuit 113 is a circuit for performing communication with an external circuit. For example, the communication circuit 113 issues a data read request to the A / D conversion circuit 10 in accordance with an instruction from the CPU 111, and the A output from the A / D conversion circuit 10 in response to the issued read request. / D conversion result DOUT and identification data DID are received. The A / D conversion result DOUT and the identification data DID received by the communication circuit 113 are stored in the storage device 112, for example.
- the storage device 112 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a plurality of registers, and the like.
- the ROM stores a program for causing the CPU 111 to execute various calculations
- the plurality of registers store the A / D conversion result DOUT received by the communication circuit 113, the identification data DID, and the like.
- the CPU 111 performs overall control of the temperature controller 1 by performing various calculations in accordance with programs stored in the storage device 112. Further, the CPU 111 generates a control signal CNT so that the control target device 2 reaches a target temperature by performing a PID calculation based on the A / D conversion result DOUT stored in the storage device 112.
- the control signal CNT generated by the CPU 111 is supplied to the operation unit 4 via an external interface circuit (not shown) and is used for controlling the heating temperature of the heater 5 as described above.
- the A / D conversion circuit 10 outputs the identification data DID associated with the A / D conversion result DOUT to the subsequent data processing control unit 11 in addition to the A / D conversion result DOUT.
- the identification data DID for example, the following four can be exemplified.
- the first example is a technique for generating identification data DID from data based on the number of execution times of A / D conversion processing.
- FIG. 3A is a diagram illustrating an example when data based on the number of executions of the A / D conversion process is used as identification data DID.
- the A / D conversion circuit 10 counts the number of executions of the A / D conversion process, and uses the count value as identification data DID.
- a counter is provided in the control unit 102, and the count value of the counter is incremented each time the A / D conversion result DOUT is output from the A / D conversion unit 10.
- the control unit 102 Whenever the A / D conversion result DOUT is output from the A / D conversion unit 10, the control unit 102 writes the A / D conversion result DOUT into the A / D conversion result register 105, and the count value of the counter at that time Is written into the identification data register 105.
- a counter that counts the number of execution times of A / D conversion processing can be exemplified.
- an 8-bit counter counts the number of executions of the A / D conversion process, resets the count value when the number of executions of the A / D conversion process is counted up to the 256th time, and starts from the 257th time. The case where the count operation starts again from “0” is shown.
- an 8-bit counter is exemplified as the counter.
- a counter having a larger number of bits is used. Use it. For example, when the A / D conversion process is executed at an interval of 1 ms, it is possible to record the number of executions of the A / D conversion process for about 49 days by using a 32-bit counter. For example, by using a 40-bit counter, it is possible to record the number of executions of A / D conversion in about 34 years, and continuously record the number of executions exceeding the life of a general product. Is also possible. Further, in a general design, a counter of about 32 bits can be prepared, so that the number of bits can be increased as necessary.
- the second example is a method for generating identification data DID from data based on the execution time of the A / D conversion process.
- FIG. 3B is a diagram illustrating an example in which the data based on the execution time of the A / D conversion process is the identification data DID.
- the execution time (time stamp) of the A / D conversion process becomes the identification data DID.
- the execution time is, for example, the time when the A / D conversion process is completed.
- the first technique is a technique in which a real-time clock is provided inside or outside the A / D conversion circuit 10.
- the control unit 102 writes the A / D conversion result DOUT into the A / D conversion result register 105 and
- the value of the real time clock is written in the identification data register 105 as identification data DID.
- the number of bits required for the real-time clock is, for example, 48 to 64 bits.
- the second method is a method of providing a counter that is incremented at a constant cycle, for example, at time 0 when power is turned on, inside or outside the control unit 102 instead of the real-time clock.
- the control unit 102 every time the A / D conversion result DOUT is output from the A / D conversion unit 10, the control unit 102 writes the A / D conversion result DOUT into the A / D conversion result register 105 and The counter value is written in the identification data register 105 as identification data DID.
- the A / D conversion result obtained by the A / D conversion process executed at a certain timing and the A / D conversion result obtained by the A / D conversion process executed at the timing before and after that are identified. It becomes possible. Furthermore, according to the first method using the real-time clock described above, the accurate time when the A / D conversion process is executed can be recorded, so that the identification data DID can be used for debugging of the temperature controller 1 and the like. Become. On the other hand, according to the second method not using the real-time clock described above, an increase in circuit scale can be suppressed.
- the third example is a method of generating identification data DID from 1-bit data whose logic level is inverted every time A / D conversion processing is executed.
- FIG. 3C is a diagram illustrating an example in which identification data DID is 1-bit data whose logic level is inverted each time an A / D conversion process is performed.
- the identification data register 105 is composed of a 1-bit storage element (flag). Further, every time the A / D conversion result DOUT is output from the A / D conversion unit 10, the control unit 102 writes the A / D conversion result DOUT in the A / D conversion result register 105 and also in the identification data register 105. The recorded 1-bit value is inverted.
- the identification data register 105 may be realized by a 1-bit counter.
- the fourth example is a technique for generating identification data DID from data based on the count value of the free-run counter.
- an 8-bit free-run counter is provided in the A / D conversion circuit 10, and the free-run counter counts continuously input pulses regardless of the execution process of the A / D conversion process.
- the value is the identification data DID. According to this, since a counter having a large bit width is not required, an increase in circuit scale can be suppressed.
- the data stored as the identification data DID may not be the count value (numerical value) of the free-run counter itself, but may be a character code with a known order such as “A to Z” of the alphabet, for example.
- Communication between the A / D conversion circuit 10 and the data processing control unit 11 is performed by, for example, an SPI (Serial Peripheral Interface).
- SPI Serial Peripheral Interface
- the communication circuit 106 on the A / D conversion circuit 10 side and the communication circuit 113 on the data processing control unit 11 side each have hardware resources necessary for communication by SPI.
- the A / D conversion result is transmitted from the A / D conversion circuit 10 to the data processing control unit 11 by the data processing control unit 11 issuing a data read request (read command).
- the circuit 10 is realized by outputting the A / D conversion result DOUT and the identification data DID as a set as a response to the read request.
- FIG. 4A is a diagram illustrating an example of a format of a transmission message of a data read request according to the first embodiment.
- FIG. 4B is a diagram illustrating an example of a response message format related to a data read request according to the first embodiment.
- the transmission message related to the data read request issued by the data processing control unit 11 is serial data in which a header is attached to the head of the data and a footer is attached to the end of the data, for example, according to the SPI protocol. It is configured as.
- FIG. 4A shows an instruction for instructing “reading a set of A / D conversion results DOUT and identification data DID from address 100H”.
- the response message transmitted from the A / D conversion circuit 10 in response to the transmission message of the data processing control unit 11 is placed at the head of the data according to the SPI protocol, similarly to the transmission message. It is configured as one frame of serial data with a header and a footer at the end of the data.
- FIG. 4B shows a case where an A / D conversion result DOUT “3356H” and identification data DID “01H” are output as a response to the read command.
- the cycle in which the data processing control unit 11 issues a read request to the A / D conversion circuit 10 is a cycle in which A / D conversion processing is executed in the A / D conversion circuit 10 (A / D conversion result register 104 and identification The cycle is the same as or shorter than the cycle in which the data register 105 is updated. Thereby, the data processing control unit 11 can continuously acquire the A / D conversion result DOUT periodically updated by the A / D conversion circuit 10.
- identification data is assigned for each A / D conversion result, and the A / D conversion result and the identification data are output as a set.
- the received circuit can determine whether the continuity of the acquired A / D conversion result is maintained.
- the data processing control unit 11 performs identification data corresponding to the acquired A / D conversion result and the A / D conversion acquired immediately before it. By comparing the identification data corresponding to the result, it is possible to determine whether or not the A / D conversion result of the same A / D conversion period is acquired and whether or not the A / D conversion result is missed. That is, it is possible for the data processing control unit 11 to determine whether the continuity of the acquired A / D conversion results is maintained.
- the data processing control unit 11 determines that the continuity of the acquired A / D conversion result is maintained, the data processing control unit 11 performs the PID calculation using the acquired A / D conversion result, and acquires the acquired A / D
- the data processing control unit 11 performs the PID calculation using the acquired A / D conversion result, and acquires the acquired A / D
- an abnormality such as a sudden change in the PID calculation result by the data processing control unit, so that the control of the temperature control system 300 can be kept stable.
- the data processing control unit 11 can deal with them as described above. It is possible to make the execution cycle of the A / D conversion process by A and the read cycle of the A / D conversion result by the data processing control unit 11 asynchronous. As a result, the data processing control unit 11 does not need to strictly define the timing for executing the constant monitoring and interrupt processing by polling, so the time restriction of the processing by the data processing control unit 11 is reduced, and the data The processing unit 11 can be easily designed.
- the read A / D is not permitted. It is possible to prevent the correspondence between the conversion result and the identification data from deviating.
- Embodiment 2 The A / D conversion circuit according to the second embodiment is different from the A / D conversion circuit 10 according to the first embodiment in that a plurality of registers for storing A / D conversion results and identification data are provided. Other points are the same as those of the A / D conversion circuit 10 according to the first embodiment.
- FIG. 5 is a diagram illustrating a configuration of a temperature regulator including an A / D conversion circuit according to the second embodiment.
- the same components as those of the temperature controller 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- the A / D conversion circuit 60 in the temperature controller 6 includes a storage unit 603 that stores an A / D conversion result and identification data.
- the storage unit 603 includes a plurality of A / D conversion result registers 604_1 to 604_n (n is an integer of 2 or more) and a plurality of identification data registers 605_1 to 605_n.
- the A / D conversion result register 604_1 and the identification data register 605_1 constitute a pair of registers 606_1.
- the A / D conversion result register 604_n and the identification data register 605_n constitute a pair of register pairs 606_n.
- the control unit 602 sends the A / D conversion result DOUT and the corresponding identification data DID to the plurality of register pairs 606_1 to 606_n. Write sequentially. For example, the control unit 602 obtains the A / D conversion result DOUT_1 by the A / D conversion process executed in a certain A / D conversion cycle and the corresponding identification data DID_1 from the A / D conversion result register 604_1 and the identification data register 605_1.
- the control unit 602 writes data to the register pairs 606_1 to 606_n in order every time the A / D conversion process is completed.
- the control unit 602 sets the oldest A / D conversion result and the identification data to the register pair in which the identification data is written. The latest A / D conversion result and identification data are overwritten.
- the transmission of the A / D conversion result from the A / D conversion circuit 60 to the data processing control unit 11 is performed by the data processing control unit 11 issuing a data read request (read command) as in the first embodiment.
- the / D conversion circuit 60 is realized by outputting the A / D conversion result DOUT and the identification data DID as a response to the read request.
- the data processing control unit 11 issues a command for requesting reading of a plurality of sets of A / D conversion results DOUT and identification data DID as the read command.
- this content will be described in detail with reference to FIGS. 6, 7A, and 7B.
- FIG. 6 is a diagram illustrating an example of assignment of addresses of the A / D conversion processing register and the identification data register.
- FIG. 7A is a diagram illustrating an example of a format of a transmission message of a data read request in the temperature controller including the A / D converter according to the second embodiment.
- FIG. 7B is a diagram illustrating an example of a response message format related to a data read request in the temperature controller including the A / D converter according to the second embodiment.
- the register pairs 606_1 to 606_n are assigned addresses in order. In this way, by sequentially assigning addresses to each of the register pairs 606_1 to 606_n, a plurality of continuous A / D conversion results and identification data can be easily read.
- a read command is issued in which the read start address is “100h” and the read number is “03h”.
- FIG. 7B data from the register addresses “100h” to “105h” is read, and A / D conversion results and identification data for three times can be acquired by one read command.
- register addresses are sequentially assigned to each of the register pairs 606_1 to 606_n, and by issuing a command designating the read start address and the read number as shown in FIG. A plurality of A / D conversion results and identification data can be acquired.
- a plurality of registers are provided as a storage unit for storing the A / D conversion result and the identification data, and the A / D conversion result and the identification data are stored.
- the A / D conversion result and the identification data for a plurality of times can be read by one read command, so that the data processing control unit 11 performs data transfer. It is possible to reduce the number of readings. This eliminates the need for high-speed and high-precision processing time management by the data processing control unit 11, facilitates the design of the data processing control unit 11, and provides a low-speed and inexpensive microcontroller (CPU) as the data processing control unit 11. Therefore, the cost can be reduced.
- CPU microcontroller
- the A / D conversion cycle by the A / D conversion circuit 10 is 1 MHz
- the A / D conversion result and the identification data are updated every 1 ⁇ s.
- the data processing control unit if the data processing control unit must read data every 1 ⁇ s as in the prior art, the data processing control unit must be operated with an operation clock corresponding to the A / D conversion processing time every 1 ⁇ s. .
- the data processing control unit executes the data reading process every (n ⁇ 1) ⁇ s. In this case, data can be acquired without missing.
- the data processing control unit may execute data read processing every 1 ms. That is, according to the A / D conversion circuit 60 according to the second embodiment, the operation clock frequency of the microcontroller as the data processing control unit 11 can be lowered as compared with the conventional case, and the cost can be reduced.
- the register is exemplified as the storage circuit that stores the A / D conversion result and the identification data, but any circuit that can store the A / D conversion result and the identification data may be used. It is not limited to registers.
- the A / D conversion circuit 60 includes one A / D conversion unit 101 .
- the present invention is not limited to this, and the A / D conversion circuit 60 includes the A / D conversion unit 101.
- a plurality may be provided.
- the address assignment of each register in the storage unit 603 is set as shown in FIG. 8, and the A / D of a plurality of channels is issued by issuing an instruction designating the read start address and the read number as described above.
- the conversion result and the identification data can be read by one read command.
- the case where the A / D conversion circuits 10 and 60 are applied to the temperature controller 1 is exemplified.
- the analog signal from the sensor or the like is periodically A / D converted, and the A The A / D conversion circuits 10 and 60 can also be applied to a recorder or the like that sequentially records the / D conversion results.
- the A / D conversion unit 101 is a ⁇ A / D conversion circuit.
- the A / D conversion unit 101 is an A / D conversion circuit of another conversion method. It may be.
- the A / D converter 101 may be a successive approximation A / D converter circuit.
- the present invention is not limited to this.
- the A / D conversion result register 104 is used as a ring buffer, and A The oldest data stored in the / D conversion result register 104 may be overwritten by the latest data.
- the analog / digital conversion circuit according to the present invention can be applied to various uses such as industrial instrumentation equipment.
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Abstract
This analog/digital conversion circuit (10) is provided with: an analog/digital conversion unit (101) that cyclically executes an analog/digital conversion process that converts an analog signal (VA) to a digital signal (DOUT); a storage unit (103); a control unit (102) that, every time the analog/digital conversion process is executed, writes to the storage unit the analog/digital conversion results (DOUT) resulting from the analog/digital conversion process and identification data (DID) associated with the analog/digital conversion results; and an output unit (106) that reads and outputs the analog/digital conversion results and corresponding identification data written to the storage unit.
Description
本発明は、アナログ/ディジタル変換回路に関する。
The present invention relates to an analog / digital conversion circuit.
プラントやビルの空調設備等に設けられる温度調節器等の計装機器は、制御対象装置の状態を監視し、制御対象装置が目標の状態になるように制御対象装置内に設けられたヒータやバルブ等を制御するものである。
例えば、下記特許文献1には、制御対象装置が目標の温度になるように制御する温度調節器が開示されている。この温度調節器は、温度センサによって検知された制御対象装置の温度の検知結果(アナログ信号)を周期的にディジタル信号に変換して測定データを生成するアナログ/ディジタル変換回路(以下、「A/D変換回路」とも称する。)と、連続した上記測定データを用いてPID(Proportional Integral Derivative)演算を行うデータ処理部(CPU等のプロセッサ)とを備えている。 Instrumentation equipment such as a temperature controller provided in a plant or building air conditioner, etc. monitors the state of the controlled device, and includes a heater or a heater provided in the controlled device so that the controlled device is in a target state. Controls valves and the like.
For example,Patent Document 1 below discloses a temperature regulator that controls a control target device so as to reach a target temperature. This temperature controller is an analog / digital conversion circuit (hereinafter referred to as “A / D”) that periodically converts the detection result (analog signal) of the temperature of the control target device detected by the temperature sensor into a digital signal. And a data processing unit (processor such as a CPU) that performs PID (Proportional Integral Derivative) computation using the continuous measurement data.
例えば、下記特許文献1には、制御対象装置が目標の温度になるように制御する温度調節器が開示されている。この温度調節器は、温度センサによって検知された制御対象装置の温度の検知結果(アナログ信号)を周期的にディジタル信号に変換して測定データを生成するアナログ/ディジタル変換回路(以下、「A/D変換回路」とも称する。)と、連続した上記測定データを用いてPID(Proportional Integral Derivative)演算を行うデータ処理部(CPU等のプロセッサ)とを備えている。 Instrumentation equipment such as a temperature controller provided in a plant or building air conditioner, etc. monitors the state of the controlled device, and includes a heater or a heater provided in the controlled device so that the controlled device is in a target state. Controls valves and the like.
For example,
温度調節器等の計装機器は、制御対象装置の状態の変化を的確に把握し、状態の変化に応じて適切な制御を行う必要がある。そのため、温度調節器等の計装機器は、センサの検知結果を周期的にA/D変換し、連続したA/D変換結果を欠落なくCPU等のデータ処理部に送信しなければならない。仮に、データ処理部側において測定データの欠落があった場合には、測定データの連続性が失われる。測定データの連続性が失われた状態において、上記データ処理部が例えば微分演算のようなPID演算を行った場合、その演算によって算出された操作量が意図しない値に急変し、制御結果が不安定になる虞がある。
Instrumentation equipment such as a temperature controller needs to accurately grasp the change in the state of the controlled device and perform appropriate control according to the change in the state. Therefore, an instrumentation device such as a temperature controller must periodically A / D convert the detection result of the sensor and transmit the continuous A / D conversion result to a data processing unit such as a CPU without omission. If there is missing measurement data on the data processing unit side, the continuity of the measurement data is lost. When the data processing unit performs a PID operation such as a differential operation in a state where the continuity of the measurement data is lost, the operation amount calculated by the operation suddenly changes to an unintended value, and the control result is not good. There is a risk of becoming stable.
しかしながら、上記データ処理部が、A/D変換回路によって周期的に更新されるA/D変換結果を漏れなく確実に取得できるようにすることは容易ではない。そこで、上記データ処理部が、取得したデータの連続性が保たれているか否かを判断し、データの連続性が保たれている場合にのみ取得したデータをPID演算に用いることにより、PID演算による操作量の急変等の異常が起こることを回避し、制御の安定性を保つことが可能となる。しかしながら、従来の温度調節器等の計装機器では、上記データ処理部が、取得したA/D変換結果の連続性が保たれているか否かを判断できなかった。
However, it is not easy for the data processing unit to reliably acquire the A / D conversion result periodically updated by the A / D conversion circuit without omission. Therefore, the data processing unit determines whether or not the continuity of the acquired data is maintained, and uses the acquired data for the PID calculation only when the continuity of the data is maintained. It is possible to avoid abnormalities such as a sudden change in the operation amount due to the control and to maintain control stability. However, in a conventional instrument such as a temperature controller, the data processing unit cannot determine whether the continuity of the acquired A / D conversion result is maintained.
例えば、一般的に、A/D変換回路とCPU等のデータ処理部とは別個の半導体チップによって構成されている。これらのチップを近接して配置できない場合には、二つの半導体チップに単一の発振子から同一のクロック信号を供給することができないことがある。このような場合には、上記半導体チップ毎に発振子を設ける必要がある。しかしながら、発振子を個別に設けた場合、それぞれの発振子のクロックを用いることにより、A/D変換処理が実行される周期とA/D変換結果の読み出し周期とが一致するようにA/D変換回路とデータ処理部を動作させたとしても、実際には、双方の動作周期に発振子の個体差や性能の違いに基づく誤差が生じる。その誤差が累積した場合、上記データ処理部が、上記A/D変換回路から同じA/D変換結果を2回取得してしまう可能性がある。仮に上記データ処理部が同じA/D変換結果を2回取得した場合、上記データ処理部は、取得したデータを見るだけでは、1回のA/D変換周期におけるA/D変換結果を2回取得したのか、それともたまたま入力値が安定していたため、連続した2回のA/D変換周期における夫々のA/D変換結果が同一値となったのかを判断することができなかった。
For example, in general, an A / D conversion circuit and a data processing unit such as a CPU are configured by separate semiconductor chips. If these chips cannot be arranged close to each other, the same clock signal may not be supplied from two oscillator chips from a single oscillator. In such a case, it is necessary to provide an oscillator for each semiconductor chip. However, when the oscillators are individually provided, by using the clocks of the respective oscillators, the A / D conversion process is executed and the A / D conversion result read period coincides with the A / D conversion result readout period. Even if the conversion circuit and the data processing unit are operated, an error based on an individual difference of oscillators or a difference in performance actually occurs in both operation cycles. If the errors accumulate, the data processing unit may acquire the same A / D conversion result twice from the A / D conversion circuit. If the data processing unit acquires the same A / D conversion result twice, the data processing unit only needs to look at the acquired data twice to obtain the A / D conversion result in one A / D conversion cycle. It was not possible to determine whether each A / D conversion result in the two consecutive A / D conversion periods had the same value because the input value was stable or it happened to be acquired.
また、上記問題の対策として、例えば、A/D変換処理の完了の有無に応じてA/D変換回路が形成された半導体チップのポートのオン/オフ状態を切り替えるとともに、データ処理部がそのポートのオン・オフ状態の切り替わりをポーリングまたは割り込み処理により検知し、その検知結果に基づいてA/D変換結果の読み出し処理を実行するという手法も考えられる。
しかしながら、この手法では、ポーリングによる判定処理や割り込み処理の後に実行するA/D変換結果の読み出し処理が遅れた場合、目的とするA/D変換周期のA/D変換結果を取得できずに、次のA/D変換周期のA/D変換結果を取得してしまう可能性がある。上記データ処理部が目的とするA/D変換周期のA/D変換結果を取りこぼした場合、上記データ処理部は、取得したデータを見るだけでは、1周期分のA/D変換結果を取りこぼしたか否かを判断することができなかった。なお、A/D変換結果の読み出し処理が遅れないようにするために、A/D変換処理を実行するタイミングやA/D変換結果を読み出すタイミングを厳密に規定することもできるが、データ処理部側の処理の時間的な制約が多くなり、データ処理部の設計が複雑になるという問題があった。 Further, as a countermeasure against the above problem, for example, the on / off state of the port of the semiconductor chip on which the A / D conversion circuit is formed is switched according to whether the A / D conversion process is completed, and the data processing unit A method is also conceivable in which the on / off state switching is detected by polling or interrupt processing, and the A / D conversion result read processing is executed based on the detection result.
However, in this method, when the A / D conversion result read process executed after the polling determination process or the interrupt process is delayed, the A / D conversion result of the target A / D conversion cycle cannot be acquired. There is a possibility of acquiring an A / D conversion result of the next A / D conversion cycle. When the data processing unit misses the A / D conversion result of the target A / D conversion cycle, does the data processing unit miss the A / D conversion result for one cycle only by looking at the acquired data? It was not possible to judge whether or not. In order to keep the reading process of the A / D conversion result from being delayed, the timing for executing the A / D conversion process and the timing for reading the A / D conversion result can be strictly defined. There is a problem that the time restriction of the processing on the side increases and the design of the data processing unit becomes complicated.
しかしながら、この手法では、ポーリングによる判定処理や割り込み処理の後に実行するA/D変換結果の読み出し処理が遅れた場合、目的とするA/D変換周期のA/D変換結果を取得できずに、次のA/D変換周期のA/D変換結果を取得してしまう可能性がある。上記データ処理部が目的とするA/D変換周期のA/D変換結果を取りこぼした場合、上記データ処理部は、取得したデータを見るだけでは、1周期分のA/D変換結果を取りこぼしたか否かを判断することができなかった。なお、A/D変換結果の読み出し処理が遅れないようにするために、A/D変換処理を実行するタイミングやA/D変換結果を読み出すタイミングを厳密に規定することもできるが、データ処理部側の処理の時間的な制約が多くなり、データ処理部の設計が複雑になるという問題があった。 Further, as a countermeasure against the above problem, for example, the on / off state of the port of the semiconductor chip on which the A / D conversion circuit is formed is switched according to whether the A / D conversion process is completed, and the data processing unit A method is also conceivable in which the on / off state switching is detected by polling or interrupt processing, and the A / D conversion result read processing is executed based on the detection result.
However, in this method, when the A / D conversion result read process executed after the polling determination process or the interrupt process is delayed, the A / D conversion result of the target A / D conversion cycle cannot be acquired. There is a possibility of acquiring an A / D conversion result of the next A / D conversion cycle. When the data processing unit misses the A / D conversion result of the target A / D conversion cycle, does the data processing unit miss the A / D conversion result for one cycle only by looking at the acquired data? It was not possible to judge whether or not. In order to keep the reading process of the A / D conversion result from being delayed, the timing for executing the A / D conversion process and the timing for reading the A / D conversion result can be strictly defined. There is a problem that the time restriction of the processing on the side increases and the design of the data processing unit becomes complicated.
本発明の目的は、周期的にA/D変換を行うA/D変換回路から連続的に複数のA/D変換結果を取得する回路において、取得した上記複数のA/D変換結果の連続性が保たれているか否かを判断できるようにすることにある。
An object of the present invention is to provide a continuity of a plurality of acquired A / D conversion results in a circuit that continuously acquires a plurality of A / D conversion results from an A / D conversion circuit that periodically performs A / D conversion. It is to be able to determine whether or not the above is maintained.
本発明に係るアナログ/ディジタル変換回路は、入力したアナログ信号をディジタル信号に変換するアナログ/ディジタル変換処理を周期的に実行するアナログ/ディジタル変換部と、記憶部と、前記アナログ/ディジタル変換部によって前記アナログ/ディジタル変換処理が実行される毎に、前記アナログ/ディジタル変換処理によるアナログ/ディジタル変換結果と、前記アナログ/ディジタル変換結果に対応付けられた識別データとを前記記憶部に書き込む制御部と、前記記憶部に書き込まれた前記アナログ/ディジタル変換結果と、対応する前記識別データとを読み出して出力する出力部とを備える。
An analog / digital conversion circuit according to the present invention includes an analog / digital conversion unit that periodically executes an analog / digital conversion process for converting an input analog signal into a digital signal, a storage unit, and the analog / digital conversion unit. A controller that writes an analog / digital conversion result by the analog / digital conversion process and identification data associated with the analog / digital conversion result to the storage unit each time the analog / digital conversion process is executed; And an output unit that reads out and outputs the analog / digital conversion result written in the storage unit and the corresponding identification data.
以上説明したことにより、本発明によれば、周期的にA/D変換を行うA/D変換回路から連続的に複数のA/D変換結果を取得する回路は、取得した上記複数のA/D変換結果の連続性が保たれているか否かを判断することができる。
As described above, according to the present invention, a circuit that continuously acquires a plurality of A / D conversion results from an A / D conversion circuit that periodically performs A / D conversion can be obtained by using the acquired A / D conversion results. It can be determined whether or not the continuity of the D conversion result is maintained.
先ず、本発明に係るアナログ/ディジタル変換回路の概要について説明する。
本発明に係るアナログ/ディジタル変換回路は、入力したアナログ信号をディジタル信号に変換するアナログ/ディジタル変換処理を周期的に実行するアナログ/ディジタル変換部と、記憶部と、前記アナログ/ディジタル変換部によって前記アナログ/ディジタル変換処理が実行される毎に、前記アナログ/ディジタル変換処理によるアナログ/ディジタル変換結果と、前記アナログ/ディジタル変換結果に対応付けられた識別データとを前記記憶部に書き込む制御部と、前記記憶部に書き込まれた前記アナログ/ディジタル変換結果と、対応する前記識別データとを読み出して出力する出力部とを備える。 First, an outline of an analog / digital conversion circuit according to the present invention will be described.
An analog / digital conversion circuit according to the present invention includes an analog / digital conversion unit that periodically executes an analog / digital conversion process for converting an input analog signal into a digital signal, a storage unit, and the analog / digital conversion unit. A controller that writes an analog / digital conversion result by the analog / digital conversion process and identification data associated with the analog / digital conversion result to the storage unit each time the analog / digital conversion process is executed; And an output unit that reads out and outputs the analog / digital conversion result written in the storage unit and the corresponding identification data.
本発明に係るアナログ/ディジタル変換回路は、入力したアナログ信号をディジタル信号に変換するアナログ/ディジタル変換処理を周期的に実行するアナログ/ディジタル変換部と、記憶部と、前記アナログ/ディジタル変換部によって前記アナログ/ディジタル変換処理が実行される毎に、前記アナログ/ディジタル変換処理によるアナログ/ディジタル変換結果と、前記アナログ/ディジタル変換結果に対応付けられた識別データとを前記記憶部に書き込む制御部と、前記記憶部に書き込まれた前記アナログ/ディジタル変換結果と、対応する前記識別データとを読み出して出力する出力部とを備える。 First, an outline of an analog / digital conversion circuit according to the present invention will be described.
An analog / digital conversion circuit according to the present invention includes an analog / digital conversion unit that periodically executes an analog / digital conversion process for converting an input analog signal into a digital signal, a storage unit, and the analog / digital conversion unit. A controller that writes an analog / digital conversion result by the analog / digital conversion process and identification data associated with the analog / digital conversion result to the storage unit each time the analog / digital conversion process is executed; And an output unit that reads out and outputs the analog / digital conversion result written in the storage unit and the corresponding identification data.
上記アナログ/ディジタル変換回路において、前記制御部は、前記アナログ/ディジタル変換部による前記アナログ/ディジタル変換結果と前記識別データの双方の前記記憶部に対する書き込みが完了するまで、前記出力部による前記記憶部の読み出しを許可しないようにしてもよい。
In the analog / digital conversion circuit, the control unit performs the storage unit by the output unit until writing of both the analog / digital conversion result and the identification data by the analog / digital conversion unit to the storage unit is completed. May not be allowed to be read.
上記アナログ/ディジタル変換回路において、前記識別データは、前記アナログ/ディジタル変換部によるアナログ/ディジタル変換処理の実行回数を示すデータであってもよい。
In the analog / digital conversion circuit, the identification data may be data indicating the number of executions of the analog / digital conversion processing by the analog / digital conversion unit.
上記アナログ/ディジタル変換回路において、前記識別データは、前記アナログ/ディジタル変換部によって前記アナログ/ディジタル変換処理が実行された時刻を示すデータであってもよい。
In the analog / digital conversion circuit, the identification data may be data indicating a time when the analog / digital conversion processing is executed by the analog / digital conversion unit.
上記アナログ/ディジタル変換回路において、前記識別データは、前記アナログ/ディジタル変換部によって前記アナログ/ディジタル変換処理が実行される毎に論理レベルが反転する1ビットのデータであってもよい。
In the analog / digital conversion circuit, the identification data may be 1-bit data whose logic level is inverted every time the analog / digital conversion process is executed by the analog / digital conversion unit.
上記アナログ/ディジタル変換回路において、前記識別データは、フリーランカウンタのカウント値に基づくデータであってもよい。
In the analog / digital conversion circuit, the identification data may be data based on a count value of a free-run counter.
上記アナログ/ディジタル変換回路において、前記記憶部は、前記アナログ/ディジタル変換処理による前記アナログ/ディジタル変換結果を記憶する第1レジスタと、前記識別データを記憶する第2レジスタとを一組とするレジスタ対を複数有し、前記制御部は、前記アナログ/ディジタル変換処理が実行される毎に、実行されたアナログ/ディジタル変換処理の前記アナログ/ディジタル変換結果と前記識別データとを前記レジスタ対に順次書き込み、前記出力部は、外部から入力された読み出し要求に応答して、複数の前記レジスタ対から複数回分の前記アナログ/ディジタル変換処理に係る前記アナログ/ディジタル変換結果および前記識別データを読み出すようにしてもよい。
In the analog / digital conversion circuit, the storage unit is a register including a first register that stores the analog / digital conversion result obtained by the analog / digital conversion process and a second register that stores the identification data. Each time the analog / digital conversion process is executed, the control unit sequentially stores the analog / digital conversion result of the executed analog / digital conversion process and the identification data in the register pair. In response to a read request input from the outside, the writing and the output unit read the analog / digital conversion result and the identification data related to the analog / digital conversion processing for a plurality of times from the plurality of register pairs. May be.
以下、本発明に係るアナログ/ディジタル変換回路の実施の形態を図面に基づいて詳細に説明する。
Hereinafter, embodiments of an analog / digital conversion circuit according to the present invention will be described in detail with reference to the drawings.
≪実施の形態1≫
図1は、実施の形態1に係るA/D変換回路を含む温度調節器を備えた温度調節システムの構成を示す図である。
同図に示される温度調節システム300は、温度調節器1、制御対象装置2、温度センサ3、操作部4、およびヒータ5を備えている。 <<Embodiment 1 >>
FIG. 1 is a diagram showing a configuration of a temperature control system including a temperature controller including an A / D conversion circuit according to the first embodiment.
Atemperature control system 300 shown in the figure includes a temperature controller 1, a control target device 2, a temperature sensor 3, an operation unit 4, and a heater 5.
図1は、実施の形態1に係るA/D変換回路を含む温度調節器を備えた温度調節システムの構成を示す図である。
同図に示される温度調節システム300は、温度調節器1、制御対象装置2、温度センサ3、操作部4、およびヒータ5を備えている。 <<
FIG. 1 is a diagram showing a configuration of a temperature control system including a temperature controller including an A / D conversion circuit according to the first embodiment.
A
温度センサ3は、制御対象装置2の温度を検知し、アナログ形式の検知信号(以下、「アナログ信号」とも称する。)VAを出力する。ヒータ5は、例えば制御対象装置2の内部に設けられ、制御対象装置2を加熱する装置である。操作部4は、ヒータ5の加熱温度を調節する装置である。例えば、操作部4は、温度調節器2からから供給された制御信号CNTに基づいてヒータ5に供給する電流または電圧を変化させることにより、ヒータ5の加熱温度を調整する。
The temperature sensor 3 detects the temperature of the control target device 2 and outputs an analog detection signal (hereinafter also referred to as “analog signal”) VA. The heater 5 is, for example, a device that is provided inside the control target device 2 and heats the control target device 2. The operation unit 4 is a device that adjusts the heating temperature of the heater 5. For example, the operation unit 4 adjusts the heating temperature of the heater 5 by changing the current or voltage supplied to the heater 5 based on the control signal CNT supplied from the temperature controller 2.
温度調節器1は、温度センサ3から出力されたアナログ信号VAを周期的にディジタル信号に変換し、変換したディジタル信号(測定データ)を用いてPID演算を行うことにより、制御対象装置2が目標の温度になるように制御信号CNTを生成する。
図2は、実施の形態1に係るA/D変換回路を含む温度調節器1の構成を示す図である。
図2に示されるように、温度調節器1は、A/D変換回路10、データ処理制御部11、およびその他図示されていない電源回路や外部入出力インターフェース回路等を備えている。 Thetemperature controller 1 periodically converts the analog signal VA output from the temperature sensor 3 into a digital signal, and performs a PID operation using the converted digital signal (measurement data), so that the control target device 2 can perform the target operation. The control signal CNT is generated so that the temperature becomes.
FIG. 2 is a diagram illustrating a configuration of thetemperature regulator 1 including the A / D conversion circuit according to the first embodiment.
As shown in FIG. 2, thetemperature controller 1 includes an A / D conversion circuit 10, a data processing control unit 11, and other power supply circuits and external input / output interface circuits not shown.
図2は、実施の形態1に係るA/D変換回路を含む温度調節器1の構成を示す図である。
図2に示されるように、温度調節器1は、A/D変換回路10、データ処理制御部11、およびその他図示されていない電源回路や外部入出力インターフェース回路等を備えている。 The
FIG. 2 is a diagram illustrating a configuration of the
As shown in FIG. 2, the
A/D変換回路10は、温度センサ3から出力されたアナログ信号VINをディジタル信号に変換する回路である。A/D変換回路10は、A/D変換結果を出力することのみならず、そのA/D変換結果に対応付けられた識別データを後段のデータ処理制御部11に出力する機能も有している。
The A / D conversion circuit 10 is a circuit that converts the analog signal VIN output from the temperature sensor 3 into a digital signal. The A / D conversion circuit 10 not only outputs the A / D conversion result but also has a function of outputting the identification data associated with the A / D conversion result to the data processing control unit 11 at the subsequent stage. Yes.
具体的に、A/D変換回路10は、A/D変換部101、制御部102、記憶部103、および通信回路106を含む。A/D変換回路10は、例えば、A/D変換部101、制御部102、記憶部103、および通信回路106が公知のCMOS製造プロセスによって1個の半導体基板に形成された1チップの半導体装置として実現されている。
Specifically, the A / D conversion circuit 10 includes an A / D conversion unit 101, a control unit 102, a storage unit 103, and a communication circuit 106. The A / D conversion circuit 10 is, for example, a one-chip semiconductor device in which an A / D conversion unit 101, a control unit 102, a storage unit 103, and a communication circuit 106 are formed on one semiconductor substrate by a known CMOS manufacturing process. It is realized as.
A/D変換部101は、温度センサ3から出力されたアナログ信号VINをディジタル信号に変換するA/D変換処理を周期的に実行する。例えば、A/D変換部101は、一定の周期で(例えば10ms毎に)、アナログ信号VINをディジタル信号DOUTに変換して出力する。A/D変換部101は、例えばΔΣ型のA/D変換器である。なお、以下の説明では、A/D変換部10によって変換されたディジタル信号DOUTを、A/D変換結果DOUTとも称する。
The A / D converter 101 periodically executes A / D conversion processing for converting the analog signal VIN output from the temperature sensor 3 into a digital signal. For example, the A / D conversion unit 101 converts the analog signal VIN into the digital signal DOUT and outputs it at a constant cycle (for example, every 10 ms). The A / D converter 101 is, for example, a ΔΣ type A / D converter. In the following description, the digital signal DOUT converted by the A / D conversion unit 10 is also referred to as an A / D conversion result DOUT.
制御部102は、A/D変換部10によるA/D変換処理が完了する毎に、完了したA/D変換処理のA/D変換結果DOUTを記憶部103に書き込むとともに、そのA/D変換結果DOUTに対応付けた識別データDIDを記憶部103に書き込む。
ここで、識別データDIDとは、あるタイミングで実行されたA/D変換処理による変換結果とその前後のタイミングで実行されたA/D変換処理による変換結果とを識別するためのデータである。なお、識別データDIDの詳細については後述する。 Each time the A / D conversion process by the A /D conversion unit 10 is completed, the control unit 102 writes the A / D conversion result DOUT of the completed A / D conversion process in the storage unit 103 and also performs the A / D conversion. The identification data DID associated with the result DOUT is written in the storage unit 103.
Here, the identification data DID is data for identifying a conversion result by an A / D conversion process executed at a certain timing and a conversion result by an A / D conversion process executed at a timing before and after that. Details of the identification data DID will be described later.
ここで、識別データDIDとは、あるタイミングで実行されたA/D変換処理による変換結果とその前後のタイミングで実行されたA/D変換処理による変換結果とを識別するためのデータである。なお、識別データDIDの詳細については後述する。 Each time the A / D conversion process by the A /
Here, the identification data DID is data for identifying a conversion result by an A / D conversion process executed at a certain timing and a conversion result by an A / D conversion process executed at a timing before and after that. Details of the identification data DID will be described later.
更に、制御部102は、後述する通信回路106による記憶部103に対するデータの読み出しの許可・不許可を指示するイネーブル信号ENを出力する。例えば、制御部102は、A/D変換結果DOUTとそのA/D変換結果DOUTに対応する識別データDINの記憶部103に対する書き込みが完了するまでイネーブル信号ENを無効な状態にすることにより、記憶部103からのデータの読み出しを禁止し、A/D変換結果DOUTと識別データDINの双方のデータの書き込みが完了したら、イネーブル信号ENを有効な状態にすることにより、記憶部103からのデータの読み出しを許可する。これにより、A/D変換結果DOUTと識別データDIDの一方しか書き換え(更新)が完了していない状況における記憶部103からのデータの読み出しが禁止され、読み出されたA/D変換結果と識別データとの対応関係がずれることを防止することができる。
Further, the control unit 102 outputs an enable signal EN instructing permission / non-permission of data reading from the storage unit 103 by the communication circuit 106 described later. For example, the control unit 102 stores the A / D conversion result DOUT and the enable signal EN in an invalid state until the writing of the identification data DIN corresponding to the A / D conversion result DOUT to the storage unit 103 is completed. When reading of data from the unit 103 is prohibited and writing of both the A / D conversion result DOUT and the identification data DIN is completed, the enable signal EN is set to a valid state, whereby the data from the storage unit 103 is read. Allow reading. As a result, reading of data from the storage unit 103 in a situation where only one of the A / D conversion result DOUT and the identification data DID has been rewritten (updated) is prohibited, and the read A / D conversion result is identified. It is possible to prevent the correspondence relationship with data from deviating.
記憶部103は、データを記憶するための記憶領域を備えた回路から構成され、A/D変換結果DOUTと識別データDIDとを記憶する。具体的に、記憶部103は、A/D変換結果DOUTを記憶するための記憶回路としてA/D変換結果レジスタ104を有し、識別データDIDを記憶するための記憶回路として識別データレジスタ105を有している。
The storage unit 103 includes a circuit having a storage area for storing data, and stores the A / D conversion result DOUT and the identification data DID. Specifically, the storage unit 103 includes an A / D conversion result register 104 as a storage circuit for storing the A / D conversion result DOUT, and an identification data register 105 as a storage circuit for storing the identification data DID. Have.
A/D変換結果レジスタ104および識別データレジスタ105は、制御部102によるデータの書き換えと、通信回路106によるデータの読み出しが可能にされている。例えば、A/D変換部10によるA/D変換処理が完了する毎に、制御部102が、完了したA/D変換処理のA/D変換結果OUTとそれに対応する識別データDIDとをA/D変換結果レジスタ104および識別データレジスタ105に書き込むことにより、A/D変換結果レジスタ104および識別データレジスタ105の値が更新される。A/D変換結果レジスタ104および識別データレジスタ105に記憶されたA/D変換結果DOUTおよび識別データDIDは、通信回路106によって定期的に読み出される。
The A / D conversion result register 104 and the identification data register 105 can be rewritten by the control unit 102 and read by the communication circuit 106. For example, every time the A / D conversion process by the A / D conversion unit 10 is completed, the control unit 102 displays the A / D conversion result OUT of the completed A / D conversion process and the identification data DID corresponding thereto as A / D By writing to the D conversion result register 104 and the identification data register 105, the values of the A / D conversion result register 104 and the identification data register 105 are updated. The A / D conversion result DOUT and the identification data DID stored in the A / D conversion result register 104 and the identification data register 105 are periodically read by the communication circuit 106.
通信回路106は、記憶部103からデータを読み出して出力する出力部として機能する。具体的に、通信回路106は、データ処理制御部11からのデータの読み出し要求に応答して、記憶部103に書き込まれたA/D変換結果DOUTと識別データDIDとを読み出し、読み出した2つのデータをデータ処理制御部11に送信する。より具体的には、通信回路106は、データ処理制御部11からデータの読み出し要求を受け取ったとき、イネーブル信号ENが有効な状態である場合には、記憶部103からA/D変換結果DOUTと識別データDIDとを読み出してデータ処理制御部11に送信し、イネーブル信号ENが無効な状態である場合には、イネーブル信号ENが有効な状態になるまで待機する。そして、イネーブル信号ENが有効な状態になったら、記憶部103からA/D変換結果DOUTと識別データDIDとを読み出してデータ処理制御部11に送信する。
The communication circuit 106 functions as an output unit that reads and outputs data from the storage unit 103. Specifically, in response to a data read request from the data processing control unit 11, the communication circuit 106 reads the A / D conversion result DOUT and the identification data DID written in the storage unit 103, and reads the two read Data is transmitted to the data processing control unit 11. More specifically, when the communication circuit 106 receives a data read request from the data processing control unit 11 and the enable signal EN is in a valid state, the communication circuit 106 receives the A / D conversion result DOUT from the storage unit 103. The identification data DID is read and transmitted to the data processing control unit 11, and when the enable signal EN is in an invalid state, the process waits until the enable signal EN is in an effective state. When the enable signal EN becomes valid, the A / D conversion result DOUT and the identification data DID are read from the storage unit 103 and transmitted to the data processing control unit 11.
データ処理制御部11は、例えばマイクロコントローラであり、CPU111、記憶装置112、通信回路113、および図示されていない外部インターフェース回路等を備えている。例えば、データ処理制御部11は、CPU111、記憶装置112、および通信回路113等が一つの半導体基板に形成された1チップのマイクロコントローラとして構成されていてもよいし、CPU111、記憶装置112、および通信回路113等が夫々別個の半導体チップに形成されたマルチチップ構成のマイクロコントローラとして構成されていてもよい。
The data processing control unit 11 is a microcontroller, for example, and includes a CPU 111, a storage device 112, a communication circuit 113, an external interface circuit (not shown), and the like. For example, the data processing control unit 11 may be configured as a one-chip microcontroller in which the CPU 111, the storage device 112, the communication circuit 113, and the like are formed on one semiconductor substrate, or the CPU 111, the storage device 112, and The communication circuit 113 or the like may be configured as a multi-chip microcontroller formed on separate semiconductor chips.
通信回路113は、外部回路と通信を行うための回路である。例えば、通信回路113は、CPU111からの指示に応じてデータの読み出し要求をA/D変換回路10に対して発行するとともに、発行した読み出し要求に応じてA/D変換回路10から出力されたA/D変換結果DOUTおよび識別データDIDを受信する。通信回路113によって受信したA/D変換結果DOUTおよび識別データDIDは、例えば記憶装置112に記憶される。
The communication circuit 113 is a circuit for performing communication with an external circuit. For example, the communication circuit 113 issues a data read request to the A / D conversion circuit 10 in accordance with an instruction from the CPU 111, and the A output from the A / D conversion circuit 10 in response to the issued read request. / D conversion result DOUT and identification data DID are received. The A / D conversion result DOUT and the identification data DID received by the communication circuit 113 are stored in the storage device 112, for example.
記憶装置112は、ROM(Read Only Memory)やRAM(Random Access Memory)、複数のレジスタ等を含む。例えば、ROMには、CPU111に各種の演算を実行させるためのプログラムが記憶され、上記複数のレジスタには、通信回路113で受信したA/D変換結果DOUTや識別データDID等が記憶され、RAMには、ROMから読み出されて展開されたプログラムやCPU111による演算結果等が記憶される。
The storage device 112 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a plurality of registers, and the like. For example, the ROM stores a program for causing the CPU 111 to execute various calculations, and the plurality of registers store the A / D conversion result DOUT received by the communication circuit 113, the identification data DID, and the like. Stores the program read from the ROM and expanded, the calculation result by the CPU 111, and the like.
CPU111は、記憶装置112に記憶されたプログラムに従って各種の演算を行うことにより、温度調節器1の統括的な制御を行う。また、CPU111は、記憶装置112に記憶されているA/D変換結果DOUTに基づいてPID演算を行うことにより、制御対象装置2が目標の温度になるように制御信号CNTを生成する。CPU111によって生成された制御信号CNTは、図示されていない外部インターフェース回路を介して操作部4に供給され、前述したようにヒータ5の加熱温度の制御に利用される。
The CPU 111 performs overall control of the temperature controller 1 by performing various calculations in accordance with programs stored in the storage device 112. Further, the CPU 111 generates a control signal CNT so that the control target device 2 reaches a target temperature by performing a PID calculation based on the A / D conversion result DOUT stored in the storage device 112. The control signal CNT generated by the CPU 111 is supplied to the operation unit 4 via an external interface circuit (not shown) and is used for controlling the heating temperature of the heater 5 as described above.
次に、識別データDIDについて詳細に説明する。
前述したように、A/D変換回路10は、A/D変換結果DOUTに加えて、そのA/D変換結果DOUTに対応付けられた識別データDIDを後段のデータ処理制御部11に出力する。識別データDIDの生成手法として、例えば以下の4つを例示することができる。 Next, the identification data DID will be described in detail.
As described above, the A /D conversion circuit 10 outputs the identification data DID associated with the A / D conversion result DOUT to the subsequent data processing control unit 11 in addition to the A / D conversion result DOUT. As a method for generating the identification data DID, for example, the following four can be exemplified.
前述したように、A/D変換回路10は、A/D変換結果DOUTに加えて、そのA/D変換結果DOUTに対応付けられた識別データDIDを後段のデータ処理制御部11に出力する。識別データDIDの生成手法として、例えば以下の4つを例示することができる。 Next, the identification data DID will be described in detail.
As described above, the A /
第1の例は、A/D変換処理の実行回数に基づくデータから識別データDIDを生成する手法である。
図3Aは、A/D変換処理の実行回数に基づくデータを識別データDIDとした場合の一例を示す図である。
同図に示されるように、A/D変換回路10がA/D変換処理の実行回数をカウントし、そのカウント値を識別データDIDとする。具体的には、制御部102内にカウンタを設け、A/D変換部10からA/D変換結果DOUTが出力される毎に、上記カウンタのカウント値がインクリメントされる。制御部102は、A/D変換部10からA/D変換結果DOUTが出力される毎に、A/D変換結果DOUTをA/D変換結果レジスタ105に書き込むとともに、その時の上記カウンタのカウント値を識別データレジスタ105に書き込む。 The first example is a technique for generating identification data DID from data based on the number of execution times of A / D conversion processing.
FIG. 3A is a diagram illustrating an example when data based on the number of executions of the A / D conversion process is used as identification data DID.
As shown in the figure, the A /D conversion circuit 10 counts the number of executions of the A / D conversion process, and uses the count value as identification data DID. Specifically, a counter is provided in the control unit 102, and the count value of the counter is incremented each time the A / D conversion result DOUT is output from the A / D conversion unit 10. Whenever the A / D conversion result DOUT is output from the A / D conversion unit 10, the control unit 102 writes the A / D conversion result DOUT into the A / D conversion result register 105, and the count value of the counter at that time Is written into the identification data register 105.
図3Aは、A/D変換処理の実行回数に基づくデータを識別データDIDとした場合の一例を示す図である。
同図に示されるように、A/D変換回路10がA/D変換処理の実行回数をカウントし、そのカウント値を識別データDIDとする。具体的には、制御部102内にカウンタを設け、A/D変換部10からA/D変換結果DOUTが出力される毎に、上記カウンタのカウント値がインクリメントされる。制御部102は、A/D変換部10からA/D変換結果DOUTが出力される毎に、A/D変換結果DOUTをA/D変換結果レジスタ105に書き込むとともに、その時の上記カウンタのカウント値を識別データレジスタ105に書き込む。 The first example is a technique for generating identification data DID from data based on the number of execution times of A / D conversion processing.
FIG. 3A is a diagram illustrating an example when data based on the number of executions of the A / D conversion process is used as identification data DID.
As shown in the figure, the A /
上記カウンタとしては、例えばA/D変換処理の実行回数をカウントするカウンタを例示することができる。例えば、図3Aには、8ビットのカウンタが、A/D変換処理の実行回数をカウントし、A/D変換処理の実行回数を256回目までカウントしたらそのカウント値をリセットするともに、257回目から再び“0”からカウント動作を開始する場合が示されている。
As the counter, for example, a counter that counts the number of execution times of A / D conversion processing can be exemplified. For example, in FIG. 3A, an 8-bit counter counts the number of executions of the A / D conversion process, resets the count value when the number of executions of the A / D conversion process is counted up to the 256th time, and starts from the 257th time. The case where the count operation starts again from “0” is shown.
上記のようにA/D変換処理の実行回数を識別データDIDとして記録することにより、あるタイミングで実行されたA/D変換処理によるA/D変換結果とその前後のタイミングで実行されたA/D変換処理によるA/D変換結果とを識別することが可能となる。
By recording the number of executions of the A / D conversion process as the identification data DID as described above, the A / D conversion result by the A / D conversion process executed at a certain timing and the A / D executed at the timing before and after the A / D conversion process are recorded. It becomes possible to identify the A / D conversion result by the D conversion process.
なお、図3Aには上記カウンタとして8ビットカウンタを例示したが、温度調節器1のデバッグのために、過去に実行したA/D変換回数を記憶したい場合には、ビット数がより大きいカウンタを用いればよい。
例えば、A/D変換処理が1ms間隔で実行される場合に、32ビットのカウンタを用いることにより、約49日分のA/D変換処理の実行回数を記録することが可能となる。 また、例えば40ビットのカウンタを用いることにより、約34年のA/D変換の実行回数を記録することが可能となり、一般的な製品の寿命を超えるような実行回数を連続して記録することも可能になる。さらに、一般的な設計において、32ビット程度のカウンタを用意することが可能であるので、必要に応じてビット数を増やすことが可能である。 In FIG. 3A, an 8-bit counter is exemplified as the counter. However, in order to store the number of A / D conversions executed in the past for debugging thetemperature controller 1, a counter having a larger number of bits is used. Use it.
For example, when the A / D conversion process is executed at an interval of 1 ms, it is possible to record the number of executions of the A / D conversion process for about 49 days by using a 32-bit counter. For example, by using a 40-bit counter, it is possible to record the number of executions of A / D conversion in about 34 years, and continuously record the number of executions exceeding the life of a general product. Is also possible. Further, in a general design, a counter of about 32 bits can be prepared, so that the number of bits can be increased as necessary.
例えば、A/D変換処理が1ms間隔で実行される場合に、32ビットのカウンタを用いることにより、約49日分のA/D変換処理の実行回数を記録することが可能となる。 また、例えば40ビットのカウンタを用いることにより、約34年のA/D変換の実行回数を記録することが可能となり、一般的な製品の寿命を超えるような実行回数を連続して記録することも可能になる。さらに、一般的な設計において、32ビット程度のカウンタを用意することが可能であるので、必要に応じてビット数を増やすことが可能である。 In FIG. 3A, an 8-bit counter is exemplified as the counter. However, in order to store the number of A / D conversions executed in the past for debugging the
For example, when the A / D conversion process is executed at an interval of 1 ms, it is possible to record the number of executions of the A / D conversion process for about 49 days by using a 32-bit counter. For example, by using a 40-bit counter, it is possible to record the number of executions of A / D conversion in about 34 years, and continuously record the number of executions exceeding the life of a general product. Is also possible. Further, in a general design, a counter of about 32 bits can be prepared, so that the number of bits can be increased as necessary.
第2の例は、A/D変換処理の実行時刻に基づくデータから識別データDIDを生成する手法である。
図3Bは、A/D変換処理の実行時刻に基づくデータを識別データDIDとした場合の一例を示す図である。この場合、同図に示されるように、A/D変換処理の実行時刻(タイムスタンプ)が識別データDIDとなる。上記実行時刻は、例えば、A/D変換処理が完了した時刻である。 The second example is a method for generating identification data DID from data based on the execution time of the A / D conversion process.
FIG. 3B is a diagram illustrating an example in which the data based on the execution time of the A / D conversion process is the identification data DID. In this case, as shown in the figure, the execution time (time stamp) of the A / D conversion process becomes the identification data DID. The execution time is, for example, the time when the A / D conversion process is completed.
図3Bは、A/D変換処理の実行時刻に基づくデータを識別データDIDとした場合の一例を示す図である。この場合、同図に示されるように、A/D変換処理の実行時刻(タイムスタンプ)が識別データDIDとなる。上記実行時刻は、例えば、A/D変換処理が完了した時刻である。 The second example is a method for generating identification data DID from data based on the execution time of the A / D conversion process.
FIG. 3B is a diagram illustrating an example in which the data based on the execution time of the A / D conversion process is the identification data DID. In this case, as shown in the figure, the execution time (time stamp) of the A / D conversion process becomes the identification data DID. The execution time is, for example, the time when the A / D conversion process is completed.
ここで、A/D変換処理の実行時刻を用いる具体的な手法として、例えば以下の2つを例示することができる。
第1の手法は、A/D変換回路10の内部または外部にリアルタイムクロックを設ける手法である。この手法では、A/D変換部101からA/D変換結果DOUTが出力される毎に、制御部102が、A/D変換結果DOUTをA/D変換結果レジスタ105に書き込むとともに、その時の上記リアルタイムクロックの値を識別データDIDとして識別データレジスタ105に書き込む。ここで、上記リアルタイムクロックに必要なビット数は、例えば48~64ビットである。 Here, for example, the following two methods can be exemplified as specific methods using the execution time of the A / D conversion process.
The first technique is a technique in which a real-time clock is provided inside or outside the A /D conversion circuit 10. In this method, every time the A / D conversion result DOUT is output from the A / D conversion unit 101, the control unit 102 writes the A / D conversion result DOUT into the A / D conversion result register 105 and The value of the real time clock is written in the identification data register 105 as identification data DID. Here, the number of bits required for the real-time clock is, for example, 48 to 64 bits.
第1の手法は、A/D変換回路10の内部または外部にリアルタイムクロックを設ける手法である。この手法では、A/D変換部101からA/D変換結果DOUTが出力される毎に、制御部102が、A/D変換結果DOUTをA/D変換結果レジスタ105に書き込むとともに、その時の上記リアルタイムクロックの値を識別データDIDとして識別データレジスタ105に書き込む。ここで、上記リアルタイムクロックに必要なビット数は、例えば48~64ビットである。 Here, for example, the following two methods can be exemplified as specific methods using the execution time of the A / D conversion process.
The first technique is a technique in which a real-time clock is provided inside or outside the A /
第2の手法は、リアルタイムクロックの代わりに、例えば電源投入時を時刻0として一定周期毎にインクリメントするカウンタを制御部102の内部または外部に設ける手法である。この手法では、A/D変換部10からA/D変換結果DOUTが出力される毎に、制御部102が、A/D変換結果DOUTをA/D変換結果レジスタ105に書き込むとともに、その時の上記カウンタの値を識別データDIDとして識別データレジスタ105に書き込む。
The second method is a method of providing a counter that is incremented at a constant cycle, for example, at time 0 when power is turned on, inside or outside the control unit 102 instead of the real-time clock. In this method, every time the A / D conversion result DOUT is output from the A / D conversion unit 10, the control unit 102 writes the A / D conversion result DOUT into the A / D conversion result register 105 and The counter value is written in the identification data register 105 as identification data DID.
上記のいずれの手法によっても、あるタイミングで実行されたA/D変換処理によるA/D変換結果と、その前後のタイミングで実行されたA/D変換処理によるA/D変換結果とを識別することが可能となる。更に、上述したリアルタイムクロックを用いる第1の手法によれば、A/D変換処理が実行された正確な時刻が記録できるため、識別データDIDを温度調節器1のデバッグ等に用いることが可能となる。一方、上述したリアルタイムクロックを用いない第2の手法によれば、回路規模の増大を抑えることができる。
With any of the above methods, the A / D conversion result obtained by the A / D conversion process executed at a certain timing and the A / D conversion result obtained by the A / D conversion process executed at the timing before and after that are identified. It becomes possible. Furthermore, according to the first method using the real-time clock described above, the accurate time when the A / D conversion process is executed can be recorded, so that the identification data DID can be used for debugging of the temperature controller 1 and the like. Become. On the other hand, according to the second method not using the real-time clock described above, an increase in circuit scale can be suppressed.
第3の例は、A/D変換処理が実行される毎に論理レベルが反転する1ビットのデータから識別データDIDを生成する手法である。
図3Cは、A/D変換処理が実行される毎に論理レベルが反転する1ビットのデータを識別データDIDとした場合の一例を示す図である。 The third example is a method of generating identification data DID from 1-bit data whose logic level is inverted every time A / D conversion processing is executed.
FIG. 3C is a diagram illustrating an example in which identification data DID is 1-bit data whose logic level is inverted each time an A / D conversion process is performed.
図3Cは、A/D変換処理が実行される毎に論理レベルが反転する1ビットのデータを識別データDIDとした場合の一例を示す図である。 The third example is a method of generating identification data DID from 1-bit data whose logic level is inverted every time A / D conversion processing is executed.
FIG. 3C is a diagram illustrating an example in which identification data DID is 1-bit data whose logic level is inverted each time an A / D conversion process is performed.
同図に示されるように、識別データレジスタ105を1ビットの記憶素子(フラグ)によって構成する。更に、A/D変換部10からA/D変換結果DOUTが出力される毎に、制御部102が、A/D変換結果DOUTをA/D変換結果レジスタ105に書き込むとともに、識別データレジスタ105に記録されている1ビットの値を反転させる。ここで、識別データレジスタ105は、1ビットカウンタで実現してもよい。
As shown in the figure, the identification data register 105 is composed of a 1-bit storage element (flag). Further, every time the A / D conversion result DOUT is output from the A / D conversion unit 10, the control unit 102 writes the A / D conversion result DOUT in the A / D conversion result register 105 and also in the identification data register 105. The recorded 1-bit value is inverted. Here, the identification data register 105 may be realized by a 1-bit counter.
これによれば、あるタイミングで実行されたA/D変換処理によるA/D変換結果と、その前後のタイミングで実行されたA/D変換処理によるA/D変換結果とを識別することが可能となる。また、識別データレジスタ105を1ビットの記憶素子によって実現することにより、必要なハードウェアリソースを少なくすることができ、回路規模の増大を抑えることができる。
According to this, it is possible to identify the A / D conversion result by the A / D conversion process executed at a certain timing and the A / D conversion result by the A / D conversion process executed at the timing before and after the A / D conversion process. It becomes. Also, by realizing the identification data register 105 with a 1-bit storage element, it is possible to reduce the necessary hardware resources and suppress an increase in circuit scale.
第4の例は、フリーランカウンタのカウント値に基づくデータから識別データDIDを生成する手法である。例えば、A/D変換回路10に8ビットのフリーランカウンタを設け、そのフリーランカウンタが、A/D変換処理の実行処理とは無関係に、連続して入力されるパルスをカウントし、そのカウント値を識別データDIDする。これによれば、ビット幅の大きなカウンタは必要ないので、回路規模の増大を抑えることができる。なお、識別データDIDとして記憶するデータは、フリーランカウンタのカウント値(数値)そのものでなくてもよく、例えばアルファベットの“A~Z”のような順番のわかるキャラクターコードであってもよい。
The fourth example is a technique for generating identification data DID from data based on the count value of the free-run counter. For example, an 8-bit free-run counter is provided in the A / D conversion circuit 10, and the free-run counter counts continuously input pulses regardless of the execution process of the A / D conversion process. The value is the identification data DID. According to this, since a counter having a large bit width is not required, an increase in circuit scale can be suppressed. Note that the data stored as the identification data DID may not be the count value (numerical value) of the free-run counter itself, but may be a character code with a known order such as “A to Z” of the alphabet, for example.
次に、A/D変換回路10とデータ処理制御部11との間の具体的な通信方法について説明する。
A/D変換回路10とデータ処理制御部11との間の通信は、例えばSPI(Serial Peripheral Interface)によって行われる。A/D変換回路10側の通信回路106とデータ処理制御部11側の通信回路113とは、SPIによる通信に必要なハードウェアリソースを夫々備えている。 Next, a specific communication method between the A /D conversion circuit 10 and the data processing control unit 11 will be described.
Communication between the A /D conversion circuit 10 and the data processing control unit 11 is performed by, for example, an SPI (Serial Peripheral Interface). The communication circuit 106 on the A / D conversion circuit 10 side and the communication circuit 113 on the data processing control unit 11 side each have hardware resources necessary for communication by SPI.
A/D変換回路10とデータ処理制御部11との間の通信は、例えばSPI(Serial Peripheral Interface)によって行われる。A/D変換回路10側の通信回路106とデータ処理制御部11側の通信回路113とは、SPIによる通信に必要なハードウェアリソースを夫々備えている。 Next, a specific communication method between the A /
Communication between the A /
A/D変換回路10からデータ処理制御部11へのA/D変換結果の送信は、前述したように、データ処理制御部11がデータの読み出し要求(読み出し命令)を発行し、A/D変換回路10が、その読み出し要求のレスポンスとして、A/D変換結果DOUTと識別データDIDとをセットにして出力することによって実現される。
As described above, the A / D conversion result is transmitted from the A / D conversion circuit 10 to the data processing control unit 11 by the data processing control unit 11 issuing a data read request (read command). The circuit 10 is realized by outputting the A / D conversion result DOUT and the identification data DID as a set as a response to the read request.
図4Aは、実施の形態1に係るデータの読み出し要求の送信電文のフォーマットの一例を示す図である。また、図4Bは、実施の形態1に係るデータの読み出し要求に係る応答電文のフォーマットの一例を示す図である。
図4Aに示されるように、データ処理制御部11が発行するデータの読み出し要求に係る送信電文は、例えばSPIプロトコルに従ってデータの先頭にヘッダが付され、データの末尾にフッタが付されたシリアルデータとして構成されている。図4Aには、”アドレス100Hから1組のA/D変換結果DOUTおよび識別データDIDを読み出す”ことを指示する命令が示されている。 FIG. 4A is a diagram illustrating an example of a format of a transmission message of a data read request according to the first embodiment. FIG. 4B is a diagram illustrating an example of a response message format related to a data read request according to the first embodiment.
As shown in FIG. 4A, the transmission message related to the data read request issued by the dataprocessing control unit 11 is serial data in which a header is attached to the head of the data and a footer is attached to the end of the data, for example, according to the SPI protocol. It is configured as. FIG. 4A shows an instruction for instructing “reading a set of A / D conversion results DOUT and identification data DID from address 100H”.
図4Aに示されるように、データ処理制御部11が発行するデータの読み出し要求に係る送信電文は、例えばSPIプロトコルに従ってデータの先頭にヘッダが付され、データの末尾にフッタが付されたシリアルデータとして構成されている。図4Aには、”アドレス100Hから1組のA/D変換結果DOUTおよび識別データDIDを読み出す”ことを指示する命令が示されている。 FIG. 4A is a diagram illustrating an example of a format of a transmission message of a data read request according to the first embodiment. FIG. 4B is a diagram illustrating an example of a response message format related to a data read request according to the first embodiment.
As shown in FIG. 4A, the transmission message related to the data read request issued by the data
また、図4Bに示されるように、データ処理制御部11の送信電文に応答してA/D変換回路10から送信される応答電文は、上記送信電文と同様に、SPIプロトコルに従ってデータの先頭にヘッダが付され、データの末尾にフッタが付された1フレームのシリアルデータとして構成されている。図4Bには、読み出し命令に対すレスポンスとして、“3356H”というA/D変換結果DOUTと、“01H”という識別データDIDとが出力された場合が示されている。
Further, as shown in FIG. 4B, the response message transmitted from the A / D conversion circuit 10 in response to the transmission message of the data processing control unit 11 is placed at the head of the data according to the SPI protocol, similarly to the transmission message. It is configured as one frame of serial data with a header and a footer at the end of the data. FIG. 4B shows a case where an A / D conversion result DOUT “3356H” and identification data DID “01H” are output as a response to the read command.
データ処理制御部11がA/D変換回路10に対して読み出し要求を発行する周期は、A/D変換回路10においてA/D変換処理が実行される周期(A/D変換結果レジスタ104および識別データレジスタ105が更新される周期)と同じか、それよりも短い周期とされる。これにより、データ処理制御部11は、A/D変換回路10によって周期的に更新されたA/D変換結果DOUTを連続して取得することができる。
The cycle in which the data processing control unit 11 issues a read request to the A / D conversion circuit 10 is a cycle in which A / D conversion processing is executed in the A / D conversion circuit 10 (A / D conversion result register 104 and identification The cycle is the same as or shorter than the cycle in which the data register 105 is updated. Thereby, the data processing control unit 11 can continuously acquire the A / D conversion result DOUT periodically updated by the A / D conversion circuit 10.
以上、本発明に係るA/D変換回路によれば、A/D変換結果毎に識別データを付与し、A/D変換結果と識別データとをセットで出力するので、A/D変換結果を受信した回路は、取得したA/D変換結果の連続性が保たれているか否かを判断することができる。
As described above, according to the A / D conversion circuit according to the present invention, identification data is assigned for each A / D conversion result, and the A / D conversion result and the identification data are output as a set. The received circuit can determine whether the continuity of the acquired A / D conversion result is maintained.
例えば、実施の形態1に係るA/D変換回路を含む温度調節器1において、データ処理制御部11が、取得したA/D変換結果に対応する識別データとその直前に取得したA/D変換結果に対応する識別データとを比較することによって、同じA/D変換周期のA/D変換結果の重複取得の有無およびA/D変換結果の取りこぼしの有無を判断することができる。すなわち、取得したA/D変換結果の連続性が保たれているか否かを、データ処理制御部11側で判断することが可能となる。これにより、データ処理制御部11は、取得したA/D変換結果の連続性が保たれていると判断した場合に、取得したA/D変換結果を用いてPID演算を行い、取得したA/D変換結果の連続性が保たれていないと判断した場合に、取得したA/D変換結果をPID演算に用いないようにする等の処理を行うことができる。これにより、データ処理制御部によるPID演算結果が急変する等の異常が起こることを回避することができるので、温度調節システム300の制御の安定性を保つことが可能となる。
For example, in the temperature controller 1 including the A / D conversion circuit according to the first embodiment, the data processing control unit 11 performs identification data corresponding to the acquired A / D conversion result and the A / D conversion acquired immediately before it. By comparing the identification data corresponding to the result, it is possible to determine whether or not the A / D conversion result of the same A / D conversion period is acquired and whether or not the A / D conversion result is missed. That is, it is possible for the data processing control unit 11 to determine whether the continuity of the acquired A / D conversion results is maintained. Thus, when the data processing control unit 11 determines that the continuity of the acquired A / D conversion result is maintained, the data processing control unit 11 performs the PID calculation using the acquired A / D conversion result, and acquires the acquired A / D When it is determined that the continuity of the D conversion result is not maintained, it is possible to perform processing such as not using the acquired A / D conversion result for the PID calculation. As a result, it is possible to avoid an abnormality such as a sudden change in the PID calculation result by the data processing control unit, so that the control of the temperature control system 300 can be kept stable.
また、A/D変換結果の重複取得またはA/D変換結果の取りこぼしがあったとしても、上記のようにデータ処理制御部11側で対処することが可能であるから、A/D変換回路10によるA/D変換処理の実行周期とデータ処理制御部11によるA/D変換結果の読み出し周期とを非同期にすることができる。これにより、データ処理制御部11側において、ポーリングによる常時監視および割り込み処理等を実行するタイミングを厳密に規定する必要がないので、データ処理制御部11による処理の時間的な制約が少なくなり、データ処理部11の設計が容易となる。
In addition, even when there are duplicate acquisitions of A / D conversion results or missing A / D conversion results, the data processing control unit 11 can deal with them as described above. It is possible to make the execution cycle of the A / D conversion process by A and the read cycle of the A / D conversion result by the data processing control unit 11 asynchronous. As a result, the data processing control unit 11 does not need to strictly define the timing for executing the constant monitoring and interrupt processing by polling, so the time restriction of the processing by the data processing control unit 11 is reduced, and the data The processing unit 11 can be easily designed.
また、実施の形態1に係るA/D変換回路によれば、A/D変換結果と識別データの双方のデータの書き込みが完了するまでデータの読み出しを許可しないので、読み出されたA/D変換結果と識別データとの対応関係がずれることを防止することができる。
In addition, according to the A / D conversion circuit according to the first embodiment, since the data reading is not permitted until the writing of both the A / D conversion result and the identification data is completed, the read A / D is not permitted. It is possible to prevent the correspondence between the conversion result and the identification data from deviating.
≪実施の形態2≫
実施の形態2に係るA/D変換回路は、A/D変換結果および識別データを記憶するためのレジスタを複数組備える点で、実施の形態1に係るA/D変換回路10と相違し、その他の点は実施の形態1に係るA/D変換回路10と同様である。
図5は、実施の形態2に係るA/D変換回路を含む温度調節器の構成を示す図である。なお、実施の形態2における温度調節器6において、実施の形態1における温度調節器1と同様の構成要素には、同一の符号を付してその詳細な説明を省略する。 <<Embodiment 2 >>
The A / D conversion circuit according to the second embodiment is different from the A /D conversion circuit 10 according to the first embodiment in that a plurality of registers for storing A / D conversion results and identification data are provided. Other points are the same as those of the A / D conversion circuit 10 according to the first embodiment.
FIG. 5 is a diagram illustrating a configuration of a temperature regulator including an A / D conversion circuit according to the second embodiment. In thetemperature controller 6 according to the second embodiment, the same components as those of the temperature controller 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
実施の形態2に係るA/D変換回路は、A/D変換結果および識別データを記憶するためのレジスタを複数組備える点で、実施の形態1に係るA/D変換回路10と相違し、その他の点は実施の形態1に係るA/D変換回路10と同様である。
図5は、実施の形態2に係るA/D変換回路を含む温度調節器の構成を示す図である。なお、実施の形態2における温度調節器6において、実施の形態1における温度調節器1と同様の構成要素には、同一の符号を付してその詳細な説明を省略する。 <<
The A / D conversion circuit according to the second embodiment is different from the A /
FIG. 5 is a diagram illustrating a configuration of a temperature regulator including an A / D conversion circuit according to the second embodiment. In the
温度調節器6におけるA/D変換回路60は、A/D変換結果および識別データを記憶する記憶部603を備えている。記憶部603は、複数のA/D変換結果レジスタ604_1~604_n(nは2以上の整数)と、複数の識別データレジスタ605_1~605_nとを備えている。A/D変換結果レジスタ604_1と識別データレジスタ605_1とは一組のレジスタ対606_1を構成している。同様に、A/D変換結果レジスタ604_nと識別データレジスタ605_nとは、一組のレジスタ対606_nを構成している。
The A / D conversion circuit 60 in the temperature controller 6 includes a storage unit 603 that stores an A / D conversion result and identification data. The storage unit 603 includes a plurality of A / D conversion result registers 604_1 to 604_n (n is an integer of 2 or more) and a plurality of identification data registers 605_1 to 605_n. The A / D conversion result register 604_1 and the identification data register 605_1 constitute a pair of registers 606_1. Similarly, the A / D conversion result register 604_n and the identification data register 605_n constitute a pair of register pairs 606_n.
制御部602は、A/D変換部10によるA/D変換処理が実行される毎に、A/D変換結果DOUTと、それに対応する識別データDIDとを上記の複数のレジスタ対606_1~606_nに順次書き込む。
例えば、制御部602は、あるA/D変換周期で実行されたA/D変換処理によるA/D変換結果DOUT_1と対応する識別データDID_1とを、A/D変換結果レジスタ604_1および識別データレジスタ605_1に書き込み、その後、次のA/D変換周期で実行されたA/D変換処理によるA/D変換結果DOUT_2とそれに対応する識別データDID_2とを、A/D変換結果レジスタ604_2および識別データレジスタ605_2に書き込む。このように、制御部602は、A/D変換処理が完了する毎に、データを順番にレジスタ対606_1~606_nに書き込む。そして、すべてのレジスタ対606_1~606_nにデータが書き込まれた状態においてA/D変換処理が実行されたら、制御部602は、最も古いA/D変換結果および識別データが書き込まれているレジスタ対に、最新のA/D変換結果および識別データを上書きする。 Each time the A / D conversion process is executed by the A /D conversion unit 10, the control unit 602 sends the A / D conversion result DOUT and the corresponding identification data DID to the plurality of register pairs 606_1 to 606_n. Write sequentially.
For example, thecontrol unit 602 obtains the A / D conversion result DOUT_1 by the A / D conversion process executed in a certain A / D conversion cycle and the corresponding identification data DID_1 from the A / D conversion result register 604_1 and the identification data register 605_1. And A / D conversion result DOUT_2 by the A / D conversion process executed in the next A / D conversion cycle and identification data DID_2 corresponding to the A / D conversion result register 604_2 and identification data register 605_2 Write to. In this way, the control unit 602 writes data to the register pairs 606_1 to 606_n in order every time the A / D conversion process is completed. When the A / D conversion process is executed in a state where data is written in all the register pairs 606_1 to 606_n, the control unit 602 sets the oldest A / D conversion result and the identification data to the register pair in which the identification data is written. The latest A / D conversion result and identification data are overwritten.
例えば、制御部602は、あるA/D変換周期で実行されたA/D変換処理によるA/D変換結果DOUT_1と対応する識別データDID_1とを、A/D変換結果レジスタ604_1および識別データレジスタ605_1に書き込み、その後、次のA/D変換周期で実行されたA/D変換処理によるA/D変換結果DOUT_2とそれに対応する識別データDID_2とを、A/D変換結果レジスタ604_2および識別データレジスタ605_2に書き込む。このように、制御部602は、A/D変換処理が完了する毎に、データを順番にレジスタ対606_1~606_nに書き込む。そして、すべてのレジスタ対606_1~606_nにデータが書き込まれた状態においてA/D変換処理が実行されたら、制御部602は、最も古いA/D変換結果および識別データが書き込まれているレジスタ対に、最新のA/D変換結果および識別データを上書きする。 Each time the A / D conversion process is executed by the A /
For example, the
A/D変換回路60からデータ処理制御部11へのA/D変換結果の送信は、実施の形態1と同様に、データ処理制御部11がデータの読み出し要求(読み出し命令)を発行し、A/D変換回路60が、その読み出し要求のレスポンスとして、A/D変換結果DOUTおよび識別データDIDを出力することによって実現される。
The transmission of the A / D conversion result from the A / D conversion circuit 60 to the data processing control unit 11 is performed by the data processing control unit 11 issuing a data read request (read command) as in the first embodiment. The / D conversion circuit 60 is realized by outputting the A / D conversion result DOUT and the identification data DID as a response to the read request.
ここで、データ処理制御部11は、上記読み出し命令として、複数セットのA/D変換結果DOUTおよび識別データDIDの読み出しを要求する命令を発行する。以下、この内容について、図6、図7A、および図7Bを用いて詳細に説明する。
Here, the data processing control unit 11 issues a command for requesting reading of a plurality of sets of A / D conversion results DOUT and identification data DID as the read command. Hereinafter, this content will be described in detail with reference to FIGS. 6, 7A, and 7B.
図6は、A/D変換処理レジスタおよび識別データレジスタのアドレスの割り付けの一例を示す図である。
図7Aは、実施の形態2に係るA/D変換器を含む温度調節器におけるデータの読み出し要求の送信電文のフォーマットの一例を示す図である。
図7Bは、実施の形態2に係るA/D変換器を含む温度調節器におけるデータの読み出し要求に係る応答電文のフォーマットの一例を示す図である。
図6に示されるように、レジスタ対606_1~606_nは、順番にアドレスが付与されている。このように、レジスタ対606_1~606_n毎に順番にアドレスを付与することにより、複数の連続したA/D変換結果および識別データの読み出しが容易となる。
例えば、図7Aに示すように、読み出しの先頭アドレスを“100h”とし、読み出し数を“03h”とする読み出し命令を発行する。これにより、図7Bに示すように、レジスタアドレス“100h”から“105h”までのデータが読み出され、1つの読み出し命令によって、3回分のA/D変換結果および識別データを取得することができる。すなわち、図6に示すようにレジスタ対606_1~606_n毎に順番にレジスタアドレスを付与し、図7Aのように読み出しの先頭アドレスと読み出し数を指定する命令を発行することにより、一つの読み出し命令によって複数回分のA/D変換結果および識別データを取得することができる。 FIG. 6 is a diagram illustrating an example of assignment of addresses of the A / D conversion processing register and the identification data register.
FIG. 7A is a diagram illustrating an example of a format of a transmission message of a data read request in the temperature controller including the A / D converter according to the second embodiment.
FIG. 7B is a diagram illustrating an example of a response message format related to a data read request in the temperature controller including the A / D converter according to the second embodiment.
As shown in FIG. 6, the register pairs 606_1 to 606_n are assigned addresses in order. In this way, by sequentially assigning addresses to each of the register pairs 606_1 to 606_n, a plurality of continuous A / D conversion results and identification data can be easily read.
For example, as shown in FIG. 7A, a read command is issued in which the read start address is “100h” and the read number is “03h”. As a result, as shown in FIG. 7B, data from the register addresses “100h” to “105h” is read, and A / D conversion results and identification data for three times can be acquired by one read command. . That is, as shown in FIG. 6, register addresses are sequentially assigned to each of the register pairs 606_1 to 606_n, and by issuing a command designating the read start address and the read number as shown in FIG. A plurality of A / D conversion results and identification data can be acquired.
図7Aは、実施の形態2に係るA/D変換器を含む温度調節器におけるデータの読み出し要求の送信電文のフォーマットの一例を示す図である。
図7Bは、実施の形態2に係るA/D変換器を含む温度調節器におけるデータの読み出し要求に係る応答電文のフォーマットの一例を示す図である。
図6に示されるように、レジスタ対606_1~606_nは、順番にアドレスが付与されている。このように、レジスタ対606_1~606_n毎に順番にアドレスを付与することにより、複数の連続したA/D変換結果および識別データの読み出しが容易となる。
例えば、図7Aに示すように、読み出しの先頭アドレスを“100h”とし、読み出し数を“03h”とする読み出し命令を発行する。これにより、図7Bに示すように、レジスタアドレス“100h”から“105h”までのデータが読み出され、1つの読み出し命令によって、3回分のA/D変換結果および識別データを取得することができる。すなわち、図6に示すようにレジスタ対606_1~606_n毎に順番にレジスタアドレスを付与し、図7Aのように読み出しの先頭アドレスと読み出し数を指定する命令を発行することにより、一つの読み出し命令によって複数回分のA/D変換結果および識別データを取得することができる。 FIG. 6 is a diagram illustrating an example of assignment of addresses of the A / D conversion processing register and the identification data register.
FIG. 7A is a diagram illustrating an example of a format of a transmission message of a data read request in the temperature controller including the A / D converter according to the second embodiment.
FIG. 7B is a diagram illustrating an example of a response message format related to a data read request in the temperature controller including the A / D converter according to the second embodiment.
As shown in FIG. 6, the register pairs 606_1 to 606_n are assigned addresses in order. In this way, by sequentially assigning addresses to each of the register pairs 606_1 to 606_n, a plurality of continuous A / D conversion results and identification data can be easily read.
For example, as shown in FIG. 7A, a read command is issued in which the read start address is “100h” and the read number is “03h”. As a result, as shown in FIG. 7B, data from the register addresses “100h” to “105h” is read, and A / D conversion results and identification data for three times can be acquired by one read command. . That is, as shown in FIG. 6, register addresses are sequentially assigned to each of the register pairs 606_1 to 606_n, and by issuing a command designating the read start address and the read number as shown in FIG. A plurality of A / D conversion results and identification data can be acquired.
以上、実施の形態2に係るA/D変換回路60によれば、A/D変換結果と識別データを記憶するための記憶部として、複数のレジスタを設け、A/D変換結果および識別データを複数セット読み出せるようにすることで、A/D変換結果の取りこぼしを防ぐことができる。例えば、データ処理制御部11によるデータの読み出し処理において1回分のA/D変換結果の取りこぼしがあったとしても、次回の読み出し処理において、取りこぼした分のA/D変換結果を取得することが可能となる。
As described above, according to the A / D conversion circuit 60 according to the second embodiment, a plurality of registers are provided as a storage unit for storing the A / D conversion result and the identification data, and the A / D conversion result and the identification data are stored. By making it possible to read a plurality of sets, it is possible to prevent missing A / D conversion results. For example, even if a single A / D conversion result is missed in the data reading process by the data processing control unit 11, it is possible to acquire the A / D conversion result for the missing data in the next reading process. It becomes.
また、実施の形態2に係るA/D変換回路60によれば、1回の読み出し命令によって複数回分のA/D変換結果および識別データを読み出すことができるので、データ処理制御部11によるデータの読み出し回数を減らすことが可能となる。
これにより、データ処理制御部11による高速且つ高精度な処理時間の管理が不要となり、データ処理制御部11の設計が容易となるとともに、データ処理制御部11として低速で安価なマイクロコントローラ(CPU)を利用することができるので、コストの低減が可能となる。 Further, according to the A /D conversion circuit 60 according to the second embodiment, the A / D conversion result and the identification data for a plurality of times can be read by one read command, so that the data processing control unit 11 performs data transfer. It is possible to reduce the number of readings.
This eliminates the need for high-speed and high-precision processing time management by the dataprocessing control unit 11, facilitates the design of the data processing control unit 11, and provides a low-speed and inexpensive microcontroller (CPU) as the data processing control unit 11. Therefore, the cost can be reduced.
これにより、データ処理制御部11による高速且つ高精度な処理時間の管理が不要となり、データ処理制御部11の設計が容易となるとともに、データ処理制御部11として低速で安価なマイクロコントローラ(CPU)を利用することができるので、コストの低減が可能となる。 Further, according to the A /
This eliminates the need for high-speed and high-precision processing time management by the data
例えば、A/D変換回路10によるA/D変換周期が1MHzである場合、A/D変換結果および識別データは1μs毎に更新される。この場合に、従来のようにデータ処理制御部が1μs毎にデータを読み出さなければならないとすると、1μs毎のA/D変換処理時間に対応した動作クロックでデータ処理制御部を動作させなければならない。
これに対し、実施の形態2に係るA/D変換回路60のようにn個のレジスタ対を設けることにより、データ処理制御部は、(n×1)μs毎にデータの読み出し処理を実行すれば、取りこぼすことなくデータを取得することができる。例えば、レジスタ対を1000組設けた場合には、データ処理制御部は、1ms毎にデータの読み出し処理を実行すればよい。すなわち、実施の形態2に係るA/D変換回路60によれば、従来よりも、データ処理制御部11としてのマイクロコントローラの動作クロック周波数を下げることが可能となり、コストの低減が可能となる。 For example, when the A / D conversion cycle by the A /D conversion circuit 10 is 1 MHz, the A / D conversion result and the identification data are updated every 1 μs. In this case, if the data processing control unit must read data every 1 μs as in the prior art, the data processing control unit must be operated with an operation clock corresponding to the A / D conversion processing time every 1 μs. .
On the other hand, by providing n register pairs as in the A /D conversion circuit 60 according to the second embodiment, the data processing control unit executes the data reading process every (n × 1) μs. In this case, data can be acquired without missing. For example, when 1000 register pairs are provided, the data processing control unit may execute data read processing every 1 ms. That is, according to the A / D conversion circuit 60 according to the second embodiment, the operation clock frequency of the microcontroller as the data processing control unit 11 can be lowered as compared with the conventional case, and the cost can be reduced.
これに対し、実施の形態2に係るA/D変換回路60のようにn個のレジスタ対を設けることにより、データ処理制御部は、(n×1)μs毎にデータの読み出し処理を実行すれば、取りこぼすことなくデータを取得することができる。例えば、レジスタ対を1000組設けた場合には、データ処理制御部は、1ms毎にデータの読み出し処理を実行すればよい。すなわち、実施の形態2に係るA/D変換回路60によれば、従来よりも、データ処理制御部11としてのマイクロコントローラの動作クロック周波数を下げることが可能となり、コストの低減が可能となる。 For example, when the A / D conversion cycle by the A /
On the other hand, by providing n register pairs as in the A /
以上、本発明者らによってなされた発明を実施の形態に基づいて具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。
Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.
例えば、実施の形態1,2において、A/D変換結果および識別データを記憶する記憶回路としてレジスタを例示したが、A/D変換結果および識別データを記憶することができる回路であればよく、レジスタに限定されない。
For example, in the first and second embodiments, the register is exemplified as the storage circuit that stores the A / D conversion result and the identification data, but any circuit that can store the A / D conversion result and the identification data may be used. It is not limited to registers.
また、実施の形態2において、A/D変換回路60が1つのA/D変換部101を備える場合を例示したが、これに限られず、A/D変換回路60がA/D変換部101を複数備えていてもよい。この場合、記憶部603における各レジスタのアドレスの割り付けを図8のように設定し、上述のように、読み出しの先頭アドレスと読み出し数を指定する命令を発行することにより、複数チャネルのA/D変換結果および識別データを一つの読み出し命令によって読み出すことが可能となる。
In the second embodiment, the case where the A / D conversion circuit 60 includes one A / D conversion unit 101 is illustrated. However, the present invention is not limited to this, and the A / D conversion circuit 60 includes the A / D conversion unit 101. A plurality may be provided. In this case, the address assignment of each register in the storage unit 603 is set as shown in FIG. 8, and the A / D of a plurality of channels is issued by issuing an instruction designating the read start address and the read number as described above. The conversion result and the identification data can be read by one read command.
また、実施の形態1,2において、A/D変換回路10、60を温度調節器1に適用する場合を例示したが、センサ等からのアナログ信号を定期的にA/D変換し、そのA/D変換結果を逐次記録するレコーダー等にもA/D変換回路10、60を適用することができる。
In the first and second embodiments, the case where the A / D conversion circuits 10 and 60 are applied to the temperature controller 1 is exemplified. However, the analog signal from the sensor or the like is periodically A / D converted, and the A The A / D conversion circuits 10 and 60 can also be applied to a recorder or the like that sequentially records the / D conversion results.
また、実施の形態1、2において、A/D変換部101がΔΣ型A/D変換回路である場合を例示したが、A/D変換部101は、別の変換方式のA/D変換回路であってもよい。例えば、A/D変換部101は、逐次比較型A/D変換回路であってもよい。
In the first and second embodiments, the A / D conversion unit 101 is a ΔΣ A / D conversion circuit. However, the A / D conversion unit 101 is an A / D conversion circuit of another conversion method. It may be. For example, the A / D converter 101 may be a successive approximation A / D converter circuit.
また、実施の形態1において、データの取りこぼしが起きないように複数のA/D変換結果レジスタ104を準備する場合を一例として説明したが、これに限られない。例えば、準備した複数のA/D変換結果レジスタ104が満杯になって新たなA/D変換結果が保存できなくなってしまった場合に、A/D変換結果レジスタ104をリングバッファとして利用し、A/D変換結果レジスタ104に記憶されている最も古いデータが最新のデータによって上書きされるようにしてもよい。
In the first embodiment, the case where a plurality of A / D conversion result registers 104 are prepared so as not to cause data loss has been described as an example. However, the present invention is not limited to this. For example, when a plurality of prepared A / D conversion result registers 104 are full and a new A / D conversion result cannot be stored, the A / D conversion result register 104 is used as a ring buffer, and A The oldest data stored in the / D conversion result register 104 may be overwritten by the latest data.
本発明に係るアナログ/ディジタル変換回路は、例えば工業用の計装機器等の様々な用途に適用できる。
The analog / digital conversion circuit according to the present invention can be applied to various uses such as industrial instrumentation equipment.
10,60…A/D変換回路、101…A/D変換部、102,602…制御部、103,603…記憶部、VA…アナログ信号、DOUT…A/D変換結果、DID…識別データ。
10, 60 ... A / D conversion circuit, 101 ... A / D conversion unit, 102,602 ... control unit, 103,603 ... storage unit, VA ... analog signal, DOUT ... A / D conversion result, DID ... identification data.
Claims (7)
- 入力したアナログ信号をディジタル信号に変換するアナログ/ディジタル変換処理を周期的に実行するアナログ/ディジタル変換部と、
記憶部と、
前記アナログ/ディジタル変換部によって前記アナログ/ディジタル変換処理が実行される毎に、前記アナログ/ディジタル変換処理によるアナログ/ディジタル変換結果と、前記アナログ/ディジタル変換結果に対応付けられた識別データとを前記記憶部に書き込む制御部と、
前記記憶部に書き込まれた前記アナログ/ディジタル変換結果と、対応する前記識別データとを読み出して出力する出力部と、を備える
ことを特徴とするアナログ/ディジタル変換回路。 An analog / digital converter that periodically executes an analog / digital conversion process for converting an input analog signal into a digital signal;
A storage unit;
Each time the analog / digital conversion process is executed by the analog / digital conversion unit, the analog / digital conversion result by the analog / digital conversion process and the identification data associated with the analog / digital conversion result are A control unit for writing to the storage unit;
An analog / digital conversion circuit comprising: an output unit that reads out and outputs the analog / digital conversion result written in the storage unit and the corresponding identification data. - 請求項1に記載のアナログ/ディジタル変換回路において、
前記制御部は、前記アナログ/ディジタル変換部による前記アナログ/ディジタル変換結果と前記識別データの双方の前記記憶部に対する書き込みが完了するまで、前記出力部による前記記憶部の読み出しを許可しない
ことを特徴とするアナログ/ディジタル変換回路。 The analog / digital conversion circuit according to claim 1,
The control unit does not allow the output unit to read the storage unit until writing of both the analog / digital conversion result and the identification data by the analog / digital conversion unit to the storage unit is completed. An analog / digital conversion circuit. - 請求項1に記載のアナログ/ディジタル変換回路において、
前記識別データは、前記アナログ/ディジタル変換部によるアナログ/ディジタル変換処理の実行回数を示すデータである
ことを特徴とするアナログ/ディジタル変換回路。 The analog / digital conversion circuit according to claim 1,
The identification data is data indicating the number of execution times of the analog / digital conversion processing by the analog / digital conversion unit. - 請求項1に記載のアナログ/ディジタル変換回路において、
前記識別データは、前記アナログ/ディジタル変換部によって前記アナログ/ディジタル変換処理が実行された時刻を示すデータである
ことを特徴とするアナログ/ディジタル変換回路。 The analog / digital conversion circuit according to claim 1,
The identification data is data indicating a time when the analog / digital conversion processing is executed by the analog / digital conversion unit. - 請求項1に記載のアナログ/ディジタル変換回路において、
前記識別データは、前記アナログ/ディジタル変換部によって前記アナログ/ディジタル変換処理が実行される毎に論理レベルが反転する1ビットのデータである
ことを特徴とするアナログ/ディジタル変換回路。 The analog / digital conversion circuit according to claim 1,
The identification data is 1-bit data whose logic level is inverted each time the analog / digital conversion unit executes the analog / digital conversion process. - 請求項1に記載のアナログ/ディジタル変換回路において、
前記識別データは、フリーランカウンタのカウント値に基づくデータである
ことを特徴とするアナログ/ディジタル変換回路。 The analog / digital conversion circuit according to claim 1,
The analog / digital conversion circuit, wherein the identification data is data based on a count value of a free-run counter. - 請求項1に記載のアナログ/ディジタル変換回路において、
前記記憶部は、前記アナログ/ディジタル変換処理による前記アナログ/ディジタル変換結果を記憶する第1レジスタと前記識別データを記憶する第2レジスタとを一組とするレジスタ対を複数有し、
前記制御部は、前記アナログ/ディジタル変換処理が実行される毎に、実行されたアナログ/ディジタル変換処理の前記アナログ/ディジタル変換結果と前記識別データとを前記レジスタ対に順次書き込み、
前記出力部は、外部から入力された読み出し要求に応答して、複数の前記レジスタ対から複数回分の前記アナログ/ディジタル変換処理の前記アナログ/ディジタル変換結果および前記識別データを読み出す
ことを特徴とするアナログ/ディジタル変換回路。 The analog / digital conversion circuit according to claim 1,
The storage unit includes a plurality of register pairs each including a first register that stores the analog / digital conversion result obtained by the analog / digital conversion process and a second register that stores the identification data.
The controller sequentially writes the analog / digital conversion result of the executed analog / digital conversion process and the identification data to the register pair each time the analog / digital conversion process is executed,
The output unit reads the analog / digital conversion result and the identification data of the analog / digital conversion processing for a plurality of times from the plurality of register pairs in response to a read request input from the outside. Analog / digital conversion circuit.
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CN109714053A (en) * | 2018-12-20 | 2019-05-03 | 成都蝠来科技有限公司 | Terminal device, the system and method for digital communication are carried out using analog signal pin |
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