WO2015192418A1 - 氧化物薄膜晶体管结构的制作方法及氧化物薄膜晶体管结构 - Google Patents

氧化物薄膜晶体管结构的制作方法及氧化物薄膜晶体管结构 Download PDF

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WO2015192418A1
WO2015192418A1 PCT/CN2014/082126 CN2014082126W WO2015192418A1 WO 2015192418 A1 WO2015192418 A1 WO 2015192418A1 CN 2014082126 W CN2014082126 W CN 2014082126W WO 2015192418 A1 WO2015192418 A1 WO 2015192418A1
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layer
oxide semiconductor
semiconductor layer
film transistor
thin film
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PCT/CN2014/082126
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English (en)
French (fr)
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胡宇彤
曾志远
苏智昱
李文辉
吕晓文
石龙强
张合静
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深圳市华星光电技术有限公司
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Priority to US14/384,447 priority Critical patent/US10629745B2/en
Publication of WO2015192418A1 publication Critical patent/WO2015192418A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an oxide thin film transistor structure and an oxide thin film transistor structure. Background technique
  • Thin film transistors are widely used as switching devices and driving devices in electronic devices. Specifically, since thin film transistors can be formed on a glass substrate or a plastic substrate, they are generally used in the field of flat panel display devices such as liquid crystal display devices (LCDs) and organic light emitting display devices (OLEDs).
  • LCDs liquid crystal display devices
  • OLEDs organic light emitting display devices
  • the oxide semiconductor has a high electron mobility (electron mobility of the oxide semiconductor > 10 cm 2 /Vs.
  • the electron mobility of the amorphous silicon (a-Si) is only 0.5 to 0.8 cm 2 /Vs), and Low temperature polysilicon (LTPS), oxide semiconductor process is simple, and has high compatibility with amorphous silicon process. It can be applied to liquid crystal display devices, organic light-emitting display devices, flexible displays, etc., and is compatible with high-generation production lines. It can be applied to large, medium and small size displays, and has good application development prospects, which is popular in the current industry research.
  • Oxide semiconductors have the advantages of high electron mobility and simple process. At the same time, there are also poor stability, which is greatly affected by temperature and humidity changes.
  • the electrical properties of oxide thin film transistors drift with time, and for process conditions, such as Film forming rate, process atmosphere, process temperature, humidity control and other requirements have higher disadvantages. Further, the oxide thin film transistor has high requirements for the insulating layer, the contact interface between the oxide semiconductor layer and the insulating layer, and the contact interface between the oxide semiconductor layer and the metal layer, in addition to the oxide semiconductor layer itself.
  • FIG. 1 is a cross-sectional view showing a structure of a conventional bottom gate barrier type oxide thin film transistor.
  • the manufacturing method of the oxide thin film transistor structure mainly includes: Step 1. Providing a substrate (100); Step 2, forming a gate electrode (200) on the substrate (100); Step 3, forming a gate electrode (100) and a gate electrode (100) a gate insulating layer (300) is formed on the gate insulating layer (300), and the gate insulating layer (300) is covered on the gate insulating layer (300); and an oxide semiconductor layer is formed on the gate insulating layer (300).
  • Step 5 forming an etch barrier layer (500) on the oxide semiconductor layer (400); Step 6, forming two via holes (510, 530) on the etch barrier layer (500) by etching to expose the oxide a semiconductor layer (400); Step 7, forming a source (610) and a drain (630) on the etch barrier layer (500), the source (610) filling a via hole (510), thereby forming an oxide semiconductor
  • the layer (400) is connected, and the drain (630) is filled with another via (530), thereby being half with the oxide
  • the conductor layer (400) is connected; step 8. forming a protective layer on the source (610) and the drain (630)
  • the etching barrier layer is performed in step 5
  • etch barrier layer (500) is generally formed by chemical vapor deposition of SiOx film layer by TEOS+02 or SiH4+N20, but the plasma affects the oxide semiconductor layer during the film formation process of the etch barrier layer (500).
  • the oxygen deficiency in the semiconductor layer (400) is reduced, and the conductivity of the channel is lowered. Therefore, after the source (610) and the drain (630) are formed, the source (610) and the drain (630) are in surface contact with the damaged oxide semiconductor layer (400), which ultimately affects the oxide thin film transistor. Electrical. Referring to FIG.
  • the oxide thin film transistor has more stable and superior electrical properties.
  • Another object of the present invention is to provide an oxide thin film transistor structure which has good electrical properties and which can improve the quality of an oxide thin film transistor.
  • the present invention first provides a method of fabricating an oxide thin film transistor structure, comprising the steps of:
  • Step 1 Provide a carrier
  • Step 2 forming an oxide semiconductor layer on the carrier
  • Step 3 forming an etch barrier layer on the oxide semiconductor layer
  • Step 4 forming two via holes on the etch barrier layer to expose a portion of the oxide semiconductor layer; Step 5, removing the surface layer of the oxide semiconductor layer exposed in the two via holes, forming two respectively and the two a groove through which the through hole communicates;
  • Step 6 Form a source and a drain on the etch barrier layer, and the source pad fills a via hole and a groove communicating therewith, thereby connecting with the oxide semiconductor layer, the drain filling the other via hole and communicating therewith The groove is connected to the oxide semiconductor layer.
  • the oxide thin film transistor structure is fabricated by chemical vapor deposition on an oxide Forming an etch barrier layer on the semiconductor layer; forming two via holes on the etch barrier layer by one thousand etching; forming a source and a drain by sputtering on the etch barrier layer; removing the exposed two by dry etching or wet etching The surface layer of the oxide semiconductor layer in the via hole.
  • the etch stop layer is formed by chemical vapor deposition of a SiOx film layer from TEOS+02 or SiH4+N20.
  • the carrier includes a substrate, a gate formed on the substrate, and a gate insulating layer formed on the substrate and the gate.
  • the method for fabricating the oxide thin film transistor structure further comprises the step of performing a post-process, the post-process comprising forming a protective layer on the source and the drain to cover the source and the drain.
  • the carrier is a substrate.
  • the method for fabricating the oxide thin film transistor structure further comprises the step of performing a post-process, the post-process comprising forming a gate insulating layer on the source and the drain, and sputtering the gate on the gate insulating layer.
  • the present invention also provides an oxide thin film transistor structure, comprising: an oxide semiconductor layer, an etch barrier layer on the oxide semiconductor layer, and a source and a drain on the etch barrier layer, wherein the etch barrier layer is provided Two through holes, the oxide semiconductor layer respectively providing two grooves corresponding to the two through holes, and the two grooves respectively communicate with the two through holes, the source filling a through hole and communicating therewith The recess is connected to the oxide semiconductor layer, and the drain fills the other via and the recess communicating therewith to be connected to the oxide semiconductor layer.
  • the oxide thin film transistor structure further includes a substrate, a gate on the substrate, a gate insulating layer on the substrate and the gate, and a protective layer on the source and the drain; the oxide semiconductor layer Provided on the gate insulating layer.
  • the oxide thin film transistor structure further includes a substrate, a gate insulating layer on the source and the drain, and a gate on the gate insulating layer; the oxide semiconductor layer is disposed on the substrate.
  • the present invention also provides an oxide thin film transistor structure, comprising: an oxide semiconductor layer, an etch barrier layer on the oxide semiconductor layer, and a source and a drain on the etch barrier layer, wherein the etch barrier layer is provided Two through holes, the oxide semiconductor layer respectively providing two grooves corresponding to the two through holes, and the two grooves respectively communicate with the two through holes, the source filling a through hole and communicating therewith a recess to be connected to the oxide semiconductor layer, the drain filling another via and a recess communicating therewith to be connected to the oxide semiconductor layer;
  • the oxide thin film transistor structure further includes a substrate, a gate on the substrate, and the semiconductor layer is disposed on the gate insulating layer ; ', ⁇ , ⁇ Advantageous Effects of Invention:
  • the method for fabricating an oxide thin film transistor structure provided by the present invention, or wet etching removes an oxide semiconductor whose characteristics are changed by destruction of 0 and H in a plasma when an etching stopper layer is formed.
  • the surface layer of the layer is such that the source and the drain are in contact with the oxide semiconductor layer which is not damaged and maintains the initial characteristics, so that the oxide thin film transistor obtained by the method has more stable and superior electrical properties, and the method Easy to operate.
  • the oxide thin film transistor structure provided by the present invention has two recesses corresponding to the two through holes of the etch barrier layer disposed in the oxide semiconductor layer, and the two recesses respectively communicate with the two through holes, so that the source and The drain is in contact with the oxide semiconductor layer which maintains the initial characteristics, so that good electrical properties can be obtained and the quality of the oxide thin film transistor can be improved.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a conventional oxide thin film transistor
  • 2 is an electrical graph of a conventional oxide thin film transistor
  • FIG. 3 is a flow chart showing a first embodiment of a method for fabricating an oxide thin film transistor structure of the present invention
  • FIG. 4 is a schematic view showing a step 4 of the first embodiment of the method for fabricating an oxide thin film transistor structure of the present invention
  • step 5 is a schematic diagram of step 5 of the first embodiment of the method for fabricating an oxide thin film transistor structure of the present invention
  • step 6 is a schematic diagram of step 6 of the first embodiment of the method for fabricating an oxide thin film transistor structure of the present invention
  • FIG. 7 is a schematic view showing a step 7 of a first embodiment of a method for fabricating an oxide thin film transistor structure of the present invention and a cross-sectional view showing a first embodiment of the oxide thin film transistor structure of the present invention
  • FIG. 8 is an oxide thin film transistor structure of the present invention. Electrical graph;
  • FIG. 9 is a flow chart showing a second embodiment of a method for fabricating an oxide thin film transistor structure of the present invention.
  • Figure 10 is a schematic view showing the third step of the second embodiment of the method for fabricating the oxide thin film transistor structure of the present invention.
  • FIG. 11 is a step of a second embodiment of a method for fabricating an oxide thin film transistor structure of the present invention Schematic diagram of 4;
  • FIG. 12 is a schematic view showing a step 5 of a second embodiment of a method for fabricating an oxide thin film transistor structure according to the present invention.
  • Figure 13 is a schematic view showing the sixth step of the second embodiment of the method for fabricating the oxide thin film transistor structure of the present invention.
  • Figure 14 is a schematic view showing the step 7 of the second embodiment of the method for fabricating the oxide thin film transistor structure of the present invention and a cross-sectional view showing the second embodiment of the structure of the oxide thin film transistor of the present invention.
  • a first embodiment of a method for fabricating an oxide thin film transistor structure according to the present invention is applicable to fabricating a bottom gate barrier type thin film transistor structure, which includes the following steps:
  • Step 1 Provide a carrier.
  • the carrier includes: a substrate 1, a gate electrode 2 formed on the substrate 1, and a gate insulating layer 3 formed on the substrate 1 and the gate electrode 2.
  • the substrate 1 is a transparent substrate, and preferably, the substrate 1 is a glass substrate.
  • Step 2 Form an oxide semiconductor layer 4 on the carrier.
  • the material of the oxide semiconductor layer 4 is indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the etch stop layer 5 is deposited on the oxide semiconductor layer 4 by chemical vapor deposition. Further, the etch stop layer 5 is formed on the oxide semiconductor layer by chemical vapor deposition of a SiOx film layer by TEOS+02 or SiH4+N20. 4 on.
  • Step 4 Two via holes 51, 53 are formed on the etch barrier layer 5 to expose a portion of the oxide semiconductor layer 4.
  • Step 5 The surface layer of the oxide semiconductor layer 4 exposed in the two via holes 51, 53 is removed, and two recesses 41, 43 respectively communicating with the two through holes 51, 53 are formed.
  • the surface layer of the oxide semiconductor layer 4 exposed in the two via holes 51, 53 is removed by dry etching or wet etching.
  • the surface layer of the oxide semiconductor layer 4 Since the surface layer of the oxide semiconductor layer 4 is damaged by 0 and H in the plasma during the formation of the etching stopper layer 5, the characteristics of the surface layer of the oxide semiconductor layer 4 are changed.
  • the surface layer of the oxide semiconductor layer 4 which has been damaged and has a characteristic change exposed in the two through holes 51, 53 is removed through this step 5.
  • the surface layer of the newly formed oxide semiconductor layer 4 in the recesses 41, 43 respectively communicating with the two through holes 51, 53 is uncorrupted and maintains the initial characteristics of the oxide semiconductor layer 4.
  • Step 6 Form a source 61 and a drain 63 on the etch barrier layer 5, and the source 61 fills a via 51 and a recess 41 communicating therewith to be connected to the oxide semiconductor layer 4, and the drain 63 is filled.
  • the other via hole 53 and the groove 43 communicating therewith are connected to the oxide semiconductor layer 4.
  • the source 61 and the drain 63 are formed on the etch barrier layer 5 by sputtering.
  • the source 61 and the drain 63 are respectively opposed to the oxide semiconductor layer which maintains the initial characteristics. 4 connections.
  • Step 7 Perform a post-process to form a protective layer 7 on the source 61 and the drain 63 to cover the source 61 and the drain 63.
  • FIG. 8 an electrical graph of a thin film transistor structure obtained by the above-described method for fabricating an oxide thin film transistor structure is shown.
  • the drain voltage Vd 10V
  • the threshold voltage Vth 0.2 V
  • the sub-value swing SS 0.13
  • the threshold voltage Vth is around 0V
  • the electrical properties of the sub-thickness swing structure are obviously good. . ' "
  • FIG. 14 is a second embodiment of a method for fabricating an oxide thin film transistor structure according to the present invention.
  • the second embodiment is suitable for fabricating a top gate barrier type thin film transistor structure.
  • the difference between this second embodiment and the first embodiment described above is that:
  • Step 1 Provide a carrier.
  • the carrier is a substrate ⁇ .
  • the substrate ⁇ is a transparent substrate, and preferably, the substrate ⁇ is a glass substrate.
  • Step 7 performing a post-process, forming a gate insulating layer 3' on the source 61 and the drain 63, and sputtering the gate 2' on the gate insulating layer 3'.
  • the present invention also provides an oxide thin film transistor structure which can be used for an LCD display device and an OLED display device.
  • FIG. 7 is a cross-sectional view showing a first embodiment of an oxide thin film transistor structure according to the present invention.
  • the oxide thin film transistor structure is a bottom gate barrier type, and includes: an oxide semiconductor layer 4; An etch stop layer 5 on the oxide semiconductor layer 4, and is located in the etch a source 61 and a drain 63 on the barrier layer 5, the etch stop layer 5 is provided with two through holes 51, 53, and the oxide semiconductor layer 4 is provided with two recesses corresponding to the two through holes 51, 53 respectively.
  • the grooves 41, 43, and the two grooves 41, 43 are respectively communicated with the two through holes 51, 53.
  • the source 61 fills a through hole 51 and a groove 41 communicating therewith, thereby forming an oxide semiconductor layer 4
  • the drain 63 fills another through hole 53 and a groove 43 communicating therewith, thereby being connected to the oxide semiconductor layer 4; further comprising a substrate 1, a gate 2 on the substrate 1, and a substrate 2 and a gate a gate insulating layer 3 on the second and a protective layer 7 on the source 61 and the drain 63; the oxide semiconductor layer 4 is disposed on the gate insulating layer 3.
  • the two recesses 41, 43 allow the source 61 and the drain 63 to be in contact with the oxide semiconductor layer 4 which maintains the initial characteristics, and it is possible to obtain good electrical properties.
  • the oxide thin film transistor structure is a top gate blocking type, which is the same as the first embodiment described above. The difference is that a substrate ⁇ , a gate insulating layer 3 ′ on the source 61 and the drain 63 , and a gate 2 ′ on the gate insulating layer 3 ′ are further included; the oxide semiconductor layer 4 is disposed on The substrate 1, on.
  • Other structures are the same as those of the first embodiment described above, and are not described herein again.
  • the method for fabricating the oxide thin film transistor structure of the present invention removes the oxide semiconductor which is changed by the destruction of 0 and yttrium in the plasma when the etch barrier layer is formed by etching.
  • the surface layer of the layer is such that the source and the drain are in contact with the oxide semiconductor layer which is not damaged and maintains the initial characteristics, so that the oxide thin film transistor obtained by the method has more stable and superior electrical properties, and the method Easy to operate.
  • the oxide thin film transistor structure provided by the present invention has two recesses corresponding to the two through holes of the etch barrier layer disposed in the oxide semiconductor layer, and the two recesses respectively communicate with the two through holes, so that the source and The drain is in contact with the oxide semiconductor layer which maintains the initial characteristics, so that good electrical properties can be obtained and the quality of the oxide thin film transistor can be improved.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种氧化物薄膜晶体管结构的制作方法及氧化物薄膜晶体管结构。该氧化物薄膜晶体管结构的制作方法包括如下步骤：步骤1、提供载体；步骤2、形成氧化物半导体层（4）；步骤3、形成蚀刻阻挡层（5）；步骤4、在蚀刻阻挡层（5）上形成两个通孔（51、53），露出部分氧化物半导体层（4）；步骤5、移除露置于两个通孔（51、53）内的氧化物半导体层（4）的表层，形成两个分别与该两个通孔（51、53）连通的凹槽（41、43）；步骤6、于蚀刻阻挡层（5）上形成源极（61）与漏极（63），且该源极（61）填充一个通孔（51）及与其连通的凹槽（41），该漏极（63）填充另一个通孔（53）及与其连通的凹槽（43）；步骤7，进行后制程。

Description

氣化物薄膜晶体管结构的制作方法及氣化物薄膜晶体管结构 技术领域
本发明涉及显示技术领域， 尤其涉及一种氧化物薄膜晶体管结构的制 作方法及氧化物薄膜晶体管结构。 背景技术
薄膜晶体管（ TFT )在电子装置中被广泛的作为开关装置和驱动装置使 用。 具体地， 因为薄膜晶体管可形成在玻璃基板或塑料基板上， 所以它们 通常用在诸如液晶显示装置 （LCD )、 有机发光显示装置 （OLED ) 等平板 显示装置领域。
氧化物半导体由于具有较高的电子迁移率 （氧化物半导体的电子迁移 率〉 10cm2/ Vs. 非晶硅（a-Si )的电子迁移率仅 0.5~0.8cm2/Vs )， 而且相比低 温多晶硅（LTPS ), 氧化物半导体制程简单， 与非晶硅制程相容性较高， 可 以应用于液晶显示装置、 有机发光显示装置、 柔性显示（Flexible )等领域， 且与高世代生产线兼容， 可应用于大中小尺寸显示， 具有良好的应用发展 前景， 为当前业界研究热门。
氧化物半导体在具有较高的电子迁移率、 制程简单等优点的同时， 目 前也存在着稳定性差， 受温、 湿度变化影响大， 氧化物薄膜晶体管电性随 时间漂移， 而且对制程条件， 如成膜速率、 制程气氛、 制程温度、 湿度控 制等要求较高的缺点。 此外， 氧化物薄膜晶体管除了对氧化物半导体层本 身， 对绝缘层、 氧化物半导体层与绝缘层的接触界面、 氧化物半导体层与 金属层接触界面都有较高的要求。
请参阅图 1，为一种现有的底栅阻挡型氧化物薄膜晶体管结构的剖面示 意图。 该氧化物薄膜晶体管结构的制作方法主要包括： 步骤 1、 提供一基板 ( 100 ); 步骤 2、 于基板（ 100 )上形成栅极（200 ); 步骤 3、 于基板（ 100 ) 与栅极（200 )上形成栅极绝缘层 （ 300 ), 使所述栅极绝缘层 （ 300 )覆盖 所述栅极（ 200 );步骤 4、于栅极绝缘层（ 300 )上形成氧化物半导体层（ 400 ); 步骤 5、 于氧化物半导体层 ( 400 ) 上形成蚀刻阻挡层 ( 500 ); 步骤 6、 在 蚀刻阻挡层 （ 500 )上通过蚀刻分别形成两个通孔（510、 530 ), 露出氧化 物半导体层（400 ); 步骤 7、 于蚀刻阻挡层（ 500 )上形成源极（610 )与漏 极（630 ), 所述源极（610 )填充一个通孔（510 ), 从而与氧化物半导体层 ( 400 )连接， 所述漏极（ 630 ) 填充另一个通孔（ 530 ), 从而与氧化物半 导体层 （400 )连接； 步骤 8、 于源极（610 ) 与漏极（630 )上形成保护层
( 700 ), 以覆盖源极 ( 610 )与漏极 ( 630 )。
在上述氧化物薄膜晶体管结构的制作方法中， 步骤 5 中蚀刻阻挡层
( 500 )一般采用由 TEOS+02或者 SiH4+N20化学气相沉积 SiOx膜层形 成， 但是在蚀刻阻挡层（ 500 )成膜过程中等离子体会影响氧化物半导体层
( 400 ) 的表面特性， 例如 SiH4+N20 中含氢， 与氧化物半导体层 ( 400 ) 的氧结合， 使得氧缺陷增加， 导致阔值电压 Vth偏负， 而 TEOS+02中的氧 会导致氧化物半导体层 ( 400 ) 中的氧缺陷减少， 使沟道的导电性降低。 因 此， 在源极（610 ) 与漏极（ 630 ) 成膜后， 源极（610 ) 与漏极（ 630 ) 与 受到破坏的氧化物半导体层（400 )表面接触， 最终影响该氧化物薄膜晶体 管的电性。请参阅图 2, 为该氧化物薄膜晶体管结构的制作方法制得的现有 氧化物薄膜晶体管结构的电性曲线图， 由图可知， 当漏极电压 Vd=10V时， 阔值电压 Vth= -5V， 亚阔值摆幅 S.S=0.45 , 该氧化物薄膜晶体管的电性较 差。 发明内容
本发明的目的在于提供一种氧化物薄膜晶体管结构的制作方法， 通过 该方法能够使源极和漏极与未受到破坏、 并保持初始特性的氧化物半导体 层接触， 使得通过该方法制得的氧化物薄膜晶体管具有更稳定、 更优异的 电性。
本发明的另一目的在于提供一种氧化物薄膜晶体管结构， 其具有良好 的电性， 能够提升氧化物薄膜晶体管的品质。
为实现上述目的， 本发明首先提供一种氧化物薄膜晶体管结构的制作 方法， 包括如下步骤：
步骤 1、 提供载体；
步骤 2、 于载体上形成氧化物半导体层；
步骤 3、 于氧化物半导体层上形成蚀刻阻挡层；
步骤 4、 在蚀刻阻挡层上形成两个通孔， 露出部分氧化物半导体层； 步骤 5、移除露置于两个通孔内的氧化物半导体层的表层， 形成两个分 别与该两个通孔连通的凹槽；
步骤 6、 于蚀刻阻挡层上形成源极与漏极， 且该源极填充一个通孔及与 其连通的凹槽， 从而与氧化物半导体层连接， 该漏极填充另一个通孔及与 其连通的凹槽， 从而与氧化物半导体层连接。
所述氧化物薄膜晶体管结构的制作方法， 通过化学气相沉积于氧化物 半导体层上形成蚀刻阻挡层； 通过千蚀刻在蚀刻阻挡层上形成两个通孔； 通过溅镀于蚀刻阻挡层上形成源极与漏极； 通过干蚀刻或者湿蚀刻移除露 置于两个通孔内的氧化物半导体层的表层。
所述蚀刻阻挡层采用由 TEOS+02或 SiH4+N20化学气相沉积 SiOx膜 层。
所述载体包括基板、 形成于基板上的栅极及形成于基板与栅极上的柵 极绝缘层。
所述氧化物薄膜晶体管结构的制作方法还包括步骤 7, 进行后制程， 该 后制程包括于源极与漏极上形成保护层， 以覆盖源极与漏极。
所述载体为一基板。
所述氧化物薄膜晶体管结构的制作方法还包括步骤 7， 进行后制程， 该 后制程包括于源极与漏极上形成栅极绝缘层， 并于该栅极绝缘层上溅镀栅 极。
本发明还提供一种氧化物薄膜晶体管结构， 包括： 氧化物半导体层、 位于氧化物半导体层上的蚀刻阻挡层、 及位于蚀刻阻挡层上的源极与漏极， 所述蚀刻阻挡层设有两个通孔， 所述氧化物半导体层分别对应该两个通孔 设置两个凹槽， 且该两个凹槽分别与该两个通孔连通， 该源极填充一个通 孔及与其连通的凹槽， 从而与氧化物半导体层连接， 该漏极填充另一个通 孔及与其连通的凹槽， 从而与氧化物半导体层连接。
所述氧化物薄膜晶体管结构还包括基板、 位于基板上的栅极、 位于该 基板与栅极上的栅极绝缘层及位于所述源极与漏极上的保护层； 所述氧化 物半导体层设置于所述栅极绝缘层上。
所述氧化物薄膜晶体管结构还包括一基板、 位于源极与漏极上的栅极 绝缘层及位于该栅极绝缘层上的栅极； 所述氧化物半导体层设置于所述基 板上。
本发明还提供一种氧化物薄膜晶体管结构， 包括： 氧化物半导体层、 位于氧化物半导体层上的蚀刻阻挡层、 及位于蚀刻阻挡层上的源极与漏极， 所述蚀刻阻挡层设有两个通孔， 所述氧化物半导体层分别对应该两个通孔 设置两个凹槽， 且该两个凹槽分别与该两个通孔连通， 该源极填充一个通 孔及与其连通的凹槽， 从而与氧化物半导体层连接， 该漏极填充另一个通 孔及与其连通的凹槽， 从而与氧化物半导体层连接；
所述氧化物薄膜晶体管结构还包括基板、 位于基板上的栅极、 位于该 半导体层设置于所述栅极绝缘层上 ;'、 ― 、 ― " 本发明的有益效果： 本发明提供的氧化物薄膜晶体管结构的制作方法 , 或者湿蚀刻， 去除了因蝕刻阻挡层成膜时受等离子体中 0及 H的破坏而导 致特性发生变化的氧化物半导体层的表层， 使得源极和漏极与未受到破坏、 并保持初始特性的氧化物半导体层接触， 所以通过该方法制得的氧化物薄 膜晶体管具有更稳定、 更优异的电性， 且该方法简便易操作。 本发明提供 的氧化物薄膜晶体管结构， 通过在氧化物半导体层设置与蚀刻阻挡层两通 孔对应的两个凹槽， 且该两个凹槽分别与该两个通孔连通， 使得源极和漏 极与保持初始特性的氧化物半导体层接触， 从而能够获取良好的电性并提 升氧化物薄膜晶体管的品质。 附图说明
为了能更进一步了解本发明的特征以及技术内容， 请参阅以下有关本 发明的详细说明与附图， 然而附图仅提供参考与说明用， 并非用来对本发 明加以限制。
附图中，
图 1为一种现有的氧化物薄膜晶体管结构的剖面示意图；
图 2为现有氧化物薄膜晶体管的电性曲线图；
图 3 为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的流程 图；
图 4为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的步骤 4 的示意图；
图 5为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的步骤 5 的示意图；
图 6为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的步骤 6 的示意图；
图 7为本发明氧化物薄膜晶体管结构的制作方法的第一实施例的步骤 7 的示意图暨本发明氧化物薄膜晶体管结构的第一实施例的剖面示意图； 图 8为本发明氧化物薄膜晶体管结构的电性曲线图；
图 9为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的流程 图；
图 10为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤 3的示意图；
图 11为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤 4的示意图；
图 12为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤 5的示意图；
图 13为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤 6的示意图；
图 14为本发明氧化物薄膜晶体管结构的制作方法的第二实施例的步骤 7的示意图暨本发明氧化物薄膜晶体管结构的第二实施例的剖面示意图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果， 以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 3至图 7 ,为本发明氧化物薄膜晶体管结构的制作方法的第一 实施例， 该第一实施例适用于制作底栅阻挡型的薄膜晶体管结构， 其包括 如下步骤：
步骤 1、 提供载体。
在该第一实施例中， 所述载体包括： 基板 1、 形成于基板 1上的栅极 2 及形成于基板 1与栅极 2上的栅极绝缘层 3。 所述基板 1为透明基板，优选 的， 所述基板 1为玻璃基板。
步骤 2、 于载体上形成氧化物半导体层 4。
优选的， 所述氧化物半导体层 4的材料为铟镓锌氧化物 （IGZO )。 步骤 3、 于氧化物半导体层 4上形成蚀刻阻挡层 5。
所述蚀刻阻挡层 5通过化学气相沉积于氧化物半导体层 4上， 进一步 的， 所述蚀刻阻挡层 5采用由 TEOS+02或 SiH4+N20化学气相沉积 SiOx 膜层形成于所述氧化物半导体层 4上。
步骤 4、 在蚀刻阻挡层 5上形成两个通孔 51、 53 , 露出部分氧化物半 导体层 4。
在该步骤 4中，通过干蚀刻的方式在蚀刻阻挡层 5上形成两个通孔 51、
53。
步骤 5、 移除露置于两个通孔 51、 53内的氧化物半导体层 4的表层， 形成两个分别与该两个通孔 51、 53连通的凹槽 41、 43。
在该步骤 5中，通过干蚀刻或者湿蚀刻的方式移除露置于两个通孔 51、 53内的氧化物半导体层 4的表层。
由于所述氧化物半导体层 4的表层在蚀刻阻挡层 5形成的过程中， 受 等离子体中 0及 H的破坏， 导致氧化物半导体层 4的表层的特性发生了变 化， 而经该步骤 5移除了露置于两个通孔 51、 53内的已受到破坏且特性发 生变化的氧化物半导体层 4的的表层。 所述两个分别与该两个通孔 51、 53 连通的凹槽 41、 43内新形成的氧化物半导体层 4的的表层则未受破坏并保 持氧化物半导体层 4的初始特性。
步骤 6、 于蚀刻阻挡层 5上形成源极 61与漏极 63， 且该源极 61填充 一个通孔 51及与其连通的凹槽 41 ,从而与氧化物半导体层 4连接， 该漏极 63填充另一个通孔 53及与其连通的凹槽 43， 从而与氧化物半导体层 4连 接。
具体的， 所述源极 61 与漏极 63通过溅镀的方式形成于蚀刻阻挡层 5 上。
由于所述凹槽 41、 43内的氧化物半导体层 4的表层未受破坏并保持氧 化物半导体层 4的初始特性， 所述源极 61与漏极 63分别与保持初始特性 的氧化物半导体层 4连接。
步骤 7、 进行后制程， 于源极 61与漏极 63上形成保护层 7, 以覆盖源 极 61与漏极 63。
请参阅图 8，为通过上述氧化物薄膜晶体管结构的制作方法制得的薄膜 晶体管结构的电性曲线图。 由图可知， 当漏极电压 Vd=10V时， 阔值电压 Vth= 0.2 V, 亚阐值摆幅 S.S=0.13， 阔值电压 Vth在 0V附近， 亚阔值摆幅 结构的电性得到明显 善。 ' "
请参阅图 9至图 14, 为本发明氧化物薄膜晶体管结构的制作方法的第 二实施例， 该笫二实施例适用于制作顶栅阻挡型的薄膜晶体管结构。 该第 二实施例与上述第一实施例的区别在于：
步骤 1 : 提供载体。
在该第二实施例中， 所述载体为 1基板 Γ。 所述基板 Γ为透明基板， 优选的， 所述基板 Γ为玻璃基板。
步骤 7: 进行后制程， 于源极 61与漏极 63上形成栅极绝缘层 3'， 并于 该栅极绝缘层 3'上溅镀栅极 2'。
其它步骤 2-6与上述第一实施例相同， 此处不再赘述。
在该氧化物薄膜晶体管结构的制作方法的基础上， 本发明还提供一种 氧化物薄膜晶体管结构， 可用于 LCD显示装置与 OLED显示装置。
请参阅图 7 , 为本发明氧化物薄膜晶体管结构第一实施例的剖面示意 图， 在该第一实施例中， 所述氧化物薄膜晶体管结构为底栅阻挡型， 包括： 氧化物半导体层 4、 位于氧化物半导体层 4上的蚀刻阻挡层 5、 及位于蚀刻 阻挡层 5上的源极 61与漏极 63 , 所述蚀刻阻挡层 5设有两个通孔 51、 53 , 所述氧化物半导体层 4分别对应该两个通孔 51、 53设置两个凹槽 41、 43， 且该两个凹槽 41、 43分别与该两个通孔 51、 53连通、 该源极 61填充一个 通孔 51及与其连通的凹槽 41 , 从而与氧化物半导体层 4连接， 该漏极 63 填充另一个通孔 53及与其连通的凹槽 43 , 从而与氧化物半导体层 4连接； 还包括基板 1、 位于基板 1上的柵极 2、 位于该基板 1与柵极 2上的栅极绝 缘层 3及位于所述源极 61与漏极 63上的保护层 7; 所述氧化物半导体层 4 设置于所述栅极绝缘层 3上。 值得一提的是， 所述两个凹槽 41、 43使得源 极 61和漏极 63与保持初始特性的氧化物半导体层 4接触， 能够获取良好 的电性。
请参阅图 14， 为本发明氧化物薄膜晶体管结构第二实施例的剖面示意 图， 在该第二实施例中， 所述氧化物薄膜晶体管结构为顶栅阻挡型， 其与 上述第一实施例的区别在于， 还包括一基板 Γ、 位于源极 61与漏极 63上 的栅极绝缘层 3'及位于该栅极绝缘层 3'上的栅极 2'； 所述氧化物半导体层 4设置于所述基板 1，上。 其它结构与上述第一实施例相同， 此处不再赘述。
综上所述， 本发明的氧化物薄膜晶体管结构的制作方法， 通过对露置 刻， 去除了因蚀刻阻挡层成膜时受等离子体中 0及 Η的破坏而导致特性发 生变化的氧化物半导体层的表层， 使得源极和漏极与未受到破坏、 并保持 初始特性的氧化物半导体层接触， 所以通过该方法制得的氧化物薄膜晶体 管具有更稳定、 更优异的电性， 且该方法简便易操作。 本发明提供的氧化 物薄膜晶体管结构， 通过在氧化物半导体层设置与蚀刻阻挡层两通孔对应 的两个凹槽， 且该两个凹槽分别与该两个通孔连通， 使得源极和漏极与保 持初始特性的氧化物半导体层接触， 从而能够获取良好的电性并提升氧化 物薄膜晶体管的品质。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明后附的权利要求的保护范围。

Claims

1、 一种氧化物薄膜晶体管结构的制作方法， 包括如下步骤： 步骤 1、 提供载体；
步骤 2、 于载体上形成氧化物半导体层；
步骤 3、 于氧化物半导体层上形成蚀刻阻挡层；
步骤 4、 在蚀刻阻挡层上形成两个通孔， 露出部分氧化物半导体层； 步骤 5、移除露置于两个通孔内的氧化物半导体层的表层， 形成两个分 别与该两个通孔连通的凹槽；
步骤 6、 于蚀刻阻挡层上形成源极与漏极， 且该源极填充一个通孔及与 其连通的凹槽， 从而与氧化物半导体层连接， 该漏极填充另一个通孔及与 其连通的凹槽， 从而与氧化物半导体层连接。
2、 如权利要求 1所述的氧化物薄膜晶体管结构的制作方法， 其中， 通 过化学气相沉积于氧化物半导体层上形成蚀刻阻挡层； 通过千蚀刻在蚀刻 阻挡层上形成两个通孔； 通过溅镀于蚀刻阻挡层上形成源极与漏极； 通过 千蚀刻或者湿蚀刻移除露置于两个通孔内的氧化物半导体层的表层。
3、 如权利要求 2所述的氧化物薄膜晶体管结构的制作方法， 其中， 所 述蚀刻阻挡层采用由 TEOS+02或 SiH4+N20化学气相沉积 SiOx膜层。
4、 如权利要求 1所述的氧化物薄膜晶体管结构的制作方法， 其特征在 于， 所述载体包括基板、 形成于基板上的栅极及形成于基板与栅极上的栅 极绝缘层。
5、 如权利要求 4所述的氧化物薄膜晶体管结构的制作方法， 还包括步 骤 7， 进行后制程， 该后制程包括于源极与漏极上形成保护层， 以覆盖源极 与漏极。
6、 如权利要求 1所述的氧化物薄膜晶体管结构的制作方法， 其中， 所 述载体为一基板。
7、 如权利要求 6所述的氧化物薄膜晶体管结构的制作方法， 还包括步 骤 7， 进行后制程， 该后制程包括于源极与漏极上形成栅极绝缘层， 并于该 栅极绝缘层上溅镀栅极。
8、 一种氧化物薄膜晶体管结构， 包括： 氧化物半导体层、 位于氧化物 半导体层上的蚀刻阻挡层、 及位于蚀刻阻挡层上的源极与漏极， 所述蚀刻 阻挡层设有两个通孔， 所述氧化物半导体层分别对应该两个通孔设置两个 凹槽， 且该两个凹槽分别与该两个通孔连通， 该源极填充一个通孔及与其 连通的凹槽， 从而与氧化物半导体层连接， 该漏极填充另一个通孔及与其 连通的凹槽， 从而与氧化物半导体层连接。
9、 如权利要求 8所述的氧化物薄膜晶体管结构， 还包括基板、 位于基 的保护层; 所述氧化 半 体层设置于所述栅极绝缘层上。 ' "、 一 "
10、 如权利要求 8所述的氧化物薄膜晶体管结构， 还包括一基板、 位 于源极与漏极上的栅极绝缘层及位于该栅极绝缘层上的栅极； 所述氧化物 半导体层设置于所述基板上。
11、 一种氧化物薄膜晶体管结构， 包括： 氧化物半导体层、 位于氧化 物半导体层上的蚀刻阻挡层、 及位于蚀刻阻挡层上的源极与漏极， 所述蚀 刻阻挡层设有两个通孔， 所述氧化物半导体层分别对应该两个通孔设置两 个凹槽， 且该两个凹槽分别与该两个通孔连通， 该源极填充一个通孔及与 其连通的凹槽， 从而与氧化物半导体层连接， 该漏极填充另一个通孔及与 其连通的凹槽， 从而与氧化物半导体层连接；
所述的氧化物薄膜晶体管结构， 还包括基板、 位于基板上的栅极、 位 氧化 半 体层设置于所述栅极绝缘层上。：λ、 二、 ― ；
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