WO2015180358A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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Publication number
WO2015180358A1
WO2015180358A1 PCT/CN2014/088080 CN2014088080W WO2015180358A1 WO 2015180358 A1 WO2015180358 A1 WO 2015180358A1 CN 2014088080 W CN2014088080 W CN 2014088080W WO 2015180358 A1 WO2015180358 A1 WO 2015180358A1
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WO
WIPO (PCT)
Prior art keywords
layer
common electrode
wire
film layer
array substrate
Prior art date
Application number
PCT/CN2014/088080
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English (en)
French (fr)
Inventor
杨盛际
董学
王海生
薛海林
刘英明
赵卫杰
刘红娟
丁小梁
王磊
王春雷
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/655,552 priority Critical patent/US20160259445A1/en
Priority to EP14873105.2A priority patent/EP3153957A4/en
Publication of WO2015180358A1 publication Critical patent/WO2015180358A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G06F3/0354—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
    • G06F3/03545—Pens or stylus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • the Touch Screen Panel has gradually spread throughout people's lives.
  • the touch structure included in the touch screen can be divided into: a mutual capacitance touch structure and a self capacitance contact structure.
  • self-capacitance touch structures due to the accuracy of their touch sensing and high signal-to-noise ratio, they are favored by major panel manufacturers.
  • the self-capacitance touch structure utilizes the principle of self-capacitance to detect the touch position of the finger.
  • a plurality of self-capacitance electrodes arranged in the same layer and independent of each other are disposed.
  • the capacitance of the respective capacitor electrodes is a fixed value
  • the touch detection chip can determine the touch position by detecting the change of the capacitance value of each capacitor electrode during the touch time period.
  • the present invention provides an array substrate comprising: a substrate, a gate and a gate line on the substrate, and an active layer on the film layer where the gate and the gate line are located;
  • the array substrate further includes: a pixel electrode disposed in the same layer as the active layer and electrically insulated; a drain, a source, and a data line on the film layer where the active layer and the pixel electrode are located, wherein the drain The pole is directly electrically connected to the pixel electrode; the common electrode layer and the plurality of strips are located on the film layer where the drain, the source and the data line are located, and are electrically insulated from the drain, the source, the data line and the pixel electrode wire.
  • the common electrode layer is disposed in a different layer from the common electrode layer, and the common electrode layer includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, and each of the wires is electrically connected to the corresponding self-capacitance electrode through the via hole. .
  • the present invention provides a display device comprising the above array substrate.
  • the present invention provides a method of fabricating the array substrate, including:
  • drain Forming the drain, the source, and the data line on the film layer where the active layer and the pixel electrode are located; wherein the drain is directly electrically connected to the pixel electrode;
  • the wire is disposed in a different layer from the common electrode layer, and the common electrode layer comprises a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, and each of the wires passes through the via hole and the corresponding self-capacitance electrode Sexual connection.
  • 1 is a top plan view of a known capacitive touch structure
  • FIG. 2 is a side view of an array substrate in an embodiment of the present invention.
  • FIG. 3 is a schematic diagram showing a positional relationship between a wire and a data line in an embodiment of the present invention
  • FIG. 4 is a top plan view of a capacitive touch structure in an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing driving timings of a display device according to an embodiment of the present invention.
  • each self-capacitance electrode needs to be connected to the touch detection chip through a separate lead wire.
  • each lead wire includes: a wire connecting the self-capacitance electrode 1 to the frame of the touch screen. 2, and a peripheral trace 4 disposed at the bezel for conducting the self-capacitance electrode 1 to the terminal 3 of the touch detection chip.
  • each self-capacitance electrode since the number of self-capacitance electrodes is very large, the corresponding lead-out lines are also very large. For example, the area occupied by each self-capacitance electrode is 5 mm*5 mm, and the 5-inch liquid crystal display requires 264 pieces. Self-capacitance electrodes, if each self-capacitance electrode is designed to be smaller, there will be more self-capacitance electrodes, then more lead wires need to be set.
  • the wires 2 and the self-capacitance electrodes 1 in the lead wires are generally disposed in the same layer, and more wires 2 cause the touch dead zone to be large, wherein
  • the touch blind zone refers to the area where the traces are concentrated in the touch screen, and the signals in the touch blind zone are relatively It is relatively turbulent, so it is called a touch dead zone, that is, the touch performance in this area cannot be guaranteed. Therefore, the touch blind area in the current self-capacitance touch structure is too large, and the touch performance of the touch screen including the self-capacitance touch structure is relatively poor.
  • an array substrate provided by an embodiment of the present invention includes: a substrate 00, a gate 11 and a gate line 12 on the substrate 00, where the gate 11 and the gate line 12 are located.
  • An active layer 20 on the film layer; the array substrate further includes:
  • a pixel electrode 40 disposed in the same layer as the active layer 20 and electrically insulated;
  • drain 31 is directly electrically connected to the pixel electrode 40;
  • the wire 60 is disposed in a different layer from the common electrode layer 50, and the common electrode layer 50 is disposed.
  • a plurality of self-capacitance electrodes 51 disposed in the same layer and insulated from each other are included, and each of the wires 60 is electrically connected to the corresponding self-capacitance electrode 51 through the via 100.
  • the array substrate includes a common electrode layer and a wire
  • the common electrode layer includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, and each of the wires is electrically connected to the corresponding self-capacitance electrode;
  • the touch electrodes (ie, self-capacitance electrodes) and the wires in the self-capacitance touch structure are embedded in the array substrate to facilitate the implementation of the in-cell touch panel.
  • the touch dead zone in the self-capacitance touch structure can be eliminated to improve the touch performance of the touch screen including the self-capacitance touch structure.
  • the common electrode layer includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, the common electrode layer can be used as a touch electrode in the self-capacitance touch structure, thereby avoiding separately setting the film layer of the touch electrode. To simplify the number of layers.
  • the pixel electrode is disposed in the same layer as the active layer, and the drain is directly electrically connected to the pixel electrode, which can reduce the number of layers included in the array substrate. Moreover, since the via hole for electrically connecting the pixel electrode and the drain is prevented from being formed by using the reticle, the complexity and cost of fabricating the array substrate can be reduced.
  • the positional connection relationship of the wires in the embodiment of the present invention may be as follows: the film is located above the drain, the source, and the data line, and the drain, the source, the data line, and the pixel electrode. Electrically insulating; and being disposed in a different layer from the common electrode layer, and each of the wires is electrically connected to a corresponding self-capacitance electrode through a via.
  • the film layer where the wire is located is located between the film layer where the drain, the source and the data line are located, and the common electrode layer.
  • the film layer of the wire is located between the film layer where the drain, the source and the data line are located, and the common electrode layer, which can reduce the interference of the human body capacitance on the signal transmitted on the wire.
  • a passivation layer is disposed between the film layer where the drain, the source and the data line are located, and the common electrode layer; the film layer where the wire is located may be located at the film layer where the drain, the source and the data line are located. Between the passivation layer and the passivation layer, it may also be located between the passivation layer and the common electrode layer.
  • a passivation layer 70 is disposed between the film layer where the drain 31, the source 32 and the data line 33 are located, and the common electrode layer 50.
  • a film layer is between the passivation layer 70 and the common electrode layer 50.
  • the array substrate further includes:
  • a first insulating layer 80 including the via 100 is located between the film layer where the wire 60 is located and the common electrode layer 50;
  • the wire 60 is electrically connected to the self-capacitance electrode 51 through the via 100 included in the first insulating layer 80.
  • the film layer where the wire is located is located between the film layer where the drain, the source and the data line are located, and the passivation layer, and the film layer where the wire is located is located in the passivation layer.
  • the embodiment is similar to the embodiment of the common electrode layer; however, when the film layer where the wire is located is located between the film layer where the drain, the source and the data line are located and the passivation layer, An insulating layer needs to be located between the film layer where the drain, source and data lines are located and the film layer where the wires are located, and does not include via holes, and the passivation layer needs to include via holes.
  • a gate insulating layer 90 is disposed between the film layer where the gate electrode 11 and the gate line 12 are located and the film layer where the active layer 20 and the pixel electrode 40 are located.
  • the film layer where the wire is located is located above the common electrode layer.
  • the film layer on which the wire is located is located above the common electrode layer, and can ensure that the connection relationship between the film layers included in the existing array substrate is not changed.
  • the array substrate further includes:
  • a second insulating layer including the via hole between the film layer where the wire is located and the common electrode layer;
  • the wire is electrically connected to the self-capacitance electrode through a via hole included in the second insulating layer.
  • the position of the wire of the embodiment of the present invention will be described below based on the relationship between the position of the wire and the position of the gate line and/or the data line.
  • an orthographic projection of the wire on the substrate substrate is within an orthographic projection of the data line on the substrate; and/or an orthographic projection of the wire on the substrate is located
  • the effect of the gate line on the underlying projection on the substrate substrate is as follows: 1) it can be ensured that the electric field generated by the wire does not affect the electric field of the pixel opening region, thereby not affecting the normal display; 2) can be avoided Affect the transmittance; 3) It can ensure that the extending direction of each wire is consistent with the extending direction of the data line, which is advantageous for the narrow frame design.
  • the via 100 is electrically connected to the corresponding self-capacitance electrode 51.
  • the orthographic projection of the wire 60 on the base substrate (the substrate substrate not shown in Fig. 3) is located within the orthographic projection of the data line 33 on the base substrate.
  • the embodiment of the positional relationship between the wire and the gate line and the data line in the embodiment of the present invention may also be other embodiments, for example, the data line and/or the gate line are in the lining.
  • An orthographic projection on the base substrate is located within an orthographic projection of the wire on the substrate; or an orthographic projection of the wire on the substrate is associated with the data line and/or gate line.
  • the orthographic projections on the substrate substrate overlap; or the orthographic projection of the wires on the substrate substrate does not overlap with the orthographic projection of the data lines and/or gate lines on the substrate substrate, etc. , will not repeat them here.
  • one self-capacitance electrode may be electrically connected to at least one wire, and the wires of the respective capacitor electrodes are electrically connected.
  • the positional relationship between the wire, the self-capacitance electrode and the common electrode layer in the embodiment of the present invention will be described below by taking FIG. 4 as an example.
  • the common electrode layer 50 includes a plurality of self-capacitance electrodes 51 arranged in a matrix and insulated from each other in a matrix arrangement.
  • One wire 60 is electrically connected to one self-capacitance electrode 51, and the wires 60 to which the respective capacitor electrodes 51 are electrically connected are different.
  • the wires 60 are disposed in different layers from the common electrode layer 50, and each of the wires 60 is electrically connected to the corresponding self-capacitance electrode 51 through the via 100.
  • the use of the wire 60 as a common electrode line for supplying power to the common electrode layer 50 during the display scanning time can save the number of traces included in the array substrate to reduce the complexity of fabricating the array substrate.
  • the common electrode line for supplying power to the common electrode layer during the scanning time can also avoid performing via etching on the film layers between the film layer and the common electrode layer where the gate and the gate line are located to electrically connect the common electrode line. And a common electrode layer to reduce the reticle used to fabricate the array substrate, reducing the cost and complexity of fabricating the array substrate.
  • the embodiment of the invention further provides a display device comprising the array substrate of the above embodiment.
  • the display device is, for example, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like, and any product or component having a display function.
  • a mobile phone for example, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like, and any product or component having a display function.
  • the display device including the array substrate has both Display function and touch function.
  • the array substrate of the embodiment of the present invention can eliminate the touch dead zone in the self-capacitance touch structure and can simplify the number of layers. Therefore, the display device of the array substrate can also eliminate the touch dead zone and improve the touch performance. Moreover, the number of layers can be simplified.
  • the display device further includes: a color filter substrate disposed opposite to the array substrate.
  • the color filter substrate includes a substrate substrate, a black matrix layer, a color film layer, a planarization layer, and a PS (cushion layer) laminated in this order.
  • An embodiment of the present invention further provides a scanning method of a display device, including:
  • the driving signals are applied to the respective capacitor electrodes in a time-sharing manner through the wires connected to the respective capacitor electrodes; the feedback signals of the respective capacitor electrodes are received, and the touch position is determined according to the feedback signals.
  • Time-division touch scanning and display scanning can reduce mutual interference between display signals and touch signals, and improve picture quality and touch accuracy.
  • the touch detection chip can apply a driving signal to the respective capacitor electrodes in a time-sharing manner through the wires connected to the respective capacitor electrodes; receive the feedback signals of the respective capacitor electrodes, and determine the touch position according to the feedback signals.
  • the touch detection chip is disposed on the circuit board, for example, on a circuit board located at the back of the display device, and may be disposed on a circuit board located in a frame area of the display device, or may be disposed on the flexible circuit board included in the array substrate. on.
  • the display driver chip and the touch detection chip can be integrated into one chip to reduce the production cost.
  • a scanning method of the display device in the embodiment of the present invention will be described in detail below with reference to FIG.
  • the time at which the display device displays each frame is divided into a display scan period (Display) and a touch scan period (Touch), for example, the display device displays a frame time of 16.7 ms. 5 ms is selected as the touch scanning time period, and the other 11.7 ms is used as the display scanning time period.
  • the duration of the two chips can be appropriately adjusted according to the processing capability of the IC chip, and is not specifically limited herein.
  • a gate scan signal is sequentially applied to each of the gate signal lines Gate1, Gate2, ..., Gate n in the display device, and a gray scale signal is applied to the data signal line Data to realize a display function.
  • the touch detection chip applies a driving signal to the respective capacitor electrodes Cx1 . . . Cxn in a time division manner; at the same time, receives the feedback signals of the respective capacitance electrodes Cx1 . . . Cxn, and passes through the respective capacitance electrodes Cx1 . . . Cxn
  • the analysis of the feedback signal determines the touch position to implement the touch function.
  • the implementation of the touch detection chip to determine the touch position by the analysis of the feedback signals of the respective capacitor electrodes Cx1 . . . Cxn is similar to the prior art embodiment, and details are not described herein again.
  • the Vcom voltage is applied to each of the capacitor electrodes to ensure that the display device is normally displayed.
  • applying a GND signal on the data signal line and each gate signal line during the touch time period can reduce the signal transmitted on the data signal line and each gate signal line to the signal transmitted on the line. interference.
  • the respective capacitor electrodes may be scanned one by one in the lateral direction, and the driving signals may be applied to the respective capacitor electrodes in a time-sharing manner; or the respective capacitor electrodes may be scanned one by one in the vertical direction to time-divide to the respective capacitor electrodes.
  • a driving signal it is also possible to apply a driving signal to the respective capacitor electrodes by means of an all driving.
  • the embodiment of the invention further provides a method for fabricating an array substrate, comprising:
  • Step 101 forming the gate and the gate line on the base substrate
  • Step 102 forming the active layer and the pixel electrode disposed in the same layer and electrically insulated on the film layer on which the gate and the gate line are located;
  • Step 103 forming the drain, the source, and the data line on the film layer where the active layer and the pixel electrode are located; wherein the drain is directly electrically connected to the pixel electrode;
  • Step 104 forming a common electrode layer and a plurality of wires electrically insulated from the drain, the source, the data line and the pixel electrode on the film layer on which the drain, the source and the data line are located;
  • the wire is disposed in a different layer from the common electrode layer, and the common electrode layer comprises a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, and each of the wires passes through the via hole and the corresponding self-capacitance electrode Sexual connection.
  • the method is described in detail below by an example.
  • the method for fabricating the array substrate provided in this example, as shown in FIG. 2, includes:
  • Step 1 forming a gate 11 and a gate line 12 on the substrate 00;
  • a common electrode line disposed in the same layer as the gate and the gate line and electrically insulated is formed on the substrate.
  • the common electrode line may or may not be fabricated.
  • Step 2 forming a gate insulating layer 90 on the film layer where the gate 11 and the gate line 12 are located;
  • Step 3 forming a same layer and electrically insulating active layer 20 and pixel electrode 40 on the gate insulating layer 90;
  • an active layer is formed on the gate insulating layer by an active mask process; the pixel electrode is formed on the gate insulating layer by a Pixel ITO Mask process.
  • the gate insulating layer needs to be etched to form a via hole exposing the common electrode line in the gate insulating layer; in the embodiment of the invention, when the common electrode line is not formed, it is not necessary. This etching step is performed.
  • Step 4 forming the drain 31, the source 32, and the data line 33 on the film layer where the active layer 20 and the pixel electrode 40 are located; wherein the drain 31 is directly electrically connected to the pixel electrode 40;
  • the drain, source, and data lines are formed by a single SD Mask process.
  • the drain 31 and the source 32 are respectively disposed on two sides of the active layer 20 , the source 32 is directly electrically connected to the active layer 20 , and the drain 31 is directly electrically connected to the pixel electrode 40 .
  • Step 5 forming a passivation layer 70 on the film layer where the drain 31, the source 32 and the data line 33 are located;
  • the patterned passivation layer it is necessary to form a via hole exposing the common electrode line in the passivation layer; and in the embodiment of the invention, when the common electrode line is not formed, it is not necessary to form an exposed common in the passivation layer.
  • the via of the electrode wire it is necessary to form a via hole exposing the common electrode line in the passivation layer; and in the embodiment of the invention, when the common electrode line is not formed, it is not necessary to form an exposed common in the passivation layer.
  • Step 6 forming a wire 60 on the passivation layer 70;
  • the wires are formed by a single Metal Wire Mask process.
  • Step 7 forming an insulating layer 80 on the film layer where the wire 60 is located, the insulating layer 80 includes a via hole 100 exposing the wire 60;
  • an insulating layer including via holes is formed by an Insulating Layer Mask process.
  • the insulating layer when the insulating layer is formed, it is necessary to form a via hole exposing the common electrode line in the insulating layer; and, when the material of the insulating layer is the same as the material of the passivation layer, the insulating layer and the passivation may be performed.
  • the layers are etched together to form vias that expose the common electrode lines.
  • Step 8 Form a self-capacitance electrode including a plurality of layers disposed in the same layer and insulated from each other on the insulating layer 80.
  • the common electrode layer 50 of the 51; the wire 60 is electrically connected to the corresponding self-capacitance electrode 51 through the via 100 included in the insulating layer 80.
  • the common electrode layer is formed, for example, by an ITO Mask (Public Electrode Layer Mask) process.
  • the embodiment of the invention further provides a method for manufacturing a color film substrate, comprising:
  • Step 1 Form a black matrix layer on the base substrate
  • a black matrix layer is formed on a base substrate by a BM Mask (black matrix layer mask) process.
  • BM Mask black matrix layer mask
  • Step 2 forming an RGB (red, green, blue) color film layer on the black matrix layer;
  • the RGB is formed on the black matrix layer by an R Mask (red sub-pixel unit mask) process, a G Mask (green sub-pixel unit mask) process, and a Mask (blue sub-pixel unit mask) process, respectively.
  • R Mask red sub-pixel unit mask
  • G Mask green sub-pixel unit mask
  • Mask blue sub-pixel unit mask
  • Step 3 forming a planarization layer on the RGB color film layer
  • Step 4 Form a spacer on the planarization layer.
  • the PS is formed by a single PS Mask process.
  • the array substrate includes a common electrode layer and a wire
  • the common electrode layer includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, and each of the wires is electrically connected to the corresponding self-capacitance electrode;
  • the touch electrodes (ie, self-capacitance electrodes) and the wires in the self-capacitance touch structure are embedded in the array substrate to facilitate the implementation of the in-cell touch screen.
  • the touch dead zone in the self-capacitance touch structure can be eliminated to improve the touch performance of the touch screen including the self-capacitance touch structure.
  • the common electrode layer includes a plurality of self-capacitance electrodes disposed in the same layer and insulated from each other, the common electrode layer can be used as a touch electrode in the self-capacitance touch structure, thereby avoiding separately setting the film layer of the touch electrode. To simplify the number of layers.

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Abstract

一种阵列基板及其制作方法和显示装置。阵列基板包括：位于衬底基板上（00）的栅极（11）和栅线（12），位于栅极（11）和栅线（12）所在膜层上的有源层（20）。所述阵列基板还包括：与有源层（20）同层设置且电性绝缘的像素电极（40）；位于有源层（20）和像素电极（40）所在膜层上的漏极（31）、源极（32）和数据线（33），其中漏极（31）与像素电极（40）直接电性连接；位于漏极（31）、源极（32）和数据线（33）所在膜层上，且与漏极（31）、源极（32）、数据线（33）和像素电极（40）电性绝缘的公共电极层（50）和多条导线（60）；其中，导线（60）与所述公共电极层（50）异层设置，公共电极层（50）包括多个同层设置且相互绝缘的自电容电极（51），且每条导线（60）通过过孔（100）与对应的自电容电极（51）电性连接。该阵列基板解决了自电容触摸结构中的触控盲区偏大的问题。

Description

阵列基板及其制作方法和显示装置 技术领域
本发明实施例涉及一种阵列基板及其制作方法和显示装置。
背景技术
随着显示技术的飞速发展，触摸屏(Touch Screen Panel)已经逐渐遍及人们的生活中。目前，触摸屏包括的触摸结构可以分为：互电容触摸结构和自电容触摸结构。对于自电容触摸结构，由于其触控感应的准确度和信噪比比较高，因而受到了各大面板厂家青睐。
目前，自电容触摸结构利用自电容的原理实现检测手指触摸位置。例如，在触摸结构中设置多个同层设置且相互独立的自电容电极，当人体未触碰屏幕时，各自电容电极所承受的电容为一固定值，当人体触碰屏幕时，触碰位置对应的自电容电极所承受的电容为固定值叠加人体电容，触控检测芯片在触控时间段通过检测各自电容电极的电容值变化可以判断出触控位置。
发明内容
第一方面，本发明提供一种阵列基板，包括：衬底基板，位于所述衬底基板上的栅极和栅线，位于所述栅极和栅线所在膜层上的有源层；所述阵列基板还包括：与所述有源层同层设置且电性绝缘的像素电极；位于所述有源层和像素电极所在膜层上的漏极、源极和数据线，其中所述漏极与像素电极直接电性连接；位于所述漏极、源极和数据线所在膜层上，且与所述漏极、源极、数据线和像素电极电性绝缘的公共电极层和多条导线。所述导线与所述公共电极层异层设置，所述公共电极层包括多个同层设置且相互绝缘的自电容电极，且每条所述导线通过过孔与对应的自电容电极电性连接。
第二方面，本发明提供一种显示装置，包括上述的阵列基板。
第三方面，本发明提供一种制作所述的阵列基板的方法，包括：
在衬底基板上形成所述栅极和栅线；
在所述栅极和栅线所在膜层上形成同层设置且电性绝缘的所述有源层和像素电极；
在所述有源层和像素电极所在膜层上形成所述漏极、源极和数据线；其中，所述漏极与像素电极直接电性连接；
在所述漏极、源极和数据线所在膜层上形成与所述漏极、源极、数据线和像素电极电性绝缘的公共电极层和多条导线；
其中，所述导线与所述公共电极层异层设置，所述公共电极层包括多个同层设置且相互绝缘的自电容电极，且每条所述导线通过过孔与对应的自电容电极电性连接。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为已知电容式触摸结构的俯视图；
图2为本发明实施例中的阵列基板的侧视图；
图3为本发明实施例中的导线和数据线的位置关系示意图；
图4为本发明实施例中的电容式触摸结构的俯视图；
图5为本发明实施例中的显示装置的驱动时序示意图。
具体实施方式
在自电容触摸结构中，每一个自电容电极需要通过单独的引出线与触控检测芯片连接，如图1所示，每条引出线包括：将自电容电极1连接至触摸屏的边框处的导线2，以及设置在边框处用于将自电容电极1导通至触控检测芯片的接线端子3的周边走线4。
在具体实施时，由于自电容电极的数量非常多，对应的引出线也会非常多，以每个自电容电极的所占面积为5mm*5mm为例，5寸的液晶显示屏就需要264个自电容电极，若将每个自电容电极设计的更小一些，则会有更多的自电容电极，那么需要设置更多的引出线。
而且，在设计时，由于为了简化膜层数量，如图1所示，一般将引出线中的导线2和自电容电极1同层设置，较多的导线2会造成触控盲区偏大，其中触控盲区是指触控屏中走线集中的区域，在这个触控盲区内的信号相对 比较紊乱，故此称为触控盲区，即在该区域内的触控性能无法保证。因此，目前的自电容触摸结构中的触控盲区偏大，造成包含所述自电容触摸结构的触摸屏的触控性能比较差。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
附图中各层膜层的厚度和形状不反映真实比例，目的只是示意说明本发明内容。
如图2所示，本发明实施例提供的一种阵列基板，包括：衬底基板00，位于衬底基板00上的栅极11和栅线12，位于所述栅极11和栅线12所在膜层上的有源层20；所述阵列基板还包括：
与有源层20同层设置且电性绝缘的像素电极40；
位于所述有源层20和像素电极40所在膜层上的漏极31、源极32和数据线33；其中，所述漏极31与像素电极40直接电性连接；
位于所述漏极31、源极32和数据线33所在膜层上，且与所述漏极31、源极32、数据线33和像素电极40电性绝缘的公共电极层50和多条导线60；
其中，所述导线60与所述公共电极层50异层设置，所述公共电极层50 包括多个同层设置且相互绝缘的自电容电极51，且每条所述导线60通过过孔100与对应的自电容电极51电性连接。
在本发明实施例中，阵列基板包含公共电极层和导线，公共电极层包括多个同层设置且相互绝缘的自电容电极，且每条导线与对应的自电容电极电性连接；从而可以实现将自电容触摸结构中的触控电极(即，自电容电极)和导线内嵌到阵列基板中，以便于实现内嵌式触摸屏。
由于导线和公共电极层异层设置，从而可以消除自电容触摸结构中的触控盲区，以提高包含所述自电容触摸结构的触摸屏的触控性能。
另外，由于公共电极层包括多个同层设置且相互绝缘的自电容电极，从而可以将公共电极层作为自电容触摸结构中的触控电极使用，避免单独设置所述触控电极所在膜层，以简化膜层数量。
像素电极与有源层同层设置，以及，所述漏极与像素电极直接电性连接，均可以减少阵列基板包含的膜层数量。而且，由于避免采用掩模版制作电性连接像素电极与漏极的过孔，从而可以降低制作阵列基板的复杂度和成本。
本发明实施例中的导线的位置连接关系只要满足如下条件即可：位于所述漏极、源极和数据线所在膜层之上，与所述漏极、源极、数据线和像素电极均电性绝缘；以及，与所述公共电极层异层设置，且每条所述导线通过过孔与对应的自电容电极电性连接。
下面将对本发明实施例中的导线与阵列基板包含的多个膜层之间的位置关系进行描述。
一、所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述公共电极层之间。
所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述公共电极层之间，可以减少人体电容对在导线上传输的信号的干扰。
例如，所述漏极、源极和数据线所在膜层和所述公共电极层之间设置有钝化层；所述导线所在膜层可以位于所述漏极、源极和数据线所在膜层和所述钝化层之间，也可以位于所述钝化层和所述公共电极层之间。
例如，在如图2所示的阵列基板中，所述漏极31、源极32和数据线33所在膜层和所述公共电极层50之间设置有钝化层70，所述导线60所在膜层位于所述钝化层70和所述公共电极层50之间。
例如，所述阵列基板还包括：
包含所述过孔100的第一绝缘层80，位于所述导线60所在膜层和所述公共电极层50之间；
其中，所述导线60通过所述第一绝缘层80包含的过孔100，与所述自电容电极51电性连接。
需要说明的是，所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述钝化层之间的实施方式，与所述导线所在膜层位于所述钝化层和所述公共电极层之间的实施方式类似；只不过，在所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述钝化层之间时，所述第一绝缘层需要位于所述漏极、源极和数据线所在膜层和所述导线所在膜层之间且不包含过孔，且所述钝化层需要包含过孔。
例如，如图2所示，所述栅极11和栅线12所在膜层与所述有源层20和像素电极40所在膜层之间设置有栅绝缘层90。
二、所述导线所在膜层位于所述公共电极层之上。
所述导线所在膜层位于所述公共电极层之上，可以保证不改变现有阵列基板包含的各膜层之间的连接关系。
例如，所述阵列基板还包括：
包含所述过孔的第二绝缘层，位于所述导线所在膜层和所述公共电极层之间；
其中，所述导线通过所述第二绝缘层包含的过孔，与所述自电容电极电性连接。
下面将以所述导线的位置与栅线和/或数据线的位置之间的关系为分类依据，对本发明实施例的所述导线的位置进行描述。
例如，所述导线在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影内；和/或所述导线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内，这样的效果是：1)可以保证所述导线产生的电场不会影响像素开口区域的电场，从而不会影响正常显示；2)可以避免影响透过率；3)可以保证各导线的延伸方向与所述数据线的延伸方向一致，有利于窄边框设计。
比如，如图3所示，通过过孔100与对应的自电容电极51电性连接的所 述导线60在所述衬底基板(图3中未示出衬底基板)上的正投影位于所述数据线33在所述衬底基板上的正投影内。
需要说明的是，本发明实施例中的所述导线与所述栅线和数据线的位置关系的实施方式也可以为其他实施方式，比如，所述数据线和/或栅线在所述衬底基板上的正投影位于所述导线在所述衬底基板上的正投影内；或者，所述导线在所述衬底基板上的正投影与所述数据线和/或栅线在所述衬底基板上的正投影部分交叠；或者，所述导线在所述衬底基板上的正投影与所述数据线和/或栅线在所述衬底基板上的正投影无交叠等，在此不再赘述。
在本发明实施例中，一个自电容电极可以与至少一条导线电性连接，且各自电容电极电性连接的导线不同。下面以图4为例，对本发明实施例中的导线、自电容电极和公共电极层的位置关系进行描述。
如图4所示，公共电极层50包括多个同层设置且相互绝缘的呈矩阵式排布的自电容电极51。一条导线60电性连接一个自电容电极51，各自电容电极51电性连接的导线60不同。导线60与公共电极层50异层设置，且每条导线60通过过孔100与对应的自电容电极51电性连接。
例如，将所述导线60作为在显示扫描时间内向所述公共电极层50供电的公共电极线使用，可以节省阵列基板包含的走线数量，以降低制作阵列基板的复杂度。
在公共电极线为与栅极和栅线所在膜层同层设置、与所述公共电极层异层设置、且通过过孔与所述公共电极层电性连接时，将所述导线作为在显示扫描时间内向所述公共电极层供电的公共电极线使用，还可以避免对位于栅极和栅线所在膜层和公共电极层之间的各膜层进行过孔刻蚀以电性连接公共电极线和公共电极层，以减少制作阵列基板所采用的掩模版，降低制作阵列基板的成本和复杂度。
本发明实施例还提供了一种显示装置，包括上述实施例的阵列基板。
该显示装置例如为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置中阵列基板的结构可以参见上述实施例，此处不再赘述。
由于本发明实施例中所述的阵列基板内嵌有自电容触摸结构中的触控电极(即，自电容电极)和导线，因此，包含上述阵列基板的显示装置同时具 有显示功能和触控功能。
由于本发明实施例中所述的阵列基板可以消除自电容触摸结构中的触控盲区并且可以简化膜层数量，因此，上述的阵列基板的显示装置也可以消除触控盲区，提高触控性能，而且可以简化膜层数量。
例如，所述显示装置还包括：与所述阵列基板相对设置的彩膜基板。例如，所述彩膜基板包括依次层叠的：衬底基板、黑矩阵层、彩膜层、平坦化层和PS(隔垫物层)。
本发明实施例还提供了一种显示装置的扫描方法，包括：
在一帧时间内，分时进行触摸扫描和显示扫描；其中：
在触摸扫描时间内，通过与各自电容电极相连的导线，分时向各自电容电极施加驱动信号；接收各自电容电极的反馈信号，并根据反馈信号判断触控位置。
分时进行触摸扫描和显示扫描，可以降低显示信号和触控信号之间的相互干扰，提高画面品质和触控准确性。例如，可以由触控检测芯片通过与各自电容电极相连的导线，分时向各自电容电极施加驱动信号；接收各自电容电极的反馈信号，并根据反馈信号判断触控位置。
触控检测芯片设置于电路板上，例如可以设置于位于显示装置背部的电路板上，可以设置于位于显示装置的边框区域的电路板上，也可以设置于所述阵列基板包含的柔性电路板上。例如，可以将显示驱动芯片和触控检测芯片整合为一个芯片，以降低生产成本。
下面将结合图5，对本发明实施例中对所述显示装置的扫描方法进行详细介绍。
如图5所示，将显示装置显示每一帧(V-sync)的时间分成显示扫描时间段(Display)和触摸扫描时间段(Touch)，比如，显示装置的显示一帧的时间为16.7ms，选取其中5ms作为触摸扫描时间段，其他的11.7ms作为显示扫描时间段，当然也可以根据IC芯片的处理能力适当的调整两者的时长，在此不做具体限定。
在显示扫描时间段(Display)，对显示装置中的每条栅极信号线Gate1，Gate2……Gate n依次施加栅扫描信号，对数据信号线Data施加灰阶信号，实现显示功能。
在触控时间段(Touch)，触控检测芯片分时向各自电容电极Cx1……Cxn施加驱动信号；同时，接收各自电容电极Cx1……Cxn的反馈信号，通过对各自电容电极Cx1……Cxn的反馈信号的分析，判断出触控位置，以实现触控功能。
例如，触控检测芯片通过对各自电容电极Cx1……Cxn的反馈信号的分析以判断出触控位置的实施方式与现有技术中实施方式类似，在此不再赘述。
如图5所示，在显示扫描时间段(Display)，各自电容电极上施加Vcom电压，可以保证显示装置正常进行显示。
如图5所示，在触控时间段(Touch)，数据信号线和各栅极信号线上施加GND信号，可以减少数据信号线和各栅极信号线上的信号对导线上传输的信号的干扰。
例如，在分时向各自电容电极施加驱动信号时，可以横向逐个扫描各自电容电极，以分时向各自电容电极施加驱动信号；也可以竖向逐个扫描各自电容电极，以分时向各自电容电极施加驱动信号，还可以采用全驱(all driving)的方式，向各自电容电极施加驱动信号。
本发明实施例还提供了一种制作阵列基板的方法，包括：
步骤101、在衬底基板上形成所述栅极和栅线；
步骤102、在所述栅极和栅线所在膜层上形成同层设置且电性绝缘的所述有源层和像素电极；
步骤103、在所述有源层和像素电极所在膜层上形成所述漏极、源极和数据线；其中，所述漏极与像素电极直接电性连接；
步骤104、在所述漏极、源极和数据线所在膜层上形成与所述漏极、源极、数据线和像素电极电性绝缘的公共电极层和多条导线；
其中，所述导线与所述公共电极层异层设置，所述公共电极层包括多个同层设置且相互绝缘的自电容电极，且每条所述导线通过过孔与对应的自电容电极电性连接。下面通过一个示例对该方法做详细描述。
示例一
本示例提供的阵列基板的制作方法，如图2所示，包括：
步骤1、在衬底基板00上形成栅极11和栅线12；
例如，通过构图工艺，在衬底基板上形成电性连接的栅极和栅线。或者， 同时在衬底基板上还形成有与栅极和栅线同层设置且电性绝缘的公共电极线；在本发明实施例中，可以制作该公共电极线，也可以不制作该公共电极线。
步骤2、在栅极11和栅线12所在膜层上形成栅绝缘层90；
步骤3、在栅绝缘层90上形成同层设置且电性绝缘的有源层20和像素电极40；
例如，通过一次Active Mask(有源层掩模)工艺，在栅绝缘层上形成有源层；通过一次Pixel ITO Mask(像素电极掩模)工艺，在栅绝缘层上形成所述像素电极。
一般在制作像素电极后，还需要对栅绝缘层进行刻蚀，以在栅绝缘层中形成露出公共电极线的过孔；而在本发明实施例中，在不制作该公共电极线时，无需进行该刻蚀步骤。
步骤4、在有源层20和像素电极40所在膜层上形成所述漏极31、源极32和数据线33；其中，所述漏极31与像素电极40直接电性连接；
例如，通过一次SD Mask(源漏掩模)工艺，形成所述的漏极、源极和数据线。形成的所述漏极31和源极32分别位于所述有源层20的两侧，源极32与有源层20直接电性连接，漏极31与像素电极40直接电性连接。
步骤5、在所述漏极31、源极32和数据线33所在膜层上形成钝化层70；
一般在图案化钝化层中，需要在钝化层中形成露出公共电极线的过孔；而在本发明实施例中，在不制作该公共电极线时，无需在钝化层中形成露出公共电极线的过孔。
步骤6、在钝化层70上形成导线60；
例如，通过一次Metal Wire Mask(导线掩模)工艺，形成所述导线。
步骤7、在导线60所在膜层上形成绝缘层80，所述绝缘层80包含露出导线60的过孔100；
例如，通过一次Insulating layer Mask(绝缘层掩模)工艺，形成包含过孔的绝缘层。在本发明示例中，在制作该绝缘层时，需要在绝缘层中形成露出公共电极线的过孔；并且，在绝缘层的材料与钝化层的材料相同时，可以对绝缘层和钝化层一起进行刻蚀，以形成露出公共电极线的过孔。
步骤8、在绝缘层80上形成包括多个同层设置且相互绝缘的自电容电极 51的公共电极层50；所述导线60通过所述绝缘层80包含的过孔100，与对应的自电容电极51电性连接。
例如，通过一次ITO Mask(公共电极层掩模)工艺，形成所述公共电极层。
本发明实施例还提供了一种彩膜基板的制作方法，包括：
步骤1、在衬底基板上形成黑矩阵层；
例如，通过一次BM Mask(黑矩阵层掩模)工艺，在衬底基板上形成黑矩阵层。
步骤2、在黑矩阵层上形成RGB(红绿蓝)彩膜层；
例如，分别通过R Mask(红色亚像素单元掩模)工艺、G Mask(绿色亚像素单元掩模)工艺、以及Mask(蓝色亚像素单元掩模)工艺，在黑矩阵层上形成所述RGB彩膜层。
步骤3、在RGB彩膜层上形成平坦化层；
步骤4、在平坦化层上形成隔垫物。
例如，通过一次PS Mask(隔垫物层掩模)工艺，形成所述PS。
在本发明以上实施例中，阵列基板包含公共电极层和导线，公共电极层包括多个同层设置且相互绝缘的自电容电极，且每条导线与对应的自电容电极电性连接；从而可以实现将自电容触摸结构中的触控电极(即，自电容电极)和导线内嵌到阵列基板中，以便于实现内嵌式触摸屏。
由于导线和公共电极层异层设置，从而可以消除自电容触摸结构中的触控盲区，以提高包含所述自电容触摸结构的触摸屏的触控性能。
另外，由于公共电极层包括多个同层设置且相互绝缘的自电容电极，从而可以将公共电极层作为自电容触摸结构中的触控电极使用，避免单独设置所述触控电极所在膜层，以简化膜层数量。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请基于并且要求于2014年5月30日递交的中国专利申请第201410240517.8号的优先权，在此全文引用上述中国专利申请公开的内容。

Claims (16)

  1. 一种阵列基板，包括：衬底基板，位于所述衬底基板上的栅极和栅线，位于所述栅极和栅线所在膜层上的有源层；该阵列基板还包括：
    与所述有源层同层设置且电性绝缘的像素电极；
    位于所述有源层和像素电极所在膜层上的漏极、源极和数据线；其中，所述漏极与像素电极直接电性连接；
    位于所述漏极、源极和数据线所在膜层上，且与所述漏极、源极、数据线和像素电极均电性绝缘的公共电极层和多条导线；
    其中，所述导线与所述公共电极层异层设置，所述公共电极层包括多个同层设置且相互绝缘的自电容电极，且每条所述导线通过过孔与对应的自电容电极电性连接。
  2. 如权利要求1所述的阵列基板，其中所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述公共电极层之间。
  3. 如权利要求2所述的阵列基板，还包括钝化层，设置在所述漏极、源极和数据线所在膜层和所述公共电极层之间；其中所述导线所在膜层位于所述钝化层和所述公共电极层之间。
  4. 如权利要求3所述的阵列基板，还包括：
    包含所述过孔的第一绝缘层，位于所述导线所在膜层和所述公共电极层之间；
    其中，所述导线通过所述第一绝缘层包含的过孔，与所述自电容电极电性连接。
  5. 如权利要求3或4所述的阵列基板，其中所述栅极和栅线所在膜层与所述有源层和像素电极所在膜层之间设置有栅绝缘层。
  6. 如权利要求1所述的阵列基板，其中所述导线所在膜层位于所述公共电极层之上。
  7. 如权利要求6所述的阵列基板，还包括：
    包含所述过孔的第二绝缘层，位于所述导线所在膜层和所述公共电极层之间；
    其中，所述导线通过所述第二绝缘层包含的过孔，与所述自电容电极电 性连接。
  8. 如权利要求1～7任一所述的阵列基板，其中所述导线在所述衬底基板上的正投影位于所述数据线和所述栅线中至少一种在所述衬底基板上的正投影内。
  9. 如权利要求1～7任一所述的阵列基板，其中将所述导线作为在显示扫描时间内向所述公共电极层供电的公共电极线使用。
  10. 一种显示装置，包括如权利要求1～9任一项所述的阵列基板。
  11. 一种阵列基板的制作方法，包括：
    在衬底基板上形成所述栅极和栅线；
    在所述栅极和栅线所在膜层上形成同层设置且电性绝缘的所述有源层和像素电极；
    在所述有源层和像素电极所在膜层上形成所述漏极、源极和数据线；其中，所述漏极与像素电极直接电性连接；
    在所述漏极、源极和数据线所在膜层上形成与所述漏极、源极、数据线和像素电极电性绝缘的公共电极层和多条导线；
    其中，所述导线与所述公共电极层异层设置，所述公共电极层包括多个同层设置且相互绝缘的自电容电极，且每条所述导线通过过孔与对应的自电容电极电性连接。
  12. 根据权利要求11所述的制作方法，其中所述导线所在膜层位于所述漏极、源极和数据线所在膜层和所述公共电极层之间。
  13. 根据权利要求12所述的制作方法，还包括：
    在形成公共电极线和多条导线之前形成钝化层，
    其中所述导线所在膜层位于所述钝化层和所述公共电极层之间。
  14. 根据权利要求13所述的制作方法，还包括：
    形成包含所述过孔的第一绝缘层，位于所述导线所在膜层和所述公共电极层之间；
    其中，所述导线通过所述第一绝缘层包含的过孔，与所述自电容电极电性连接。
  15. 根据权利要求11所述的制作方法，其中所述导线所在膜层位于所述公共电极层之上。
  16. 根据权利要求11所述的制作方法，还包括：
    形成包含所述过孔的第二绝缘层，位于所述导线所在膜层和所述公共电极层之间；
    其中，所述导线通过所述第二绝缘层包含的过孔，与所述自电容电极电性连接。
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CN104022128A (zh) * 2014-05-30 2014-09-03 京东方科技集团股份有限公司 一种阵列基板及其制作方法、以及显示装置

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