WO2015161536A1 - 显示面板的驱动电路及其驱动方法 - Google Patents

显示面板的驱动电路及其驱动方法 Download PDF

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Publication number
WO2015161536A1
WO2015161536A1 PCT/CN2014/077662 CN2014077662W WO2015161536A1 WO 2015161536 A1 WO2015161536 A1 WO 2015161536A1 CN 2014077662 W CN2014077662 W CN 2014077662W WO 2015161536 A1 WO2015161536 A1 WO 2015161536A1
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Prior art keywords
source
drain
signal
film transistor
thin film
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PCT/CN2014/077662
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English (en)
French (fr)
Inventor
何小祥
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深圳市华星光电技术有限公司
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Priority to US14/380,530 priority Critical patent/US9640147B2/en
Publication of WO2015161536A1 publication Critical patent/WO2015161536A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display panel technologies, and in particular, to a driving circuit of a display panel and a driving method thereof.
  • the traditional narrow frame design technology generally uses multi-layer metal wiring or GOA (Gate driver On Array) is implemented by two techniques.
  • GOA Gate driver On Array
  • the above-mentioned technical scheme of the multilayer metal trace does not significantly achieve a narrow bezel. On the contrary, it increases the probability of the panel being short-circuited, resulting in a decrease in yield and an increase in cost.
  • the technical solution of the above GOA can significantly realize a narrow bezel and can save the gate chip (Gate The cost of IC).
  • the conventional GOA circuit includes an input portion, an output portion, a reset portion, and a holding portion.
  • the width-to-length ratio of the TFT in the reset portion cannot be large (far from the aspect ratio of the TFT of the output portion), so the reset tension of the entire GOA circuit Less than the output thrust, resulting in a large reset edge delay of the output signal.
  • the reset TFT also needs a large aspect ratio, increases the leakage of the reset TFT, increases the entire GOA area, and the delay of the reset edge of the output signal is still large.
  • the TFT of the reset portion is turned off, but due to the TFT process, the parasitic capacitance Cgs/Cgd is inevitably contained in the TFT, and the output signal is outputted at the drain (Drain) end of the TFT of the reset portion.
  • the abrupt change of the output signal is inevitably coupled to the gate of the TFT of the reset portion through the parasitic Cgs/Cgd, with the result that the TFT of the reset portion cannot be stably turned off, and thus the output signal has a partial voltage loss.
  • An object of the present invention is to provide a driving circuit for a display panel and a driving method thereof, which can prevent leakage of an output signal line, thereby causing a signal output line to stably output a signal to be output.
  • a driving circuit for a display panel comprising: a capacitor comprising a first plate and a second plate, wherein the second plate is connected to a signal output line; and a first thin film transistor including a first gate a first source and a first drain, wherein the first gate and the first source are connected, and the first gate and the first source are both used to receive the first signal source a first control signal; a second thin film transistor including a second gate, a second source, and a second drain, wherein the first drain is connected to the second source, and the second drain is The first plate of the capacitor is connected, the second gate is for receiving a second control signal sent by a second signal source, and a third thin film transistor comprises a third gate, a third source, and a third drain, the third gate is connected to the first drain, the third source is configured to receive a first power signal, and a fourth thin film transistor includes a fourth gate and a fourth source And a fourth drain, the fourth gate is connected to the third drain, and the fourth source is configured
  • the sixth thin film transistor is configured to receive a first signal of the signal output line, and is configured to be turned on according to the first signal in the first time period, so that the a fifth power signal is output to the sixth gate via the eighth source and the eighth drain, wherein the fifth power signal is used to control the reset film in the first period of time
  • the transistor is turned off; the reset thin film transistor is configured to be turned off according to the fifth power signal in the first period of time.
  • the seventh thin film transistor is configured to be turned off in a second period of time to prevent the third power source signal from being outputted through the ninth source and the ninth drain Said fourth source.
  • the seventh thin film transistor and the fourth thin film transistor are further configured to cooperate in a second period of time to block the fourth drain and the second drain The second signal in the connection line is reset.
  • the output thin film transistor is further configured to be turned on in the second period of time to reset the first signal in the signal output line together with the reset thin film transistor.
  • the first time period corresponds to a signal output stage of the output signal line, and the first time period and the second time period are adjacent two time periods, The first time period is before the second time period.
  • the first control signal is a scan signal of a pixel of a previous row corresponding to a current row of pixels.
  • a driving circuit for a display panel comprising: a capacitor comprising a first plate and a second plate, wherein the second plate is connected to a signal output line; and a first thin film transistor including a first gate a first source and a first drain, wherein the first gate and the first source are connected, and the first gate and the first source are both used to receive the first signal source a first control signal; a second thin film transistor including a second gate, a second source, and a second drain, wherein the first drain is connected to the second source, and the second drain is The first plate of the capacitor is connected, the second gate is for receiving a second control signal sent by a second signal source, and a third thin film transistor comprises a third gate, a third source, and a third drain, the third gate is connected to the first drain, the third source is configured to receive a first power signal, and a fourth thin film transistor includes a fourth gate and a fourth source And a fourth drain, the fourth gate is connected to the third drain, and the fourth source is configured
  • the output thin film transistor has a first aspect ratio
  • the reset thin film transistor has a second aspect ratio
  • the first aspect ratio is greater than the second aspect ratio
  • the sixth thin film transistor is configured to receive a first signal of the signal output line, and is configured to be turned on according to the first signal in the first time period, so that the a fifth power signal is output to the sixth gate via the eighth source and the eighth drain, wherein the fifth power signal is used to control the reset film in the first period of time
  • the transistor is turned off; the reset thin film transistor is configured to be turned off according to the fifth power signal in the first period of time.
  • the driving circuit further includes: a seventh thin film transistor including a ninth gate, a ninth source, and a ninth drain, wherein the ninth gate is configured to receive the fifth signal a fifth control signal sent by the source, the ninth source is for receiving the second power signal, and the ninth drain is connected to the fourth source.
  • the seventh thin film transistor is configured to be turned off in a second period of time to prevent the third power source signal from being outputted through the ninth source and the ninth drain Said fourth source.
  • the seventh thin film transistor and the fourth thin film transistor are further configured to cooperate in a second period of time to block the fourth drain and the second drain The second signal in the connection line is reset.
  • the output thin film transistor is further configured to be turned on in the second period of time to reset the first signal in the signal output line together with the reset thin film transistor.
  • the first time period corresponds to a signal output stage of the output signal line, and the first time period and the second time period are adjacent two time periods, The first time period is before the second time period.
  • the first control signal is a scan signal of a pixel of a previous row corresponding to a current row of pixels.
  • a driving method for use in a driving circuit of the above display panel comprising: the sixth thin film transistor receiving a first signal in the signal output line, and according to the first signal at the first Turning on in a time period to cause the fifth power signal to be output to the sixth gate via the eighth source and the eighth drain, wherein the fifth power signal is used for the first
  • the reset thin film transistor is turned off in a period of time; the reset thin film transistor is turned off according to the fifth power signal in the first period of time.
  • the method further includes the step of: turning off the seventh thin film transistor in the second period of time to prevent the third power source signal from passing through the ninth source and the ninth drain Outputting to the fourth source; the seventh thin film transistor and the fourth thin film transistor cooperate in a second period of time to block a connection between the fourth drain and the second drain The second signal in the line is reset.
  • the method further includes the step of: turning on the output thin film transistor in the second period of time to reset the first signal in the signal output line together with the reset thin film transistor .
  • the present invention is advantageous in avoiding leakage of the signal output line and avoiding leakage of a connection line between the fourth drain and the second drain, so that the signal output line stably outputs the desired output.
  • the signal in addition, also facilitates reducing the reset edge delay of the signal output by the signal output line.
  • FIG. 1 is a schematic view showing a first embodiment of a driving circuit of a display panel of the present invention
  • FIG. 2 is a schematic view showing a second embodiment of a driving circuit of a display panel of the present invention
  • Figure 3 is a timing diagram of the driving circuit of Figures 1 and 2;
  • Figure 4 is a schematic diagram of the actual voltage value of the output signal
  • Figure 5 is a schematic diagram of a reset edge delay of an output signal
  • FIG. 6 is a flow chart of a first embodiment of a driving method of a display panel of the present invention.
  • Fig. 7 is a flow chart showing a second embodiment of the driving method of the display panel of the present invention.
  • FIG. 1 is a schematic diagram of a first embodiment of a driving circuit of a display panel of the present invention.
  • the driving circuit of the display panel of the present embodiment includes a capacitor 110, a signal output line 141, a first thin film transistor 111, a second thin film transistor 112, a third thin film transistor 113, a fourth thin film transistor 114, a fifth thin film transistor 115, and a reset film.
  • the transistor 117, the reset thin film transistor 116, the sixth thin film transistor 118, and the seventh thin film transistor 119 are all exemplified by a P-type transistor.
  • the thin film transistor may be an N-type transistor.
  • the capacitor 110 includes a first plate 1101 and a second plate 1102.
  • the second plate 1102 is connected to a signal output line 141.
  • the signal output terminal 1411 of the signal output line 141 is used to output a correlation signal.
  • the first thin film transistor 111 includes a first gate 1111, a first source 1112, and a first drain 1113.
  • the first gate 1111 is connected to the first source 1112, and the first gate 1111 is connected.
  • the first source 1112 is configured to receive the first control signal N-1 sent by the first signal source 121.
  • the first thin film transistor 111 is a first switch, and the opening or closing of the first thin film transistor 111 corresponds to opening or closing of a first current channel between the first source 1112 and the first drain 1113. .
  • the output of the driving circuit of each row is used as an input of the driving circuit of the next row, and the input of the driving circuit of each row is the output of the driving circuit of the previous row, wherein the first control signal N-1
  • the scan signal of the previous row of pixels corresponding to the current row of pixels that is, the output of the pixel of the previous row is used as the input of the pixel of the row, and for the pixel of the Nth row, the first control signal N-1 is the pixel of the N-1 row.
  • Scan signal, N is a positive integer.
  • the second thin film transistor 112 includes a second gate 1121, a second source 1122, and a second drain 1123.
  • the first drain 1113 is connected to the second source 1122, and the second drain 1123 is connected.
  • the first gate plate 1101 is connected to the capacitor 110, and the second gate 1121 is configured to receive the second control signal CK sent by the second signal source 122.
  • the second thin film transistor 112 is a second switch, and the opening or closing of the second thin film transistor 112 corresponds to the opening or closing of the second current channel between the second source 1122 and the second drain 1123. .
  • the third thin film transistor 113 includes a third gate electrode 1131, a third source 1132, and a third drain 1133.
  • the third gate 1131 is connected to the first drain 1113.
  • the third source 1132 And configured to receive the first power signal input by the first power input terminal 131.
  • the third thin film transistor 113 is a third switch, and the opening or closing of the third thin film transistor 113 corresponds to the opening or closing of the third current channel between the third source 1132 and the third drain 1133. .
  • the fourth thin film transistor 114 includes a fourth gate 1141, a fourth source 1142, and a fourth drain 1143.
  • the fourth gate 1141 is connected to the third drain 1133, and the fourth source 1142 And receiving a second power signal input by the second power input terminal 132, wherein the fourth drain 1143 is connected to the second drain 1123.
  • the fourth thin film transistor 114 is a fourth switch, and the opening or closing of the fourth thin film transistor 114 corresponds to the opening or closing of the fourth current channel between the fourth source 1142 and the fourth drain 1143. .
  • the fifth thin film transistor 115 includes a fifth gate 1151, a fifth source 1152, and a fifth drain 1153.
  • the fifth gate 1151 is configured to receive the third control signal 3CK sent by the third signal source 123.
  • the fifth drain 1153 is connected to the third drain 1133, and the fifth source 1152 is configured to receive a third power signal input by the third power input terminal 133.
  • the fifth thin film transistor 115 is a fifth switch, and the opening or closing of the fifth thin film transistor 115 corresponds to the opening or closing of the fifth current channel between the fifth source 1152 and the fifth drain 1153. .
  • the reset thin film transistor 116 includes a sixth gate 1161, a sixth source 1162, and a sixth drain 1163.
  • the sixth gate 1161 is connected to the fifth drain 1153, and the sixth drain 1163 is The signal output line 141 is connected, and the sixth source 1162 is configured to receive a fourth power signal input by the fourth power input terminal 134.
  • the reset thin film transistor 116 is a sixth switch, and the turning on or off of the reset thin film transistor 116 corresponds to turning on or off the sixth current path between the sixth source 1162 and the sixth drain 1163.
  • the output thin film transistor 117 includes a seventh gate 1171, a seventh source 1172, and a seventh drain 1173.
  • the seventh source 1172 is configured to receive a fourth control signal XCK sent by the fourth signal source 124.
  • the seventh gate 1171 is connected to the second drain 1123, and the seventh drain 1173 is connected to the signal output line 141.
  • the output thin film transistor 117 is a seventh switch, and the turning on or off of the output thin film transistor 117 corresponds to turning on or off the seventh current path between the seventh source 1172 and the seventh drain 1173.
  • the sixth thin film transistor 118 includes an eighth gate 1181, an eighth source 1182, and an eighth drain 1183.
  • the eighth gate 1181 is connected to the signal output line 141, and the eighth source 1182 is used.
  • Receiving a fifth power signal input by the fifth power input terminal 135, the eighth drain 1183 is connected to the sixth gate 1161.
  • the sixth thin film transistor 118 is an eighth switch, and the opening or closing of the sixth thin film transistor 118 corresponds to the opening or closing of the eighth current channel between the eighth source 1182 and the eighth drain 1183. .
  • the output thin film transistor 117 has a first aspect ratio
  • the reset thin film transistor 116 has a second aspect ratio, the first aspect ratio being greater than the second aspect ratio.
  • the first aspect ratio is 180 microns/5 microns
  • the second aspect ratio is 10 microns/5 microns.
  • the sixth thin film transistor 118 is configured to receive the first signal of the signal output line 141, and is configured to be in the first time period 301 according to the first signal. Turning on, so that the fifth power signal is output to the sixth gate 1161 via the eighth source 1182 and the eighth drain 1183, wherein the fifth power signal is used in the
  • the reset thin film transistor 116 is controlled to be turned off in a period of time 301.
  • the reset thin film transistor 116 is configured to be turned off according to the fifth power signal in the first time period 301.
  • the first time period 301 corresponds to a signal output stage of the output signal line.
  • the first control signal N-1 is high.
  • the second control signal CK is a high level signal
  • the third control signal 3CK is a high level signal
  • the fourth control signal XCK is a low level signal
  • the fifth control signal 3 -2CK is a high level signal.
  • the second control signal CK, the third control signal 3CK, the fourth control signal XCK, and the fifth control signal 3-2CK may each be a clock signal.
  • the reset thin film transistor 116, the sixth thin film transistor 118, and the seventh thin film transistor 119 are all N-type transistors, in the first time period 301, the first control signal N-1 a low level signal, the second control signal CK is a low level signal, the third control signal 3CK is a low level signal, the fourth control signal XCK is a high level signal, and the fifth control Signal 3-2CK is a low level signal.
  • the sixth thin film transistor 118 is triggered to be turned off by the signal in the signal line output during the first time period 301 (the signal output stage of the output signal line), so that the The fifth power signal is output to the sixth gate 1161, so that the reset thin film transistor 116 is turned off in the first period 301, the signal output line 141 is prevented from leaking, and the first A connection line between the four drains 1143 and the second drain 1123 leaks, so that the signal output line 141 stably outputs a signal to be output.
  • the above technical solution is also advantageous for reducing the reset edge delay of the signal output by the signal output line 141.
  • the output signal 401 before the improvement is -6.99V, and experimentally verified, the improved output signal 402 is -6.9999V. Therefore, the above technical solution can make the output signal in the signal output line 141 closer to the target value.
  • FIG. 2 is a schematic diagram of a second embodiment of a driving circuit of a display panel of the present invention. This embodiment is similar to the first embodiment described above, except that:
  • the driving circuit further includes a seventh thin film transistor 119.
  • the seventh thin film transistor 119 includes a ninth gate electrode 1191, a ninth source electrode 1192, and a ninth drain electrode 1193, and the ninth gate electrode 1191 is configured to receive the fifth control signal sent by the fifth signal source 125. 3-2CK, the ninth source 1192 is configured to receive the second power signal, and the ninth drain 1193 is connected to the fourth source 1142, that is, the fourth source 1142 passes the The ninth source 1192 and the ninth drain 1193 receive the second power signal.
  • the seventh thin film transistor 119 is a ninth switch, and the opening or closing of the seventh thin film transistor 119 corresponds to the opening or closing of the ninth current channel between the ninth source electrode 1192 and the ninth drain 1193. .
  • the seventh thin film transistor 119 is configured to be turned off in the second period 302 to prevent the third power signal from being output to the ninth source 1192 and the ninth drain 1193 to The fourth source 1142.
  • the first time period 301 and the second time period 302 are two adjacent time periods, and the first time period 301 is located before the second time period 302, that is, the second time. Segment 302 is the next time period adjacent to the first time period 301.
  • the first control signal N-1 is high.
  • the second control signal CK is a high level signal
  • the third control signal 3CK is a low level signal
  • the fourth control signal XCK is a high level signal
  • the fifth control signal 3 -2CK is a high level signal.
  • the seventh thin film transistor 119 and the fourth thin film transistor 114 are further configured to cooperate in the second period 302 to block the fourth drain 1143 and the second drain.
  • the second signal in the connection line between 1123 is reset.
  • the output thin film transistor 117 is further configured to be turned on in the second period 302 to reset the first signal in the signal output line 141 together with the reset thin film transistor 116.
  • the reset thin film transistor 116 can be assisted to quickly reset the output signal in the signal output line 141. So that the reset of the output signal becomes smaller along the delay. Meanwhile, since the current capability of the output thin film transistor 117 is large, the aspect ratio of the reset thin film transistor 116 can be reduced to 10 ⁇ m/5 ⁇ m, which reduces the leakage of the reset thin film transistor 116, thereby reducing the entire GOA (Gate Driver On Array) area.
  • GOA Gate Driver On Array
  • the reset edge 5011 of the improved output signal 501 has a delay of 1.48u
  • the reset edge of the improved output signal 502 has a delay of 50u of 0.9u, wherein 1u is 1 micron, and the delay along the reset is reduced.
  • the small rate is (1.48-0.9)/1.48 ⁇ 39.19%.
  • the reset edges 5011 and 5021 shown in FIG. 5 are both rising edges (for the case of a P-type transistor), of course, the reset edges 5011 and 5021 may also be falling edges (for the case of an N-type transistor).
  • FIG. 6 is a flowchart of a first embodiment of a driving method of a display panel of the present invention.
  • the driving method of this embodiment is implemented in the driving circuit of the display panel in FIG. 1 or 2.
  • Step 601 the sixth thin film transistor 118 receives the first signal in the signal output line 141.
  • Step 602 the sixth thin film transistor 118 is turned on in the first time period 301 according to the first signal, so that the fifth power signal passes through the eighth source 1182 and the eighth drain. 1183 is output to the sixth gate 1161, wherein the fifth power signal is used to turn off the reset thin film transistor 116 in the first period of time 301.
  • Step 603 the reset thin film transistor 116 is turned off according to the fifth power signal in the first time period 301.
  • the sixth thin film transistor 118 is triggered to be turned off by the signal in the signal line output during the first time period 301 (the signal output stage of the output signal line), so that the The fifth power signal is output to the sixth gate 1161, so that the reset thin film transistor 116 is turned off in the first period 301, the signal output line 141 is prevented from leaking, and the first A connection line between the four drains 1143 and the second drain 1123 leaks, so that the signal output line 141 stably outputs a signal to be output.
  • the above technical solution is also advantageous for reducing the reset edge delay of the signal output by the signal output line 141.
  • the output signal 401 before the improvement is -6.99V, and experimentally verified, the improved output signal 402 is -6.9999V. Therefore, the above technical solution can make the output signal in the signal output line 141 closer to the target value.
  • FIG. 7 is a flowchart of a second embodiment of a driving method of a display panel of the present invention. This embodiment is similar to the first embodiment described above, except that:
  • the method further includes the following steps:
  • Step 701 the seventh thin film transistor 119 is turned off in the second period 302 to prevent the third power signal from being output to the fourth source through the ninth source 1192 and the ninth drain 1193. Pole 1142.
  • Step 702 the seventh thin film transistor 119 and the fourth thin film transistor 114 cooperate in the second time period 302 to block the connection line between the fourth drain 1143 and the second drain 1123.
  • Step 703 the output thin film transistor 117 is turned on in the second period 302 to reset the first signal in the signal output line 141 together with the reset thin film transistor 116.
  • the reset thin film transistor 116 can be assisted to quickly reset the output signal in the signal output line 141. So that the reset of the output signal becomes smaller along the delay. Meanwhile, since the current capability of the output thin film transistor 117 is large, the aspect ratio of the reset thin film transistor 116 can be reduced to 10 ⁇ m/5 ⁇ m, which reduces the leakage of the reset thin film transistor 116, thereby reducing the entire GOA (Gate Driver On Array) area.
  • GOA Gate Driver On Array
  • the reset edge 5011 of the improved output signal 501 has a delay of 1.48u
  • the reset edge of the improved output signal 502 has a delay of 50u of 0.9u, wherein 1u is 1 micron, and the delay along the reset is reduced.
  • the small rate is (1.48-0.9)/1.48 ⁇ 39.19%.
  • the reset edges 5011 and 5021 shown in FIG. 5 are both rising edges (for the case of a P-type transistor), of course, the reset edges 5011 and 5021 may also be falling edges (for the case of an N-type transistor).

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Abstract

一种显示面板的驱动电路及其驱动方法，驱动电路包括：电容（110）；第一薄膜晶体管（111）、第二薄膜晶体管(112)、第三薄膜晶体管(113)、第四薄膜晶体管(114)、第五薄膜晶体管(115)、第六薄膜晶体管(118)；复位薄膜晶体管(116)；输出薄膜晶体管(117)；第六漏极(1163)、第七漏极(1173)、第八栅极(1181)与信号输出线(141)连接，第六源极(1162)用于接收第四电源信号；第八源极(1182)用于接收第五电源信号，第八漏极(1183)与第六栅极(1161)连接。

Description

显示面板的驱动电路及其驱动方法 技术领域
本发明涉及显示面板技术领域，特别涉及一种显示面板的驱动电路及其驱动方法。
 背景技术
传统的显示面板一般采用窄边框设计的技术方案。
传统的窄边框设计的技术方案一般采用多层金属走线或GOA（Gate driver On Array）二种技术来实现，然而，上述多层金属走线的技术方案并不能显著地实现窄边框，相反，其会增加面板短路的几率，使得良率下降以及成本上升。上述GOA的技术方案可以显著地实现窄边框，且能省去栅极芯片（Gate IC）的成本。
目前，传统的GOA电路包含：输入部分，输出部分，复位部分，保持部分。其中，输出部分中的TFT（Thin Film Transistor）的宽长比很大，如，例如，其达到180u/5u，1u=1微米；复位部分的TFT的宽长比次之，例如，其可达到30u/5u。
在实践中，发明人发现现有技术至少存在以下问题：
由于TFT的漏电流会随着宽长比的增加而增加，所以复位部分的TFT的宽长比不能很大（远达不到输出部分的TFT的宽长比），所以整个GOA电路的复位拉力小于输出推力，从而导致输出信号的复位沿时延较大。目前，没有技术把输出部分TFT和复位部分TFT整合使用。使得复位TFT也需要较大的宽长比，增加复位TFT的漏电，增加整个GOA面积，且输出信号的复位沿的时延还较大。
目前，在输出信号的输出阶段，复位部分的TFT处于关闭状态，但由于TFT制程原因，TFT中不可避免的含有寄生电容Cgs/Cgd，输出信号在复位部分的TFT的漏极（Drain）端输出，输出信号的突变不可避免地会通过寄生Cgs/Cgd耦合到复位部分的TFT的栅极（Gate）端，结果导致复位部分的TFT不能稳定地关闭，因此输出信号会有部分电压损失。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种显示面板的驱动电路及其驱动方法，其能避免输出信号线漏电，从而使得信号输出线稳定地输出所要输出的信号。
 技术解决方案
一种显示面板的驱动电路，所述驱动电路包括：一电容，包括第一极板和第二极板，所述第二极板与信号输出线连接；一第一薄膜晶体管，包括第一栅极、第一源极和第一漏极，所述第一栅极和所述第一源极连接，所述第一栅极和所述第一源极均用于接收第一信号源所发送的第一控制信号；一第二薄膜晶体管，包括第二栅极、第二源极和第二漏极，所述第一漏极与所述第二源极连接，所述第二漏极与所述电容的所述第一极板连接，所述第二栅极用于接收第二信号源所发送的第二控制信号；一第三薄膜晶体管，包括第三栅极、第三源极和第三漏极，所述第三栅极与所述第一漏极连接，所述第三源极用于接收第一电源信号；一第四薄膜晶体管，包括第四栅极、第四源极和第四漏极，所述第四栅极与所述第三漏极连接，所述第四源极用于接收第二电源信号，所述第四漏极与所述第二漏极连接；一第五薄膜晶体管，包括第五栅极、第五源极和第五漏极，所述第五栅极用于接收第三信号源所发送的第三控制信号，所述第五漏极与所述第三漏极连接，所述第五源极用于接收第三电源信号；一复位薄膜晶体管，包括第六栅极、第六源极和第六漏极，所述第六栅极与所述第五漏极连接，所述第六漏极与所述信号输出线连接，所述第六源极用于接收第四电源信号；一输出薄膜晶体管，包括第七栅极、第七源极和第七漏极，所述第七源极用于接收第四信号源所发送的第四控制信号，所述第七栅极与所述第二漏极连接，所述第七漏极与所述信号输出线连接；一第六薄膜晶体管，包括第八栅极、第八源极和第八漏极，所述第八栅极与所述信号输出线连接，所述第八源极用于接收第五电源信号，所述第八漏极与所述第六栅极连接；一第七薄膜晶体管，包括第九栅极、第九源极和第九漏极，所述第九栅极用于接收第五信号源所发出的第五控制信号，所述第九源极用于接收所述第二电源信号，所述第九漏极与所述第四源极连接；所述输出薄膜晶体管具有第一宽长比，所述复位薄膜晶体管具有第二宽长比，所述第一宽长比大于所述第二宽长比。
在上述显示面板的驱动电路中，所述第六薄膜晶体管用于接收所述信号输出线的第一信号，并用于根据所述第一信号在所述第一时间段中开启，以使所述第五电源信号经所述第八源极和所述第八漏极输出至所述第六栅极，其中，所述第五电源信号用于在所述第一时间段中控制所述复位薄膜晶体管关闭；所述复位薄膜晶体管用于在所述第一时间段中根据所述第五电源信号关闭。
在上述显示面板的驱动电路中，所述第七薄膜晶体管用于在第二时间段中关闭，以阻止所述第三电源信号经所述第九源极和所述第九漏极输出至所述第四源极。
在上述显示面板的驱动电路中，所述第七薄膜晶体管和所述第四薄膜晶体管还用于在第二时间段中共同作用，以阻止所述第四漏极和所述第二漏极之间的连接线中的第二信号复位。
在上述显示面板的驱动电路中，所述输出薄膜晶体管还用于在所述第二时间段中开启，以与所述复位薄膜晶体管共同对所述信号输出线中的第一信号进行复位。
在上述显示面板的驱动电路中，所述第一时间段对应所述输出信号线的信号输出阶段，所述第一时间段和所述第二时间段是相邻的两个时间段，所述第一时间段位于所述第二时间段之前。
在上述显示面板的驱动电路中，所述第一控制信号为当前行像素所对应的上一行像素的扫描信号。
一种显示面板的驱动电路，所述驱动电路包括：一电容，包括第一极板和第二极板，所述第二极板与信号输出线连接；一第一薄膜晶体管，包括第一栅极、第一源极和第一漏极，所述第一栅极和所述第一源极连接，所述第一栅极和所述第一源极均用于接收第一信号源所发送的第一控制信号；一第二薄膜晶体管，包括第二栅极、第二源极和第二漏极，所述第一漏极与所述第二源极连接，所述第二漏极与所述电容的所述第一极板连接，所述第二栅极用于接收第二信号源所发送的第二控制信号；一第三薄膜晶体管，包括第三栅极、第三源极和第三漏极，所述第三栅极与所述第一漏极连接，所述第三源极用于接收第一电源信号；一第四薄膜晶体管，包括第四栅极、第四源极和第四漏极，所述第四栅极与所述第三漏极连接，所述第四源极用于接收第二电源信号，所述第四漏极与所述第二漏极连接；一第五薄膜晶体管，包括第五栅极、第五源极和第五漏极，所述第五栅极用于接收第三信号源所发送的第三控制信号，所述第五漏极与所述第三漏极连接，所述第五源极用于接收第三电源信号；一复位薄膜晶体管，包括第六栅极、第六源极和第六漏极，所述第六栅极与所述第五漏极连接，所述第六漏极与所述信号输出线连接，所述第六源极用于接收第四电源信号；一输出薄膜晶体管，包括第七栅极、第七源极和第七漏极，所述第七源极用于接收第四信号源所发送的第四控制信号，所述第七栅极与所述第二漏极连接，所述第七漏极与所述信号输出线连接；一第六薄膜晶体管，包括第八栅极、第八源极和第八漏极，所述第八栅极与所述信号输出线连接，所述第八源极用于接收第五电源信号，所述第八漏极与所述第六栅极连接。
在上述显示面板的驱动电路中，所述输出薄膜晶体管具有第一宽长比，所述复位薄膜晶体管具有第二宽长比，所述第一宽长比大于所述第二宽长比。
在上述显示面板的驱动电路中，所述第六薄膜晶体管用于接收所述信号输出线的第一信号，并用于根据所述第一信号在所述第一时间段中开启，以使所述第五电源信号经所述第八源极和所述第八漏极输出至所述第六栅极，其中，所述第五电源信号用于在所述第一时间段中控制所述复位薄膜晶体管关闭；所述复位薄膜晶体管用于在所述第一时间段中根据所述第五电源信号关闭。
在上述显示面板的驱动电路中，所述驱动电路还包括：一第七薄膜晶体管，包括第九栅极、第九源极和第九漏极，所述第九栅极用于接收第五信号源所发出的第五控制信号，所述第九源极用于接收所述第二电源信号，所述第九漏极与所述第四源极连接。
在上述显示面板的驱动电路中，所述第七薄膜晶体管用于在第二时间段中关闭，以阻止所述第三电源信号经所述第九源极和所述第九漏极输出至所述第四源极。
在上述显示面板的驱动电路中，所述第七薄膜晶体管和所述第四薄膜晶体管还用于在第二时间段中共同作用，以阻止所述第四漏极和所述第二漏极之间的连接线中的第二信号复位。
在上述显示面板的驱动电路中，所述输出薄膜晶体管还用于在所述第二时间段中开启，以与所述复位薄膜晶体管共同对所述信号输出线中的第一信号进行复位。
在上述显示面板的驱动电路中，所述第一时间段对应所述输出信号线的信号输出阶段，所述第一时间段和所述第二时间段是相邻的两个时间段，所述第一时间段位于所述第二时间段之前。
在上述显示面板的驱动电路中，所述第一控制信号为当前行像素所对应的上一行像素的扫描信号。
一种用于上述显示面板的驱动电路中的驱动方法，所述方法包括：所述第六薄膜晶体管接收所述信号输出线中的第一信号，并根据所述第一信号在所述第一时间段中开启，以使所述第五电源信号经所述第八源极和所述第八漏极输出至所述第六栅极，其中，所述第五电源信号用于所述第一时间段中关闭所述复位薄膜晶体管；所述复位薄膜晶体管在所述第一时间段中根据所述第五电源信号关闭。
在上述驱动方法中，所述方法还包括以下步骤：所述第七薄膜晶体管在第二时间段中关闭，以阻止所述第三电源信号经所述第九源极和所述第九漏极输出至所述第四源极；所述第七薄膜晶体管和所述第四薄膜晶体管在第二时间段中共同作用，以阻止所述第四漏极和所述第二漏极之间的连接线中的第二信号复位。
在上述驱动方法中，所述方法还包括以下步骤：所述输出薄膜晶体管在所述第二时间段中开启，以与所述复位薄膜晶体管共同对所述信号输出线中的第一信号进行复位。
 有益效果
相对现有技术，本发明有利于避免所述信号输出线漏电，以及避免所述第四漏极和所述第二漏极之间连接线漏电，从而使得所述信号输出线稳定地输出所要输出的信号，此外，还有利于减小所述信号输出线所输出的信号的复位沿时延。
 附图说明
图1为本发明的显示面板的驱动电路的第一实施例的示意图；
图2为本发明的显示面板的驱动电路的第二实施例的示意图；
图3为图1和图2中的驱动电路的时序图；
图4为输出信号的实际电压值的示意图；
图5为输出信号的复位沿时延的示意图；
图6为本发明的显示面板的驱动方法的第一实施例的流程图；
图7为本发明的显示面板的驱动方法的第二实施例的流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
参考图1，图1为本发明的显示面板的驱动电路的第一实施例的示意图。
本实施例的显示面板的驱动电路包括电容110、信号输出线141、第一薄膜晶体管111、第二薄膜晶体管112、第三薄膜晶体管113、第四薄膜晶体管114、第五薄膜晶体管115、复位薄膜晶体管116、输出薄膜晶体管117和第六薄膜晶体管118。
在本实施例中，所述第一薄膜晶体管111、所述第二薄膜晶体管112、所述第三薄膜晶体管113、所述第四薄膜晶体管114、所述第五薄膜晶体管115、所述输出薄膜晶体管117、所述复位薄膜晶体管116、所述第六薄膜晶体管118、所述第七薄膜晶体管119均以P型三极管为例，当然，上述薄膜晶体管还可以为N型三极管。
其中，所述电容110包括第一极板1101和第二极板1102，所述第二极板1102与信号输出线141连接，所述信号输出线141的信号输出端1411用于输出相关信号。
所述第一薄膜晶体管111包括第一栅极1111、第一源极1112和第一漏极1113，所述第一栅极1111和所述第一源极1112连接，所述第一栅极1111和所述第一源极1112均用于接收第一信号源121所发送的第一控制信号N-1。所述第一薄膜晶体管111为第一开关，所述第一薄膜晶体管111的开启或关闭对应所述第一源极1112和所述第一漏极1113之间的第一电流通道的开启或关闭。在本实施例中，每一行所述驱动电路的输出用作下一行驱动电路的输入，每一行所述驱动电路的输入为上一行驱动电路的输出，其中，所述第一控制信号N-1可以为当前行像素所对应的上一行像素的扫描信号，即，上一行像素的输出作为本行像素的输入，对于第N行像素，所述第一控制信号N-1为N-1行像素的扫描信号，N为正整数。
所述第二薄膜晶体管112包括第二栅极1121、第二源极1122和第二漏极1123，所述第一漏极1113与所述第二源极1122连接，所述第二漏极1123与所述电容110的所述第一极板1101连接，所述第二栅极1121用于接收第二信号源122所发送的第二控制信号CK。所述第二薄膜晶体管112为第二开关，所述第二薄膜晶体管112的开启或关闭对应所述第二源极1122和所述第二漏极1123之间的第二电流通道的开启或关闭。
所述第三薄膜晶体管113包括第三栅极1131、第三源极1132和第三漏极1133，所述第三栅极1131与所述第一漏极1113连接，所述第三源极1132用于接收第一电源输入端131所输入的第一电源信号。所述第三薄膜晶体管113为第三开关，所述第三薄膜晶体管113的开启或关闭对应所述第三源极1132和所述第三漏极1133之间的第三电流通道的开启或关闭。
所述第四薄膜晶体管114包括第四栅极1141、第四源极1142和第四漏极1143，所述第四栅极1141与所述第三漏极1133连接，所述第四源极1142用于接收第二电源输入端132所输入的第二电源信号，所述第四漏极1143与所述第二漏极1123连接。所述第四薄膜晶体管114为第四开关，所述第四薄膜晶体管114的开启或关闭对应所述第四源极1142和所述第四漏极1143之间的第四电流通道的开启或关闭。
所述第五薄膜晶体管115包括第五栅极1151、第五源极1152和第五漏极1153，所述第五栅极1151用于接收第三信号源123所发送的第三控制信号3CK，所述第五漏极1153与所述第三漏极1133连接，所述第五源极1152用于接收第三电源输入端133所输入的第三电源信号。所述第五薄膜晶体管115为第五开关，所述第五薄膜晶体管115的开启或关闭对应所述第五源极1152和所述第五漏极1153之间的第五电流通道的开启或关闭。
所述复位薄膜晶体管116包括第六栅极1161、第六源极1162和第六漏极1163，所述第六栅极1161与所述第五漏极1153连接，所述第六漏极1163与所述信号输出线141连接，所述第六源极1162用于接收第四电源输入端134所输入的第四电源信号。所述复位薄膜晶体管116为第六开关，所述复位薄膜晶体管116的开启或关闭对应所述第六源极1162和所述第六漏极1163之间的第六电流通道的开启或关闭。
所述输出薄膜晶体管117包括第七栅极1171、第七源极1172和第七漏极1173，所述第七源极1172用于接收第四信号源124所发送的第四控制信号XCK，所述第七栅极1171与所述第二漏极1123连接，所述第七漏极1173与所述信号输出线141连接。所述输出薄膜晶体管117为第七开关，所述输出薄膜晶体管117的开启或关闭对应所述第七源极1172和所述第七漏极1173之间的第七电流通道的开启或关闭。
所述第六薄膜晶体管118包括第八栅极1181、第八源极1182和第八漏极1183，所述第八栅极1181与所述信号输出线141连接，所述第八源极1182用于接收第五电源输入端135所输入的第五电源信号，所述第八漏极1183与所述第六栅极1161连接。所述第六薄膜晶体管118为第八开关，所述第六薄膜晶体管118的开启或关闭对应所述第八源极1182和所述第八漏极1183之间的第八电流通道的开启或关闭。
在本实施例中，所述输出薄膜晶体管117具有第一宽长比，所述复位薄膜晶体管116具有第二宽长比，所述第一宽长比大于所述第二宽长比。在本实施例中，所述第一宽长比为180微米/5微米，所述第二宽长比为10微米/5微米。
如图3所示，在本实施例中，所述第六薄膜晶体管118用于接收所述信号输出线141的第一信号，并用于根据所述第一信号在所述第一时间段301中开启，以使所述第五电源信号经所述第八源极1182和所述第八漏极1183输出至所述第六栅极1161，其中，所述第五电源信号用于在所述第一时间段301中控制所述复位薄膜晶体管116关闭。所述复位薄膜晶体管116用于在所述第一时间段301中根据所述第五电源信号关闭。其中，所述第一时间段301对应所述输出信号线的信号输出阶段。
在所述第一薄膜晶体管111、所述第二薄膜晶体管112、所述第三薄膜晶体管113、所述第四薄膜晶体管114、所述第五薄膜晶体管115、所述输出薄膜晶体管117、所述复位薄膜晶体管116、所述第六薄膜晶体管118、所述第七薄膜晶体管119均为P型三极管的情况下，在所述第一时间段301中，所述第一控制信号N-1为高电平信号，所述第二控制信号CK为高电平信号，所述第三控制信号3CK为高电平信号，所述第四控制信号XCK为低电平信号，所述第五控制信号3-2CK为高电平信号。其中，所述第二控制信号CK、所述第三控制信号3CK、所述第四控制信号XCK和所述第五控制信号3-2CK均可以为时钟信号。当然，在所述第一薄膜晶体管111、所述第二薄膜晶体管112、所述第三薄膜晶体管113、所述第四薄膜晶体管114、所述第五薄膜晶体管115、所述输出薄膜晶体管117、所述复位薄膜晶体管116、所述第六薄膜晶体管118、所述第七薄膜晶体管119均为N型三极管的情况下，在所述第一时间段301中，所述第一控制信号N-1为低电平信号，所述第二控制信号CK为低电平信号，所述第三控制信号3CK为低电平信号，所述第四控制信号XCK为高电平信号，所述第五控制信号3-2CK为低电平信号。
在本实施例中，通过在所述第一时间段301（所述输出信号线的信号输出阶段），利用所述信号线输出中的信号来触发所述第六薄膜晶体管118关闭，使得所述第五电源信号输出至所述第六栅极1161中，从而使得所述复位薄膜晶体管116在所述第一时间段301中关闭，避免了所述信号输出线141漏电，以及避免了所述第四漏极1143和所述第二漏极1123之间连接线漏电，从而使得所述信号输出线141稳定地输出所要输出的信号。此外，上述技术方案还有利于减小所述信号输出线141所输出的信号的复位沿时延。
假设所述信号输出线141中的目标输出信号为-7V（伏特），改进前的输出信号401为-6.99V，经过实验验证，改进后的输出信号402为-6.9999V。因此，上述技术方案可使得所述信号输出线141中的输出信号更加接近目标值。
参考图2，图2为本发明的显示面板的驱动电路的第二实施例的示意图。本实施例与上述第一实施例相似，不同之处在于：
所述驱动电路还包括第七薄膜晶体管119。所述第七薄膜晶体管119包括第九栅极1191、第九源极1192和第九漏极1193，所述第九栅极1191用于接收第五信号源125所发出的所述第五控制信号3-2CK，所述第九源极1192用于接收所述第二电源信号，所述第九漏极1193与所述第四源极1142连接，即，所述第四源极1142通过所述第九源极1192和所述第九漏极1193接收所述第二电源信号。所述第七薄膜晶体管119为第九开关，所述第七薄膜晶体管119的开启或关闭对应所述第九源极1192和所述第九漏极1193之间的第九电流通道的开启或关闭。
在本实施例中，所述第七薄膜晶体管119用于在第二时间段302中关闭，以阻止所述第三电源信号经所述第九源极1192和所述第九漏极1193输出至所述第四源极1142。
其中，所述第一时间段301和所述第二时间段302是相邻的两个时间段，所述第一时间段301位于所述第二时间段302之前，即，所述第二时间段302为与所述第一时间段301的相邻的下一个时间段。
在所述第一薄膜晶体管111、所述第二薄膜晶体管112、所述第三薄膜晶体管113、所述第四薄膜晶体管114、所述第五薄膜晶体管115、所述输出薄膜晶体管117、所述复位薄膜晶体管116、所述第六薄膜晶体管118、所述第七薄膜晶体管119均为P型三极管的情况下，在所述第二时间段302中，所述第一控制信号N-1为高电平信号，所述第二控制信号CK为高电平信号，所述第三控制信号3CK为低电平信号，所述第四控制信号XCK为高电平信号，所述第五控制信号3-2CK为高电平信号。在所述第一薄膜晶体管111、所述第二薄膜晶体管112、所述第三薄膜晶体管113、所述第四薄膜晶体管114、所述第五薄膜晶体管115、所述输出薄膜晶体管117、所述复位薄膜晶体管116、所述第六薄膜晶体管118、所述第七薄膜晶体管119均为N型三极管的情况下，在所述第二时间段302中，所述第一控制信号N-1为低电平信号，所述第二控制信号CK为低电平信号，所述第三控制信号3CK为高电平信号，所述第四控制信号XCK为低电平信号，所述第五控制信号3-2CK为低电平信号。
在本实施例中，所述第七薄膜晶体管119和所述第四薄膜晶体管114还用于在第二时间段302中共同作用，以阻止所述第四漏极1143和所述第二漏极1123之间的连接线中的第二信号复位。
在本实施例中，所述输出薄膜晶体管117还用于在所述第二时间段302中开启，以与所述复位薄膜晶体管116共同对所述信号输出线141中的第一信号进行复位。
在本实施例中，由于所述输出薄膜晶体管117的第一宽长比较大，电流能力很强，因此可以协助所述复位薄膜晶体管116迅速地对所述信号输出线141中的输出信号进行复位，使得所述输出信号的复位沿时延变小。同时，由于所述输出薄膜晶体管117的电流能力较大，所述复位薄膜晶体管116的宽长比可以缩减为10微米/5微米，减小了所述复位薄膜晶体管116的漏电，从而减小整个GOA（Gate driver On Array）的面积。
如图5所示，改进前的输出信号501的复位沿5011时延为1.48u，改进后的输出信号502的复位沿5021时延为0.9u，其中1u为1微米，复位沿时延的减小率为（1.48-0.9）/1.48≈39.19%。其中，图5中所示的复位沿5011和5021均为上升沿（针对P型三极管的情况），当然，所述复位沿5011和5021还可以为下降沿（针对N型三极管的情况）。
参考图6，图6为本发明的显示面板的驱动方法的第一实施例的流程图。本实施例的驱动方法实施于图1或图2中的显示面板的驱动电路中。
本实施例的驱动方法包括以下步骤：
步骤601，所述第六薄膜晶体管118接收所述信号输出线141中的第一信号。
步骤602，所述第六薄膜晶体管118根据所述第一信号在所述第一时间段301中开启，以使所述第五电源信号经所述第八源极1182和所述第八漏极1183输出至所述第六栅极1161，其中，所述第五电源信号用于所述第一时间段301中关闭所述复位薄膜晶体管116。
步骤603，所述复位薄膜晶体管116在所述第一时间段301中根据所述第五电源信号关闭。
在本实施例中，通过在所述第一时间段301（所述输出信号线的信号输出阶段），利用所述信号线输出中的信号来触发所述第六薄膜晶体管118关闭，使得所述第五电源信号输出至所述第六栅极1161中，从而使得所述复位薄膜晶体管116在所述第一时间段301中关闭，避免了所述信号输出线141漏电，以及避免了所述第四漏极1143和所述第二漏极1123之间连接线漏电，从而使得所述信号输出线141稳定地输出所要输出的信号。此外，上述技术方案还有利于减小所述信号输出线141所输出的信号的复位沿时延。
假设所述信号输出线141中的目标输出信号为-7V（伏特），改进前的输出信号401为-6.99V，经过实验验证，改进后的输出信号402为-6.9999V。因此，上述技术方案可使得所述信号输出线141中的输出信号更加接近目标值。
参考图7，图7为本发明的显示面板的驱动方法的第二实施例的流程图。本实施例与上述第一实施例相似，不同之处在于：
在本实施例中，所述方法还包括以下步骤：
步骤701，所述第七薄膜晶体管119在第二时间段302中关闭，以阻止所述第三电源信号经所述第九源极1192和所述第九漏极1193输出至所述第四源极1142。
步骤702，所述第七薄膜晶体管119和所述第四薄膜晶体管114在第二时间段302中共同作用，以阻止所述第四漏极1143和所述第二漏极1123之间的连接线中的第二信号复位。
步骤703，所述输出薄膜晶体管117在所述第二时间段302中开启，以与所述复位薄膜晶体管116共同对所述信号输出线141中的第一信号进行复位。
在本实施例中，由于所述输出薄膜晶体管117的第一宽长比较大，电流能力很强，因此可以协助所述复位薄膜晶体管116迅速地对所述信号输出线141中的输出信号进行复位，使得所述输出信号的复位沿时延变小。同时，由于所述输出薄膜晶体管117的电流能力较大，所述复位薄膜晶体管116的宽长比可以缩减为10微米/5微米，减小了所述复位薄膜晶体管116的漏电，从而减小整个GOA（Gate driver On Array）的面积。
如图5所示，改进前的输出信号501的复位沿5011时延为1.48u，改进后的输出信号502的复位沿5021时延为0.9u，其中1u为1微米，复位沿时延的减小率为（1.48-0.9）/1.48≈39.19%。其中，图5中所示的复位沿5011和5021均为上升沿（针对P型三极管的情况），当然，所述复位沿5011和5021还可以为下降沿（针对N型三极管的情况）。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
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Claims (19)

  1. 一种显示面板的驱动电路，其中
    所述驱动电路包括：
    一电容，包括第一极板和第二极板，所述第二极板与信号输出线连接；
    一第一薄膜晶体管，包括第一栅极、第一源极和第一漏极，所述第一栅极和所述第一源极连接，所述第一栅极和所述第一源极均用于接收第一信号源所发送的第一控制信号；
    一第二薄膜晶体管，包括第二栅极、第二源极和第二漏极，所述第一漏极与所述第二源极连接，所述第二漏极与所述电容的所述第一极板连接，所述第二栅极用于接收第二信号源所发送的第二控制信号；
    一第三薄膜晶体管，包括第三栅极、第三源极和第三漏极，所述第三栅极与所述第一漏极连接，所述第三源极用于接收第一电源信号；
    一第四薄膜晶体管，包括第四栅极、第四源极和第四漏极，所述第四栅极与所述第三漏极连接，所述第四源极用于接收第二电源信号，所述第四漏极与所述第二漏极连接；
    一第五薄膜晶体管，包括第五栅极、第五源极和第五漏极，所述第五栅极用于接收第三信号源所发送的第三控制信号，所述第五漏极与所述第三漏极连接，所述第五源极用于接收第三电源信号；
    一复位薄膜晶体管，包括第六栅极、第六源极和第六漏极，所述第六栅极与所述第五漏极连接，所述第六漏极与所述信号输出线连接，所述第六源极用于接收第四电源信号；
    一输出薄膜晶体管，包括第七栅极、第七源极和第七漏极，所述第七源极用于接收第四信号源所发送的第四控制信号，所述第七栅极与所述第二漏极连接，所述第七漏极与所述信号输出线连接；
    一第六薄膜晶体管，包括第八栅极、第八源极和第八漏极，所述第八栅极与所述信号输出线连接，所述第八源极用于接收第五电源信号，所述第八漏极与所述第六栅极连接；以及
    一第七薄膜晶体管，包括第九栅极、第九源极和第九漏极，所述第九栅极用于接收第五信号源所发出的第五控制信号，所述第九源极用于接收所述第二电源信号，所述第九漏极与所述第四源极连接；
    所述输出薄膜晶体管具有第一宽长比，所述复位薄膜晶体管具有第二宽长比，所述第一宽长比大于所述第二宽长比。
  2. 根据权利要求1所述的显示面板的驱动电路，其中
    所述第六薄膜晶体管用于接收所述信号输出线的第一信号，并用于根据所述第一信号在所述第一时间段中开启，以使所述第五电源信号经所述第八源极和所述第八漏极输出至所述第六栅极，其中，所述第五电源信号用于在所述第一时间段中控制所述复位薄膜晶体管关闭；
    所述复位薄膜晶体管用于在所述第一时间段中根据所述第五电源信号关闭。
  3. 根据权利要求1所述的显示面板的驱动电路，其中
    所述第七薄膜晶体管用于在第二时间段中关闭，以阻止所述第三电源信号经所述第九源极和所述第九漏极输出至所述第四源极。
  4. 根据权利要求3所述的显示面板的驱动电路，其中
    所述第七薄膜晶体管和所述第四薄膜晶体管还用于在第二时间段中共同作用，以阻止所述第四漏极和所述第二漏极之间的连接线中的第二信号复位。
  5. 根据权利要求3所述的显示面板的驱动电路，其中
    所述输出薄膜晶体管还用于在所述第二时间段中开启，以与所述复位薄膜晶体管共同对所述信号输出线中的第一信号进行复位。
  6. 根据权利要求3所述的显示面板的驱动电路，其中
    所述第一时间段对应所述输出信号线的信号输出阶段，所述第一时间段和所述第二时间段是相邻的两个时间段，所述第一时间段位于所述第二时间段之前。
  7. 根据权利要求1所述的显示面板的驱动电路，其中
    所述第一控制信号为当前行像素所对应的上一行像素的扫描信号。
  8. 一种显示面板的驱动电路，其中
    所述驱动电路包括：
    一电容，包括第一极板和第二极板，所述第二极板与信号输出线连接；
    一第一薄膜晶体管，包括第一栅极、第一源极和第一漏极，所述第一栅极和所述第一源极连接，所述第一栅极和所述第一源极均用于接收第一信号源所发送的第一控制信号；
    一第二薄膜晶体管，包括第二栅极、第二源极和第二漏极，所述第一漏极与所述第二源极连接，所述第二漏极与所述电容的所述第一极板连接，所述第二栅极用于接收第二信号源所发送的第二控制信号；
    一第三薄膜晶体管，包括第三栅极、第三源极和第三漏极，所述第三栅极与所述第一漏极连接，所述第三源极用于接收第一电源信号；
    一第四薄膜晶体管，包括第四栅极、第四源极和第四漏极，所述第四栅极与所述第三漏极连接，所述第四源极用于接收第二电源信号，所述第四漏极与所述第二漏极连接；
    一第五薄膜晶体管，包括第五栅极、第五源极和第五漏极，所述第五栅极用于接收第三信号源所发送的第三控制信号，所述第五漏极与所述第三漏极连接，所述第五源极用于接收第三电源信号；
    一复位薄膜晶体管，包括第六栅极、第六源极和第六漏极，所述第六栅极与所述第五漏极连接，所述第六漏极与所述信号输出线连接，所述第六源极用于接收第四电源信号；
    一输出薄膜晶体管，包括第七栅极、第七源极和第七漏极，所述第七源极用于接收第四信号源所发送的第四控制信号，所述第七栅极与所述第二漏极连接，所述第七漏极与所述信号输出线连接；
    一第六薄膜晶体管，包括第八栅极、第八源极和第八漏极，所述第八栅极与所述信号输出线连接，所述第八源极用于接收第五电源信号，所述第八漏极与所述第六栅极连接。
  9. 根据权利要求8所述的显示面板的驱动电路，其中
    所述输出薄膜晶体管具有第一宽长比，所述复位薄膜晶体管具有第二宽长比，所述第一宽长比大于所述第二宽长比。
  10. 根据权利要求9所述的显示面板的驱动电路，其中
    所述第六薄膜晶体管用于接收所述信号输出线的第一信号，并用于根据所述第一信号在所述第一时间段中开启，以使所述第五电源信号经所述第八源极和所述第八漏极输出至所述第六栅极，其中，所述第五电源信号用于在所述第一时间段中控制所述复位薄膜晶体管关闭；
    所述复位薄膜晶体管用于在所述第一时间段中根据所述第五电源信号关闭。
  11. 根据权利要求8所述的显示面板的驱动电路，其中
    所述驱动电路还包括：
    一第七薄膜晶体管，包括第九栅极、第九源极和第九漏极，所述第九栅极用于接收第五信号源所发出的第五控制信号，所述第九源极用于接收所述第二电源信号，所述第九漏极与所述第四源极连接。
  12. 根据权利要求11所述的显示面板的驱动电路，其中
    所述第七薄膜晶体管用于在第二时间段中关闭，以阻止所述第三电源信号经所述第九源极和所述第九漏极输出至所述第四源极。
  13. 根据权利要求12所述的显示面板的驱动电路，其中
    所述第七薄膜晶体管和所述第四薄膜晶体管还用于在第二时间段中共同作用，以阻止所述第四漏极和所述第二漏极之间的连接线中的第二信号复位。
  14. 根据权利要求12所述的显示面板的驱动电路，其中
    所述输出薄膜晶体管还用于在所述第二时间段中开启，以与所述复位薄膜晶体管共同对所述信号输出线中的第一信号进行复位。
  15. 根据权利要求12所述的显示面板的驱动电路，其中
    所述第一时间段对应所述输出信号线的信号输出阶段，所述第一时间段和所述第二时间段是相邻的两个时间段，所述第一时间段位于所述第二时间段之前。
  16. 根据权利要求8所述的显示面板的驱动电路，其中
    所述第一控制信号为当前行像素所对应的上一行像素的扫描信号。
  17. 一种用于如权利要求8所述的显示面板的驱动电路中的驱动方法，其中
    所述方法包括：
    所述第六薄膜晶体管接收所述信号输出线中的第一信号，并根据所述第一信号在所述第一时间段中开启，以使所述第五电源信号经所述第八源极和所述第八漏极输出至所述第六栅极，其中，所述第五电源信号用于所述第一时间段中关闭所述复位薄膜晶体管；
    所述复位薄膜晶体管在所述第一时间段中根据所述第五电源信号关闭。
  18. 根据权利要求17所述的驱动方法，其中
    所述方法还包括以下步骤：
    所述第七薄膜晶体管在第二时间段中关闭，以阻止所述第三电源信号经所述第九源极和所述第九漏极输出至所述第四源极；
    所述第七薄膜晶体管和所述第四薄膜晶体管在第二时间段中共同作用，以阻止所述第四漏极和所述第二漏极之间的连接线中的第二信号复位。
  19. 根据权利要求18所述的驱动方法，其中
    所述方法还包括以下步骤：
    所述输出薄膜晶体管在所述第二时间段中开启，以与所述复位薄膜晶体管共同对所述信号输出线中的第一信号进行复位。
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Publication number Priority date Publication date Assignee Title
TWI544474B (zh) * 2014-11-19 2016-08-01 友達光電股份有限公司 移位暫存器
CN107633799A (zh) * 2017-10-13 2018-01-26 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080101529A1 (en) * 2006-10-26 2008-05-01 Mitsubishi Electric Corporation Shift register and image display apparatus containing the same
US20080297495A1 (en) * 2007-06-04 2008-12-04 Samsung Electronics Co., Ltd Apparatus for driving a display device, display device including the same, and method thereof
CN102708778A (zh) * 2011-11-28 2012-10-03 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
CN103280196A (zh) * 2012-09-19 2013-09-04 上海中航光电子有限公司 一种移位寄存器及薄膜晶体管液晶显示器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7889157B2 (en) * 2003-12-30 2011-02-15 Lg Display Co., Ltd. Electro-luminescence display device and driving apparatus thereof
US7957110B2 (en) * 2005-01-25 2011-06-07 Hannstar Display Corporation Display apparatus current discharging method
TWI271115B (en) * 2005-08-30 2007-01-11 Au Optronics Corp Active display and driving circuit of a pixel thereof
KR101369883B1 (ko) * 2007-02-26 2014-03-25 삼성디스플레이 주식회사 액정 표시 장치
CN102708824B (zh) * 2012-05-31 2014-04-02 京东方科技集团股份有限公司 薄膜晶体管阈值电压偏移补偿电路及goa电路、显示器
CN103280796B (zh) * 2013-01-12 2014-12-10 辽宁工程技术大学 供电***母联开关柔性倒闸技术及其实现方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080101529A1 (en) * 2006-10-26 2008-05-01 Mitsubishi Electric Corporation Shift register and image display apparatus containing the same
US20080297495A1 (en) * 2007-06-04 2008-12-04 Samsung Electronics Co., Ltd Apparatus for driving a display device, display device including the same, and method thereof
CN102708778A (zh) * 2011-11-28 2012-10-03 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
CN103280196A (zh) * 2012-09-19 2013-09-04 上海中航光电子有限公司 一种移位寄存器及薄膜晶体管液晶显示器

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