WO2015154566A1 - 电路启动方法、控制电路及电压基准电路 - Google Patents

电路启动方法、控制电路及电压基准电路 Download PDF

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Publication number
WO2015154566A1
WO2015154566A1 PCT/CN2015/071145 CN2015071145W WO2015154566A1 WO 2015154566 A1 WO2015154566 A1 WO 2015154566A1 CN 2015071145 W CN2015071145 W CN 2015071145W WO 2015154566 A1 WO2015154566 A1 WO 2015154566A1
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Prior art keywords
operational amplifier
reference voltage
circuit
output
input
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PCT/CN2015/071145
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English (en)
French (fr)
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李斌斌
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中兴通讯股份有限公司
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Priority to EP15776793.0A priority Critical patent/EP3182242A4/en
Priority to US15/503,196 priority patent/US10317920B2/en
Publication of WO2015154566A1 publication Critical patent/WO2015154566A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to circuit control technology, in particular to a circuit starting method, a control circuit and a voltage reference circuit.
  • voltage reference generation circuits are widely used in analog circuit systems.
  • a large capacitance of a micro-level is externally connected to the output of the circuit to meet the requirements.
  • the external connection of a large capacitor at the output of the circuit delays the start-up time of the entire circuit and is not conducive to large-scale product testing.
  • the embodiment of the invention provides a circuit starting method, a control circuit and a voltage reference circuit, which can realize fast start of the circuit on the basis of meeting the requirements of high precision and low power consumption.
  • An embodiment of the present invention provides a control circuit, including: an operational amplifier circuit and a comparison control circuit;
  • the operational amplifier circuit is configured to establish an input reference voltage and an output reference voltage through an operational amplifier and an external capacitor;
  • the comparison control circuit is configured to perform a flip operation when the input reference voltage and the output reference voltage are identical, and output an enable signal to the operational amplifier to turn off the operational amplifier.
  • the comparison control circuit is a comparator
  • the input reference voltage and the output reference voltage of the operational amplifier circuit together serve as an input to the comparator, and the output of the comparator is an enable signal.
  • the comparator is a comparator with a falling hysteresis.
  • the operational amplifier circuit comprises: a power supply, an operational amplifier, a transistor, an external capacitor, a bias current source, and a resistor;
  • the transistor is a PMOS transistor or an NMOS transistor.
  • the power supply is connected to the power input end of the operational amplifier and the drain of the PMOS transistor; the output end of the operational amplifier is connected to the gate of the PMOS transistor; the source of the PPMOS transistor is respectively connected to the end of the external capacitor and the bias current The positive end of the source is connected; the other end of the external capacitor and the negative end of the bias current source are grounded; the input reference voltage is used as the forward input of the operational amplifier; the source voltage of the PMOS transistor is the output The terminal reference voltage is used as a negative input of the operational amplifier; the forward input terminal and the negative input terminal of the operational amplifier are connected by a resistor.
  • the embodiment of the invention further provides a circuit starting method, the method comprising:
  • the input terminal reference voltage and the output terminal reference voltage are established by an operational amplifier and an external capacitor in the operational amplifier circuit; when the input terminal reference voltage and the output terminal reference voltage are identical, the comparison control circuit performs a flip operation, and outputs an enable signal to The operational amplifier is to turn off the operational amplifier.
  • the embodiment of the invention further provides a voltage reference circuit, comprising: a voltage reference generation circuit and a control circuit for controlling the voltage reference generation circuit; the control circuit includes an operational amplifier circuit and a comparison control circuit; wherein
  • the operational amplifier circuit is configured to establish an input reference voltage and an output reference voltage through an operational amplifier and an external capacitor;
  • the comparison control circuit is configured to perform a flip operation when the input reference voltage and the output reference voltage are identical, and output an enable signal to the operational amplifier to turn off the operational amplifier.
  • the circuit starting method, the control circuit and the voltage reference circuit provided by the embodiments of the present invention establish an input terminal reference voltage and an output terminal reference voltage through an operational amplifier and an external capacitor in the operational amplifier circuit; when the input terminal reference voltage and the output terminal When the reference voltages coincide, the comparison control circuit performs a flip operation and outputs an enable signal to the operational amplifier to turn off the operational amplifier. In this way, the fast start of the circuit can be realized on the basis of meeting the requirements of high precision and low power consumption.
  • control circuit is simple, convenient, and easy to implement.
  • FIG. 1 is a schematic structural diagram of a control circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a control circuit in a practical application of the present invention.
  • FIG. 3 is a schematic structural diagram of a hysteresis comparator according to an embodiment of the present invention.
  • the input terminal reference voltage and the output terminal reference voltage are established by an operational amplifier and an external capacitor in the operational amplifier circuit; when the input terminal reference voltage and the output terminal reference voltage are identical, the comparison control circuit performs a flip operation And outputting an enable signal to the operational amplifier to turn off the operational amplifier.
  • control circuit 1 is a schematic structural diagram of a control circuit according to an embodiment of the present invention. As shown in FIG. 1, the control circuit includes: an operational amplifier circuit 10 and a comparison control circuit 20;
  • the operational amplifier circuit 10 is configured to establish an input reference voltage and an output reference voltage through an operational amplifier and an external capacitor;
  • the comparison control circuit 20 is configured to perform a flip operation when the input reference voltage and the output reference voltage are identical, and output an enable signal to the operational amplifier to turn off the operational amplifier.
  • the operational amplifier circuit 10 includes: a power supply VDD, an operational amplifier EA, a transistor MP, an external capacitor C, a bias current source Ibias, and a resistor R; wherein the transistor MP It is a PMOS tube or an NMOS tube.
  • the comparison control circuit 20 is a comparator
  • the power supply VDD is connected to the power input terminal of the operational amplifier EA and the drain of the PMOS transistor MP; the output terminal of the operational amplifier EA is connected to the gate of the PMOS transistor MP; the source of the PMOS transistor MP is respectively connected to the external capacitor One end of C is connected to the forward end of the bias current source Ibias; the other end of the external capacitor C and the negative end of the bias current source Ibias are grounded; the input reference voltage VREF_INT is used as the forward direction of the operational amplifier EA Input; the source voltage of the PMOS transistor MP is the output reference voltage VREF_OUT, and the output reference voltage VREF_OUT is input as the negative direction of the operational amplifier EA; the positive input and the negative input of the operational amplifier EA The terminals are connected by a resistor R.
  • the reference core starts to operate, generates the reference voltage VREF_INT, and uses the reference voltage VREF_INT as the forward input of the operational amplifier EA.
  • the reference voltage VREF_INT is quickly established after the entire voltage reference generation circuit is powered on by the power supply VDD, as the quick start.
  • the input reference voltage VREF_INT of the voltage reference generation circuit is connected in the form of a unity gain negative feedback such that the voltages of the two input terminals of the operational amplifier EA are embedded in the same size.
  • the output terminal of the operational amplifier EA is connected to the output reference voltage VREF_OUT as the output of the entire voltage reference generation circuit, thereby providing a reference voltage for other external circuits.
  • a small reference current causes the settling time of the output reference voltage VREF_OUT to be relatively long, so that the output reference voltage VREF_OUT is still at a low level after the input reference voltage VREF_INT is established.
  • the forward input terminal of the operational amplifier EA is at a high level
  • the negative input terminal is at a low level
  • the operational amplifier EA is operated in a comparator mode
  • the gate output of the transistor MP is at a low level, which is used as a switch tube.
  • the transistor MP is turned on to further charge the external capacitor C.
  • the magnitude of the current is determined by the width-to-length ratio of the transistor MP. The larger the current, the shorter the settling time of the output reference voltage VREF_OUT.
  • the operational amplifier EA since the operational amplifier EA has a certain reaction time, the current is too large, which may cause overcharging of the external capacitor C.
  • the operational amplifier EA When the output reference voltage VREF_OUT is established, close to the input reference voltage VREF_INT, the operational amplifier EA starts to enter the operational mode, and the output reference voltage VREF_OUT is pulled by the negative feedback, so that the external capacitor C is no longer charged.
  • the transistor MP operates in the saturation region, so that the output reference voltage VREF_OUT and the input reference voltage VREF_INT are clamped, that is, the output reference voltage VREF_OUT reaches the set value.
  • the operational amplifier EA since the operational amplifier EA has a certain reaction time, if the current flowing from the transistor MP is too large, the output reference voltage VREF_OUT has a small overcharge voltage.
  • the current flowing through the transistor MP must be large, the overcharge voltage is unavoidable; due to the presence of the operational amplifier EA, the overcharge voltage rises little. And can be recovered in a short time.
  • the overcharge voltage can be utilized to provide sufficient flip space for the comparator. It should be noted that due to the existence of the overcharge voltage, the bias current source Ibias is required to be large enough to ensure that the overcharge of the output reference voltage VREF_OUT falls to a set value in a short time.
  • the comparator is flipped to provide an enable signal VREF_OK to the operational amplifier EA; the enable signal VREF_OK controls the operational amplifier EA to be turned off to avoid unnecessary waste of power consumption.
  • the positive input terminal and the negative input terminal of the operational amplifier EA are connected by a resistor R; the resistor R has two functions: 1) theoretically, the two input voltages of the operational amplifier EA are guaranteed to be the same. At the same time, no large current flows, so that the external capacitor C directly communicates with the input reference voltage VREF_INT, thereby affecting the input reference voltage VREF_INT; 2) ensuring the output reference voltage VREF_OUT as the output of the entire voltage reference generation circuit, When other external circuits provide the reference voltage, if there is a slight leakage current at the output, the current reference voltage VREF_INT can be supplied to the output terminal reference voltage VREF_OUT through the resistor R to ensure the stability of the output reference voltage VREF_OUT.
  • a comparator as shown in FIG. 3 may be further selected, and the comparator is a hysteresis comparator.
  • the hysteresis effect occurs only when the output reference voltage VREF_OUT falls, that is, the hysteresis comparator is flipped when the output reference voltage VREF_OUT is smaller than the input reference voltage VREF_INT to a certain extent. .
  • the rising process of the output reference voltage VREF_OUT is still equal to the input reference voltage VREF_INT.
  • the hysteresis comparator will flip again, thereby turning on the operational amplifier EA again, and the external capacitor C can be recharged through the MP tube until the output reference voltage VREF_OUT reaches the input reference voltage VREF_INT again. Value.
  • the voltage reference generation circuit according to the embodiment of the present invention can realize the quick start of the voltage reference generation circuit on the basis of meeting the requirements of the high precision and low power consumption.
  • an embodiment of the present invention further provides a circuit startup method, comprising: establishing an input reference voltage and an output reference voltage through an operational amplifier and an external capacitor in an operational amplifier circuit; When the terminal reference voltage and the output terminal reference voltage coincide, the comparison control circuit performs a flip operation and outputs an enable signal VREF_OK to the operational amplifier to turn off the operational amplifier.
  • the embodiment of the present invention further provides a voltage reference circuit, including: a voltage reference generation circuit and a control circuit for controlling the voltage reference generation circuit; wherein, as shown in FIG. 1, the control circuit includes: an operational amplifier Circuit 10, comparison control circuit 20; wherein
  • the operational amplifier circuit 10 is configured to establish an input reference voltage and an output reference voltage through an operational amplifier and an external capacitor;
  • the comparison control circuit 20 is configured to perform a flip operation when the input reference voltage and the output reference voltage are identical, and output an enable signal VREF_OK to the operational amplifier to turn off the operational amplifier.
  • the operational amplifier circuit 10 includes: a power supply VDD, an operational amplifier EA, a transistor MP, an external capacitor C, a bias current source Ibias, and a resistor R; wherein the transistor MP It is a PMOS tube or an NMOS tube.
  • the comparison control circuit 20 is a comparator
  • the power supply VDD is connected to the power input terminal of the operational amplifier EA and the drain of the PMOS transistor MP; the output terminal of the operational amplifier EA is connected to the gate of the PMOS transistor MP; the source of the PMOS transistor MP is respectively connected to the external capacitor One end of C is connected to the forward end of the bias current source Ibias; the other end of the external capacitor C and the negative end of the bias current source Ibias are grounded; the input reference voltage VREF_INT is used as the forward direction of the operational amplifier EA Input; the source voltage of the PMOS transistor MP is the output reference voltage VREF_OUT, and the output reference voltage VREF_OUT is input as the negative direction of the operational amplifier EA; the positive input and the negative input of the operational amplifier EA The terminals are connected by a resistor R.
  • the reference core starts to operate, generates the reference voltage VREF_INT, and uses the reference voltage VREF_INT as the forward input of the operational amplifier EA.
  • the reference voltage VREF_INT is quickly established after the entire voltage reference generation circuit is powered on by the power supply VDD, as the quick start.
  • the input reference voltage VREF_INT of the voltage reference generation circuit is connected in the form of a unity gain negative feedback such that the voltages of the two input terminals of the operational amplifier EA are embedded in the same size.
  • the output terminal of the operational amplifier EA is connected to the output reference voltage VREF_OUT as the output of the entire voltage reference generation circuit, thereby providing a reference voltage for other external circuits.
  • a small reference current causes the settling time of the output reference voltage VREF_OUT to be relatively long, so that the output reference voltage VREF_OUT is still at a low level after the input reference voltage VREF_INT is established.
  • the forward input terminal of the operational amplifier EA is at a high level
  • the negative input terminal is at a low level
  • the operational amplifier EA is operated in a comparator mode
  • the gate output of the transistor MP is at a low level, which is used as a switch tube.
  • the transistor MP is turned on to further charge the external capacitor C.
  • the magnitude of the current is determined by the width-to-length ratio of the transistor MP. The larger the current, the shorter the settling time of the output reference voltage VREF_OUT.
  • the operational amplifier EA since the operational amplifier EA has a certain reaction time, the current is too large, which may cause overcharging of the external capacitor C.
  • the operational amplifier EA When the output reference voltage VREF_OUT is established, close to the input reference voltage VREF_INT, the operational amplifier EA starts to enter the operational mode, and the output reference voltage VREF_OUT is pulled by the negative feedback, so that the external capacitor C is no longer charged.
  • the transistor MP operates in the saturation region, so that the output reference voltage VREF_OUT and the input reference voltage VREF_INT are clamped, that is, the output reference voltage VREF_OUT reaches the set value.
  • the operational amplifier EA since the operational amplifier EA has a certain reaction time, if the current flowing from the transistor MP is too large, the output reference voltage VREF_OUT has a small overcharge voltage.
  • the current flowing through the transistor MP must be large, the overcharge voltage is unavoidable; due to the presence of the operational amplifier EA, the overcharge voltage rises little. And can be recovered in a short time.
  • the overcharge voltage can be utilized to provide sufficient flip space for the comparator. It should be noted that due to the existence of the overcharge voltage, the bias current source Ibias is required to be large enough to ensure that the overcharge of the output reference voltage VREF_OUT falls to a set value in a short time.
  • the comparator is flipped to provide an enable signal VREF_OK to the operational amplifier EA; the enable signal VREF_OK controls the operational amplifier EA to be turned off to avoid unnecessary waste of power consumption.
  • the positive input terminal and the negative input terminal of the operational amplifier EA are connected by a resistor R; the resistor R has two functions: 1) from a theoretical point of view, the two input voltages of the operational amplifier EA are guaranteed to be uniform. At the same time, no large current flows, so that the external capacitor C directly communicates with the input reference voltage VREF_INT, thereby affecting the input reference voltage VREF_INT; 2) ensuring the output reference voltage VREF_OUT as the output of the entire voltage reference generation circuit, When other external circuits provide the reference voltage, if there is a slight leakage current at the output, the current reference voltage VREF_INT can be supplied to the output terminal reference voltage VREF_OUT through the resistor R to ensure the stability of the output reference voltage VREF_OUT.
  • a comparator as shown in FIG. 3 may be further selected, and the comparator is a hysteresis comparator.
  • the hysteresis effect occurs only when the output reference voltage VREF_OUT falls, that is, the hysteresis comparator is flipped when the output reference voltage VREF_OUT is smaller than the input reference voltage VREF_INT to a certain extent. .
  • the rising process of the output reference voltage VREF_OUT is still equal to the input reference voltage VREF_INT.
  • the hysteresis comparator will flip again, thereby turning on the operational amplifier EA again, and the external capacitor C can be recharged through the MP tube until the output reference voltage VREF_OUT reaches the input reference voltage VREF_INT again. Value.
  • a circuit starting method, a control circuit, and a voltage reference circuit provided by the embodiments of the present invention have the following beneficial effects: establishing an input terminal reference voltage and an output terminal reference voltage through an operational amplifier and an external capacitor in the operational amplifier circuit;
  • the comparison control circuit performs a flip operation, and outputs an enable signal to the operational amplifier to turn off the operational amplifier, thereby being able to meet the requirements of high precision and low power consumption. Achieve fast start-up of the circuit.

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Abstract

一种电路启动方法、控制电路及电压基准电路。控制电路包括运放电路（10）和比较控制电路（20）；其中，运放电路（10），配置为通过运算放大器（EA）和外接电容（C）建立输入端基准电压（VREF_INT）和输出端基准电压（VREF_OUT）；比较控制电路（20），配置为当输入端基准电压（VREF_INT）和输出端基准电压（VREF_OUT）一致时，执行翻转操作，并输出使能信号（VREF_OK）至运算放大器（EA），以关闭运算放大器（EA）。

Description

电路启动方法、控制电路及电压基准电路 技术领域
本发明涉及电路控制技术，尤其涉及一种电路启动方法、控制电路及电压基准电路。
背景技术
目前，电压基准生成电路在模拟电路***中得到广泛应用。为了满足电压基准生成电路高精度和低功耗的要求，通常采用在电路输出端外接一个微法级的大电容的方式来满足要求。然而，在电路的输出端外接一个大电容会延时整个电路的启动时间，并不利于大规模产品测试。
发明内容
本发明实施例提供了一种电路启动方法、控制电路及电压基准电路，能够在满足高精度和低功耗的指标要求的基础上，实现电路的快速启动。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供一种控制电路，包括：运放电路和比较控制电路；其中，
所述运放电路，配置为通过运算放大器和外接电容建立输入端基准电压和输出端基准电压；
所述比较控制电路，配置为当所述输入端基准电压和输出端基准电压一致时，执行翻转操作，并输出使能信号至所述运算放大器，以关闭所述运算放大器。
上述方案中，所述比较控制电路为比较器；
相应地，所述运放电路的输入端基准电压和输出端基准电压共同作为所述比较器的输入，所述比较器的输出为使能信号。
上述方案中，所述比较器为带下降迟滞的比较器。
上述方案中，所述运放电路包括：电源、运算放大器、晶体管、外接电容、偏置电流源及电阻；其中，
所述晶体管为PMOS管或NMOS管。
上述方案中，在所述运放电路中，当所述晶体管为PMOS管时，
所述电源与运算放大器的电源输入端和PMOS管的漏极相连；所述运算放大器的输出端与PMOS管的栅极相连；所述PPMOS管的源极分别与外接电容的一端和偏置电流源的正向端相连；所述外接电容的另一端和偏置电流源的负向端均接地；所述输入端基准电压作为运算放大器的正向输入；所述PMOS管的源极电压为输出端基准电压，并将所述输出端基准电压作为运算放大器的负向输入；所述运算放大器的正向输入端和负向输入端之间通过电阻相连。
本发明实施例还提供一种电路启动方法，该方法包括：
通过运放电路中的运算放大器和外接电容建立输入端基准电压和输出端基准电压；当所述输入端基准电压和输出端基准电压一致时，比较控制电路执行翻转操作，并输出使能信号至所述运算放大器，以关闭所述运算放大器。
本发明实施例又提供一种电压基准电路，包括：电压基准生成电路和控制电压基准生成电路的控制电路；所述控制电路包括运放电路和比较控制电路；其中，
所述运放电路，配置为通过运算放大器和外接电容建立输入端基准电压和输出端基准电压；
所述比较控制电路，配置为当所述输入端基准电压和输出端基准电压一致时，执行翻转操作，并输出使能信号至所述运算放大器，以关闭所述运算放大器。
本发明实施例所提供的电路启动方法、控制电路及电压基准电路，通过运放电路中的运算放大器和外接电容建立输入端基准电压和输出端基准电压；当所述输入端基准电压和输出端基准电压一致时，比较控制电路执行翻转操作，并输出使能信号至所述运算放大器，以关闭所述运算放大器。如此，能够在满足高精度和低功耗的指标要求的基础上，实现电路的快速启动。
而且，本发明实施例中，所述控制电路，实现方案简单、方便，易于实现。
附图说明
图1为本发明实施例控制电路的组成结构示意图；
图2为本发明实际应用中控制电路的组成结构示意图；
图3为本发明实施例迟滞比较器的结构示意图。
具体实施方式
在本发明实施例中，通过运放电路中的运算放大器和外接电容建立输入端基准电压和输出端基准电压；当所述输入端基准电压和输出端基准电压一致时，比较控制电路执行翻转操作，并输出使能信号至所述运算放大器，以关闭所述运算放大器。
下面结合附图及具体实施例对本发明再作进一步详细的说明。
图1为本发明实施例控制电路的组成结构示意图，如图1所示，所述控制电路包括：运放电路10、比较控制电路20；其中，
所述运放电路10，配置为通过运算放大器和外接电容建立输入端基准电压和输出端基准电压；
所述比较控制电路20，配置为当所述输入端基准电压和输出端基准电压一致时，执行翻转操作，并输出使能信号至所述运算放大器，以关闭所述运算放大器。
这里，如图2所示，在实际应用中，所述运放电路10包括：电源VDD、运算放大器EA、晶体管MP、外接电容C、偏置电流源Ibias及电阻R；其中，所述晶体管MP为PMOS管或NMOS管。
这里，如图2所示，在实际应用中，所述比较控制电路20为比较器；
相应地，所述运放电路10的输入端基准电压VREF_INT和输出端基准电压VREF_OUT共同作为所述比较器的输入，所述比较器的输出为使能信号VREF_OK。
在所述运放电路10中，当所述晶体管MP为PMOS管时，如图2所示的运放电路的各部件的连接关系为：
所述电源VDD与运算放大器EA的电源输入端和PMOS管MP的漏极相连；所述运算放大器EA的输出端与PMOS管MP的栅极相连；所述PMOS管MP的源极分别与外接电容C的一端和偏置电流源Ibias的正向端相连；所述外接电容C的另一端和偏置电流源Ibias的负向端均接地；所述输入端基准电压VREF_INT作为运算放大器EA的正向输入；所述PMOS管MP的源极电压为输出端基准电压VREF_OUT，并将所述输出端基准电压VREF_OUT作为运算放大器EA的负向输入；所述运算放大器EA的正向输入端和负向输入端之间通过电阻R相连。
在实际应用中，如图2所示，当电压基准生成电路通过电源VDD上电后，基准核心开始工作，产生基准电压VREF_INT，并将所述基准电压VREF_INT作为运算放大器EA的正向输入。这里，需要说明的是，由于基准核心只有很小的容性负载，所以，所述基准电压VREF_INT在整个电压基准生成电路通过电源VDD上电完成后，很快就会建立起来，作为该快速启动电压基准生成电路的输入端基准电压VREF_INT。进一步地，将运算放大器EA接成单位增益负反馈形式，使得运算放大器EA的两个输入端电压嵌成一样大小。同时，运算放大器EA的输出端接输出端基准电压VREF_OUT，作为整个电压基准生成电路的输出，从而为其它外接电路提供基准电压。
在实际应用中，由于模拟电路***对电压基准生成电路的精度要求比较高，并且有小的噪声，好的电源抑制比，因此通常在输出端基准电压VREF_OUT端接有微法(uF)级的大电容C。
然而，大的电容，小的基准电流会造成输出端基准电压VREF_OUT的建立时间比较长，使得在输入端基准电压VREF_INT建立完成后，输出端基准电压VREF_OUT仍然处于一个低电平。此时，运算放大器EA的正向输入端为高电平，负向输入端为低电平，运算放大器EA工作在比较器模式；晶体管MP的栅级输出为低电平，作为开关管使用，将晶体管MP打开，进一步为外接电容C进行充电。电流的大小由晶体管MP宽长比决定，电流越大，输出端基准电压VREF_OUT的建立时间越短。但是，由于运算放大器EA有一定的反应时间，电流太大会造成外接电容C的过度充电。
当输出端基准电压VREF_OUT建立起来后，与输入端基准电压VREF_INT接近时，运算放大器EA开始进入运放模式，利用负反馈将输出端基准电压VREF_OUT拉住，使得外接电容C不再往上充电，晶体管MP工作在饱和区，使得输出端基准电压VREF_OUT和输入端基准电压VREF_INT嵌位，即输出端基准电压VREF_OUT达到设定值。
但是，由于运算放大器EA有一定的反应时间，所以如果从晶体管MP流过的电流过大，输出端基准电压VREF_OUT就会有一个小的过充电压。然而，当对输出端基准电压VREF_OUT的建立时间要求比较短，流经晶体管MP的电流必须大，所述过充电压不可避免；由于运算放大器EA的存在，所述过充电压的上升幅度很小，并且在很短的时间内可以恢复。同时，可以利用所述过充电压，提供给比较器足够的翻转空间。需要说明的是，由于所述过充电压的存在，要求偏置电流源Ibias足够大，以保证输出端基准电压VREF_OUT的过充在很短时间内降到设定值。
进一步地，当输出端基准电压VREF_OUT建立完成后，比较器翻转，提供给运算放大器EA一个使能信号VREF_OK；所述使能信号VREF_OK控制运算放大器EA关闭，以免造成不必要的功耗浪费。
同时，在运算放大器EA的正向输入端和负向输入端之间通过电阻R相连；所述电阻R存在两个作用：1)从理论的角度讲，保证运算放大器EA的两个输入电压一致的同时不会流过大电流，以致于外接电容C与输入端基准电压VREF_INT直接连通，从而影响输入端基准电压VREF_INT；2)保证输出端基准电压VREF_OUT作为整个电压基准生成电路的输出，在给其它外接电路提供基准电压时，如果输出端存在有轻微的漏电情况下，可以通过电阻R由输入端基准电压VREF_INT提供给输出端基准电压VREF_OUT小的电流，从而保证输出端基准电压VREF_OUT的稳定。
进一步地，如果输出端存在有比较大的漏电情况下，通过电阻R由输入端基准电压VREF_INT提供给输出端基准电压VREF_OUT的电流已经不能满足需求，输出端基准电压VREF_OUT会不断下降。因此，在本发明实施例中，可以进一步选用如图3所示的比较器，所述比较器为迟滞比较器。如此，由于该比较器带半边迟滞功能，只有在输出端基准电压VREF_OUT下降时才会产生迟滞效应，即输出端基准电压VREF_OUT比输入端基准电压VREF_INT小到一定程度时，迟滞比较器才会翻转。输出端基准电压VREF_OUT的上升过程翻转域值仍等于输入端基准电压VREF_INT。当输出端基准电压VREF_OUT下降到一定程度时，迟滞比较器会再次翻转，从而再次打开运算放大器EA，能够通过MP管重新对外接电容C充电，直到输出端基准电压VREF_OUT重新达到输入端基准电压VREF_INT的值。
如此，通过本发明实施例所述的电压基准生成电路，能够在满足高精度和低功耗的指标要求的基础上，实现电压基准生成电路的快速启动。
基于上述电压基准生成电路，本发明实施例还提供了一种电路启动方法，该方法包括：通过运放电路中的运算放大器和外接电容建立输入端基准电压和输出端基准电压；当所述输入端基准电压和输出端基准电压一致时，比较控制电路执行翻转操作，并输出使能信号VREF_OK至所述运算放大器，以关闭所述运算放大器。
基于上述控制电路，本发明实施例又提供了一种电压基准电路，包括：电压基准生成电路和控制电压基准生成电路的控制电路；其中，如图1所示，所述控制电路包括：运放电路10、比较控制电路20；其中，
所述运放电路10，配置为通过运算放大器和外接电容建立输入端基准电压和输出端基准电压；
所述比较控制电路20，配置为当所述输入端基准电压和输出端基准电压一致时，执行翻转操作，并输出使能信号VREF_OK至所述运算放大器，以关闭所述运算放大器。
这里，如图2所示，在实际应用中，所述运放电路10包括：电源VDD、运算放大器EA、晶体管MP、外接电容C、偏置电流源Ibias及电阻R；其中，所述晶体管MP为PMOS管或NMOS管。
这里，如图2所示，在实际应用中，所述比较控制电路20为比较器；
相应地，所述运放电路10的输入端基准电压VREF_INT和输出端基准电压VREF_OUT共同作为所述比较器的输入，所述比较器的输出为使能信号VREF_OK。
在所述运放电路10中，当所述晶体管MP为PMOS管时，如图2所示的运放电路的各部件的连接关系为：
所述电源VDD与运算放大器EA的电源输入端和PMOS管MP的漏极相连；所述运算放大器EA的输出端与PMOS管MP的栅极相连；所述PMOS管MP的源极分别与外接电容C的一端和偏置电流源Ibias的正向端相连；所述外接电容C的另一端和偏置电流源Ibias的负向端均接地；所述输入端基准电压VREF_INT作为运算放大器EA的正向输入；所述PMOS管MP的源极电压为输出端基准电压VREF_OUT，并将所述输出端基准电压VREF_OUT作为运算放大器EA的负向输入；所述运算放大器EA的正向输入端和负向输入端之间通过电阻R相连。
在实际应用中，如图2所示，当电压基准生成电路通过电源VDD上电后，基准核心开始工作，产生基准电压VREF_INT，并将所述基准电压VREF_INT作为运算放大器EA的正向输入。这里，需要说明的是，由于基准核心只有很小的容性负载，所以，所述基准电压VREF_INT在整个电压基准生成电路通过电源VDD上电完成后，很快就会建立起来，作为该快速启动电压基准生成电路的输入端基准电压VREF_INT。进一步地，将运算放大器EA接成单位增益负反馈形式，使得运算放大器EA的两个输入端电压嵌成一样大小。同时，运算放大器EA的输出端接输出端基准电压VREF_OUT，作为整个电压基准生成电路的输出，从而为其它外接电路提供基准电压。
在实际应用中，由于模拟电路***对电压基准生成电路的精度要求比较高，并且有小的噪声，好的电源抑制比，因此通常在输出端基准电压VREF_OUT端接有微法(uF)级的大电容C。
然而，大的电容，小的基准电流会造成输出端基准电压VREF_OUT的建立时间比较长，使得在输入端基准电压VREF_INT建立完成后，输出端基准电压VREF_OUT仍然处于一个低电平。此时，运算放大器EA的正向输入端为高电平，负向输入端为低电平，运算放大器EA工作在比较器模式；晶体管MP的栅级输出为低电平，作为开关管使用，将晶体管MP打开，进一步为外接电容C进行充电。电流的大小由晶体管MP宽长比决定，电流越大，输出端基准电压VREF_OUT的建立时间越短。但是，由于运算放大器EA有一定的反应时间，电流太大会造成外接电容C的过度充电。
当输出端基准电压VREF_OUT建立起来后，与输入端基准电压VREF_INT接近时，运算放大器EA开始进入运放模式，利用负反馈将输出端基准电压VREF_OUT拉住，使得外接电容C不再往上充电，晶体管MP工作在饱和区，使得输出端基准电压VREF_OUT和输入端基准电压VREF_INT嵌位，即输出端基准电压VREF_OUT达到设定值。
但是，由于运算放大器EA有一定的反应时间，所以如果从晶体管MP流过的电流过大，输出端基准电压VREF_OUT就会有一个小的过充电压。然而，当对输出端基准电压VREF_OUT的建立时间要求比较短，流经晶体管MP的电流必须大，所述过充电压不可避免；由于运算放大器EA的存在，所述过充电压的上升幅度很小，并且在很短的时间内可以恢复。同时，可以利用所述过充电压，提供给比较器足够的翻转空间。需要说明的是，由于所述过充电压的存在，要求偏置电流源Ibias足够大，以保证输出端基准电压VREF_OUT的过充在很短时间内降到设定值。
进一步地，当输出端基准电压VREF_OUT建立完成后，比较器翻转，提供给运算放大器EA一个使能信号VREF_OK；所述使能信号VREF_OK控制运算放大器EA关闭，以免造成不必要的功耗浪费。
同时，在运算放大器EA的正向输入端和负向输入端之间通过电阻R相连；所述电阻R存在两个作用：1)从理论的角度将，保证运算放大器EA的两个输入电压一致的同时不会流过大电流，以致于外接电容C与输入端基准电压VREF_INT直接连通，从而影响输入端基准电压VREF_INT；2)保证输出端基准电压VREF_OUT作为整个电压基准生成电路的输出，在给其它外接电路提供基准电压时，如果输出端存在有轻微的漏电情况下，可以通过电阻R由输入端基准电压VREF_INT提供给输出端基准电压VREF_OUT小的电流，从而保证输出端基准电压VREF_OUT的稳定。
进一步地，如果输出端存在有比较大的漏电情况下，通过电阻R由输入端基准电压VREF_INT提供给输出端基准电压VREF_OUT的电流已经不能满足需求，输出端 基准电压VREF_OUT会不断下降。因此，在本发明实施例中，可以进一步选用如图3所示的比较器，所述比较器为迟滞比较器。如此，由于该比较器带半边迟滞功能，只有在输出端基准电压VREF_OUT下降时才会产生迟滞效应，即输出端基准电压VREF_OUT比输入端基准电压VREF_INT小到一定程度时，迟滞比较器才会翻转。输出端基准电压VREF_OUT的上升过程翻转域值仍等于输入端基准电压VREF_INT。当输出端基准电压VREF_OUT下降到一定程度时，迟滞比较器会再次翻转，从而再次打开运算放大器EA，能够通过MP管重新对外接电容C充电，直到输出端基准电压VREF_OUT重新达到输入端基准电压VREF_INT的值。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
如上所述，本发明实施例提供的一种电路启动方法、控制电路及电压基准电路具有以下有益效果：通过运放电路中的运算放大器和外接电容建立输入端基准电压和输出端基准电压；当输入端基准电压和输出端基准电压一致时，比较控制电路执行翻转操作，并输出使能信号至运算放大器，以关闭运算放大器，进而能够在满足高精度和低功耗的指标要求的基础上，实现电路的快速启动。

Claims (10)

  1. 一种控制电路，包括：运放电路和比较控制电路；
    所述运放电路，配置为通过运算放大器和外接电容建立输入端基准电压和输出端基准电压；
    所述比较控制电路，配置为当所述输入端基准电压和输出端基准电压一致时，执行翻转操作，并输出使能信号至所述运算放大器，以关闭所述运算放大器。
  2. 根据权利要求1所述的控制电路，其中，所述比较控制电路为比较器；
    所述运放电路的输入端基准电压和输出端基准电压共同作为所述比较器的输入，所述比较器的输出为使能信号。
  3. 根据权利要求2所述的控制电路，其中，所述比较器为带下降迟滞的比较器。
  4. 根据权利要求1至3中任一项所述的控制电路，其中，所述运放电路包括：电源、运算放大器、晶体管、外接电容、偏置电流源及电阻；其中，
    所述晶体管为PMOS管或NMOS管。
  5. 根据权利要求4所述的控制电路，其中，在所述运放电路中，当所述晶体管为PMOS管时，
    所述电源与运算放大器的电源输入端和PMOS管的漏极相连；所述运算放大器的输出端与PMOS管的栅极相连；所述PPMOS管的源极分别与外接电容的一端和偏置电流源的正向端相连；所述外接电容的另一端和偏置电流源的负向端均接地；所述输入端基准电压作为运算放大器的正向输入；所述PMOS管的源极电压为输出端基准电压，并将所述输出端基准电压作为运算放大器的负向输入；所述运算放大器的正向输入端和负向输入端之间通过电阻相连。
  6. 一种电路启动方法，所述方法包括：
    通过运放电路中的运算放大器和外接电容建立输入端基准电压和输出端基准电压；当所述输入端基准电压和输出端基准电压一致时，比较控制电路执行翻转操作，并输出使能信号至所述运算放大器，以关闭所述运算放大器。
  7. 一种电压基准电路，包括：电压基准生成电路和控制电压基准生成电路的控制电路；所述控制电路包括运放电路和比较控制电路；
    所述运放电路，配置为通过运算放大器和外接电容建立输入端基准电压和输出端基准电压；
    所述比较控制电路，配置为当所述输入端基准电压和输出端基准电压一致时，执行翻转操作，并输出使能信号至所述运算放大器，以关闭所述运算放大器。
  8. 根据权利要求7所述的电压基准电路，其中，所述比较控制电路为比较器；
    所述运放电路的输入端基准电压和输出端基准电压共同作为所述比较器的输入，所述比较器的输出为使能信号；其中，所述比较器为带下降迟滞的比较器。
  9. 根据权利要求7或8所述的电压基准电路，其中，所述运放电路包括：电源、运算放大器、晶体管、外接电容、偏置电流源及电阻；其中，
    所述晶体管为PMOS管或NMOS管。
  10. 根据权利要求9所述的电压基准电路，其中，在所述运放电路中，当所述晶体管为PMOS管时，
    所述电源与运算放大器的电源输入端和PMOS管的漏极相连；所述运算放大器的输出端与PMOS管的栅极相连；所述PMOS管的源极分别与外接电容的一端和偏置电流源的正向端相连；所述外接电容的另一端和偏置电流源的负向端均接地；所述输入端基准电压作为运算放大器的正向输入；所述PMOS管的源极电压为输出端基准电压，并将所述输出端基准电压作为运算放大器的负向输入；所述运算放大器的正向输入端和负向输入端之间通过电阻相连。
PCT/CN2015/071145 2014-08-15 2015-01-20 电路启动方法、控制电路及电压基准电路 WO2015154566A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102609023A (zh) * 2012-03-12 2012-07-25 北京经纬恒润科技有限公司 一种内建模拟电源电路
WO2013147806A1 (en) * 2012-03-29 2013-10-03 Integrated Device Technology, Inc. Apparatuses and methods responsive to output variations in voltage regulators
WO2014038785A1 (ko) * 2012-09-05 2014-03-13 주식회사 실리콘웍스 제어된 스타트 업이 가능한 로우 드랍아웃 회로 및 그 제어 방법
CN203520222U (zh) * 2013-11-12 2014-04-02 北京经纬恒润科技有限公司 一种低压差线性稳压器
CN103885517A (zh) * 2012-12-20 2014-06-25 北京兆易创新科技股份有限公司 低压差稳压器和低压差稳压器输出电压的控制方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784652B1 (en) * 2003-02-25 2004-08-31 National Semiconductor Corporation Startup circuit for bandgap voltage reference generator
JP2005117784A (ja) * 2003-10-08 2005-04-28 Rohm Co Ltd スイッチング電源装置
JP2010146526A (ja) * 2008-12-22 2010-07-01 Panasonic Corp 基準電圧発生回路
CN101673938B (zh) * 2009-09-29 2012-06-27 杭州士兰微电子股份有限公司 输出短路的软恢复控制电路及其在dc-dc转换器中的应用
CN102147630A (zh) 2010-12-13 2011-08-10 北京大学 控制器及具有该控制器的驱动电路
CN103036538B (zh) * 2012-12-06 2016-05-18 国民技术股份有限公司 校准比较器失调电压的电路及其方法
CN103647519B (zh) 2013-12-17 2016-08-17 电子科技大学 一种运算放大器的输入级
CN103905006B (zh) * 2014-03-28 2017-10-24 深圳创维－Rgb电子有限公司 一种具有占空比限制功能的d类功放芯片及其装置
CN103973237B (zh) * 2014-04-30 2017-02-22 广州钧衡微电子科技有限公司 一种功率放大器的分阶段过压保护电路
WO2016069802A1 (en) * 2014-10-28 2016-05-06 Advanced Charging Technologies, LLC Electrical circuit for delivering power to consumer electronic devices
US9405309B2 (en) * 2014-11-29 2016-08-02 Infineon Technologies Ag Dual mode low-dropout linear regulator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102609023A (zh) * 2012-03-12 2012-07-25 北京经纬恒润科技有限公司 一种内建模拟电源电路
WO2013147806A1 (en) * 2012-03-29 2013-10-03 Integrated Device Technology, Inc. Apparatuses and methods responsive to output variations in voltage regulators
WO2014038785A1 (ko) * 2012-09-05 2014-03-13 주식회사 실리콘웍스 제어된 스타트 업이 가능한 로우 드랍아웃 회로 및 그 제어 방법
CN103885517A (zh) * 2012-12-20 2014-06-25 北京兆易创新科技股份有限公司 低压差稳压器和低压差稳压器输出电压的控制方法
CN203520222U (zh) * 2013-11-12 2014-04-02 北京经纬恒润科技有限公司 一种低压差线性稳压器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3182242A4 *

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EP3182242A4 (en) 2017-09-06
CN105373178B (zh) 2018-02-02

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