WO2015149474A1 - 模拟电压源电路及显示装置 - Google Patents

模拟电压源电路及显示装置 Download PDF

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Publication number
WO2015149474A1
WO2015149474A1 PCT/CN2014/085334 CN2014085334W WO2015149474A1 WO 2015149474 A1 WO2015149474 A1 WO 2015149474A1 CN 2014085334 W CN2014085334 W CN 2014085334W WO 2015149474 A1 WO2015149474 A1 WO 2015149474A1
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WO
WIPO (PCT)
Prior art keywords
voltage
circuit
resistor
output
voltage adjustment
Prior art date
Application number
PCT/CN2014/085334
Other languages
English (en)
French (fr)
Inventor
刘晓鹏
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/439,875 priority Critical patent/US9711101B2/en
Publication of WO2015149474A1 publication Critical patent/WO2015149474A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0045—Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates to an analog voltage source circuit and display device. Background technique
  • the power consumption of known technology LCD panels has always been a key factor in product design, system verification, and customer use. Reducing power consumption has also been an important part of product design.
  • Known technology In the display, notebook, PAD or mobile phone use, after the device is in standby for a certain period of time, the system reduces the brightness of the panel by reducing the brightness of the backlight or other means, in order to save power.
  • the known technology uses the single-chip integrated memory to support the PSR (Plane-Self-Refresh) function when using the LCD panel timing control chip of the eDP1.3 interface standard. The system can enter the PSR mode when displaying a still picture.
  • the timing control chip takes over the graphics processor through the built-in buffer memory to reduce the load of the graphics processor, so the graphics processor and the display interface can enter a low power state to reduce the overall power consumption of the system. Save the new still picture update to the buffer memory through the graphics processor, or jump out of the PSR mode to display the changing image picture, effectively reducing system power consumption and extending the notebook battery life.
  • the analog voltage source AVDD used in the liquid crystal panel is usually controlled by a converter between DC and DC, that is, the DC-DC conversion circuit outputs a certain frequency of AC AC signal to generate the required AVDD.
  • Voltage, and feedback output voltage to the duty cycle control circuit through the output voltage sampling circuit the duty cycle control circuit controls the output voltage of the DC-DC conversion circuit according to the feedback of the output voltage sampling circuit to ensure the output of the AVDD output terminal The voltage is maintained at a constant value.
  • the voltage output from the AVDD output required by the known liquid crystal panel is fixed.
  • the system indicating panel reduces the backlight or performs the PSR output, since the voltage value of AVDD remains unchanged, Not conducive to reducing the power consumption of the system.
  • Embodiments of the present disclosure provide an analog voltage source circuit and a display device for adjusting a voltage outputted by an analog voltage source of a liquid crystal panel, thereby reducing power consumption of the liquid crystal panel.
  • An embodiment of the present disclosure provides an analog voltage source circuit, the circuit comprising: a voltage input a terminal, a DC-DC conversion circuit, a voltage output terminal, a duty ratio control circuit, and an output voltage sampling circuit, wherein the output voltage sampling circuit is configured to feed back the magnitude of the output voltage to the duty cycle control circuit,
  • the duty control circuit is configured to control the magnitude of the output voltage of the DC-DC conversion circuit according to the feedback of the output voltage sampling circuit, wherein the circuit further includes: a voltage adjustment circuit, the voltage adjustment circuit The input end is used for inputting a voltage adjustment signal, and the output end of the voltage regulating circuit is connected to the output voltage sampling circuit, and the voltage regulating circuit controls to raise or lower the output voltage sampling circuit according to the voltage adjustment signal.
  • the feedback further increases or decreases the voltage output by the voltage output.
  • An analog voltage source circuit provided by an embodiment of the present disclosure, wherein the circuit further includes: a voltage regulating circuit, an input end of the voltage regulating circuit is configured to input a voltage adjusting signal, an output end of the voltage regulating circuit, and the output voltage Connected to the sampling circuit, the voltage regulating circuit controls to increase or decrease the feedback of the output voltage sampling circuit according to the voltage adjustment signal, thereby increasing or decreasing the voltage outputted by the voltage output terminal.
  • the analog voltage source circuit provided by the disclosed embodiment can adjust the voltage of the analog voltage source output of the liquid crystal panel when receiving the CON signal of the system indicating panel to reduce the backlight or perform the PSR output, thereby reducing the power consumption of the liquid crystal panel.
  • the output voltage sampling circuit includes a first resistor and a second resistor connected in series between the voltage output terminal and a ground point, and the first resistor is connected to the voltage output end, wherein the a second resistor connected to the ground point, the duty cycle control circuit extracting voltage feedback from a connection point between the first resistor and the second resistor, the voltage regulating circuit having two outputs, respectively The two ends of the first resistor are connected.
  • the output voltage sampling circuit includes a first resistor and a second resistor connected in series between the voltage output terminal and the grounding point, the first resistor is connected to the voltage output terminal, and the second resistor and the grounding point Connected, the duty cycle control circuit extracts voltage feedback from a connection point between the first resistor and the second resistor, the voltage regulating circuit has two output ends, respectively, and two of the first resistors Connected at the end, it is convenient and simple in the actual circuit design.
  • the voltage regulating circuit includes a third resistor and a switching device, the gate of the switching device is input with the voltage adjustment signal, and the other two poles are respectively coupled to the first end of the first resistor and the The first end of the third resistor is connected; the second end of the third resistor is connected to the second end of the first resistor.
  • the voltage regulating circuit includes a third resistor and a switching device, which is convenient and simple in actual circuit design.
  • the switching device is a transistor, a gate of the transistor is connected to the voltage regulating signal input end, a source is connected to a first end of the third resistor, and a drain and the first The first ends of the resistors are connected.
  • the switching device is a transistor, it is simple and easy to implement in actual circuit design.
  • the output voltage sampling circuit includes a first resistor and a second resistor connected in series between the voltage output terminal and the voltage regulating circuit, and the first resistor is connected to the voltage output terminal.
  • the second resistor is connected to the voltage regulating circuit, and the duty control circuit extracts voltage feedback from a connection point between the first resistor and the second resistor, the voltage regulating circuit has two outputs The terminals are respectively connected to one end of the second resistor close to the grounding point and the grounding point.
  • the output voltage sampling circuit includes a first resistor and a second resistor connected in series between the voltage output terminal and the voltage regulating circuit, the first resistor is connected to the voltage output terminal, and the second resistor Connected to the voltage regulating circuit, the duty cycle control circuit extracts voltage feedback from a connection point between the first resistor and the second resistor, the voltage regulating circuit has two output ends, respectively The end of the second resistor close to the grounding point and the grounding point are connected, which is convenient and simple in the actual circuit design.
  • the voltage regulating circuit includes a third resistor and a switching device, the gate of the switching device is input with the voltage adjusting signal, and the other two poles are respectively opposite to an end of the second resistor that is close to a ground point.
  • the grounding point is connected; the first end of the third resistor is connected to one end of the second resistor close to the grounding point, and the second end of the third resistor is connected to the grounding point.
  • the voltage regulating circuit includes a third resistor and a switching device, which is convenient and simple in actual circuit design.
  • the switching device is a transistor, a gate of the transistor is connected to the voltage adjustment signal input end, a source is connected to a first end of the third resistor, and a drain and the ground point Connected.
  • the switching device is a transistor, it is simple and easy to implement in actual circuit design.
  • the transistor when the transistor is an N-type thin film transistor, if the voltage adjustment signal is a low level signal, the N-type thin film transistor is turned off, and if the voltage adjustment signal is a high level signal, The N-type thin film transistor is turned on.
  • the transistor when the transistor is an N-type thin film transistor, if the voltage adjustment signal is a low level signal, the N-type thin film transistor is turned off, and if the voltage adjustment signal is a high level signal, The N-type thin film transistor is turned on, which is convenient and simple in the actual circuit.
  • the transistor when the transistor is a P-type thin film transistor, if the voltage adjustment signal is a low level signal, the P-type thin film transistor is turned on, and if the voltage adjustment signal is a high level signal, The P-type thin film transistor is turned off.
  • the transistor when the transistor is a P-type thin film transistor, if the voltage adjustment signal is a low level signal, the P-type thin film transistor is turned on, and if the voltage adjustment signal is a high level signal, the P-type The thin film transistor is turned off, which is convenient and simple in the actual circuit.
  • the voltage regulation circuit is integrated inside the duty cycle control circuit. In this way, the voltage regulating circuit is integrated inside the duty cycle control circuit, which is convenient and simple in practical applications.
  • Embodiments of the present disclosure also provide a display device including the analog voltage source circuit described above.
  • the display device provided by the embodiment of the present disclosure since the device includes the above-described analog voltage source circuit, the display device provided by the embodiment of the present disclosure can reduce power consumption.
  • FIG. 1 is a schematic structural diagram of an analog voltage source circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another analog voltage source circuit according to an embodiment of the present disclosure
  • Schematic diagram of three analog voltage source circuits Figure 4 (a), 4 (b) and 4 (c) are timing diagrams of the voltage regulation signal, feedback voltage VFB and output voltage of the analog voltage source circuit of Figure 3, respectively.
  • Embodiments of the present disclosure provide an analog voltage source circuit and a display device for adjusting a voltage outputted by an analog voltage source of a liquid crystal panel, thereby reducing power consumption of the liquid crystal panel.
  • an exemplary embodiment of the present disclosure provides an analog voltage source circuit, the circuit including: a voltage input terminal Vin, a DC-DC conversion circuit 10, a voltage output terminal AVDD, and a duty ratio control circuit 11 And an output voltage sampling circuit 12 for feeding back the magnitude of the output voltage to the duty control circuit 11, the duty control circuit 11 for using the output voltage
  • the magnitude of the output voltage of the DC-DC conversion circuit 10 is controlled by the feedback of the sampling circuit 12, wherein the circuit further includes: a voltage adjustment circuit 13, the voltage adjustment An input end of the circuit 13 is used for inputting a voltage adjustment signal, and an output end of the voltage adjustment circuit 13 is connected to the output voltage sampling circuit 12, and the voltage adjustment circuit 13 controls to raise or lower the voltage according to the voltage adjustment signal.
  • the feedback of the output voltage sampling circuit 12 further increases or decreases the voltage outputted by the voltage output terminal AVDD.
  • the voltage output from the voltage output terminal AVDD is lowered, and the voltage output from the voltage output terminal AVDD is increased from the energy-saving operating state to the normal operating state.
  • the DC-DC conversion circuit 10, the duty cycle control circuit 11, and the output voltage sampling circuit 12 in an analog voltage source circuit provided by an exemplary embodiment of the present disclosure are stable for the current generation.
  • a circuit of AVDD voltage wherein the DC-DC conversion circuit 10 includes an inductor coil, a diode D and a capacitor C, the inductor coil, the diode D and the capacitor C constitute a main loop of the DC-DC converter circuit 10, and the reference in the duty ratio control circuit 11
  • the pin LX is a pin of a pulse width modulation (PWM) signal, the PWM signal outputted by the pin LX is coupled with the inductor L, and the DC-DC conversion circuit is controlled according to the feedback of the output voltage sampling circuit 12.
  • PWM pulse width modulation
  • the magnitude of the output voltage of 10; the pin FB in the duty ratio control circuit 11 is a pin of the voltage sampling circuit, and the output voltage sampling circuit 12 is used to feed back the magnitude of the output voltage to the duty control circuit 11;
  • the ratio control circuit 11 is grounded via the pin PGND.
  • the DC-DC conversion circuit 10, the duty ratio control circuit 11, and the output voltage sampling circuit 12 are the same as the known techniques, and therefore the operation principle thereof is also the same as the known technique, and will not be described herein.
  • An input terminal of the voltage regulating circuit 13 in the exemplary embodiment of the present disclosure is connected to an input terminal CON for inputting a voltage adjustment signal, and an output terminal of the voltage regulating circuit 13 is connected to the output voltage sampling circuit 12, and the voltage adjusting circuit 13 is based on The voltage adjustment signal controls to increase or decrease the feedback of the output voltage sampling circuit 12, thereby increasing or decreasing the voltage outputted by the voltage output terminal AVDD.
  • the output voltage sampling circuit 12 includes a first resistor R1 and a second resistor R2 connected in series between the voltage output terminal AVDD and the ground point, the first resistor 1 is connected to the voltage output terminal AVDD, and the second resistor R2 is connected to the ground point.
  • the duty ratio control circuit 11 extracts voltage feedback from a connection point between the first resistor R1 and the second resistor R2, and the voltage adjustment circuit 13 has two output terminals respectively connected to both ends of the first resistor R1.
  • the voltage regulating circuit 13 in the exemplary embodiment of the present disclosure includes a third resistor R3 and a switching device Q, the control electrode of the switching device Q is connected to the voltage regulating signal input terminal CON, and the other two poles respectively
  • the first end N1 of the first resistor R1 is connected to the first end N2 of the third resistor R3; the third resistor
  • the second terminal N3 of the third resistor is connected to the second terminal N4 of the first resistor.
  • the switching device Q in the exemplary embodiment of the present disclosure is a transistor Q, and the gate of the transistor Q is connected to the voltage regulating signal input terminal CON.
  • the source is connected to the first terminal N2 of the third resistor R3, and the drain is connected to the first terminal N1 of the first resistor R1.
  • the transistor Q is an N-type thin film transistor, if the voltage adjustment signal is a low level signal, the N-type thin film transistor is turned off, and if the voltage adjustment signal is a high level signal, the N-type thin film transistor is turned on.
  • the transistor Q is a P-type thin film transistor
  • the P-type thin film transistor is turned on, and if the voltage adjustment signal is a high level signal, the P-type The thin film transistor is turned off.
  • the transistor Q in the exemplary embodiment of the present disclosure is described by taking an N-type thin film transistor as an example, and the voltage adjustment signal for inputting the input terminal CON of the input voltage adjustment signal is from the system end of the liquid crystal panel, an exemplary embodiment of the present disclosure
  • the voltage adjustment signal input by the voltage adjustment signal input terminal CON is a low level signal or a high level signal.
  • the transistor Q is turned off, and the voltage regulating circuit 13 does not operate.
  • the transistor Q When the voltage adjustment signal is a high level signal, the transistor Q is turned on, and the voltage regulating circuit 13 starts to operate. At this time, the third resistor R3 is connected in parallel with the first resistor R1, and then connected in series with the second resistor R2. Exemplary embodiments of the present disclosure
  • V AVDD (l + (R ⁇ I /R3)/R2) * V FB , where: M ⁇ R3 represents the resistance value after the first resistor R1 and the third resistor R3 are connected in parallel.
  • the pin FB of the duty control circuit 11 in FIG. 1 is a pin of the voltage sampling circuit for receiving the voltage VFB fed back across the second resistor R2, if the received feedback voltage VFB and the duty control circuit 11 are received.
  • the preset feedback voltage reference voltage is different, the received feedback voltage VFB is adjusted by the duty ratio control circuit 11 so that the value of the feedback voltage V FB remains unchanged.
  • An exemplary analog voltage supply circuit provided by an exemplary embodiment of the present disclosure can adjust the voltage value outputted by the AVDD output terminal in real time, for example, a third resistor in the voltage regulating circuit 13 of the exemplary embodiment of the present disclosure may be used.
  • the value of the resistance of R3 can be set to 50 ⁇ ⁇ - 100 ⁇ ⁇ , and an analog voltage source circuit provided by an exemplary embodiment of the present disclosure can be adjusted for input voltage through the liquid crystal panel system end.
  • the adjustment will cause the analog resistance value across the transistor Q to be different when the transistor Q connected thereto is turned on, and then R1 ⁇ R3 and R2
  • the ratios are different, resulting in different voltage values at the AVDD output, and the specific value of the voltage drop output to the AVDD output in the exemplary embodiment of the present disclosure is adjusted according to the actual needs of the system or the liquid crystal panel.
  • the output voltage sampling circuit 12 includes a first resistor R1 connected in series between the voltage output terminal AVDD and the voltage regulating circuit 13 and The second resistor R2, the first resistor R1 is connected to the voltage output terminal AVDD, the second resistor R2 is connected to the voltage regulating circuit 13, and the duty ratio control circuit 11 extracts the voltage from the connection point between the first resistor R1 and the second resistor R2.
  • the voltage regulating circuit 13 has two output terminals respectively connected to one end of the second resistor R2 close to the grounding point and the grounding point.
  • the voltage regulating circuit 13 in the exemplary embodiment of the present disclosure includes a third resistor R3 and a switching device Q, the control electrode of the switching device Q is connected to the voltage regulating signal input terminal CON, and the other two poles respectively
  • An end N5 of the second resistor R2 is connected to the grounding point;
  • the first end N6 of the third resistor R3 is connected to an end N5 of the second resistor R2 that is close to the grounding point, and the third resistor
  • the second terminal N7 of R3 is connected to the ground point
  • the switching device Q in the exemplary embodiment of the present disclosure is a transistor Q, the gate of the transistor Q is connected to the voltage regulating signal input terminal CON, the source and the The first terminal N6 of the third resistor R3 is connected, and the drain is connected to the ground point.
  • the transistor Q When the transistor Q is an N-type thin film transistor, if the voltage adjustment signal is a low level signal, the N-type thin film transistor is turned off, and if the voltage adjustment signal is a high level signal, the N-type thin film transistor is turned on.
  • the transistor Q When the transistor Q is a P-type thin film transistor, if the voltage adjustment signal is a low level signal, the P-type thin film transistor is turned on, and if the voltage adjustment signal is a high level signal, the P-type The thin film transistor is turned off.
  • the transistor Q in the exemplary embodiment of the present disclosure is described by taking an N-type thin film transistor as an example, and the voltage adjustment signal for inputting the input terminal CON of the input voltage adjustment signal is from the system end of the liquid crystal panel, an exemplary embodiment of the present disclosure
  • the voltage adjustment signal input by the voltage adjustment signal input terminal CON is a low level signal or a high level signal.
  • the transistor Q is turned on.
  • the voltage adjustment signal is a low level signal, the transistor Q is turned off.
  • the third resistor R3 is connected in series with the second resistor R2, and then connected in series with the first resistor R1.
  • the AVDD output is obtained after the voltage adjustment circuit 13 of the exemplary embodiment of the present disclosure is adjusted.
  • the voltage value at the output of the terminal is smaller than the voltage output at the AVDD output of the known technique.
  • An exemplary analog voltage supply circuit provided by an exemplary embodiment of the present disclosure can adjust the voltage value outputted by the AVDD output terminal in real time, for example, a third resistor in the voltage regulating circuit 13 of the exemplary embodiment of the present disclosure.
  • the value of R3 can be set from 50 ⁇ to 100 ⁇ .
  • the specific value of the voltage drop output to the AVDD output terminal in the exemplary embodiment of the present disclosure is adjusted according to the actual needs of the system or the liquid crystal panel.
  • the voltage adjustment circuit 13 of the exemplary embodiment of the present disclosure is performed according to the requirements of the system and the image displayed by the customer on the liquid crystal panel. Adjustment.
  • an exemplary embodiment of the present disclosure also provides another analog voltage source circuit.
  • the voltage regulating circuit 13 is disposed inside the duty control circuit 11, wherein the voltage regulating circuit 13 is internally provided with a receiving and recognizing module 20 for receiving and identifying a voltage regulating signal that is transmitted to the voltage regulating circuit 13 in real time for input voltage regulation.
  • the input terminal CON of the signal is input to the reception recognition module 20 in the voltage adjustment circuit 13 through the pin of the duty control circuit 11, and the input terminal CON for inputting the voltage adjustment signal is input to the voltage adjustment in the exemplary embodiment of the present disclosure.
  • the timing diagram of the voltage adjustment signal in the circuit 13 is as shown in FIG.
  • the amplitude, duty cycle or frequency of the voltage adjustment signal is converted and converted by the reception recognition module 20 inside the voltage adjustment circuit 13 to control the duty.
  • the reference voltage value of the duty ratio control circuit 11 is changed by the adjustment signal of the reference voltage of the control circuit 11, and the feedback adjustment module 21 in the voltage adjustment circuit 13 adjusts the received feedback voltage VFB after the reference voltage value is changed, so that The adjusted feedback voltage VFB and the reference adjusted by the reception recognition module 20 in the exemplary embodiment of the present disclosure
  • the same pressure, 4 (b) only the above description, the calculation of the voltage data shown Gen AVDD output terminal of the timing diagram of the feedback voltage VFB variations in FIG.
  • V AmD (l + m / R2 V FB , the voltage output from the AVDD output will also change due to the change of VFB.
  • the timing diagram of the voltage output from the AVDD output is shown in Figure 4(c).

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Abstract

一种模拟电压源电路及显示装置，所述电路包括：电压输入端、DC-DC变换电路、电压输出端、占空比控制电路和输出电压采样电路，输出电压采样电路用于向占空比控制电路反馈输出电压的大小，占空比控制电路用于根据输出电压采样电路的反馈而控制DC-DC变换电路的输出电压的大小，所述电路还包括：电压调节电路，电压调节电路的输入端用于输入电压调节信号，电压调节电路的输出端与输出电压采样电路相连，电压调节电路根据电压调节信号来控制升高或降低输出电压采样电路的反馈，进而使电压输出端输出的电压升高或降低。该模拟电压源电路及显示装置能够调节液晶面板模拟电压源输出的电压，进而降低液晶面板的功耗。

Description

模拟电压源电路及显示装置 技术领域
本公开涉及一种模拟电压源电路及显示装置。 背景技术
已知的技术的液晶面板的功耗一直是产品设计、 ***验证及客户使用比 较关注的要素， 降低功耗也一直是产品设计中比较重要的环节。 已知的技术 在显示器、 笔记本、 PAD或手机使用中， 在设备待机一定时间后， ***通过 降低背光亮度或其它方式实现面板的亮度降低， 以期达到节省功耗的目的。 已知的技术在使用 eDP1.3接口标准的液晶面板时序控制芯片时，釆用单芯片 整合式内存支持 PSR ( Panel-Self-Refresh )功能， ***在显示静止画面时可 进入 PSR模式， 此时， 时序控制芯片通过内建的緩冲存储器将接管绘图处理 器刷新画面， 降低绘图处理器的负载， 于是绘图处理器与显示接口得以进入 低功耗状态来降低***整体的功耗， ***也可通过绘图处理器将新的静止画 面更新储存到緩冲存储器中， 或者跳出 PSR模式来显示不断改变的影像画 面， 有效的降低***功耗并延长笔记型计算机电池使用时间。
在已知的技术的液晶面板设计中，液晶面板使用的模拟电压源 AVDD通 常是由直流与直流之间的转换器， 即 DC-DC变换电路输出一定频率的交流 AC信号控制生成所需的 AVDD电压， 并通过输出电压釆样电路向占空比控 制电路反馈输出电压的大小， 占空比控制电路根据输出电压釆样电路的反馈 而控制 DC-DC变换电路的输出电压， 保证 AVDD输出端输出的电压维持在 一个恒定的值。
综上所述， 已知的技术的液晶面板所需的 AVDD输出端输出的电压是固 定不变的， 在接收到***指示面板降低背光或进行 PSR输出时， 由于 AVDD 的电压值保持不变， 不利于降低***的功耗。 发明内容
本公开的实施例提供了一种模拟电压源电路及显示装置， 用以调节液晶 面板模拟电压源输出的电压， 进而降低液晶面板的功耗。
本公开的实施例提供的一种模拟电压源电路， 所述电路包括： 电压输入 端、 DC-DC变换电路、 电压输出端、 占空比控制电路和输出电压釆样电路， 所述输出电压釆样电路用于向所述占空比控制电路反馈所述输出电压的大 小， 所述占空比控制电路用于根据所述输出电压釆样电路的反馈而控制所述 DC-DC变换电路的输出电压的大小，其中，所述电路还包括： 电压调节电路， 所述电压调节电路的输入端用于输入电压调节信号， 电压调节电路的输出端 与所述输出电压釆样电路相连， 所述电压调节电路根据所述电压调节信号来 控制升高或降低所述输出电压釆样电路的反馈， 进而使所述电压输出端输出 的电压升高或降低。
由本公开的实施例提供的一种模拟电压源电路， 由于该电路还包括： 电 压调节电路， 所述电压调节电路的输入端用于输入电压调节信号， 电压调节 电路的输出端与所述输出电压釆样电路相连， 所述电压调节电路根据所述电 压调节信号来控制升高或降低所述输出电压釆样电路的反馈， 进而使所述电 压输出端输出的电压升高或降低， 因此， 本公开的实施例提供的模拟电压源 电路， 在接收到***指示面板降低背光或进行 PSR输出的 CON信号时， 能 够调节液晶面板模拟电压源输出的电压， 进而降低液晶面板的功耗。
在一些实施例中， 所述输出电压釆样电路包括串联连接于所述电压输出 端与接地点之间的第一电阻和第二电阻， 所述第一电阻与电压输出端相连， 所述第二电阻与接地点相连， 所述占空比控制电路从所述第一电阻与所述第 二电阻之间的连接点提取电压反馈， 所述电压调节电路具有两个输出端， 分 别与所述第一电阻的两端相连。
这样， 由于输出电压釆样电路包括串联连接于所述电压输出端与接地点 之间的第一电阻和第二电阻， 所述第一电阻与电压输出端相连， 所述第二电 阻与接地点相连， 所述占空比控制电路从所述第一电阻与所述第二电阻之间 的连接点提取电压反馈， 所述电压调节电路具有两个输出端， 分别与所述第 一电阻的两端相连， 在实际电路设计中方便、 简单。
在一些实施例中， 所述电压调节电路包括第三电阻和开关器件， 所述开 关器件的控制极输入有所述电压调节信号， 另两极分别与所述第一电阻的第 一端和所述第三电阻的第一端相连； 所述第三电阻的第二端与所述第一电阻 的第二端相连。
这样， 电压调节电路包括第三电阻和开关器件，在实际电路设计中方便、 简单。 在一些实施例中， 所述开关器件为晶体管， 所述晶体管的栅极与所述电 压调节信号输入端相连， 源极与所述第三电阻的第一端相连， 漏极与所述第 一电阻的第一端相连。
这样， 当开关器件为晶体管时， 在实际电路设计中简单、 易行。
在一些实施例中， 所述输出电压釆样电路包括串联连接于所述电压输出 端与所述电压调节电路之间的第一电阻和第二电阻， 所述第一电阻与电压输 出端相连， 所述第二电阻与所述电压调节电路相连， 所述占空比控制电路从 所述第一电阻与所述第二电阻之间的连接点提取电压反馈， 所述电压调节电 路具有两个输出端， 分别与所述第二电阻的靠近接地点的一端以及接地点相 连。
这样， 由于输出电压釆样电路包括串联连接于所述电压输出端与所述电 压调节电路之间的第一电阻和第二电阻， 所述第一电阻与电压输出端相连， 所述第二电阻与所述电压调节电路相连， 所述占空比控制电路从所述第一电 阻与所述第二电阻之间的连接点提取电压反馈， 所述电压调节电路具有两个 输出端， 分别与所述第二电阻的靠近接地点的一端以及接地点相连， 在实际 电路设计中方便、 简单易行。
在一些实施例中， 所述电压调节电路包括第三电阻和开关器件， 所述开 关器件的控制极输入有所述电压调节信号， 另两极分别与所述第二电阻的靠 近接地点的一端和所述接地点相连； 所述第三电阻的第一端与所述第二电阻 的靠近接地点的一端相连， 所述第三电阻的第二端与所述接地点相连。
这样， 电压调节电路包括第三电阻和开关器件，在实际电路设计中方便、 简单。
在一些实施例中， 所述开关器件为晶体管， 所述晶体管的栅极与所述电 压调节信号输入端相连， 源极与所述第三电阻的第一端相连， 漏极与所述接 地点相连。
这样， 当开关器件为晶体管时， 在实际电路设计中简单、 易行。
在一些实施例中， 当所述晶体管为 N型薄膜晶体管时， 若所述电压调节 信号为低电平信号， 所述 N型薄膜晶体管关闭， 若所述电压调节信号为高电 平信号， 所述 N型薄膜晶体管导通。
这样， 当所述晶体管为 N型薄膜晶体管时， 若所述电压调节信号为低电 平信号， 所述 N型薄膜晶体管关闭， 若所述电压调节信号为高电平信号， 所 述 N型薄膜晶体管导通， 在实际电路中方便、 简单。
在一些实施例中， 当所述晶体管为 P型薄膜晶体管时， 若所述电压调节 信号为低电平信号， 所述 P型薄膜晶体管导通， 若所述电压调节信号为高电 平信号， 所述 P型薄膜晶体管关闭。
这样， 当所述晶体管为 P型薄膜晶体管时， 若所述电压调节信号为低电 平信号， 所述 P型薄膜晶体管导通， 若所述电压调节信号为高电平信号， 所 述 P型薄膜晶体管关闭， 在实际电路中方便、 简单。
在一些实施例中， 所述电压调节电路集成于所述占空比控制电路内部。 这样， 将电压调节电路集成于所述占空比控制电路内部， 在实际应用中 方便、 简单。
本公开的实施例还提供了一种显示装置， 所述装置包括上述的模拟电压 源电路。
由本公开的实施例提供的显示装置， 由于该装置包括上述的模拟电压源 电路， 因此， 本公开的实施例提供的显示装置能够降低功耗。 附图说明
图 1为本公开的实施例提供的一种模拟电压源电路结构示意图； 图 2为本公开的实施例提供的另一种模拟电压源电路结构示意图； 图 3为本公开的实施例提供的第三种模拟电压源电路结构示意图； 图 4 ( a )、 4 ( b )和 4 ( c )分别为图 3的模拟电压源电路的电压调节信 号、 反馈电压 VFB和输出电压的时序图。 具体实施方式
本公开的实施例提供了一种模拟电压源电路及显示装置， 用以调节液晶 面板模拟电压源输出的电压， 进而降低液晶面板的功耗。
如图 1所示， 本公开的示例性实施例提供了一种模拟电压源电路， 所述 电路包括： 电压输入端 Vin、 DC-DC变换电路 10、 电压输出端 AVDD、 占空 比控制电路 11和输出电压釆样电路 12，所述输出电压釆样电路 12用于向所 述占空比控制电路 11反馈所述输出电压的大小， 所述占空比控制电路 11用 于根据所述输出电压釆样电路 12的反馈而控制所述 DC-DC变换电路 10的 输出电压的大小， 其中， 所述电路还包括： 电压调节电路 13， 所述电压调节 电路 13的输入端用于输入电压调节信号， 电压调节电路 13的输出端与所述 输出电压釆样电路 12相连， 所述电压调节电路 13根据所述电压调节信号来 控制升高或降低所述输出电压釆样电路 12 的反馈， 进而使所述电压输出端 AVDD输出的电压升高或降低。 本公开的示例性实施例中液晶面板由正常工 作状态到节能工作状态时， 电压输出端 AVDD输出的电压降低， 由节能工作 状态到正常工作状态时， 电压输出端 AVDD输出的电压升高。
下面结合附图详细介绍本公开的示例性实施例提供的模拟电压源电路由 正常工作状态到节能工作状态时， 电压输出端输出的电压降低的方法。
如图 1 所示， 本公开的示例性实施例提供的一种模拟电压源电路中的 DC-DC变换电路 10、 占空比控制电路 11 以及输出电压釆样电路 12为目前 常用的生成稳定的 AVDD电压的电路，其中 DC-DC变换电路 10包括电感线 圈 、 二极管 D和电容 C， 电感线圈 、 二极管 D和电容 C构成 DC-DC变 换电路 10的主回路，占空比控制电路 11中的引脚 LX为脉冲宽度调制（Pulse width modulation, PWM )信号的引脚， 引脚 LX输出的 PWM信号与电感线 圈 L进行耦合作用，并根据输出电压釆样电路 12的反馈而控制 DC-DC变换 电路 10的输出电压的大小； 占空比控制电路 11中的引脚 FB为电压釆样回 路的引脚， 输出电压釆样电路 12用于向占空比控制电路 11反馈输出电压的 大小； 占空比控制电路 11通过引脚 PGND接地。 DC-DC变换电路 10、 占空 比控制电路 11以及输出电压釆样电路 12与已知的技术相同， 因此其工作原 理也与已知的技术相同， 在此不予赘述。 本公开的示例性实施例中的电压调 节电路 13的输入端与用于输入电压调节信号的输入端 CON相连， 电压调节 电路 13的输出端与输出电压釆样电路 12相连，电压调节电路 13根据所述电 压调节信号来控制升高或降低所述输出电压釆样电路 12的反馈，进而使电压 输出端 AVDD输出的电压升高或降低。 输出电压釆样电路 12包括串联连接 于电压输出端 AVDD与接地点之间的第一电阻 R1和第二电阻 R2，第一电阻 1与电压输出端 AVDD相连， 第二电阻 R2与接地点相连， 占空比控制电路 11从第一电阻 R1与第二电阻 R2之间的连接点提取电压反馈， 电压调节电 路 13具有两个输出端， 分别与第一电阻 R1的两端相连。 例如， 本公开的示 例性实施例中的电压调节电路 13包括第三电阻 R3和开关器件 Q， 所述开关 器件 Q的控制极与所述电压调节信号输入端 CON相连， 另两极分别与所述 第一电阻 R1的第一端 N1和第三电阻 R3的第一端 N2相连； 所述第三电阻 3的第二端 N3与所述第一电阻的第二端 N4相连， 本公开的示例性实施例 中的开关器件 Q为晶体管 Q， 晶体管 Q的栅极与所述电压调节信号输入端 CON相连， 源极与所述第三电阻 R3的第一端 N2相连， 漏极与所述第一电 阻 R1的第一端 N1相连。 当晶体管 Q为 N型薄膜晶体管时， 若所述电压调 节信号为低电平信号， 所述 N型薄膜晶体管关闭， 若所述电压调节信号为高 电平信号， 所述 N型薄膜晶体管导通； 当所述晶体管 Q为 P型薄膜晶体管 时， 若所述电压调节信号为低电平信号， 所述 P型薄膜晶体管导通， 若所述 电压调节信号为高电平信号， 所述 P型薄膜晶体管关闭。
本公开的示例性实施例中的晶体管 Q以 N型薄膜晶体管为例进行介绍， 用于输入电压调节信号的输入端 CON输入的电压调节信号来自液晶面板的 ***端， 本公开的示例性实施例中的电压调节信号输入端 CON输入的电压 调节信号为低电平信号或高电平信号， 当电压调节信号为低电平信号时， 晶 体管 Q关闭， 电压调节电路 13不工作， 此时本公开的示例性实施例提供的 模拟电压源电路与已知的技术的模拟电压源电路相同，其 AVDD输出端输出 的电压计算公式为： , = (1 + M/R2;) * 。 当电压调节信号为高电平信号时， 晶体管 Q导通， 电压调节电路 13开始工作， 此时， 第三电阻 R3与第一电阻 R1并联连接， 之后再与第二电阻 R2串联连接， 此时本公开的示例性实施例
VAVDD = (l + (R\ I /R3)/R2) * VFB , 其中： M〃R3表示第一电阻 Rl 和第三电阻 R3 并联后的电阻值。 图 1中占空比控制电路 11的引脚 FB为电压釆样回路的引 脚， 用于接收第二电阻 R2两端反馈的电压 VFB， 如果接收到的反馈电压 VFB 与占空比控制电路 11中预先设定的反馈电压基准电压不同，则通过占空比控 制电路 11调节接收到的反馈电压 VFB， 使得反馈电压 VFB的值保持不变。 由 于第一电阻 R1和第三电阻 R3并联后的电阻值 M〃R3小于第一电阻 R1的电 阻值 R1， 通过比较公式 VAmD = (1 + RI/R2) * VFB和 VAmD = (l + (Rl I /R3)/R2) * VFB， 得到经过本公开的示例性实施例的电压调节电路 13调节后， AVDD输出端 输出的电压值比已知的技术中 AVDD输出端输出的电压值小。本公开的示例 性实施例提供的一种模拟电压源电路可以实时可控的调节 AVDD输出端输 出的电压值，例如，可以将本公开的示例性实施例的电压调节电路 13中的第 三电阻 R3的阻值的取值范围可以设置为 50ΚΩ-100ΚΩ，本公开的示例性实 施例提供的一种模拟电压源电路可以通过液晶面板***端调节用于输入电压 调节信号的输入端 CON输入的电压调节信号的幅值、 频率及占空比， 调节 后会导致与其连接的晶体管 Q导通时晶体管 Q两端的模拟电阻值也不同，继 而 R1〃R3与 R2的比值不同， 导致 AVDD输出端输出的电压值不同， 本公开 的示例性实施例中对 AVDD输出端输出的电压降低的具体值根据***或液 晶面板的实际需要进行调整。
如图 2所示， 本公开的示例性实施例提供的另一种模拟电压源电路， 输 出电压釆样电路 12包括串联连接于电压输出端 AVDD与电压调节电路 13之 间的第一电阻 R1和第二电阻 R2， 第一电阻 R1与电压输出端 AVDD相连， 第二电阻 R2与电压调节电路 13相连， 占空比控制电路 11从第一电阻 R1与 第二电阻 R2之间的连接点提取电压反馈，电压调节电路 13具有两个输出端， 分别与第二电阻 R2的靠近接地点的一端以及接地点相连。 例如， 本公开的 示例性实施例中的电压调节电路 13包括第三电阻 R3和开关器件 Q， 所述开 关器件 Q的控制极与所述电压调节信号输入端 CON相连， 另两极分别与所 述第二电阻 R2的靠近接地点的一端 N5和所述接地点相连； 所述第三电阻 R3的第一端 N6与所述第二电阻 R2的靠近接地点的一端 N5相连， 所述第 三电阻 R3的第二端 N7与所述接地点相连，本公开的示例性实施例中的开关 器件 Q为晶体管 Q，晶体管 Q的栅极与所述电压调节信号输入端 CON相连， 源极与所述第三电阻 R3的第一端 N6相连， 漏极与所述接地点相连。 当晶体 管 Q为 N型薄膜晶体管时， 若所述电压调节信号为低电平信号， 所述 N型 薄膜晶体管关闭， 若所述电压调节信号为高电平信号， 所述 N型薄膜晶体管 导通； 当所述晶体管 Q为 P型薄膜晶体管时， 若所述电压调节信号为低电平 信号， 所述 P型薄膜晶体管导通， 若所述电压调节信号为高电平信号， 所述 P型薄膜晶体管关闭。
本公开的示例性实施例中的晶体管 Q以 N型薄膜晶体管为例进行介绍， 用于输入电压调节信号的输入端 CON输入的电压调节信号来自液晶面板的 ***端， 本公开的示例性实施例中的电压调节信号输入端 CON输入的电压 调节信号为低电平信号或高电平信号， 当电压调节信号为高电平信号时， 晶 体管 Q导通，此时本公开的示例性实施例提供的模拟电压源电路与已知的技 术的模拟电压源电路相同， 其 AVDD 输出端输出的电压计算公式为： , = (1 + M/R2) * ^。 当电压调节信号为低电平信号时， 晶体管 Q关闭， 此 时，第三电阻 R3与第二电阻 R2串联连接，之后再与第一电阻 R1串联连接， 此时本公开的示例性实施例提供的模拟电压源电路中 AVDD输出端输出的 电压发生变化， 计算公式为： , = (l + Rl/(R2 + R3)) * 。 图 2中占空比控制 电路 11的引脚 FB为电压釆样回路的引脚， 用于接收第二电阻 R2与第三电 阻串联后反馈的电压 VFB， 如果接收到的反馈电压 VFB与占空比控制电路 11 中预先设定的反馈电压基准电压不同，则通过占空比控制电路 11调节接收到 的反馈电压 VFB， 使得反馈电压 VFB 的值保持不变。 通过比较公式 VAVDD = (1 + M/R2) * ^和 = (1 + M/(R2 + R3)) * ^， 得到经过本公开的示例性 实施例的电压调节电路 13调节后， AVDD输出端输出的电压值比已知的技 术中 AVDD输出端输出的电压值小。本公开的示例性实施例提供的一种模拟 电压源电路可以实时可控的调节 AVDD输出端输出的电压值， 例如， 可以将 本公开的示例性实施例的电压调节电路 13中的第三电阻 R3的阻值的取值范 围可以设置为 50ΚΩ-100ΚΩ。 本公开的示例性实施例中对 AVDD输出端输 出的电压降低的具体值根据***或液晶面板的实际需要进行调整。
在液晶面板的实际应用中， AVDD输出端输出的电压降低之后， 液晶面 板显示的图像品质也会降低， 如图像色彩或 Gamma特性会变差， 甚至出现 图像异常。 因此， 需要在保证 AVDD输出端输出的电压降低后能够使得液晶 面板正常显示的前提下， 根据***及客户对液晶面板显示的图像的要求， 通 过本公开的示例性实施例的电压调节电路 13进行调节。
如图 3所示， 本公开的示例性实施例还提供了另一种模拟电压源电路。 将电压调节电路 13设置于占空比控制电路 11 内部， 其中电压调节电路 13 内部设置有接收和识别实时传入到电压调节电路 13 中的电压调节信号的接 收识别模块 20， 用于输入电压调节信号的输入端 CON通过占空比控制电路 11的引脚输入到电压调节电路 13内的接收识别模块 20， 本公开的示例性实 施例中用于输入电压调节信号的输入端 CON输入到电压调节电路 13中的电 压调节信号的时序图如图 4 ( a )所示， 通过电压调节电路 13 内部的接收识 别模块 20将电压调节信号的幅值、占空比或频率计算转换后输出控制占空比 控制电路 11基准电压的调节信号， 进而改变占空比控制电路 11的基准电压 值， 基准电压值改变后电压调节电路 13内的反馈调节模块 21将对接收到的 反馈电压 VFB进行调节， 使得调节后的反馈电压 VFB与通过本公开的示例性 实施例中的接收识别模块 20调节后的基准电压相同，反馈电压 VFB变化后的 时序图如图 4 ( b )所示， 才艮据上面的描述， AVDD输出端输出的电压的计算 公式为： VAmD=(l + m/R2 VFB, 由于 VFB发生变化， 则 AVDD输出端输出的 电压也会发生变化，此时 AVDD输出端输出的电压的时序图如图 4(c)所示。 公开的精神和范围。 这样， 倘若本公开的这些修改和变型属于本公开权利要 求及其等同技术的范围之内， 则本公开也意图包含这些改动和变型在内。
本申请要求于 2014年 4月 2 日递交的中国专利申请第 201410131409.7 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种模拟电压源电路， 包括： 电压输入端、 DC-DC变换电路、 电压输 出端、 占空比控制电路和输出电压釆样电路， 所述输出电压釆样电路用于向 所述占空比控制电路反馈所述输出电压的大小， 所述占空比控制电路用于根 据所述输出电压釆样电路的反馈而控制所述 DC-DC 变换电路的输出电压的 大小， 所述电路还包括：
所述电压调节信号来控制升高或降低所述输出电压釆样电路的反馈， 进而使 所述电压输出端输出的电压升高或降低。
2、根据权利要求 1所述的电路， 其中， 所述输出电压釆样电路包括串联 连接于所述电压输出端与接地点之间的第一电阻和第二电阻， 所述第一电阻 与电压输出端相连， 所述第二电阻与接地点相连， 所述占空比控制电路从所 述第一电阻与所述第二电阻之间的连接点提取电压反馈， 所述电压调节电路 具有两个输出端， 分别与所述第一电阻的两端相连。
3、根据权利要求 2所述的电路， 其中， 所述电压调节电路包括第三电阻 和开关器件， 所述开关器件的控制极输入有所述电压调节信号， 另两极分别 与所述第一电阻的第一端和所述第三电阻的第一端相连； 所述第三电阻的第 二端与所述第一电阻的第二端相连。
4、 根据权利要求 3所述的电路， 其中， 所述开关器件为晶体管， 所述晶 体管的栅极与所述电压调节信号输入端相连， 源极与所述第三电阻的第一端 相连， 漏极与所述第一电阻的第一端相连。
5、根据权利要求 1所述的电路， 其中， 所述输出电压釆样电路包括串联 连接于所述电压输出端与所述电压调节电路之间的第一电阻和第二电阻， 所 述第一电阻与电压输出端相连， 所述第二电阻与所述电压调节电路相连， 所 述占空比控制电路从所述第一电阻与所述第二电阻之间的连接点提取电压反 馈， 所述电压调节电路具有两个输出端， 分别与所述第二电阻的靠近接地点 的一端以及接地点相连。
6、根据权利要求 5所述的电路， 其中， 所述电压调节电路包括第三电阻 和开关器件， 所述开关器件的控制极输入有所述电压调节信号， 另两极分别 与所述第二电阻的靠近接地点的一端和所述接地点相连； 所述第三电阻的第 一端与所述第二电阻的靠近接地点的一端相连， 所述第三电阻的第二端与所 述接地点相连。
7、 根据权利要求 6所述的电路， 其中， 所述开关器件为晶体管， 所述晶 体管的栅极与所述电压调节信号输入端相连， 源极与所述第三电阻的第一端 相连， 漏极与所述接地点相连。
8、根据权利要求 4或 7所述的电路， 其中， 当所述晶体管为 N型薄膜晶 体管时， 若所述电压调节信号为低电平信号， 所述 N型薄膜晶体管关闭， 若 所述电压调节信号为高电平信号， 所述 N型薄膜晶体管导通。
9、根据权利要求 4或 7所述的电路， 其中， 当所述晶体管为 P型薄膜晶 体管时， 若所述电压调节信号为低电平信号， 所述 P型薄膜晶体管导通， 若 所述电压调节信号为高电平信号， 所述 P型薄膜晶体管关闭。
10、根据权利要求 1-9中任一项所述的电路， 其中， 所述电压调节电路集 成于所述占空比控制电路内部。
11、 一种显示装置， 其中， 所述装置包括权利要求 1-10任一项所述的电 路。
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