WO2015105204A1 - Thermal interface material and semiconductor chip package comprising same - Google Patents

Thermal interface material and semiconductor chip package comprising same Download PDF

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Publication number
WO2015105204A1
WO2015105204A1 PCT/KR2014/000112 KR2014000112W WO2015105204A1 WO 2015105204 A1 WO2015105204 A1 WO 2015105204A1 KR 2014000112 W KR2014000112 W KR 2014000112W WO 2015105204 A1 WO2015105204 A1 WO 2015105204A1
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Prior art keywords
pcm
semiconductor chip
thermal interface
polymer
interface material
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PCT/KR2014/000112
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French (fr)
Korean (ko)
Inventor
정세영
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엔트리움 주식회사
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Priority to PCT/KR2014/000112 priority Critical patent/WO2015105204A1/en
Publication of WO2015105204A1 publication Critical patent/WO2015105204A1/en

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    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K5/00—Heat-transfer, heat-exchange or heat-storage materials, e.g. refrigerants; Materials for the production of heat or cold by chemical reactions other than by combustion
    • C09K5/02—Materials undergoing a change of physical state when used
    • C09K5/06—Materials undergoing a change of physical state when used the change of state being from liquid to solid or vice versa
    • C09K5/063—Materials absorbing or liberating heat during crystallisation; Heat storage materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Definitions

  • the present invention relates to a thermal interface material and a semiconductor chip package including the same, and more particularly, to a thermal interface material having excellent heat dissipation characteristics and a semiconductor chip package including the same.
  • a heat generation phenomenon of the semiconductor chip becomes a problem.
  • a heat spreader using a metal material having high thermal conductivity or the like may be attached to the semiconductor chip package to release heat generated from the semiconductor chip to the outside.
  • a thermal interface material may be attached between the semiconductor chip package and the heat sink to facilitate heat transfer from the semiconductor chip package to the heat sink.
  • the technical problem to be achieved by the technical idea of the present invention is to provide a thermal interface material excellent in heat dissipation characteristics and heat conduction characteristics.
  • Another object of the present invention is to provide a semiconductor chip package including the thermal interface material.
  • a thermal interface material includes a polymer matrix; And a PCM ball dispersed in the polymer matrix, wherein the PCM ball comprises: a PCM core comprising a phase change material; And a first coating layer surrounding the PCM core.
  • the phase change material may undergo a phase change from a solid phase to a liquid phase within the operating temperature range of the semiconductor chip.
  • the melting point of the phase change material may range from 50 to 200 ° C.
  • the phase change material may be paraffin, polyethylene glycol, inorganic hydrates, or fatty acids.
  • the first coating layer may include an electrically conductive material.
  • the first coating layer may be a metal, graphene, carbon black, carbon nanotube, or conductive polymer.
  • the melting point of the first coating layer may be higher than the melting point of the PCM core.
  • the first coating layer may be formed of a single layer or a stacked structure of a plurality of layers.
  • the thermal interface material may further include a polymer interlayer formed between the PCM core ball and the first coating layer.
  • the method may further include a conductive polymer, carbon nanotubes, or graphene dispersed in the polymer matrix.
  • a thermal interface material includes a porous carbon matrix having a plurality of pores formed therein; And a phase change material layer (PCM) formed on the inner walls of the pores.
  • PCM phase change material layer
  • the porous carbon matrix may be a carbon foam.
  • a semiconductor chip package includes: a semiconductor chip; A heat spreader on the semiconductor chip; And a thermal interface material connecting the semiconductor chip and the heat sink and including a polymer matrix and PCM balls dispersed in the polymer matrix.
  • the heat sink may include a porous carbon matrix having a plurality of pores formed therein; And a PCM ball formed in the pores, wherein the PCM ball may include a PCM core and a first coating layer surrounding the PCM core.
  • an electronic device includes the semiconductor chip package.
  • the thermal interface material according to the present invention comprises a PCM ball comprising materials which change phase from solid phase to liquid phase or from liquid phase to solid phase in the operating temperature range of the semiconductor chip.
  • the PCM ball may absorb heat generated in the semiconductor chip as the phase changes, thereby preventing heat generation or abnormal high temperature phenomenon of the semiconductor chip package.
  • FIG. 1 is a cross-sectional view illustrating a thermal interface material according to exemplary embodiments of the present invention.
  • FIG. 2 is a cross-sectional view illustrating a thermal interface material according to exemplary embodiments of the present invention.
  • FIG 3 is a cross-sectional view illustrating a thermal interface material according to exemplary embodiments of the present invention.
  • FIG. 4 is a cross-sectional view illustrating a semiconductor chip package according to some example embodiments of the inventive concepts.
  • FIG. 5 is a cross-sectional view illustrating a semiconductor chip package according to some example embodiments of the inventive concepts.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor chip package in accordance with some example embodiments of the inventive concepts.
  • FIG. 7 is a cross-sectional view illustrating a semiconductor chip package in accordance with some example embodiments of the inventive concepts.
  • FIG. 8 is a schematic diagram illustrating an operating temperature distribution of a semiconductor chip package using a thermal interface material according to example embodiments.
  • PCM ball phase change material ball
  • a PCM core comprising a phase change material
  • a thermal interface material comprising a first coating layer surrounding the PCM core.
  • FIG. 1 is a cross-sectional view illustrating a thermal interface material 100 in accordance with exemplary embodiments of the present invention.
  • the thermal interface material 100 may include a plurality of PCM balls 120 and a plurality of polymer balls 130 dispersed in the matrix 110.
  • the matrix 110 may be a thermal grease type matrix such as a silicone resin, or alternatively, the matrix 110 may be a rigid type matrix such as an epoxy resin.
  • a polymer matrix such as polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET) may be used.
  • PMMA polymethyl methacrylate
  • PET polyethylene terephthalate
  • the type of the matrix 110 is not limited thereto.
  • PCM ball 120 may include a PCM core 122 and a first coating layer 124 surrounding the PCM core 122.
  • the PCM core 122 may be formed in various shapes such as spherical or elliptical, and the first coating layer 124 may be formed in a shape surrounding the PCM core 122 with a predetermined thickness.
  • the first coating layer 124 may be formed to a thickness of about 10-200 nm, but the thickness of the first coating layer 124 is not limited thereto, and the shape of the PCM core 122 and the first coating layer are limited thereto.
  • the thickness of the semiconductor device may vary depending on the type of the semiconductor chip 124 and the type of the semiconductor chip package.
  • the PCM core 122 may include a phase change material such as paraffin, polyethylene glycol, inorganic hydrates, fatty acids, and the like.
  • PCM core 122 may have a melting point in the range of 50-200 ° C.
  • the PCM core 122 may include a combination of two or more materials having different melting points.
  • the PCM core 122 may be formed to include both silicone resin and paraffin resin.
  • the first coating layer 124 may include an electrically conductive material.
  • the first coating layer 124 may include metal, graphene, carbon black, carbon nanotube, conductive polymer, or the like.
  • the first coating layer 124 may include a metal such as silver, gold, copper, aluminum, or the like.
  • the first coating layer 124 may be made of polypyrrol, polyacetylene, poly (p-phenylene), polysulfurnitrile ( poly (sulfurnitrile)), poly (phenylene sulfide), polyaniline, poly (p-phenylenevinylene), PEDOT: PSS [poly (3,4-ethylenedioxythiophene) poly (styrene sulfonate)] or derivatives thereof.
  • the melting point of the first cladding layer 124 may be higher than the melting point of the PCM core 122.
  • the first coating layer 124 may be formed as a single layer to surround the PCM core 122, or alternatively, the first coating layer 124 may be formed as a multilayer structure having two or more layers to surround the PCM core 122.
  • the PCM ball 120 may further include a polymer interlayer 126 formed between the first coating layer 124 and the PCM core 122.
  • the polymer interlayer 126 may comprise a material that is not active with respect to the PCM core 122.
  • the PCM core 122 may cause a phase change from the solid phase to the liquid phase, or from the liquid phase to the solid phase within the operating temperature range of the semiconductor chip. For example, when the semiconductor chip is operated, heat may be generated to raise the temperature of the semiconductor chip to about 100 ° C. or more, and when the paraffin resin having a melting point of about 62 ° C. is used as the PCM core 122, the PCM core is used.
  • Reference numeral 122 may cause a phase change from a solid phase to a liquid phase at about 62 ° C.
  • the latent heat of paraffin was reported to be about 145-240 kJ / kg (MNA Hawlader, MS Uddin, MM Khin, "Microencapsulated PCM Thermal-Energy Storage System,” Appl. Energy 74, 195 ( 2003). That is, the temperature of the PCM core 122 is kept constant while absorbing this latent heat in the process of paraffin phase transition from solid phase to liquid phase. Accordingly, the thermal interface material 100 including the PCM core 122 may keep the temperature of the semiconductor chip low. Meanwhile, the contents related to the temperature change of the phase change material will be described later in detail with reference to FIG. 8.
  • the first cladding layer 124 has a higher melting point than the PCM core 122.
  • the melting point of the first coating layer 124 may be higher than the operating temperature range of the semiconductor chip. Therefore, even after the PCM core 122 causes a phase change from a solid phase to a liquid phase, the first coating layer 124 may not be melted and may remain in shape while surrounding the PCM core 122. When the temperature of the semiconductor chip decreases, the PCM core 122 contained in the first coating layer 124 may change phase from the liquid phase to the solid phase again.
  • the polymer ball 130 may include a polymer core 132 and a second coating layer 134 surrounding the polymer core 132.
  • the polymer core 132 may be formed in various shapes such as spherical or elliptical, and the second coating layer 134 may have a shape surrounding the polymer core with a predetermined thickness.
  • the second coating layer 134 may be formed to a thickness of about 10-200 nm, but is not limited thereto.
  • the shape of the polymer core 132, the type of the second coating layer 134, and the semiconductor chip package may be formed. It may have a variety of thickness depending on the type.
  • the polymer core 132 may include a polymer material such as polyester resin or silicone resin. Although the type of the polymer core 132 is exemplarily listed, the type of the polymer core 132 is not limited thereto.
  • the second coating layer 134 may include a conductive material such as metal, graphene, carbon black, carbon nanotube, or conductive polymer.
  • the second coating layer 134 includes an electrically conductive material and may be a material having high thermal conductivity.
  • the polymer balls 130 may be dispersed at a predetermined concentration in the thermal interface material 100.
  • the predetermined concentration may correspond, for example, to several tens of volume percent.
  • the concentration of the polymer balls 130 is high, the polymer balls 130 may be connected to each other in the thermal interface material 100.
  • the second coating layer 134 formed on the surface of the polymer balls 130 is an electrically conductive material and / or a thermally conductive material, the second coating layers 134 of the adjacent polymer balls 130 may be connected to each other to be electrically or thermally connected. Paths can be formed. Therefore, when a semiconductor chip (not shown) and a heat sink (not shown) are connected through the thermal interface material 100, heat generated from the semiconductor chip is further transferred to the heat sink through the heat path of the polymer balls 130. Can be easily delivered.
  • the PCM balls 120 dispersed in the polymer matrix 110 may absorb heat that may occur in the semiconductor chip, thereby causing a phase change from a solid phase to a liquid phase. Since the surrounding heat is absorbed in the phase change process, the thermal interface material 100 may have an excellent heat dissipation effect. In addition, heat generated in the semiconductor chip may be more easily transferred to the heat sink by the polymer balls 130 dispersed in the polymer matrix 110.
  • FIG. 2 is a cross-sectional view illustrating a thermal interface material 200 according to other embodiments of the present invention.
  • the thermal interface material 200 may include a plurality of PCM balls 220 dispersed in the matrix 210.
  • the matrix 210 may be a polymer matrix in which graphene, carbon nanotubes, conductive polymers, etc. are dispersed.
  • the matrix 210 may have carbon nanotubes dispersed at a predetermined concentration inside the polymer.
  • the carbon nanotubes, graphene or conductive polymers dispersed in the polymer matrix may be a material having a higher thermal conductivity than the polymer matrix.
  • the matrix 210 in which the carbon nanotubes, graphene or conductive polymers are dispersed may be formed. Heat that may be generated in the semiconductor chip (not shown) may be more easily transferred to the heat sink (not shown).
  • PCM balls 220 may include a PCM core 222 and a first covering layer 224 surrounding the PCM core 222.
  • the PCM core 222 may include a material causing a phase change from a solid phase to a liquid phase or from a liquid phase to a solid phase in the operating temperature range of the semiconductor chip.
  • the melting point of the PCM core 222 may correspond to about 50 to about 150 degrees.
  • the first coating layer 224 may include a conductive material.
  • the first coating layer 224 may be formed of one or more layers.
  • a polymer interlayer 226 may be further formed between the PCM core 222 and the first coating layer 224.
  • the PCM ball 220 may absorb the heat generated from the semiconductor chip to cause a phase change from a solid phase to a liquid phase. Therefore, abnormal heat generation phenomenon and abnormal high temperature phenomenon of the semiconductor chip having the thermal interface material 200 attached thereto can be prevented.
  • the thermal interface material 200 includes a polymer matrix having a high thermal conductivity or a matrix in which carbon nanotubes are dispersed and include PCM balls 220 dispersed in the matrix. Therefore, the thermal interface material 200 may have excellent heat dissipation effect because the surrounding heat is absorbed during the phase change process of the PCM balls 220.
  • FIG 3 is a cross-sectional view illustrating a thermal interface material 300 according to other embodiments of the present invention.
  • the thermal interface material 300 may include a matrix 310 and a PCM layer 320 inside pores 312 formed in the matrix 310.
  • the matrix 310 may include a porous material having a plurality of pores 312 formed therein.
  • the matrix 310 may comprise a porous carbon material or carbon foam.
  • the pores 312 in the matrix 310 may have various sizes and be connected to each other.
  • the matrix 310 may include a porous carbon material having a thermal conductivity of 50 W / mK or more.
  • the matrix 310 may comprise carbon foam having a thermal conductivity of at least 50 W / mK.
  • PCM layer 320 may be conformally formed within pores 312 of matrix 310.
  • the PCM layer 320 may be formed to a predetermined thickness on the sidewalls of the pores 312 of the matrix 310, such as to fill the interior of the pores 312 when the pores 312 are small in diameter. Can be formed.
  • a PCM material may be prepared, and the PCM material may be heated to a temperature above the melting point of the PCM material.
  • the paraffin may be heated to a temperature of about 60 to 70 ° C. to prepare a PCM solution including the paraffin material in solution.
  • the porous matrix 310 may be prepared, and the porous matrix 310 may be immersed in the PCM solution.
  • the porous matrix 310 may be separated from the PCM solution and cooled.
  • the PCM layer 320 may be conformally formed inside the pores 312 of the porous matrix 310.
  • the PCM layer 320 may be formed to fill the interior of the pores 312.
  • the thickness of the PCM layer 320 may vary depending on the pore 312 size, concentration of PCM material, immersion conditions, and the like.
  • the thermal interface material 300 may include a PCM layer 320 formed in the pores 312, and the PCM layer 320 may absorb heat generated from the semiconductor chip to cause a phase change from a solid phase to a liquid phase. Therefore, abnormal heat generation phenomenon and abnormal high temperature phenomenon of the semiconductor chip having the thermal interface material 200 attached thereto can be prevented.
  • FIG. 4 is a cross-sectional view illustrating a semiconductor chip package 1000 according to some example embodiments of the inventive concepts.
  • the semiconductor chip package 1000 may include a printed circuit board 1010, a semiconductor chip 1020, a heat sink 1030, and a thermal interface material 1100.
  • the semiconductor chip 1020 may be mounted on the printed circuit board 1010.
  • the bump 1040 formed on the active surface of the semiconductor chip 1020 may be electrically connected to the pad 1050 on the printed circuit board 1010.
  • An underfill 1060 may be filled between the active surface of the semiconductor chip 1020 and the printed circuit board 1010.
  • the underfill 1060 may include an epoxy resin.
  • the semiconductor chip 1020 is mounted on the printed circuit board 1010 through flip-chip bonding, but the present invention is not limited thereto.
  • the semiconductor chip 1020 may be mounted on the printed circuit board 1010 in such a manner that a wire (not shown) connects the semiconductor chip 1020 and the printed circuit board 1010.
  • FIG. 4 the semiconductor chip 1020 may be mounted on the printed circuit board 1010 in such a manner that a wire (not shown) connects the semiconductor chip 1020 and the printed circuit board 1010.
  • FIG. 4 illustrates that one semiconductor chip 1020 is mounted on a printed circuit board 1010, two or more semiconductor chips 1020 may be stacked, wire bonded (not shown), or through. It may be connected to each other through a silicon via (TSV) (not shown) and mounted on the printed circuit board 1010.
  • TSV silicon via
  • a heat sink 1030 covering the semiconductor chip 1020 may be attached to the printed circuit board 1010.
  • the heat sink 1030 may be formed using a material having high thermal conductivity to efficiently dissipate heat generated from the semiconductor chip 1020 to the outside.
  • the heat sink 1030 includes copper (Cu), aluminum (Al), tungsten copper (WCu), aluminum carbide (AlSiC), aluminum nitride (AlN), beryllium oxide (BeO), and the like. can do.
  • the heat sink 1030 is formed by coating at least one of metals such as nickel (Ni), silver (Ag), gold (Au), tin (Sn), and chromium (Cr) on the surface of the material having high thermal conductivity.
  • the heat sink 1030 may be formed of silicon carbide (AlSiC) as a base material, and a plating layer including nickel (Ni) may be further formed on the surface of the base material.
  • the heat sink 1030 may be formed in various shapes to maximize heat dissipation from the semiconductor chip 1020. Although not shown, an uneven portion may be formed in an upper portion of the heat sink 1030, or an upper portion of the heat sink 1030 may be formed in a fin shape to increase the surface area of the heat sink 1030.
  • the heat sink 1030 may be attached onto the printed circuit board via a nonconductive adhesive 1090.
  • the thermal interface material 1100 may be interposed between the top surface of the semiconductor chip 1020 and the bottom surface of the heat sink 1030. That is, the first surface 1020 of the thermal interface material 1100 may contact the upper surface of the semiconductor chip, and the second surface of the thermal interface material 1100 may contact the lower surface of the heat sink 1030.
  • the thermal interface material 1100 may be formed on a portion of the upper surface of the semiconductor chip 1020 between the semiconductor chip 1020 and the heat sink 1030, or may cover the entire upper surface of the semiconductor chip 1020. have.
  • Thermal interface material 1100 may include a plurality of PCM balls 1120 and a plurality of polymer balls 1130 dispersed in a polymer matrix 1110.
  • the plurality of PCM balls 1120 may each include a PCM core 1122 made of PCM material, and a first coating layer 1124 surrounding the PCM core 1122 and made of a conductive material.
  • a polymer interlayer 1126 may be further formed between the first cladding layer 1124 and the PCM core 1122.
  • the plurality of polymer balls 1130 may each include a polymer core 1132 made of a polymer material, and a second coating layer 1134 made of a conductive material surrounding the polymer core 1132.
  • Thermal interface material 1100 may be similar to thermal interface material 100 described with reference to FIG. 1.
  • an insulating layer 1070 may be interposed between the upper surface of the semiconductor chip 1020 and the thermal interface material 1100.
  • the insulating layer 1070 electrically connects the semiconductor chip 1020 from the PCM balls 1120 and the plurality of polymer balls 1130 including the first coating layer 1124 and the second coating layer 1134 each including a conductive material. It can be insulated.
  • a plurality of solder balls 1080 may be formed below the printed circuit board 1010.
  • the semiconductor package 1000 has a high thermal conductivity of the thermal interface material 1100, thereby effectively transferring heat generated when the semiconductor chip 1020 is operated to the heat sink 1030.
  • the PCM balls 1120 in the thermal interface material 1100 include materials that have a predetermined latent heat and may phase change within an operating temperature range of the semiconductor chip 1020, the semiconductor chip ( The heat generated during operation of the 1020 may be absorbed, thereby effectively reducing the temperature of the semiconductor chip package 1000.
  • the semiconductor chip package 1000 according to the present invention may be included in various electronic devices.
  • the electronic device may be a notebook, a desktop, a mobile phone, a smartphone, a PDA, a digital camera, a camcorder, a display device, an audio, a TV, an LED device, and the like.
  • the type of the electronic device is not limited thereto.
  • FIG. 5 is a cross-sectional view illustrating a semiconductor chip package 1000a according to some example embodiments of the inventive concepts. Since the semiconductor chip package 1000a is substantially the same as the semiconductor chip package 1000 described with reference to FIG. 4 except for the thermal interface material 1200, the differences will be described with reference to the difference.
  • thermal interface material 1200 may include a polymer matrix 1210 and a plurality of PCM balls 1220 dispersed within polymer matrix 1210. Graphene, carbon nanotubes, conductive polymers, etc. may be dispersed in the polymer matrix 1210.
  • the PCM balls 1220 may be composed of a PCM core 1222 and a first coating layer 1224 surrounding the PCM core 1222.
  • the thermal interface material 1200 may be similar to the thermal interface material 200 described with reference to FIG. 2.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor chip package 1000b according to some example embodiments of the inventive concepts. Since the semiconductor chip package 1000b is substantially the same as the semiconductor chip package 1000 described with reference to FIG. 4 except for the thermal interface material 1300, the difference will be described.
  • the thermal interface material 1300 may include a matrix 1310 and a PCM layer 1320 inside the pores 1312 formed in the matrix 1310.
  • the matrix 1310 may comprise a porous carbon material or carbon foam.
  • the PCM layer 1320 may be conformally formed inside the pores 1312 of the matrix 1310.
  • the PCM layer 1320 may be formed to a predetermined thickness on the sidewalls of the pores 1312 of the matrix 1310, for example filling the interior of the pore 1312 when the pores 1312 are small in diameter. It can be formed to be.
  • FIG. 7 is a cross-sectional view illustrating a semiconductor chip package 2000 according to some example embodiments of the inventive concepts. Since the semiconductor chip package 2000 is substantially the same as the semiconductor chip package 1000 described with reference to FIG. 4 except for the structure of the heat sink 2030, the differences will be mainly described.
  • the semiconductor chip package 2000 may include a printed circuit board 1010, a semiconductor chip 1020, a heat sink 2030, and a thermal interface material 1100.
  • the heat sink 2030 may be formed on the printed circuit board 1010 to cover the semiconductor chip 1020.
  • the heat sink 2030 may include a matrix 2032 and a plurality of pores 2034 formed in the matrix 2032, and may include a plurality of PCM balls 2036 dispersed in the pores 2034. .
  • Matrix 2032 may include a porous carbon material, such as carbon foam.
  • carbon foam is made from a pitch of high thermal conductivity, is a network structure in which carbon is connected in three dimensions, and is a porous material having an open pore structure.
  • the pores 2034 may be formed to have a diameter of about several tens of nanometers to several micrometers.
  • the matrix 2032 has a structure in which the pores 2034 are opened therein so that fluid can enter and exit, and the surface area of the matrix 2032 is excellent in thermal conductivity.
  • matrix 2032 may have a thermal conductivity of at least 50 W / mK.
  • PCM ball 2036 may include a PCM core 2037 and a first coating layer 2038 surrounding the PCM core 2037.
  • the PCM core 2037 may include a material that causes a phase change from a liquid phase to a solid phase or a phase change from a solid phase to a liquid phase within an operating temperature range of the semiconductor chip 1020.
  • the first coating layer 2038 may include a conductive material such as metal, carbon nanotube, graphene, carbon black, conductive polymer, or the like.
  • heat dissipation characteristics may be excellent.
  • FIG. 7 illustrates the semiconductor chip package 2000 including the thermal interface material 1100 described with reference to FIG. 4
  • the semiconductor chip package 2000 may include the thermal interface material 1200 described with reference to FIG. 5.
  • the thermal interface material 1300 described with reference to FIG. 6 may also be included.
  • FIG. 8 is a schematic diagram illustrating an operating temperature distribution of a semiconductor chip package using a thermal interface material according to example embodiments.
  • T1 represents the melting point of the PCM core material contained in the PCM ball, and in the present invention, T1 is located within the operating temperature range of the semiconductor chip.
  • a semiconductor chip may operate at 20 to 120 ° C., and a paraffin resin having a melting point of 62 ° C. may be used as the PCM core.
  • the temperature of the semiconductor chip may gradually increase, and the temperature of the thermal interface material may also increase until the temperature of the semiconductor chip reaches T1 in the I section.
  • the temperature of the semiconductor chip is higher than T1, and the PCM core in the thermal interface material may start to change phase from solid phase to liquid phase.
  • the phase change process is an endothermic process, and the PCM core including the paraffin resin may absorb latent heat of about 145-240 kJ / kg. Since the PCM core has no temperature change during the phase change, the temperature of the thermal interface material may be maintained near T1 even if the temperature of the semiconductor chip increases to T2. Accordingly, the thermal interface material in section II may have a flat temperature section. In section III, the temperature of the thermal interface material starts to rise again after all the PCM cores contained in the thermal interface material have changed phase to liquid phase.
  • T2 which is a temperature at which the temperature of the thermal interface material starts to rise again, may vary depending on the amount of the PCM core included in the thermal interface material, the type of the PCM core, or the latent heat size of the PCM core.
  • the temperature of the thermal interface material according to the chip temperature of the semiconductor chip package to which the thermal interface material does not include the PCM ball is shown as a dotted line.
  • Thermal interface materials that do not include PCM balls may increase in temperature in proportion to an increase in the temperature of the semiconductor chip. Therefore, it can be seen that the thermal interface material including the PCM ball according to the present invention has an excellent heat dissipation effect than the thermal interface material without the PCM ball.
  • the present invention can be used in all fields using the adhesive material with high thermal conductivity efficiency, such as electronics industry, machine mountain.

Abstract

Disclosed is a thermal interface material. Provided is a thermal interface material, comprising: a polymer matrix; and phase change material (PCM) balls dispersed in the polymer matrix, wherein the PCM balls include a PCM core containing a phase change material, and a first coating layer covering the PCM core.

Description

열 계면 물질 및 이를 포함하는 반도체 칩 패키지Thermal Interface Materials and Semiconductor Chip Packages Comprising the Same
본 발명의 기술적 사상은 열 계면 물질(thermal interface material) 및 이를 포함하는 반도체 칩 패키지에 관한 것으로서, 더욱 상세하게는, 방열 특성이 우수한 열 계면 물질 및 이를 포함하는 반도체 칩 패키지에 관한 것이다.The present invention relates to a thermal interface material and a semiconductor chip package including the same, and more particularly, to a thermal interface material having excellent heat dissipation characteristics and a semiconductor chip package including the same.
반도체 칩이 고집적화됨에 따라 반도체 칩의 발열 현상이 문제된다. 이를 해결하기 위하여, 반도체 칩 패키지 상에 열 전도도가 높은 금속 물질 등을 사용한 방열판(heat spreader)을 부착하여 반도체 칩에서 발생하는 열을 외부로 방출시킬 수 있다. 또한, 열 계면 물질을 반도체 칩 패키지 및 방열판 사이에 부착하여 반도체 칩 패키지로부터 방열판으로의 열전달을 촉진시킬 수 있다.As the semiconductor chip is highly integrated, a heat generation phenomenon of the semiconductor chip becomes a problem. In order to solve this problem, a heat spreader using a metal material having high thermal conductivity or the like may be attached to the semiconductor chip package to release heat generated from the semiconductor chip to the outside. In addition, a thermal interface material may be attached between the semiconductor chip package and the heat sink to facilitate heat transfer from the semiconductor chip package to the heat sink.
선행기술문헌으로는 한국공개특허 제2002-0093474호 (2002.12.16. 공개)가 있다.Prior art documents include Korean Patent Publication No. 2002-0093474 (published Dec. 16, 2002).
본 발명의 기술적 사상이 이루고자 하는 기술적 과제는 방열 특성 및 열 전도 특성이 우수한 열 계면 물질을 제공하는 것이다.The technical problem to be achieved by the technical idea of the present invention is to provide a thermal interface material excellent in heat dissipation characteristics and heat conduction characteristics.
또한, 본 발명의 기술적 사상이 이루고자 하는 다른 기술적 과제는, 상기 열 계면 물질을 포함하여 구성된 반도체 칩 패키지를 제공하는 것이다.Another object of the present invention is to provide a semiconductor chip package including the thermal interface material.
상기 기술적 과제를 달성하기 위한 본 발명의 기술적 사상에 따른 열 계면 물질은, 폴리머 매트릭스(polymer matrix); 및 상기 폴리머 매트릭스 내에 분산된 PCM 볼(phase change material ball);을 포함하며, 상기 PCM 볼은, 상변화 물질을 포함하는 PCM 코어; 상기 PCM 코어를 둘러싸는 제1 피복층을 포함한다.In accordance with an aspect of the present invention, a thermal interface material includes a polymer matrix; And a PCM ball dispersed in the polymer matrix, wherein the PCM ball comprises: a PCM core comprising a phase change material; And a first coating layer surrounding the PCM core.
예시적인 실시예들에 있어서, 상기 상변화 물질은 반도체 칩의 작동 온도 범위 내에서 고상(solid phase)에서 액상(liquid phase)으로 상변화를 거칠 수 있다.In example embodiments, the phase change material may undergo a phase change from a solid phase to a liquid phase within the operating temperature range of the semiconductor chip.
예시적인 실시예들에 있어서, 상기 상변화 물질의 융점은 50 내지 200℃의 범위일 수 있다.In exemplary embodiments, the melting point of the phase change material may range from 50 to 200 ° C.
예시적인 실시예들에 있어서, 상기 상변화 물질은 파라핀(paraffin), 폴리에틸렌 글리콜(polyethylene glycol), 무기수화물(inorganic hydrates), 지방산(fatty acid)일 수 있다.In example embodiments, the phase change material may be paraffin, polyethylene glycol, inorganic hydrates, or fatty acids.
예시적인 실시예들에 있어서, 상기 제1 피복층은 전기 전도성 물질을 포함할 수 있다.In example embodiments, the first coating layer may include an electrically conductive material.
예시적인 실시예들에 있어서, 상기 제1 피복층은 금속, 그래핀(graffin), 카본 블랙(carbon black), 카본 나노 튜브(carbon nanotube), 또는 전도성 폴리머일 수 있다.In example embodiments, the first coating layer may be a metal, graphene, carbon black, carbon nanotube, or conductive polymer.
예시적인 실시예들에 있어서, 상기 제1 피복층의 융점(melting point)은 상기 PCM 코어의 융점보다 높을 수 있다.In exemplary embodiments, the melting point of the first coating layer may be higher than the melting point of the PCM core.
예시적인 실시예들에 있어서, 상기 제1 피복층은 단일 층 또는 복수의 층들의 적층 구조로 형성될 수 있다.In example embodiments, the first coating layer may be formed of a single layer or a stacked structure of a plurality of layers.
예시적인 실시예들에 있어서, 상기 열 계면 물질은 상기 PCM 코어 볼 및 상기 제1 피복층 사이에 형성되는 폴리머 중간층을 더 포함할 수 있다.In example embodiments, the thermal interface material may further include a polymer interlayer formed between the PCM core ball and the first coating layer.
예시적인 실시예들에 있어서, 상기 폴리머 매트릭스 내에 분산된 전도성 폴리머, 카본 나노 튜브 또는 그래핀을 더 포함할 수 있다.In example embodiments, the method may further include a conductive polymer, carbon nanotubes, or graphene dispersed in the polymer matrix.
상기 기술적 과제를 달성하기 위한 본 발명의 다른 기술적 사상에 따른 열 계면 물질은, 내부에 다수의 포어들(pores)이 형성된 다공성 카본 매트릭스(porous carbon matrix); 및 상기 포어들 내벽 상에 형성된 PCM 층(phase change material layer);을 포함한다.According to another aspect of the present invention, a thermal interface material includes a porous carbon matrix having a plurality of pores formed therein; And a phase change material layer (PCM) formed on the inner walls of the pores.
예시적인 실시예들에 있어서, 상기 다공성 카본 매트릭스는 카본 폼(carbon foam)일 수 있다.In example embodiments, the porous carbon matrix may be a carbon foam.
상기 기술적 과제를 달성하기 위한 본 발명의 다른 기술적 사상에 따른 반도체 칩 패키지는, 반도체 칩; 상기 반도체 칩 상부의 방열판(heat spreader); 및 상기 반도체 칩 및 상기 방열판을 연결하며, 폴리머 매트릭스 및 상기 폴리머 매트릭스 내에 분산된 PCM 볼을 포함하는 열 계면 물질을 포함한다.According to another aspect of the present invention, a semiconductor chip package includes: a semiconductor chip; A heat spreader on the semiconductor chip; And a thermal interface material connecting the semiconductor chip and the heat sink and including a polymer matrix and PCM balls dispersed in the polymer matrix.
예시적인 실시예들에 있어서, 상기 방열판은, 내부에 다수의 포어들이 형성된 다공성 카본 매트릭스; 및 상기 포어들 내부에 형성된 PCM 볼을 포함하며, 상기 PCM 볼은 PCM 코어 및 상기 PCM 코어를 둘러싸는 제1 피복층을 포함할 수 있다.In example embodiments, the heat sink may include a porous carbon matrix having a plurality of pores formed therein; And a PCM ball formed in the pores, wherein the PCM ball may include a PCM core and a first coating layer surrounding the PCM core.
상기 기술적 과제를 달성하기 위한 본 발명의 또 다른 기술적 사상에 따른 전자 소자는, 상기 반도체 칩 패키지를 포함한다.In accordance with still another aspect of the inventive concept, an electronic device includes the semiconductor chip package.
본 발명에 따른 열 계면 물질은 반도체 칩의 작동 온도 범위에서 고상으로부터 액상으로, 또는 액상으로부터 고상으로 상변화하는 물질들을 포함하는 PCM 볼을 포함한다. 상기 반도체 칩의 작동 온도가 상승할 때 상기 PCM 볼이 상변화하면서 상기 반도체 칩에 발생하는 열을 흡수할 수 있으므로, 상기 반도체 칩 패키지의 발열 또는 이상 고온 현상을 방지할 수 있다.The thermal interface material according to the present invention comprises a PCM ball comprising materials which change phase from solid phase to liquid phase or from liquid phase to solid phase in the operating temperature range of the semiconductor chip. When the operating temperature of the semiconductor chip increases, the PCM ball may absorb heat generated in the semiconductor chip as the phase changes, thereby preventing heat generation or abnormal high temperature phenomenon of the semiconductor chip package.
도 1은 본 발명의 예시적인 실시예들에 따른 열 계면 물질을 나타내는 단면도이다. 1 is a cross-sectional view illustrating a thermal interface material according to exemplary embodiments of the present invention.
도 2는 본 발명의 예시적인 실시예들에 따른 열 계면 물질을 나타내는 단면도이다.2 is a cross-sectional view illustrating a thermal interface material according to exemplary embodiments of the present invention.
도 3은 본 발명의 예시적인 실시예들에 따른 열 계면 물질을 나타내는 단면도이다.3 is a cross-sectional view illustrating a thermal interface material according to exemplary embodiments of the present invention.
도 4는 본 발명의 예시적인 실시예들에 따른 반도체 칩 패키지를 나타내는 단면도이다.4 is a cross-sectional view illustrating a semiconductor chip package according to some example embodiments of the inventive concepts.
도 5는 본 발명의 예시적인 실시예들에 따른 반도체 칩 패키지를 나타내는 단면도이다.5 is a cross-sectional view illustrating a semiconductor chip package according to some example embodiments of the inventive concepts.
도 6은 본 발명의 예시적인 실시예들에 따른 반도체 칩 패키지를 나타내는 단면도이다.6 is a cross-sectional view illustrating a semiconductor chip package in accordance with some example embodiments of the inventive concepts.
도 7은 본 발명의 예시적인 실시예들에 따른 반도체 칩 패키지를 나타내는 단면도이다.7 is a cross-sectional view illustrating a semiconductor chip package in accordance with some example embodiments of the inventive concepts.
도 8은 예시적인 실시예들에 따른 열 계면 물질을 사용한 반도체 칩 패키지의 작동 온도 분포를 나타내는 개략도이다.8 is a schematic diagram illustrating an operating temperature distribution of a semiconductor chip package using a thermal interface material according to example embodiments.
폴리머 매트릭스(polymer matrix); 및Polymer matrix; And
상기 폴리머 매트릭스 내에 분산된 PCM 볼(phase change material ball);을 포함하며,PCM ball (phase change material ball) dispersed in the polymer matrix;
상기 PCM 볼은,The PCM ball,
상변화 물질을 포함하는 PCM 코어; 및A PCM core comprising a phase change material; And
상기 PCM 코어를 둘러싸는 제1 피복층을 포함하는 것을 특징으로 하는 열 계면 물질(thermal interface material)이 제공된다.A thermal interface material is provided comprising a first coating layer surrounding the PCM core.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 본 발명의 실시예들은 당해 기술 분야에서 통상의 지식을 가진 자에게 본 발명의 기술적 사상을 더욱 완전하게 설명하기 위하여 제공되는 것이며, 하기 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 기술적 사상의 범위가 하기 실시예에 한정되는 것은 아니다. 오히려, 이들 실시예는 본 개시를 더욱 충실하고 완전하게 하고, 당업자에게 본 발명의 기술적 사상을 완전하게 전달하기 위하여 제공되는 것이다. 본 명세서에서 사용된 바와 같이, 용어 "및/또는"은 해당 열거된 항목 중 어느 하나 및 하나 이상의 모든 조합을 포함한다. 동일한 부호는 시종 동일한 요소를 의미한다. 나아가, 도면에서의 다양한 요소와 영역은 개략적으로 그려진 것이다. 따라서, 본 발명의 기술적 사상은 첨부한 도면에 그려진 상대적인 크기나 간격에 의해 제한되지 않는다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully explain the technical idea of the present invention to those skilled in the art, and the following embodiments may be modified in many different forms, and The scope of the technical idea is not limited to the following examples. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items. Like numbers refer to like elements all the time. Furthermore, various elements and regions in the drawings are schematically drawn. Therefore, the technical idea of the present invention is not limited by the relative size or the distance drawn in the accompanying drawings.
도 1은 본 발명의 예시적인 실시예들에 따른 열 계면 물질(100)을 나타내는 단면도이다. 1 is a cross-sectional view illustrating a thermal interface material 100 in accordance with exemplary embodiments of the present invention.
도 1을 참조하면, 열 계면 물질(100)은 매트릭스(110) 내부에 분산된 복수 개의 PCM 볼들(120) 및 복수 개의 폴리머 볼들(130)을 포함할 수 있다. Referring to FIG. 1, the thermal interface material 100 may include a plurality of PCM balls 120 and a plurality of polymer balls 130 dispersed in the matrix 110.
매트릭스(110)는 실리콘계 수지 등의 써멀 그리스(thermal grease) 타입 매트릭스일 수 있고, 이와는 달리 에폭시 수지(epoxy resin) 등의 리지드(rigid) 타입 매트릭스일 수 있다. 또한, PMMA(polymethyl metacrylate, 폴리메틸 메타크릴레이트) 또는 PET(polyethylene terephthalate, 폴리에텔렌 테레프탈레이트) 등의 폴리머 매트릭스가 사용될 수도 있다. 그러나, 매트릭스(110)의 종류가 이에 한정되는 것은 아니다. The matrix 110 may be a thermal grease type matrix such as a silicone resin, or alternatively, the matrix 110 may be a rigid type matrix such as an epoxy resin. In addition, a polymer matrix such as polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET) may be used. However, the type of the matrix 110 is not limited thereto.
PCM 볼(120)은 PCM 코어(122) 및 PCM 코어(122)를 둘러싸는 제1 피복층(124)을 포함할 수 있다. PCM 코어(122)는 구형 또는 타원형 등 다양한 형상으로 형성될 수 있고, 제1 피복층(124)은 소정의 두께로 PCM 코어(122)를 둘러싸는 형상으로 형성될 수 있다. 예를 들어, 제1 피복층(124)은 약 10-200 nm의 두께로 형성될 수 있으나, 제1 피복층(124)의 두께가 이에 한정되는 것은 아니며, PCM 코어(122)의 형상과 제1 피복층(124)의 종류, 반도체 칩 패키지의 종류에 따라 다양한 두께를 가질 수 있다. PCM ball 120 may include a PCM core 122 and a first coating layer 124 surrounding the PCM core 122. The PCM core 122 may be formed in various shapes such as spherical or elliptical, and the first coating layer 124 may be formed in a shape surrounding the PCM core 122 with a predetermined thickness. For example, the first coating layer 124 may be formed to a thickness of about 10-200 nm, but the thickness of the first coating layer 124 is not limited thereto, and the shape of the PCM core 122 and the first coating layer are limited thereto. The thickness of the semiconductor device may vary depending on the type of the semiconductor chip 124 and the type of the semiconductor chip package.
예시적인 실시예들에 있어서, PCM 코어(122)는 파라핀(paraffin), 폴리에틸렌 글리콜(polyethylene glycol), 무기수화물(inorganic hydrates), 지방산(fatty acid) 등의 상변화 물질을 포함할 수 있다. PCM 코어(122)는 50 내지 200℃의 범위인 융점을 가질 수 있다. 한편, PCM 코어(122)는 융점이 서로 다른 두 가지 이상의 물질을 조합하여 포함할 수도 있다. 예를 들어, PCM 코어(122)는 실리콘계 수지 및 파라핀계 수지를 모두 포함하도록 형성될 수도 있다. In example embodiments, the PCM core 122 may include a phase change material such as paraffin, polyethylene glycol, inorganic hydrates, fatty acids, and the like. PCM core 122 may have a melting point in the range of 50-200 ° C. The PCM core 122 may include a combination of two or more materials having different melting points. For example, the PCM core 122 may be formed to include both silicone resin and paraffin resin.
제1 피복층(124)은 전기 전도성 물질을 포함할 수 있다. 예시적인 실시예들에 있어서, 제1 피복층(124)은 금속, 그래핀(graffin), 카본 블랙(carbon black), 카본 나노 튜브(carbon nanotube), 또는 전도성 폴리머 등을 포함할 수 있다. 제1 피복층(124)이 금속을 포함하는 경우, 제1 피복층(124)은 은, 금, 구리, 알루미늄 등의 금속을 포함할 수 있다. 제1 피복층(124)이 전도성 폴리머를 포함하는 경우, 제1 피복층(124)은 폴리피롤(polypyrrol), 폴리아세틸렌(polyacetylene), 폴리피페닐린(poly(p-phenylene)), 폴리설퍼니트릴(poly(sulfurnitrile)), 폴리페닐린 설파이드(poly(phenylene sulfide)), 폴리아닐린(polyaniline), 폴리피페닐린비닐렌(poly(p-phenylenevinylene)), PEDOT:PSS [poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate)] 또는 이들의 유도체들(derivatives)을 포함할 수 있다. 제1 피복층(124)의 융점은 PCM 코어(122)의 융점보다 높을 수 있다. 제1 피복층(124)은 단일층으로 형성되어 PCM 코어(122)를 둘러쌀 수도 있고, 이와는 달리, 2 층 이상의 다중막 구조로 형성되어 PCM 코어(122)를 둘러쌀 수도 있다. The first coating layer 124 may include an electrically conductive material. In example embodiments, the first coating layer 124 may include metal, graphene, carbon black, carbon nanotube, conductive polymer, or the like. When the first coating layer 124 includes a metal, the first coating layer 124 may include a metal such as silver, gold, copper, aluminum, or the like. When the first coating layer 124 includes a conductive polymer, the first coating layer 124 may be made of polypyrrol, polyacetylene, poly (p-phenylene), polysulfurnitrile ( poly (sulfurnitrile)), poly (phenylene sulfide), polyaniline, poly (p-phenylenevinylene), PEDOT: PSS [poly (3,4-ethylenedioxythiophene) poly (styrene sulfonate)] or derivatives thereof. The melting point of the first cladding layer 124 may be higher than the melting point of the PCM core 122. The first coating layer 124 may be formed as a single layer to surround the PCM core 122, or alternatively, the first coating layer 124 may be formed as a multilayer structure having two or more layers to surround the PCM core 122.
한편, PCM 볼(120)은 제1 피복층(124)과 PCM 코어(122) 사이에 형성된 폴리머 중간층(126)을 더 포함할 수도 있다. 예를 들어, 폴리머 중간층(126)은 PCM 코어(122)에 대하여 활성을 갖지 않는 물질을 포함할 수 있다. PCM 코어(122)가 제1 피복층(124)과 직접 접촉하여 부반응(side reaction)이 발생하는 경우, 폴리머 중간층(126)을 PCM 코어(122) 및 제1 피복층(124) 사이에 형성함으로써 이러한 부반응 등 원치 않는 반응의 발생 및 PCM 코어(122)의 손상을 방지할 수 있다. The PCM ball 120 may further include a polymer interlayer 126 formed between the first coating layer 124 and the PCM core 122. For example, the polymer interlayer 126 may comprise a material that is not active with respect to the PCM core 122. When the side reaction occurs because the PCM core 122 is in direct contact with the first coating layer 124, this side reaction is formed by forming a polymer interlayer 126 between the PCM core 122 and the first coating layer 124. The occurrence of unwanted reactions and damage to the PCM core 122 can be prevented.
PCM 코어(122)는 반도체 칩의 작동 온도 범위 내에서 고상에서 액상으로, 또는 액상에서 고상으로 상변화를 일으킬 수 있다. 예를 들어, 반도체 칩이 작동할 때 발열이 발생하여 반도체 칩의 온도가 약 100℃ 이상까지 상승할 수 있고, PCM 코어(122)로서 융점이 약 62℃인 파라핀 수지를 사용하는 경우, PCM 코어(122)는 약 62℃에서 고상에서 액상으로 상변화를 일으킬 수 있다. 이러한 상변화 과정에서 파라핀의 잠열(latent heat)은 약 145-240kJ/kg인 것으로 보고되었다(M. N. A. Hawlader, M. S. Uddin, M. M. Khin, "Microencapsulated PCM Thermal-Energy Storage System," Appl. Energy 74, 195 (2003)을 참조하였음). 즉, 파라핀이 고상에서 액상으로 상변화하는 과정에서 이러한 잠열을 흡수하는 동안 PCM 코어(122)의 온도는 일정하게 유지된다. 따라서, PCM 코어(122)를 포함한 열 계면 물질(100)은 반도체 칩의 온도를 낮게 유지시킬 수 있다. 한편, 상변화 물질의 온도 변화와 관련된 내용은 도 8을 참조로 추후에 상세히 설명한다.The PCM core 122 may cause a phase change from the solid phase to the liquid phase, or from the liquid phase to the solid phase within the operating temperature range of the semiconductor chip. For example, when the semiconductor chip is operated, heat may be generated to raise the temperature of the semiconductor chip to about 100 ° C. or more, and when the paraffin resin having a melting point of about 62 ° C. is used as the PCM core 122, the PCM core is used. Reference numeral 122 may cause a phase change from a solid phase to a liquid phase at about 62 ° C. In this phase change, the latent heat of paraffin was reported to be about 145-240 kJ / kg (MNA Hawlader, MS Uddin, MM Khin, "Microencapsulated PCM Thermal-Energy Storage System," Appl. Energy 74, 195 ( 2003). That is, the temperature of the PCM core 122 is kept constant while absorbing this latent heat in the process of paraffin phase transition from solid phase to liquid phase. Accordingly, the thermal interface material 100 including the PCM core 122 may keep the temperature of the semiconductor chip low. Meanwhile, the contents related to the temperature change of the phase change material will be described later in detail with reference to FIG. 8.
예시적인 실시예들에 있어서, 제1 피복층(124)은 PCM 코어(122)보다 높은 융점을 가진다. 예를 들어, 제1 피복층(124)의 융점은 반도체 칩의 작동 온도 범위보다 높을 수 있다. 따라서, PCM 코어(122)가 고상에서 액상으로 상변화를 일으킨 이후에도 제1 피복층(124)은 용융되지 않고 PCM 코어(122)를 둘러싼 채 형태를 유지시킬 수 있다. 반도체 칩의 온도가 감소하는 경우 제1 피복층(124) 내부에 담겨진 PCM 코어(122)는 액상에서 고상으로 다시 상변화할 수 있다. In example embodiments, the first cladding layer 124 has a higher melting point than the PCM core 122. For example, the melting point of the first coating layer 124 may be higher than the operating temperature range of the semiconductor chip. Therefore, even after the PCM core 122 causes a phase change from a solid phase to a liquid phase, the first coating layer 124 may not be melted and may remain in shape while surrounding the PCM core 122. When the temperature of the semiconductor chip decreases, the PCM core 122 contained in the first coating layer 124 may change phase from the liquid phase to the solid phase again.
폴리머 볼(130)은 폴리머 코어(132) 및 폴리머 코어(132)를 둘러싸는 제2 피복층(134)을 포함할 수 있다. 폴리머 코어(132)는 구형 또는 타원형 등 다양한 형상으로 형성될 수 있고, 제2 피복층(134)은 소정의 두께로 폴리머 코어를 둘러싸는 형상을 형성될 수 있다. 예를 들어, 제2 피복층(134)은 약 10-200 nm의 두께로 형성될 수 있으나 이에 한정되는 것은 아니며, 폴리머 코어(132)의 형상과 제2 피복층(134)의 종류, 반도체 칩 패키지의 종류에 따라 다양한 두께를 가질 수 있다.The polymer ball 130 may include a polymer core 132 and a second coating layer 134 surrounding the polymer core 132. The polymer core 132 may be formed in various shapes such as spherical or elliptical, and the second coating layer 134 may have a shape surrounding the polymer core with a predetermined thickness. For example, the second coating layer 134 may be formed to a thickness of about 10-200 nm, but is not limited thereto. The shape of the polymer core 132, the type of the second coating layer 134, and the semiconductor chip package may be formed. It may have a variety of thickness depending on the type.
폴리머 코어(132)는 폴리에스터 수지, 실리콘계 수지 등의 폴리머 재료를 포함할 수 있다. 폴리머 코어(132)의 종류를 예시적으로 열거하였으나, 폴리머 코어(132)의 종류가 이에 한정되는 것은 아니다. The polymer core 132 may include a polymer material such as polyester resin or silicone resin. Although the type of the polymer core 132 is exemplarily listed, the type of the polymer core 132 is not limited thereto.
제2 피복층(134)은 금속, 그래핀, 카본 블랙, 카본 나노 튜브, 또는 전도성 폴리머와 같은 전도성 물질을 포함할 수 있다. 제2 피복층(134)은 전기 전도성 물질을 포함하며, 열 전도도가 높은 물질일 수 있다. The second coating layer 134 may include a conductive material such as metal, graphene, carbon black, carbon nanotube, or conductive polymer. The second coating layer 134 includes an electrically conductive material and may be a material having high thermal conductivity.
폴리머 볼(130)은 열 계면 물질(100) 내에 소정의 농도를 가지며 분산될 수 있다. 상기 소정의 농도는 예를 들어 수 내지 수십 부피%에 해당할 수 있다. 예를 들어, 폴리머 볼(130)의 농도가 높을 때 열 계면 물질(100) 내에서 폴리머 볼들(130)이 서로 연결될 수 있다. 폴리머 볼들(130)의 표면에 형성되는 제2 피복층(134)은 전기 전도성 물질이거나 그리고/또는 열 전도성 물질이므로, 인접한 폴리머 볼들(130)의 제2 피복층들(134)이 서로 연결되어 전기 또는 열의 패스(path)를 형성할 수 있다. 따라서, 반도체 칩(도시되지 않음) 및 방열판(도시되지 않음)을 열 계면 물질(100)을 통해 연결한 경우, 상기 반도체 칩에서 발생한 열이 폴리머 볼들(130)의 열 패스를 통해 상기 방열판으로 더 쉽게 전달될 수 있다.The polymer balls 130 may be dispersed at a predetermined concentration in the thermal interface material 100. The predetermined concentration may correspond, for example, to several tens of volume percent. For example, when the concentration of the polymer balls 130 is high, the polymer balls 130 may be connected to each other in the thermal interface material 100. Since the second coating layer 134 formed on the surface of the polymer balls 130 is an electrically conductive material and / or a thermally conductive material, the second coating layers 134 of the adjacent polymer balls 130 may be connected to each other to be electrically or thermally connected. Paths can be formed. Therefore, when a semiconductor chip (not shown) and a heat sink (not shown) are connected through the thermal interface material 100, heat generated from the semiconductor chip is further transferred to the heat sink through the heat path of the polymer balls 130. Can be easily delivered.
본 발명에 따른 열 계면 물질(100)은, 폴리머 매트릭스(110) 내에 분산된 PCM 볼들(120)이 반도체 칩에서 발생할 수 있는 열을 흡수하여 고상에서 액상으로 상변화를 일으킬 수 있다. 상기 상변화 과정에서 주변의 열을 흡수하므로 열 계면 물질(100)은 방열 효과가 우수할 수 있다. 또한, 폴리머 매트릭스(110) 내에 분산된 폴리머 볼(130)에 의해 상기 반도체 칩에서 발생할 수 있는 열이 방열판으로 더 쉽게 전달될 수 있다.In the thermal interface material 100 according to the present invention, the PCM balls 120 dispersed in the polymer matrix 110 may absorb heat that may occur in the semiconductor chip, thereby causing a phase change from a solid phase to a liquid phase. Since the surrounding heat is absorbed in the phase change process, the thermal interface material 100 may have an excellent heat dissipation effect. In addition, heat generated in the semiconductor chip may be more easily transferred to the heat sink by the polymer balls 130 dispersed in the polymer matrix 110.
도 2는 본 발명의 다른 실시예들에 따른 열 계면 물질(200)을 나타내는 단면도이다. 2 is a cross-sectional view illustrating a thermal interface material 200 according to other embodiments of the present invention.
도 2를 참조하면, 열 계면 물질(200)은 매트릭스(210) 내부에 분산된 복수 개의 PCM 볼들(220)을 포함할 수 있다. Referring to FIG. 2, the thermal interface material 200 may include a plurality of PCM balls 220 dispersed in the matrix 210.
매트릭스(210)는 그래핀, 카본 나노 튜브, 전도성 고분자 등이 분산된 폴리머 매트릭스일 수 있다. 예시적인 실시예들에 있어서, 매트릭스(210)는 폴리머 내부에 카본 나노 튜브가 소정의 농도로 분산되어 있을 수 있다. 상기 폴리머 매트릭스 내에 분산된 카본 나노 튜브, 그래핀 또는 전도성 고분자 등은 상기 폴리머 매트릭스보다 열 전도도가 높은 물질일 수 있고, 따라서, 카본 나노 튜브, 그래핀 또는 전도성 고분자 등이 분산된 매트릭스(210)는 반도체 칩(도시되지 않음)에서 발생할 수 있는 열이 방열판(도시되지 않음)으로 더 쉽게 전달될 수 있게 한다.The matrix 210 may be a polymer matrix in which graphene, carbon nanotubes, conductive polymers, etc. are dispersed. In example embodiments, the matrix 210 may have carbon nanotubes dispersed at a predetermined concentration inside the polymer. The carbon nanotubes, graphene or conductive polymers dispersed in the polymer matrix may be a material having a higher thermal conductivity than the polymer matrix. Thus, the matrix 210 in which the carbon nanotubes, graphene or conductive polymers are dispersed may be formed. Heat that may be generated in the semiconductor chip (not shown) may be more easily transferred to the heat sink (not shown).
PCM 볼들(220)은 PCM 코어(222)와 PCM 코어(222)를 둘러싸는 제1 피복층(224)을 포함할 수 있다. PCM 코어(222)는 반도체 칩의 작동 온도 범위에서 고상으로부터 액상으로 또는 액상으로부터 고상으로 상변화를 일으키는 물질을 포함할 수 있다. 예를 들어, PCM 코어(222)의 융점은 약 50 내지 약 150도에 해당할 수 있다. 제1 피복층(224)은 전도성 물질을 포함할 수 있다. 제1 피복층(224)은 하나 이상의 층으로 형성될 수 있다. 또한, PCM 코어(222) 및 제1 피복층(224) 사이에 폴리머 중간층(226)이 더 형성될 수 있다. PCM balls 220 may include a PCM core 222 and a first covering layer 224 surrounding the PCM core 222. The PCM core 222 may include a material causing a phase change from a solid phase to a liquid phase or from a liquid phase to a solid phase in the operating temperature range of the semiconductor chip. For example, the melting point of the PCM core 222 may correspond to about 50 to about 150 degrees. The first coating layer 224 may include a conductive material. The first coating layer 224 may be formed of one or more layers. In addition, a polymer interlayer 226 may be further formed between the PCM core 222 and the first coating layer 224.
PCM 볼(220)은 반도체 칩에서 발생한 열을 흡수하여 고상에서 액상으로 상변화를 일으킬 수 있다. 따라서, 열 계면 물질(200)을 부착한 반도체 칩의 이상 발열 현상 및 이상 고온 현상 등을 방지할 수 있다. The PCM ball 220 may absorb the heat generated from the semiconductor chip to cause a phase change from a solid phase to a liquid phase. Therefore, abnormal heat generation phenomenon and abnormal high temperature phenomenon of the semiconductor chip having the thermal interface material 200 attached thereto can be prevented.
본 발명에 따른 열 계면 물질(200)은, 열 전도도가 높은 폴리머 매트릭스 또는 카본 나노 튜브가 분산된 매트릭스를 포함하며 매트릭스 내에 분산된 PCM 볼들(220)을 포함한다. 따라서, PCM 볼들(220)의 상변화 과정에서 주변의 열을 흡수하므로 열 계면 물질(200)은 방열 효과가 우수할 수 있다.The thermal interface material 200 according to the present invention includes a polymer matrix having a high thermal conductivity or a matrix in which carbon nanotubes are dispersed and include PCM balls 220 dispersed in the matrix. Therefore, the thermal interface material 200 may have excellent heat dissipation effect because the surrounding heat is absorbed during the phase change process of the PCM balls 220.
도 3은 본 발명의 다른 실시예들에 따른 열 계면 물질(300)을 나타내는 단면도이다.3 is a cross-sectional view illustrating a thermal interface material 300 according to other embodiments of the present invention.
도 3을 참조하면, 열 계면 물질(300)은 매트릭스(310) 및 매트릭스(310)에 형성된 포어들(pores)(312) 내부의 PCM 층(320)을 포함할 수 있다. Referring to FIG. 3, the thermal interface material 300 may include a matrix 310 and a PCM layer 320 inside pores 312 formed in the matrix 310.
매트릭스(310)는 내부에 복수 개의 포어들(312)이 형성된 다공성 재료를 포함할 수 있다. 예를 들어, 매트릭스(310)는 다공성 카본 재료 또는 카본 폼(carbon foam)을 포함할 수 있다. 매트릭스(310) 내부의 포어들(312)은 다양한 사이즈를 가지며 서로 연결될 수 있다. 상기 매트릭스(310)는 50 W/mK 이상의 열전도도를 갖는 다공성 카본 재료를 포함할 수 있다. 예를 들어, 매트릭스(310)는 50 W/mK 이상의 열전도도를 갖는 카본 폼을 포함할 수 있다. The matrix 310 may include a porous material having a plurality of pores 312 formed therein. For example, the matrix 310 may comprise a porous carbon material or carbon foam. The pores 312 in the matrix 310 may have various sizes and be connected to each other. The matrix 310 may include a porous carbon material having a thermal conductivity of 50 W / mK or more. For example, the matrix 310 may comprise carbon foam having a thermal conductivity of at least 50 W / mK.
PCM 층(320)은 매트릭스(310)의 포어들(312) 내부에 컨포말하게 형성될 수 있다. PCM 층(320)은 매트릭스(310)의 포어들(312)의 측벽 상에 소정의 두께로 형성될 수 있고, 예를 들어, 포어들(312) 직경이 작은 경우 포어(312) 내부를 채우도록 형성될 수 있다. PCM layer 320 may be conformally formed within pores 312 of matrix 310. The PCM layer 320 may be formed to a predetermined thickness on the sidewalls of the pores 312 of the matrix 310, such as to fill the interior of the pores 312 when the pores 312 are small in diameter. Can be formed.
상기 매트릭스(310)의 포어들(312) 내부에 PCM 층(320)을 컨포말하게 형성하기 위하여, PCM 물질을 준비하고, 상기 PCM 물질의 융점 이상의 온도로 상기 PCM 물질을 가열할 수 있다. 예를 들어, 상기 PCM 물질로서 파라핀을 사용할 때, 약 60 내지 70℃의 온도로 파라핀을 가열하여 용액 상태의 파라핀 물질을 포함하는 PCM 용액을 준비할 수 있다. 이후, 다공성 매트릭스(310)를 준비하고, 상기 PCM 용액 내에 다공성 매트릭스(310)을 침지시킬(immerse) 수 있다. 이후, 상기 다공성 매트릭스(310)를 상기 PCM 용액으로부터 분리하여 냉각시킬 수 있다. 이 경우 다공성 매트릭스(310)의 포어들(312) 내부에 PCM 층(320)이 컨포말하게 형성될 수 있다. 또한, 포어들(312) 사이즈가 작은 경우 PCM 층(320)은 포어들(312) 내부를 채우도록 형성될 수 있다. PCM 층(320)의 두께는 포어(312) 사이즈, PCM 재료의 농도, 침지 조건 등에 따라 달라질 수 있다.In order to conformally form the PCM layer 320 inside the pores 312 of the matrix 310, a PCM material may be prepared, and the PCM material may be heated to a temperature above the melting point of the PCM material. For example, when using paraffin as the PCM material, the paraffin may be heated to a temperature of about 60 to 70 ° C. to prepare a PCM solution including the paraffin material in solution. Thereafter, the porous matrix 310 may be prepared, and the porous matrix 310 may be immersed in the PCM solution. Thereafter, the porous matrix 310 may be separated from the PCM solution and cooled. In this case, the PCM layer 320 may be conformally formed inside the pores 312 of the porous matrix 310. Also, when the pores 312 are small in size, the PCM layer 320 may be formed to fill the interior of the pores 312. The thickness of the PCM layer 320 may vary depending on the pore 312 size, concentration of PCM material, immersion conditions, and the like.
열 계면 물질(300)은 포어들(312) 내부에 형성된 PCM 층(320)을 포함하며, PCM 층(320)은 반도체 칩에서 발생한 열을 흡수하여 고상에서 액상으로 상변화를 일으킬 수 있다. 따라서, 열 계면 물질(200)을 부착한 반도체 칩의 이상 발열 현상 및 이상 고온 현상 등을 방지할 수 있다.The thermal interface material 300 may include a PCM layer 320 formed in the pores 312, and the PCM layer 320 may absorb heat generated from the semiconductor chip to cause a phase change from a solid phase to a liquid phase. Therefore, abnormal heat generation phenomenon and abnormal high temperature phenomenon of the semiconductor chip having the thermal interface material 200 attached thereto can be prevented.
도 4는 본 발명의 예시적인 실시예들에 따른 반도체 칩 패키지(1000)를 나타내는 단면도이다. 4 is a cross-sectional view illustrating a semiconductor chip package 1000 according to some example embodiments of the inventive concepts.
도 4를 참조하면, 반도체 칩 패키지(1000)는 인쇄 회로 기판(1010), 반도체 칩(1020), 방열판(1030) 및 열 계면 물질(1100)을 포함할 수 있다. Referring to FIG. 4, the semiconductor chip package 1000 may include a printed circuit board 1010, a semiconductor chip 1020, a heat sink 1030, and a thermal interface material 1100.
반도체 칩(1020)은 인쇄 회로 기판(1010) 상에 실장될 수 있다. 예를 들어, 반도체 칩(1020)의 활성면에 형성된 범프(1040)를 통해 인쇄 회로 기판(1010) 상의 패드(1050)에 전기적으로 연결될 수 있다. 반도체 칩(1020)의 활성면과 인쇄 회로 기판(1010) 사이에는 언더필(1060)이 채워질 수 있다. 예를 들면, 언더필(1060)은 에폭시 수지 등을 포함할 수 있다. 한편, 도 4에서는 반도체 칩(1020)이 플립칩 본딩(flip-chip bonding) 방식을 통해 인쇄 회로 기판(1010) 상에 실장된 것을 예시적으로 도시하였으나, 본 발명이 이에 한정되는 것은 아니며, 본딩 와이어(도시되지 않음)가 반도체 칩(1020)과 인쇄 회로 기판(1010)을 연결하는 방식으로 반도체 칩(1020)이 인쇄 회로 기판(1010) 상에 실장될 수도 있다. 또한, 도 4에서는 하나의 반도체 칩(1020)이 인쇄 회로 기판(1010) 상에 실장된 것을 도시하였으나, 이와는 달리 두 개 이상의 반도체 칩들(1020)이 적층되고, 와이어 본딩(도시되지 않음) 또는 스루 실리콘 비아(through silicon via, TSV)(도시되지 않음)를 통해 서로 연결되어 인쇄 회로 기판(1010) 상에 실장될 수도 있다. The semiconductor chip 1020 may be mounted on the printed circuit board 1010. For example, the bump 1040 formed on the active surface of the semiconductor chip 1020 may be electrically connected to the pad 1050 on the printed circuit board 1010. An underfill 1060 may be filled between the active surface of the semiconductor chip 1020 and the printed circuit board 1010. For example, the underfill 1060 may include an epoxy resin. Meanwhile, in FIG. 4, the semiconductor chip 1020 is mounted on the printed circuit board 1010 through flip-chip bonding, but the present invention is not limited thereto. The semiconductor chip 1020 may be mounted on the printed circuit board 1010 in such a manner that a wire (not shown) connects the semiconductor chip 1020 and the printed circuit board 1010. In addition, although FIG. 4 illustrates that one semiconductor chip 1020 is mounted on a printed circuit board 1010, two or more semiconductor chips 1020 may be stacked, wire bonded (not shown), or through. It may be connected to each other through a silicon via (TSV) (not shown) and mounted on the printed circuit board 1010.
인쇄 회로 기판(1010) 상에 반도체 칩(1020)을 커버하는 방열판(1030)이 부착될 수 있다. 방열판(1030)은 반도체 칩(1020)에서 발생하는 열을 효율적으로 외부로 발산할 수 있도록 열전도도가 높은 물질을 사용하여 형성할 수 있다. 예시적인 실시예들에 있어서, 방열판(1030)은 구리(Cu), 알루미늄(Al), 텅스텐구리(WCu), 탄화규소알루미늄(AlSiC), 질화 알루미늄(AlN), 산화베릴륨(BeO) 등을 포함할 수 있다. 또한, 방열판(1030)은 전술한 열전도도가 높은 물질 표면에 니켈(Ni), 은(Ag), 금(Au), 주석(Sn), 크롬(Cr) 등의 금속 중 적어도 하나를 코팅하여 형성될 수도 있다. 예를 들어, 방열판(1030)은 탄화규소알루미늄(AlSiC)을 모재로 하고, 상기 모재의 표면에 니켈(Ni)을 포함하는 도금층이 더 형성될 수도 있다. 방열판(1030)은 반도체 칩(1020)으로부터의 열 방출을 최대화할 수 있도록 다양한 형상으로 형성될 수 있다. 도시되지는 않았지만, 방열판(1030)의 상부에 요철부가 형성되거나, 방열판(1030) 상부가 핀(fin) 형상으로 형성되어 방열판(1030)의 표면적을 증가시킬 수도 있다. 방열판(1030)은 비전도성 접착제(nonconductive adhesive)(1090)를 통하여 인쇄 회로 기판 상에 부착될 수 있다.A heat sink 1030 covering the semiconductor chip 1020 may be attached to the printed circuit board 1010. The heat sink 1030 may be formed using a material having high thermal conductivity to efficiently dissipate heat generated from the semiconductor chip 1020 to the outside. In exemplary embodiments, the heat sink 1030 includes copper (Cu), aluminum (Al), tungsten copper (WCu), aluminum carbide (AlSiC), aluminum nitride (AlN), beryllium oxide (BeO), and the like. can do. In addition, the heat sink 1030 is formed by coating at least one of metals such as nickel (Ni), silver (Ag), gold (Au), tin (Sn), and chromium (Cr) on the surface of the material having high thermal conductivity. May be For example, the heat sink 1030 may be formed of silicon carbide (AlSiC) as a base material, and a plating layer including nickel (Ni) may be further formed on the surface of the base material. The heat sink 1030 may be formed in various shapes to maximize heat dissipation from the semiconductor chip 1020. Although not shown, an uneven portion may be formed in an upper portion of the heat sink 1030, or an upper portion of the heat sink 1030 may be formed in a fin shape to increase the surface area of the heat sink 1030. The heat sink 1030 may be attached onto the printed circuit board via a nonconductive adhesive 1090.
열 계면 물질(1100)은 반도체 칩(1020)의 상면과 방열판(1030)의 하부면 사이에 개재될 수 있다. 즉, 열 계면 물질(1100)의 제1 면(1020)은 반도체 칩의 상면과 접촉하고, 열 계면 물질(1100)의 제2 면은 방열판(1030)의 하부면과 접촉할 수 있다. 열 계면 물질(1100)은 반도체 칩(1020)과 방열판(1030) 사이에서, 반도체 칩(1020)의 상면의 일부 상에 형성될 수도 있고, 반도체 칩(1020)의 상면 전체를 덮도록 형성될 수도 있다. 열 계면 물질(1100)은 폴리머 매트릭스(1110) 내에 분산된 복수의 PCM 볼들(1120) 및 복수의 폴리머 볼들(1130)을 포함할 수 있다. 복수의 PCM 볼들(1120)은 각각 PCM 물질로 이루어진 PCM 코어(1122), 및 상기 PCM 코어(1122)를 둘러싸며 전도성 물질로 이루어진 제1 피복층(1124)을 포함할 수 있다. 제1 피복층(1124) 및 PCM 코어(1122) 사이에 폴리머 중간층(1126)이 더 형성될 수도 있다. 복수의 폴리머 볼들(1130)은 각각 폴리머 물질로 이루어진 폴리머 코어(1132), 및 상기 폴리머 코어(1132)를 둘러싸며 전도성 물질로 이루어진 제2 피복층(1134)을 포함할 수 있다. 열 계면 물질(1100)은 도 1을 참조로 설명한 열 계면 물질(100)과 유사할 수 있다. The thermal interface material 1100 may be interposed between the top surface of the semiconductor chip 1020 and the bottom surface of the heat sink 1030. That is, the first surface 1020 of the thermal interface material 1100 may contact the upper surface of the semiconductor chip, and the second surface of the thermal interface material 1100 may contact the lower surface of the heat sink 1030. The thermal interface material 1100 may be formed on a portion of the upper surface of the semiconductor chip 1020 between the semiconductor chip 1020 and the heat sink 1030, or may cover the entire upper surface of the semiconductor chip 1020. have. Thermal interface material 1100 may include a plurality of PCM balls 1120 and a plurality of polymer balls 1130 dispersed in a polymer matrix 1110. The plurality of PCM balls 1120 may each include a PCM core 1122 made of PCM material, and a first coating layer 1124 surrounding the PCM core 1122 and made of a conductive material. A polymer interlayer 1126 may be further formed between the first cladding layer 1124 and the PCM core 1122. The plurality of polymer balls 1130 may each include a polymer core 1132 made of a polymer material, and a second coating layer 1134 made of a conductive material surrounding the polymer core 1132. Thermal interface material 1100 may be similar to thermal interface material 100 described with reference to FIG. 1.
한편, 반도체 칩(1020) 상면 및 열 계면 물질(1100) 사이에 절연층(1070)이 개재될 수도 있다. 절연층(1070)은 각각 전도성 물질을 포함하는 제1 피복층(1124) 및 제2 피복층(1134)을 포함하는 PCM 볼들(1120) 및 다수의 폴리머 볼들(1130)로부터 반도체 칩(1020)을 전기적으로 절연시킬 수 있다.Meanwhile, an insulating layer 1070 may be interposed between the upper surface of the semiconductor chip 1020 and the thermal interface material 1100. The insulating layer 1070 electrically connects the semiconductor chip 1020 from the PCM balls 1120 and the plurality of polymer balls 1130 including the first coating layer 1124 and the second coating layer 1134 each including a conductive material. It can be insulated.
인쇄 회로 기판(1010)의 하부에는 복수의 솔더볼들(1080)이 형성될 수 있다. A plurality of solder balls 1080 may be formed below the printed circuit board 1010.
본 발명에 따른 반도체 패키지(1000)는 열 계면 물질(1100)의 열 전도도가 높아 반도체 칩(1020)의 작동 시 발생하는 열을 방열판(1030)으로 효과적으로 전달할 수 있다. 또한, 열 계면 물질(1100) 내의 PCM 볼들(1120)은 소정의 잠열을 가지며 반도체 칩(1020)의 작동 온도 범위 내에서 상변화할 수 있는 물질들을 포함하므로, 상변화가 일어나는 과정에서 반도체 칩(1020)의 작동 시 발생할 수 있는 열을 흡수할 수 있고, 이에 따라 반도체 칩 패키지(1000)의 온도를 효과적으로 감소시킬 수 있다.The semiconductor package 1000 according to the present invention has a high thermal conductivity of the thermal interface material 1100, thereby effectively transferring heat generated when the semiconductor chip 1020 is operated to the heat sink 1030. In addition, since the PCM balls 1120 in the thermal interface material 1100 include materials that have a predetermined latent heat and may phase change within an operating temperature range of the semiconductor chip 1020, the semiconductor chip ( The heat generated during operation of the 1020 may be absorbed, thereby effectively reducing the temperature of the semiconductor chip package 1000.
한편, 본 발명에 따른 반도체 칩 패키지(1000)는 다양한 전자 장치에 포함될 수 있다. 예를 들어, 상기 전자 장치는 노트북, 데스크탑, 핸드폰, 스마트폰, PDA, 디지털 카메라, 캠코더, 디스플레이 장치, 오디오, TV, LED 장치 등일 수 있다. 그러나, 상기 전자 장치의 종류가 이에 한정되는 것은 아니다. Meanwhile, the semiconductor chip package 1000 according to the present invention may be included in various electronic devices. For example, the electronic device may be a notebook, a desktop, a mobile phone, a smartphone, a PDA, a digital camera, a camcorder, a display device, an audio, a TV, an LED device, and the like. However, the type of the electronic device is not limited thereto.
도 5는 본 발명의 예시적인 실시예들에 따른 반도체 칩 패키지(1000a)를 나타내는 단면도이다. 상기 반도체 칩 패키지(1000a)는 열 계면 물질(1200)을 제외하면 도 4를 참조로 설명한 반도체 칩 패키지(1000)와 실질적으로 동일하므로, 차이점을 중심으로 설명한다.5 is a cross-sectional view illustrating a semiconductor chip package 1000a according to some example embodiments of the inventive concepts. Since the semiconductor chip package 1000a is substantially the same as the semiconductor chip package 1000 described with reference to FIG. 4 except for the thermal interface material 1200, the differences will be described with reference to the difference.
도 5를 참조하면, 열 계면 물질(1200)은 폴리머 매트릭스(1210) 및 폴리머 매트릭스(1210) 내에 분산된 다수의 PCM 볼들(1220)을 포함할 수 있다. 폴리머 매트릭스(1210)에 그래핀, 카본 나노 튜브, 전도성 고분자 등이 분산될 수 있다. 상기 PCM 볼들(1220)은 PCM 코어(1222) 및 PCM 코어(1222)를 둘러싸는 제1 피복층(1224)으로 구성될 수 있다. 상기 열 계면 물질(1200)은 도 2를 참조로 설명한 열 계면 물질(200)과 유사할 수 있다.Referring to FIG. 5, thermal interface material 1200 may include a polymer matrix 1210 and a plurality of PCM balls 1220 dispersed within polymer matrix 1210. Graphene, carbon nanotubes, conductive polymers, etc. may be dispersed in the polymer matrix 1210. The PCM balls 1220 may be composed of a PCM core 1222 and a first coating layer 1224 surrounding the PCM core 1222. The thermal interface material 1200 may be similar to the thermal interface material 200 described with reference to FIG. 2.
도 6은 본 발명의 예시적인 실시예들에 따른 반도체 칩 패키지(1000b)를 나타내는 단면도이다. 상기 반도체 칩 패키지(1000b)는 열 계면 물질(1300)을 제외하면 도 4를 참조로 설명한 반도체 칩 패키지(1000)와 실질적으로 동일하므로, 차이점을 중심으로 설명한다.6 is a cross-sectional view illustrating a semiconductor chip package 1000b according to some example embodiments of the inventive concepts. Since the semiconductor chip package 1000b is substantially the same as the semiconductor chip package 1000 described with reference to FIG. 4 except for the thermal interface material 1300, the difference will be described.
도 6을 참조하면, 열 계면 물질(1300)은 매트릭스(1310) 및 매트릭스(1310)에 형성된 포어들(1312) 내부의 PCM 층(1320)을 포함할 수 있다. 예를 들어, 매트릭스(1310)는 다공성 카본 재료 또는 카본 폼을 포함할 수 있다. PCM 층(1320)은 매트릭스(1310)의 포어들(1312) 내부에 컨포말하게 형성될 수 있다. PCM 층(1320)은 매트릭스(1310)의 포어들(1312)의 측벽 상에 소정의 두께로 형성될 수 있고, 예를 들어, 포어들(1312) 직경이 작은 경우 상기 포어(1312) 내부를 채우도록 형성될 수 있다. Referring to FIG. 6, the thermal interface material 1300 may include a matrix 1310 and a PCM layer 1320 inside the pores 1312 formed in the matrix 1310. For example, the matrix 1310 may comprise a porous carbon material or carbon foam. The PCM layer 1320 may be conformally formed inside the pores 1312 of the matrix 1310. The PCM layer 1320 may be formed to a predetermined thickness on the sidewalls of the pores 1312 of the matrix 1310, for example filling the interior of the pore 1312 when the pores 1312 are small in diameter. It can be formed to be.
도 7은 본 발명의 예시적인 실시예들에 따른 반도체 칩 패키지(2000)를 나타내는 단면도이다. 상기 반도체 칩 패키지(2000)는 방열판(2030)의 구조를 제외하면 도 4를 참조로 설명한 반도체 칩 패키지(1000)와 실질적으로 동일하므로, 차이점을 중심으로 설명한다.7 is a cross-sectional view illustrating a semiconductor chip package 2000 according to some example embodiments of the inventive concepts. Since the semiconductor chip package 2000 is substantially the same as the semiconductor chip package 1000 described with reference to FIG. 4 except for the structure of the heat sink 2030, the differences will be mainly described.
도 7을 참조하면, 반도체 칩 패키지(2000)는 인쇄 회로 기판(1010), 반도체 칩(1020), 방열판(2030) 및 열 계면 물질(1100)을 포함할 수 있다. 방열판(2030)은 반도체 칩(1020)을 커버하도록 인쇄 회로 기판(1010) 상에 형성될 수 있다. Referring to FIG. 7, the semiconductor chip package 2000 may include a printed circuit board 1010, a semiconductor chip 1020, a heat sink 2030, and a thermal interface material 1100. The heat sink 2030 may be formed on the printed circuit board 1010 to cover the semiconductor chip 1020.
방열판(2030)은 매트릭스(2032) 및 상기 매트릭스(2032) 내부에 형성된 복수의 포어들(2034)을 포함하며, 포어들(2034) 내부에 분산된 복수의 PCM 볼들(2036)을 포함할 수 있다. The heat sink 2030 may include a matrix 2032 and a plurality of pores 2034 formed in the matrix 2032, and may include a plurality of PCM balls 2036 dispersed in the pores 2034. .
매트릭스(2032)는 카본 폼 등과 같은 다공성 카본 재료를 포함할 수 있다. 예를 들면, 카본 폼은 열전도도가 높은 핏치(pitch)로부터 제조되며, 카본이 3차원으로 연결된 네트워크 구조이며, 열린 포어 구조를 갖는 다공성 물질이다. 예시적인 실시예들에 있어서, 포어들(2034)은 약 수십 나노미터 내지 수 마이크로미터의 직경을 갖도록 형성될 수 있다. 매트릭스(2032)는 내부에 포어들(2034)이 열린 구조로 형성되어 유체가 드나들 수 있고, 표면적이 넓어 열전도도가 우수하다. 예를 들면, 매트릭스(2032)는 50 W/mK 이상의 열전도도를 가질 수 있다. Matrix 2032 may include a porous carbon material, such as carbon foam. For example, carbon foam is made from a pitch of high thermal conductivity, is a network structure in which carbon is connected in three dimensions, and is a porous material having an open pore structure. In example embodiments, the pores 2034 may be formed to have a diameter of about several tens of nanometers to several micrometers. The matrix 2032 has a structure in which the pores 2034 are opened therein so that fluid can enter and exit, and the surface area of the matrix 2032 is excellent in thermal conductivity. For example, matrix 2032 may have a thermal conductivity of at least 50 W / mK.
PCM 볼(2036)은 PCM 코어(2037) 및 상기 PCM 코어(2037)를 둘러싸는 제1 피복층(2038)을 포함할 수 있다. PCM 코어(2037)는 반도체 칩(1020)의 작동 온도 범위에서 액상에서 고상으로 상변화를 일으키거나, 고상에서 액상으로 상변화를 일으키는 물질을 포함할 수 있다. 제1 피복층(2038)은 금속, 카본 나노 튜브, 그래핀, 카본 블랙, 전도성 고분자 등의 전도성 물질을 포함할 수 있다. PCM ball 2036 may include a PCM core 2037 and a first coating layer 2038 surrounding the PCM core 2037. The PCM core 2037 may include a material that causes a phase change from a liquid phase to a solid phase or a phase change from a solid phase to a liquid phase within an operating temperature range of the semiconductor chip 1020. The first coating layer 2038 may include a conductive material such as metal, carbon nanotube, graphene, carbon black, conductive polymer, or the like.
본 발명에 따른 방열판(2030)은 포어들(2034) 내부에 분산된 PCM 볼들(2036)이 반도체 칩의 작동 시 발생하는 열을 효과적으로 흡수할 수 있으므로, 방열 특성이 우수할 수 있다. In the heat sink 2030 according to the present invention, since the PCM balls 2036 dispersed in the pores 2034 may effectively absorb heat generated when the semiconductor chip is operated, heat dissipation characteristics may be excellent.
도 7에는 도 4를 참조로 설명한 열 계면 물질(1100)을 포함하는 반도체 칩 패키지(2000)를 설명하였으나, 이와는 달리 반도체 칩 패키지(2000)는 도 5를 참조로 설명한 열 계면 물질(1200) 또는 도 6을 참조로 설명한 열 계면 물질(1300)을 포함할 수도 있다.Although FIG. 7 illustrates the semiconductor chip package 2000 including the thermal interface material 1100 described with reference to FIG. 4, the semiconductor chip package 2000 may include the thermal interface material 1200 described with reference to FIG. 5. The thermal interface material 1300 described with reference to FIG. 6 may also be included.
도 8은 예시적인 실시예들에 따른 열 계면 물질을 사용한 반도체 칩 패키지의 작동 온도 분포를 나타내는 개략도이다.8 is a schematic diagram illustrating an operating temperature distribution of a semiconductor chip package using a thermal interface material according to example embodiments.
도 8을 참조하면, 반도체 칩 상에 PCM 볼이 분산된 열 계면 물질을 부착한 반도체 칩 패키지의 칩 온도에 따른 열 계면 물질의 온도를 실선으로 도시하였다. T1은 PCM 볼 내에 포함된 PCM 코어 물질의 융점을 나타내며, 본 발명에서 T1이 반도체 칩의 작동 온도 범위 내에 위치한다. 예를 들어, 반도체 칩이 20 내지 120℃에서 작동할 수 있고, PCM 코어로서 융점이 62℃인 파라핀 수지를 사용할 수 있다. Referring to FIG. 8, the temperature of the thermal interface material according to the chip temperature of the semiconductor chip package to which the thermal interface material having PCM balls dispersed on the semiconductor chip is attached is illustrated by a solid line. T1 represents the melting point of the PCM core material contained in the PCM ball, and in the present invention, T1 is located within the operating temperature range of the semiconductor chip. For example, a semiconductor chip may operate at 20 to 120 ° C., and a paraffin resin having a melting point of 62 ° C. may be used as the PCM core.
반도체 칩이 동작함에 따라 반도체 칩의 온도는 서서히 증가할 수 있고, I 구간에서 반도체 칩의 온도가 T1에 도달할 때까지 열 계면 물질의 온도 역시 증가할 수 있다. II 구간에서, 반도체 칩의 온도가 T1보다 높아지고, 열 계면 물질 내의 PCM 코어가 고상에서 액상으로 상변화를 일으키기 시작할 수 있다. 한편, 전술한 바와 같이, 상기 상변화 과정은 흡열 과정이며, 파라핀 수지를 포함하는 상기 PCM 코어는 약 145-240kJ/kg의 잠열(latent heat)을 흡수할 수 있다. 상기 상변화가 일어나는 과정에서 상기 PCM 코어는 온도 변화가 없으므로, 반도체 칩의 온도가 T2까지 증가하더라도 열 계면 물질의 온도는 T1 근처에서 유지될 수 있다. 이에 따라 II 구간에서 열 계면 물질은 평탄한 온도 구간을 가질 수 있다. III 구간에서, 열 계면 물질 내에 포함된 상기 PCM 코어가 모두 액상으로 상변화한 이후에 다시 열 계면 물질의 온도가 상승하기 시작한다. As the semiconductor chip operates, the temperature of the semiconductor chip may gradually increase, and the temperature of the thermal interface material may also increase until the temperature of the semiconductor chip reaches T1 in the I section. In section II, the temperature of the semiconductor chip is higher than T1, and the PCM core in the thermal interface material may start to change phase from solid phase to liquid phase. As described above, the phase change process is an endothermic process, and the PCM core including the paraffin resin may absorb latent heat of about 145-240 kJ / kg. Since the PCM core has no temperature change during the phase change, the temperature of the thermal interface material may be maintained near T1 even if the temperature of the semiconductor chip increases to T2. Accordingly, the thermal interface material in section II may have a flat temperature section. In section III, the temperature of the thermal interface material starts to rise again after all the PCM cores contained in the thermal interface material have changed phase to liquid phase.
한편, 열 계면 물질의 온도가 다시 상승하기 시작하는 온도인 T2는 열 계면 물질 내에 포함된 PCM 코어의 양, PCM 코어의 물질 종류 또는 PCM 코어의 잠열 크기 등에 따라 달라질 수 있다. Meanwhile, T2, which is a temperature at which the temperature of the thermal interface material starts to rise again, may vary depending on the amount of the PCM core included in the thermal interface material, the type of the PCM core, or the latent heat size of the PCM core.
비교를 위하여, 도 8에 PCM 볼을 포함하지 않는 열 계면 물질을 부착한 반도체 칩 패키지의 칩 온도에 따른 열 계면 물질의 온도를 점선으로 도시하였다. PCM 볼을 포함하지 않는 열 계면 물질은 반도체 칩의 온도가 상승하는 것에 비례하여 온도가 증가할 수 있다. 따라서, 본 발명에 따른 PCM 볼을 포함하는 열 계면 물질은 PCM 볼을 포함하지 않는 열 계면 물질보다 방열 효과가 뛰어남을 확인할 수 있다.For comparison, in FIG. 8, the temperature of the thermal interface material according to the chip temperature of the semiconductor chip package to which the thermal interface material does not include the PCM ball is shown as a dotted line. Thermal interface materials that do not include PCM balls may increase in temperature in proportion to an increase in the temperature of the semiconductor chip. Therefore, it can be seen that the thermal interface material including the PCM ball according to the present invention has an excellent heat dissipation effect than the thermal interface material without the PCM ball.
이상에서 설명한 본 발명의 기술적 사상이 전술한 실시예 및 첨부된 도면에 한정되지 않으며, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것은, 본 발명의 기술적 사상이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The technical spirit of the present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in the art.
본 발명은 전자산업, 기계산엄 등 열전도 효율을 높은 접착물질을 사용하는 모든 분야에 사용될 수 있다.The present invention can be used in all fields using the adhesive material with high thermal conductivity efficiency, such as electronics industry, machine mountain.

Claims (14)

  1. 폴리머 매트릭스(polymer matrix); 및Polymer matrix; And
    상기 폴리머 매트릭스 내에 분산된 PCM 볼(phase change material ball);을 포함하며,PCM ball (phase change material ball) dispersed in the polymer matrix;
    상기 PCM 볼은,The PCM ball,
    상변화 물질을 포함하는 PCM 코어; 및A PCM core comprising a phase change material; And
    상기 PCM 코어를 둘러싸는 제1 피복층을 포함하는 것을 특징으로 하는 열 계면 물질(thermal interface material).And a first coating layer surrounding the PCM core.
  2. 제1항에 있어서, The method of claim 1,
    상기 상변화 물질은 반도체 칩의 작동 온도 범위 내에서 고상(solid phase)에서 액상(liquid phase)으로 상변화를 거치는 것을 특징으로 하는 열 계면 물질.And the phase change material undergoes a phase change from a solid phase to a liquid phase within an operating temperature range of the semiconductor chip.
  3. 제1항에 있어서, The method of claim 1,
    상기 상변화 물질의 융점은 50 내지 200도의 범위인 것을 특징으로 하는 열 계면 물질.The melting point of the phase change material is a thermal interface material, characterized in that the range of 50 to 200 degrees.
  4. 제1항에 있어서,The method of claim 1,
    상기 상변화 물질은 파라핀(paraffin), 폴리에틸렌 글리콜(polyethylene glycol), 무기수화물(inorganic hydrates), 지방산(fatty acid)인 것을 특징으로 하는 열 계면 물질.The phase change material may be paraffin, polyethylene glycol, inorganic hydrates, or a fatty acid.
  5. 제1항에 있어서, The method of claim 1,
    상기 제1 피복층은 전기 전도성 물질을 포함하는 것을 특징으로 하는 열 계면 물질.And the first coating layer comprises an electrically conductive material.
  6. 제1항에 있어서, The method of claim 1,
    상기 제1 피복층은 금속, 그래핀(graffin), 카본 블랙(carbon black), 카본 나노 튜브(carbon nanotube), 또는 전도성 폴리머인 것을 특징으로 하는 열 계면 물질.The first coating layer is a thermal interface material, characterized in that the metal, graphene (graffin), carbon black (carbon black), carbon nanotube (carbon nanotube), or a conductive polymer.
  7. 제1항에 있어서,The method of claim 1,
    상기 제1 피복층의 융점(melting point)은 상기 PCM 코어의 융점보다 높은 것을 특징으로 하는 열 계면 물질.And wherein the melting point of the first cladding layer is higher than the melting point of the PCM core.
  8. 제1항에 있어서,The method of claim 1,
    상기 제1 피복층은 단일 층 또는 복수의 층들의 적층 구조로 형성되는 것을 특징으로 하는 열 계면 물질.And the first coating layer is formed of a single layer or a laminated structure of a plurality of layers.
  9. 제1항에 있어서,The method of claim 1,
    상기 PCM 볼은,The PCM ball,
    상기 PCM 코어 볼 및 상기 제1 피복층 사이에 형성되는 폴리머 중간층을 더 포함하는 것을 특징으로 하는 열 계면 물질.And a polymer interlayer formed between the PCM core ball and the first coating layer.
  10. 제1항에 있어서,The method of claim 1,
    상기 폴리머 매트릭스 내에 분산된 폴리머 볼을 더 포함하며,Further comprising polymer balls dispersed within the polymer matrix,
    상기 폴리머 볼은,The polymer ball,
    폴리머 코어; 및 Polymer cores; And
    상기 폴리머 코어를 둘러싸는 제2 피복층을 포함하는 것을 특징으로 하는 열 계면 물질.And a second coating layer surrounding the polymer core.
  11. 제1항에 있어서, The method of claim 1,
    상기 폴리머 매트릭스 내에 분산된 전도성 폴리머, 카본 나노 튜브 또는 그래핀을 더 포함하는 열 계면 물질.Thermal interface material further comprising a conductive polymer, carbon nanotubes or graphene dispersed in the polymer matrix.
  12. 내부에 다수의 포어들(pores)이 형성된 다공성 카본 매트릭스(porous carbon matrix); 및 상기 포어들 내벽 상에 형성된 PCM 층(phase change material layer);을 포함하는 열 계면 물질.A porous carbon matrix having a plurality of pores formed therein; And a phase change material layer (PCM) formed on the inner walls of the pores.
  13. 제12항에 있어서, The method of claim 12,
    상기 다공성 카본 매트릭스는 카본 폼(carbon foam)인 것을 특징으로 하는 열 계면 물질.The porous carbon matrix is a thermal interface material, characterized in that the carbon foam (carbon foam).
  14. 반도체 칩;Semiconductor chips;
    상기 반도체 칩 상부의 방열판(heat spreader); 및 A heat spreader on the semiconductor chip; And
    상기 반도체 칩 및 상기 방열판을 연결하며, 폴리머 매트릭스 및 상기 폴리머 매트릭스 내에 분산된 PCM 볼을 포함하는 열 계면 물질을 포함하는 반도체 칩 패키지.And a thermal interface material connecting the semiconductor chip and the heat sink, the thermal interface material including a polymer matrix and PCM balls dispersed in the polymer matrix.
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