WO2015056695A1 - 制御装置および制御方法 - Google Patents
制御装置および制御方法 Download PDFInfo
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- WO2015056695A1 WO2015056695A1 PCT/JP2014/077397 JP2014077397W WO2015056695A1 WO 2015056695 A1 WO2015056695 A1 WO 2015056695A1 JP 2014077397 W JP2014077397 W JP 2014077397W WO 2015056695 A1 WO2015056695 A1 WO 2015056695A1
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- unit
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- interrupt signal
- interrupt
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0421—Multiprocessor system
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/22—Pc multi processor system
- G05B2219/2231—Master slave
Definitions
- the present invention relates to a control device that constitutes at least a part of a control system used to control the operation of a machine or equipment, and a control method therefor.
- Such a control system includes a programmable controller (hereinafter also referred to as “PLC”).
- PLC programmable controller
- Such a control system includes an IO (Input Output) unit that is in charge of signal input from an external switch or sensor and signal output to an external relay or actuator.
- IO Input Output
- IO interrupt means a function that executes interrupt processing when a signal is input from the outside
- power interruption interrupt means that power supplied to a PLC or the like is cut off
- a function that executes an interrupt process means a scheduled interrupt, which means a function that executes an interrupt process at predetermined intervals.
- Patent Document 1 discloses an interrupt system having a host device and peripheral devices connected to a network.
- Patent Document 2 notifies a device that requires an interrupt signal for performing synchronization processing at the same timing in a control device having a serial bus configuration, A control device with reduced fluctuations is disclosed.
- an IO interrupt is to be realized using an interrupt signal input to the IO unit, it is necessary to propagate the interrupt signal input to the IO unit to the computation subject via a bus or a network. At this time, the time required to transmit the interrupt signal may affect the execution of the user program.
- Patent Document 1 only teaches a transmission method of an interrupt signal, and does not consider the input timing of the interrupt signal.
- Patent Document 2 employs a configuration in which an interrupt signal for performing a synchronization process is notified to a device that requires the same timing, but in this configuration, it is necessary to notify an interrupt signal to a plurality of devices. There is a problem that the amount of transmission increases. Therefore, there is a demand for a control device that can more freely control the execution timing of various programs executed by interrupt generation.
- a control device constituting at least a part of a control system includes a master control unit and at least one slave control unit connected to the master control unit via at least a communication line.
- the slave control unit acquires timing information from the timing unit when the timing unit synchronized with the master control unit, the input unit that receives the interrupt signal, and the interrupt signal through the input unit are received.
- the master control unit and the control unit are further connected via an interrupt line, and the slave control unit notifies an input of an interrupt signal to the master control unit via the interrupt line.
- the slave control unit notifies the master control unit of information indicating the input of the interrupt signal via the communication line.
- the master control unit is configured to periodically make an inquiry to the slave control unit via the communication line, and the slave control unit receives an interrupt when receiving an inquiry from the master control unit. If the signal is received, the master controller is notified of information indicating the input of the interrupt signal.
- the communication line includes a downlink for transmitting data from the master control unit to the slave control unit, and an uplink for transmitting data from the slave control unit to the master control unit.
- the master controller completes data transmission from the slave controller via the uplink
- the master controller transmits a command for deactivating the uplink to the slave controller via the downlink, and an interrupt line.
- control device includes a plurality of slave control units, and the control device includes means for limiting the slave control units that can notify the master control unit of the input of the interrupt signal.
- the slave control unit that receives a request transmitted from the master control unit via the communication line is configured to be limited to a slave control unit that can be notified of an interrupt signal input.
- each of the slave control units is inserted into an interrupt line, and a logic of a signal for notifying the input of the interrupt signal from the previous stage slave control unit and a signal for notifying the input of its own interrupt signal
- An OR circuit that outputs the sum as a signal for notifying the input of a new interrupt signal, and whether to output a signal for notifying the input of a new interrupt signal output from the OR circuit to the slave control unit in the subsequent stage. And a circuit for switching between them.
- a control method in a control system including a master control unit and at least one slave control unit connected to the master control unit via at least a communication line.
- the slave control unit when the slave control unit receives the interrupt signal via the input unit, the slave control unit acquires information indicating the timing from the timing unit synchronized with the master control unit, and masters the input of the interrupt signal.
- the control device can more freely control the execution timing of various programs in the interrupt process.
- control system a system centered on a PLC will be exemplified.
- PLC the PLC
- various industrial computers can be mainly used.
- a new processing device an Arimetic device
- such a new processing device can also be employed.
- FIG. 1 is a schematic diagram showing an overall configuration of a PLC system 1 according to the present embodiment.
- the PLC system 1 includes a main processing device 2 and one or more remote IO devices 3.
- the main processing device 2 and the remote IO device 3 are control devices that constitute at least a part of the PLC system 1.
- the main processing device 2 is connected to one or more remote IO devices 3 via the field bus 4.
- Each of the remote IO devices 3 has a communication module 12 for connecting to the field bus 4.
- the main processing device 2 executes a control program (including a user program and a system program), and calculates an output signal to an external relay or actuator in response to an input signal from an external switch or sensor. More specifically, the main processing device 2 includes a CPU unit 10, an IO unit 20, and a power supply unit 30. The CPU unit 10 and the IO unit 20 are connected to each other via the internal bus 5 so that data communication is possible. The power supply unit 30 supplies power of an appropriate voltage to the CPU unit 10 and the IO unit 20.
- the CPU unit 10 is a computation subject including a processor and a main memory for executing a control program.
- the CPU unit 10 includes a communication module 42 for exchanging data with the remote IO device 3 via the field bus 4.
- the field bus 4 is preferably a communication method capable of communicating at a predetermined control cycle (capable of real-time communication).
- the remote IO device 3 receives an input signal from an external switch or sensor, transmits the received input signal to the main processing device 2 via the field bus 4, and transmits the field bus 4 from the main processing device 2.
- the signal received via the terminal is output to an external relay or actuator.
- the remote IO device 3 includes a master unit 40 and one or more IO units 20.
- the master unit 40 and the IO unit 20 are connected to each other via the internal bus 5 so that data communication is possible.
- the master unit 40 mainly controls the operation of the IO unit 20 (IO data update timing and the like) and also controls data communication with the main processing device 2.
- the IO unit 20 has a general input / output processing function in addition to the function of data communication with the CPU unit 10 or the master unit 40 via the internal bus 5. That is, the IO unit 20 is in charge of signal input from an external switch or sensor and / or signal output to an external relay or actuator.
- the IO unit 20 inputs / outputs binarized data such as on / off.
- the IO unit 20 collects information on whether a certain object is detected (ON) or no object is detected (OFF) from the detection sensor.
- the IO unit 20 can activate (activate) a command (on) or deactivate (deactivate) a command (off) for an output destination such as a relay or an actuator.
- an output destination such as a relay or an actuator.
- the CPU unit 10 corresponds to a master control unit
- the IO unit 20 corresponds to a slave control unit
- the master unit 40 corresponds to a master control unit
- the IO unit 20 corresponds to a slave control unit. That is, each of the CPU unit 10 and the master unit 40 that are the master control units is connected to at least one IO unit 20 via the internal bus 5 that is a communication line.
- each of the main processing device 2 and the remote IO device 3 includes an IRQ bus 6 that is an interrupt line for transmitting an interrupt input. That is, the main processing device 2 and the remote IO device 3 are further connected via an interrupt line.
- an IRQ bus 6 for transmitting an interrupt signal is provided in addition to the internal bus 5 for exchanging data between the CPU unit 10 or the master unit 40 and the IO unit 20, an IRQ bus 6 for transmitting an interrupt signal is provided.
- the interrupt processing is executed by combining these two types of buses.
- the timing when the interrupt signal is input can be acquired and used. That is, when the IO unit 20 receives the interrupt signal, the IO unit 20 acquires information indicating timing from the time measuring means, and the IO unit 20 masters the input of the interrupt signal via the IRQ bus 6 that is an interrupt line. Notify the control unit (CPU unit 10 or master unit 40). Subsequently, when the IO unit 20 receives a request from the master control unit (CPU unit 10 or master unit 40) via the internal bus 5, the IO unit 20 transmits information indicating the acquired timing to the master control unit via the internal bus 5. To do. The master control unit (CPU unit 10 or master unit 40) executes various interrupt processes using the timing at which the interrupt signal from the IO unit 20 is input.
- FIG. 2 is a schematic diagram showing a connection configuration in the main processing apparatus 2 according to the present embodiment.
- the connection configuration in the remote IO device 3 is the same as that of the main processing device 2.
- the part describing the CPU unit 10 can be replaced with the master unit 40.
- CPU unit 10 and one or more IO units 20-1, 20-2, 20-3 (hereinafter may be collectively referred to as “IO unit 20”).
- the communication lines are connected to each other via an internal bus 5 (downlink 51 and uplink 52) so that data communication is possible.
- the CPU unit 10 and the one or more IO units 20 are also connected via the IRQ bus 6.
- the IRQ bus 6 is an interrupt line for transmitting an interrupt signal input to one of the IO units 20 to the CPU unit 10.
- the IRQ bus 6 may notify the input of an interrupt signal in accordance with a predetermined protocol. However, in the present embodiment, only the signal change indicating ON / OFF is propagated. That is, the IRQ bus 6 employs a wired wiring configuration.
- each of the IO units 20 When each of the IO units 20 detects the input of an interrupt signal, it sends a signal for notifying it to the next stage via the IRQ bus 6. In addition, each IO unit 20 receives an interrupt signal input notification from another IO unit 20 arranged in the subsequent stage via the IRQ bus 6 and re-sends (forwards) the interrupt signal to the next stage. . At this time, if an interrupt signal is input also in the local station, the IO unit 20 superimposes the signal and outputs it to the next stage. Each IO unit 20 includes an interrupt notification circuit 250 for sequentially transferring notification of input of an interrupt signal. Details of the interrupt notification circuit 250 will be described later.
- the internal bus 5 any configuration may be adopted as long as data can be exchanged between the master control unit (CPU unit 10) and the IO unit 20.
- a digital chain connection is employed in which independent links are provided for different data transmission directions.
- the internal bus 5 has a master / slave configuration, a downlink (hereinafter also referred to as “DL”) 51 for transmitting data from the master control unit to the slave control unit, and a slave It consists of a communication channel paired with an uplink (Up Link: hereinafter also referred to as “UL”) 52 that transmits data from the control unit to the master control unit.
- the communication channel may be one line (a pair) or more lines may be prepared.
- serial communication is adopted, and the target data is transmitted in a line in time series. That is, on the downlink 51, data is transmitted in one direction from the master control unit (CPU unit 10) to the slave control unit (IO unit 20). On the other hand, in the uplink 52, data is transmitted in one direction via the uplink 52 from one of the slave control units (IO units 20) to the master control unit (CPU unit 10).
- each of the IO units 20 When each of the IO units 20 receives a signal sequence transmitted through the downlink 51 or the uplink 52, the IO unit 20 performs a necessary process after decoding the signal sequence. Each IO unit 20 regenerates the signal train and then re-sends (forwards) it to the next stage.
- each IO unit 20 includes a receiving unit (hereinafter also referred to as “RX”) 210 a and a transmitting unit (hereinafter also referred to as “TX”) 210 b regarding the downlink 51.
- RX receiving unit
- TX transmitting unit
- a reception unit 220a and a transmission unit 220b are included.
- CPU unit 10 includes a main control unit 100, a fieldbus control unit 110, a receiving unit 112, a transmitting unit 114, and an internal bus control unit 130.
- the CPU unit 10 is not only connected to the internal bus 5 (downlink 51 and uplink 52) and the IRQ bus 6, but also connected to the field bus 4 via the reception unit 112 and the transmission unit 114.
- the field bus control unit 110 manages data communication via the field bus 4, and the internal bus control unit 130 manages data communication via the internal bus 5 and the IRQ bus 6.
- the main control unit 100 executes control programs (including user programs and system programs) while exchanging data between the fieldbus control unit 110 and the internal bus control unit 130.
- FIG. 3 is a schematic diagram showing a hardware configuration of the CPU unit 10 constituting the main processing device 2 according to the present embodiment.
- the field bus control unit 110 of the CPU unit 10 transmits / receives data to / from other devices at predetermined control intervals via the field bus 4 in cooperation with the reception unit 112 and the transmission unit 114. More specifically, the fieldbus control unit 110 includes a fieldbus communication controller 120, a memory controller 122, a FIFO (First In First Out) memory 124, a reception buffer 126, and a transmission buffer 128.
- a fieldbus communication controller 120 includes a fieldbus communication controller 120, a memory controller 122, a FIFO (First In First Out) memory 124, a reception buffer 126, and a transmission buffer 128.
- FIFO First In First Out
- the fieldbus communication controller 120 interprets a command or the like transmitted via the fieldbus 4 and executes processing necessary for realizing communication via the fieldbus 4.
- the fieldbus communication controller 120 performs data copy processing from the upper communication frame and data write processing to the upper communication frame that are sequentially stored in the FIFO memory 124.
- the memory controller 122 is a control circuit that realizes a function such as DMA (Direct Memory Access), and controls writing / reading of data to / from the FIFO memory 124, the reception buffer 126, the transmission buffer 128, and the like.
- DMA Direct Memory Access
- the FIFO memory 124 temporarily stores the upper communication frames received via the field bus 4 and sequentially outputs the upper communication frames according to the stored order.
- the reception buffer 126 includes data indicating a state value to be output from the output unit of the IO unit 20 connected to its own device (hereinafter referred to as “OUT data”) among the data included in the upper communication frame sequentially stored in the FIFO memory 124. Is also extracted and stored temporarily.
- the transmission buffer 128 is process data indicating a state value detected at the input unit of the IO unit 20 and is data (hereinafter referred to as “IN”) to be written in a predetermined area of the upper communication frame sequentially stored in the FIFO memory 124. Also referred to as “data”.) Temporarily stored.
- the main control unit 100 includes a processor 102, a nonvolatile memory 104, and a main memory 108.
- the processor 102 executes a control program corresponding to the control target.
- the processor 102 reads out the control program 106 from the non-volatile memory 104 and the like, and develops and executes it in the main memory 108.
- state values to be output from the output unit of the IO unit 20 are sequentially calculated based on the state values detected by the input unit of the IO unit 20.
- the main control unit 100 gives instructions to the fieldbus control unit 110 and the internal bus control unit 130 and controls data transfer between the fieldbus control unit 110 and the internal bus control unit 130.
- the internal bus control unit 130 transmits / receives data to / from the IO unit 20 via the internal bus 5 (downlink 51 and uplink 52) in a control cycle shorter than the control cycle in the fieldbus 4.
- Internal bus control unit 130 includes an internal bus communication controller 132, an interrupt circuit 134, a counter 136, a transmission circuit 142, a reception circuit 144, and a storage unit 160.
- the internal bus communication controller 132 mainly manages (as a master) data communication via the internal bus 5.
- the internal bus communication controller 132 is a data frame (hereinafter also referred to as “TRG_frame (IN)”) including a command (trigger) that requests IN data to the IO unit 20 in accordance with an instruction from the main control unit 100.
- TRG_frame a data frame including OUT data to be reflected to the IO unit 20 (hereinafter also referred to as “OUT_frame”) is transmitted onto the internal bus 5.
- each IO unit 20 refreshes the input unit of its own unit, and then internally includes a data frame including a state value (IN data) after the refresh (hereinafter also referred to as “IN_frame”).
- TRG_frame (IN) or OUT_frame may be transmitted to a specific IO unit 20 or may be transmitted (multicast / broadcast) to all the IO units 20 connected to the internal bus 5.
- the interrupt circuit 134 When the interrupt circuit 134 receives the input of the interrupt signal via the IRQ bus 6, the interrupt circuit 134 notifies the internal bus communication controller 132 of the input of the interrupt signal.
- the counter 136 is an example of a time measuring means for measuring various timings, and continues counting up at a predetermined cycle.
- the timing can be acquired using the count value of the counter 136.
- the count value of the counter 136 is synchronized with the count value of the counter included in the IO unit 20, and the control based on the timing can be realized by using the count value notified from any of the IO units 20.
- the transmission circuit 142 generates and transmits a downlink data frame of the internal bus 5 in accordance with an instruction from the internal bus communication controller 132.
- the reception circuit 144 receives a data frame flowing on the uplink of the internal bus 5 and outputs it to the internal bus communication controller 132.
- the storage unit 160 corresponds to a buffer memory that stores data transmitted through the internal bus 5. More specifically, the storage unit 160 includes a shared memory 162, a reception memory 164, and a transmission memory 166.
- Shared memory 162 temporarily stores data exchanged between fieldbus control unit 110 and internal bus control unit 130.
- the reception memory 164 temporarily stores IN data received from the IO unit 20 via the internal bus 5.
- the transmission memory 166 temporarily stores OUT data included in the upper communication frame received by the fieldbus control unit 110.
- FIG. 4 is a schematic diagram showing a hardware configuration of the master unit 40 that constitutes the remote IO device 3 according to the present embodiment.
- the master unit 40 is different from the CPU unit 10 in that a main control unit 150 is provided instead of the main control unit 100.
- the main control unit 150 does not execute a control program or the like, but controls data communication via the field bus 4 and data communication with the remote IO device 3 via the internal bus 5.
- the main control unit 150 includes a processor 152 and a memory 158.
- FIG. 5 is a schematic diagram showing a hardware configuration of the IO unit 20 constituting the PLC system 1 according to the present embodiment.
- each of the IO units 20 includes an inverse serial converter (de-serializer: hereinafter also referred to as “DES unit”) 212 and 222 and a serial converter (SER: serializer: hereinafter “SER unit”). 216, 226 and repeat units 214, 224.
- DES unit de-serializer
- SER unit serializer: hereinafter “SER unit”.
- the DES unit 212, the repeat unit 214, and the SER unit 216 correspond to the reception unit 210a and the transmission unit 210b for the downlink 51 illustrated in FIG. These portions execute processing related to transmission / reception of data (data frame) flowing through the downlink 51.
- the DES unit 222, the repeat unit 224, and the SER unit 226 correspond to the reception unit 220a and the transmission unit 220b for the uplink 52 illustrated in FIG.
- Each of the IO units 20 further includes a reception processing unit 230, a transmission processing unit 240, a processor 200, a shared memory 202, an IO module 206, and a nonvolatile memory 208 that are connected to each other via a bus 236. , An interrupt notification circuit 250 and a counter 270.
- the reception processing unit 230 performs processing related to reception of data frames transmitted via the downlink 51 and the uplink 52. More specifically, the reception processing unit 230 includes a decoding unit 232 and a CRC check unit 234. The decoding unit 232 decodes the received data frame according to a predetermined algorithm to generate data. The CRC check unit 234 performs an error check (for example, a CRC (Cyclic Redundancy Check) code) on the decoded data. Then, the data determined to be normal by the error check is output to the processor 200 or the like.
- an error check for example, a CRC (Cyclic Redundancy Check) code
- the transmission processing unit 240 executes processing related to data frame transmission via the downlink 51 and the uplink 52. That is, the transmission processing unit 240 is connected to the repeat units 214 and 224, and controls the configuration and timing of the data frame to be retransmitted (forwarded) to the next-stage IO unit 20 in accordance with an instruction from the processor 200 or the like. More specifically, the transmission processing unit 240 includes a CRC generation unit 242 and an encoding unit 244. The CRC generation unit 242 calculates an error control code (CRC) for the data from the processor 200 or the like and adds it to the data. The encoding unit 244 encodes the data from the CRC generation unit 242 and outputs the encoded data to the corresponding repeat unit.
- CRC error control code
- the processor 200 is an arithmetic entity that mainly controls the IO unit 20.
- the processor 200 stores a data frame received via the reception processing unit 230 in the shared memory 202 by executing a pre-stored program or the like, or reads predetermined data from the shared memory 202 to generate a data frame.
- the data is output to the transmission processing unit 240 for generation.
- the shared memory 202 temporarily stores a reception buffer 203 for temporarily storing a data frame received via the reception processing unit 230 and a data frame for transmission to the transmission processing unit 240.
- the shared memory 202 includes an area for storing various data.
- the IO module 206 receives an input signal from an external switch or sensor, writes the value to the shared memory 202, and sends the signal to an external relay according to the value written in the corresponding area of the shared memory 202. And output to the actuator. That is, the IO module 206 includes at least one of an input unit that collects a state value (IN data) of an externally input signal and an output unit that outputs a signal of a specified state value (OUT data).
- the nonvolatile memory 208 stores various data in a nonvolatile manner. More specifically, the non-volatile memory 208 holds setting information (configuration) describing setting values of each IO unit 20.
- the interrupt notification circuit 250 When an interrupt signal is input to the IO module 206, the interrupt notification circuit 250 sends a signal for notifying it to the next stage via the IRQ bus 6. When the interrupt notification circuit 250 receives an interrupt signal input notification from another IO unit 20 (interrupt notification circuit 250) arranged in the subsequent stage via the IRQ bus 6, the interrupt notification circuit 250 outputs the interrupt signal to the next stage. Re-send to (forward).
- the counter 270 is an example of a time measuring means for measuring various timings, and is synchronized with the counter 136 of the CPU unit 10 or the master unit 40 that is a master control unit. More specifically, in each of the IO units 20, the counter 270 is incremented (incremented), and the master control unit sends the count value of its own counter 136 to the IO unit 20 via the internal bus 5. Notify every cycle. The IO unit 20 appropriately updates the value of the counter 270 based on the count value notified from the master control unit.
- Measure means is not limited to the counter 270, and various methods can be adopted.
- the master control unit broadcasts time data via the internal bus 5 at a predetermined cycle, and acquires the timing at which an interrupt factor occurs based on the broadcast time data. May be.
- each of the main control unit 100 of the CPU unit 10, the main control unit 150 of the master unit 40, and the remote IO device 3 has been illustrated using a processor.
- the present invention is not limited thereto.
- a hardware circuit such as an application specific integrated circuit (ASIC) or a field-programmable gate array (FPGA) may be used.
- ASIC application specific integrated circuit
- FPGA field-programmable gate array
- some or all of the components may be implemented as software.
- the parts corresponding to the receivers 210a and 220a and the transmitters 210b and 220b shown in FIG. 2 are mounted using a physical circuit such as an ASIC, and the processor executes a program for the other parts. It may be realized.
- FIG. 6 is a diagram for explaining an interrupt process in the PLC system 1 according to the present embodiment.
- the CPU unit 10 that is a master control unit and the IO unit 20 that is a slave control unit are connected to each other via an internal bus 5 that is a communication line and an IRQ bus 6 that is an interrupt line.
- Each of the IO units 20 includes timing means (counter 270) synchronized with the CPU unit 10 and an input unit (IO module 206) that receives an interrupt signal.
- the IO unit 20 acquires information indicating the timing from the timing unit and notifies the master control unit of the input of the interrupt signal via the interrupt line.
- the IO unit 20 transmits information indicating the acquired timing to the master control unit via the communication line.
- IO unit 20 acquires a time stamp (step S2). That is, when some interrupt factor occurs and the input value changes from OFF to ON (or ON to OFF), the count value held by the counter 270 at the changed timing is acquired as a time stamp.
- the interrupt signal is not limited to an externally input signal, and may be a signal generated internally in any unit.
- the acquired time stamp is temporarily stored in the IO unit 20.
- the state value is changed to a value indicating that an interrupt factor has occurred.
- the value of the corresponding internal flag is updated.
- the term “time stamp” is used as an example of information indicating the timing at which the interrupt signal is input.
- the present invention is not limited to this, and the timing at which the interrupt signal is input is specified. Any information that can be used may be used.
- the IO unit 20 After obtaining the time stamp or in parallel with obtaining the time stamp, the IO unit 20 notifies the CPU unit 10 of the input of the interrupt signal via the IRQ bus 6 which is an interrupt line (step S3). .
- the CPU unit 10 When the CPU unit 10 receives an interrupt signal input notification (interrupt factor) from any of the IO units 20, the CPU unit 10 identifies the IO unit 20 to which the interrupt signal is input, and identifies the cause of the interrupt signal. Execute (step S4). Then, the CPU unit 10 requests a time stamp from the IO unit 20 via the internal bus 5 (downlink 51) in order to acquire the timing at which the interrupt signal is input (step S5). In response to this request, the IO unit 20 to which the interrupt signal has been input reads the stored time stamp and transmits it to the CPU unit 10 via the internal bus 5 (uplink 52) (step S6).
- interrupt signal input notification interrupt factor
- the CPU unit 10 that has received the time stamp from the IO unit 20 executes an interrupt process using the received time stamp (step S7).
- step S4 data is exchanged between the CPU unit 10 and the IO unit 20. May be performed. This exchange variation will be described later with some examples.
- the transmission band between the IO unit 20 and the CPU unit 10 or the master unit 40 needs to be sufficiently large, and the clock frequency of the internal bus 5 must be increased. As the clock frequency increases, the power consumption of the components related to transmission increases.
- the PLC system 1 employs an internal bus 5 including independent links depending on the data transmission direction, and even if a function for reducing power consumption is implemented using the independent link configuration. Good. This function of reducing power consumption is not directly related to the essence of the present invention, and is arbitrarily adopted.
- one link of the internal bus 5 composed of uplink / downlink is suspended (inactivated) when not communicating. Regardless of communication or non-communication, the other link is basically activated, and if necessary, the other link is activated using the other link.
- the uplink is a target for activation / deactivation because of the ease of command transmission from the master control unit to the slave control unit.
- FIG. 7 is a diagram for explaining a method for realizing low power consumption in the PLC system 1 according to the present embodiment.
- FIG. 7A shows a state in which both the downlink 51 and the uplink 52 are active
- FIG. 7B shows that the uplink 51 is maintained while the downlink 51 is kept active. Indicates a state of rest. By maintaining the state as shown in FIG. 7B as much as possible, power consumption is reduced.
- the master controller (CPU unit 10 or master unit 40) completes data transmission from the slave controller (IO unit 20) via the uplink 52
- a command for deactivating the uplink 52 is issued. Is transmitted to the slave side via the downlink 51, and when data is to be acquired from the slave control unit, a command for activating the uplink 52 is transmitted to the slave side via the downlink 51.
- the slave control unit keeps the downlink 51 active, and activates / deactivates the uplink 52 according to a command from the master control unit transmitted via the uplink 52. . That is, the downlink 51 is maintained in the active state, thereby facilitating the activation / pause control of the uplink 52.
- the operations of the DES unit 222, the repeat unit 224, and the SER unit 226 are stopped according to the situation.
- the clock frequency of the internal bus 5 is relatively high (for example, several hundred M order to GHz order or more)
- the power consumption of these components becomes relatively large, so that the power consumption can be suppressed by stopping.
- the processor 200 instructs these components to operate and stop (active / standby command). That is, the IO unit 20 that functions as a slave control unit includes a conversion circuit (DES unit 222, repeat unit 224, and SER unit 226) that converts a signal transmitted through the uplink 52. And deactivation of the uplink 52 includes power interruption to these conversion circuits.
- the master control unit (CPU unit 10 or master unit 40) includes a receiving circuit (receiving circuit in the internal bus control unit 130) for receiving a signal flowing on the uplink 52, and the uplink 52 is inactive. During this period, the power supply of the receiving circuit can also be shut off. As a result, power consumption can be reduced not only in the IO unit 20 but also in the CPU unit 10.
- the master control unit CPU unit 10 or master unit 40
- the uplink is performed.
- a command for activating 52 is transmitted to the slave control unit via the downlink 51.
- FIG. 8 is a time chart showing an example of a procedure for reducing power consumption in the PLC system 1 according to the present embodiment.
- FIG. 8A shows data (hereinafter referred to as “IN data”) collected by the slave control unit (IO module 206 shown in FIG. 5) from the master control unit to the slave control unit when the uplink 52 is in an inactive state. Is also referred to as “.” Is a processing example for requesting transmission to the master control unit.
- FIG. 8B shows data to be output from the slave control unit (IO module 206 shown in FIG. 5) to the slave control unit from the master control unit when the uplink 52 is inactive (hereinafter referred to as “OUT data”). Is also referred to as “.”).
- the IN data request operation for the slave control unit is also referred to as “IN data refresh”, and the OUT data transmission operation for the slave control unit is also referred to as “OUT data refresh”.
- the master control unit first transmits a data frame (command) for activating the dormant receiving unit 220a and transmitting unit 220b via the downlink 51. (Hereinafter also referred to as “WakeUP_frame”.) 302 is transmitted.
- the slave control unit that has received the WakeUP_frame 302 changes the inactive uplink 52 to the active state.
- the master control unit transmits a data frame (hereinafter also referred to as “TRG_frame (IN)”) 304 including a command (trigger) for executing IN data refresh via the downlink 51 following the WakeUP_frame 302.
- TRG_frame (IN) 304 the slave control unit generates IN_frame 314 including the IN data acquired by the IO module of the local station, and transmits the IN_frame 314 to the master control unit via the uplink 52.
- the master control unit When reception of the IN_frame 314 from the slave control unit is completed, the master control unit transmits a data frame (hereinafter referred to as “PowerDown_frame” including a command for deactivating the active reception unit 220a and transmission unit 220b via the downlink 51. Is also referred to as “.” 308 is transmitted.
- the slave control unit that has received the PowerDown_frame 308 changes the uplink 52 in the active state to the inactive state.
- the uplink 52 is activated only during the period of executing the IN data refresh, and is maintained in the inactive state during the other periods. By such a procedure, low power consumption can be realized.
- the master control unit in the OUT data refresh, the master control unit first transmits WakeUP_frame 302 via the downlink 51.
- the slave control unit that has received the WakeUP_frame 302 changes the inactive uplink 52 to the active state.
- the master control unit generates OUT_frame 306 including OUT data and transmits the OUT_frame 306 to the slave control unit via the downlink 51.
- the slave control unit When reception of OUT_frame 306 from the master control unit is completed, the slave control unit transmits a data frame (hereinafter also referred to as “ACK_frame”) 316 indicating successful reception of OUT_frame 306 via the uplink 52.
- ACK_frame a data frame
- the master control unit determines that the OUT refresh has been successful, and transmits the PowerDown_frame 308 via the downlink 51.
- the slave control unit that has received the PowerDown_frame 308 changes the uplink 52 in the active state to the inactive state.
- the uplink 52 is activated only during the period of executing the OUT data refresh, and is maintained in the inactive state during other periods. By such a procedure, low power consumption can be realized.
- FIG. 8 illustrates the exchange of data between the master control unit and one slave control unit
- the frame is sequentially transferred to the subsequent slave control unit and the same processing is executed. May be. That is, by adopting a method (multicast or broadcast) that transfers data all at once to all slave control units connected to the master control unit, the same processing is performed on all slave control units. Can be executed.
- a necessary process may be executed on a specific slave control unit using a method such as message transfer.
- FIG. 9 is a time chart showing a processing procedure (first implementation example) when an interrupt signal is input in the PLC system 1 according to the present embodiment.
- the processing procedure includes five phases: interrupt activation, time stamp collection, application execution, data output, and interrupt factor clear.
- any IO unit 20 receives an interrupt signal via the IO module 206 (step S100)
- the IO unit 20 receives the interrupt signal when the interrupt signal is input.
- a time stamp is acquired (step S102). That is, the IO unit 20 acquires information indicating timing from the time measuring means. Then, the IO unit 20 notifies the CPU unit 10 (master control unit) of the input of the interrupt signal via the IRQ bus 6 (interrupt line) (step S104).
- the internal bus control unit 130 of the CPU unit 10 In response to the notification of the input of the interrupt signal via the IRQ bus 6, the internal bus control unit 130 of the CPU unit 10 generates a frame for specifying the IO unit 20 to which the interrupt signal is input (step S106). ). Then, the internal bus control unit 130 of the CPU unit 10 transmits the generated frame to the IO unit 20 via the downlink 51 (step S108).
- the generated frame is a data frame (hereinafter also referred to as “TRG_frame (IRQ)”) including a WakeUP_frame for changing to an active state and a command (trigger) that requests an input state of an interrupt signal.
- TRG_frame IRQ
- the internal bus control unit 130 of the CPU unit 10 cannot determine which IO unit 20 the interrupt signal is from. Therefore, the internal bus control unit 130 broadcasts the generated frame. Or you may multicast with respect to IO unit 20 which may perform notification of an interruption signal.
- the IO unit 20 that has received the TRG_frame (IRQ) and has previously notified the interrupt signal reads the input state of the interrupt signal to its own station (step S110) and transmits it to the CPU unit 10 as the IRQ_frame (step S110). S112).
- TRG_frame (IRQ) is preferably transmitted (multicasted) only to the IO unit 20 that accepts the input of the interrupt signal. That is, the slave control unit that receives a request (TRG_frame (IRQ)) transmitted from the master control unit via the communication line is limited to a slave control unit that can notify the input of an interrupt signal. It is preferable.
- TRG_frame (IRQ) is transferred only to the IO units 20 of # 1 to # 4.
- an attribute (identification number) is given to the generated TRG_frame (IRQ) and the attribute of the frame to be received for each IO unit 20 Can be used in advance.
- the internal bus control unit 130 of the CPU unit 10 updates the interrupt factor based on the IRQ_frame from each IO unit 20. Then, the internal bus control unit 130 of the CPU unit 10 notifies the occurrence of an interrupt factor to the main control unit 100 of the CPU unit 10 (step S114). The main control unit 100 of the CPU unit 10 activates the interrupt task in response to the notification of the occurrence of the interrupt factor (step S116).
- the interrupt factor indicates the input state of the interrupt signal in each IO unit 20 and is typically held as the value of a flag provided for each IO unit 20.
- the interrupt task executed in the main control unit 100 of the CPU unit 10 reads the interrupt factor from the internal bus control unit 130, and receives an interrupt signal (the interrupt factor is generated). And the interrupt factor is read (step S118).
- the main control unit 100 of the CPU unit 10 indicates to the internal bus control unit 130 the timing at which the interrupt signal is input from the IO unit 20 to which the interrupt signal is input.
- An IN data refresh for collecting time stamps is instructed (step S120).
- the internal bus control unit 130 of the CPU unit 10 generates TRG_frame (IN) and transmits it via the downlink 51 (step S122).
- the main control unit 100 of the CPU unit 10 transmits TRG_frame (IN) to the specified IO unit 20.
- the IO unit 20 that has received TRG_frame (IN) reads the input value in its own station (step S124), and transmits it to the CPU unit 10 as IN_frame (nWord) including IN data for n words (step S126).
- IN_frame (nWord) includes an input value (current value) input to the IO module 206, a state value indicating an input state of the interrupt signal, a time stamp value, and the like.
- the internal bus control unit 130 of the CPU unit 10 passes IN_frame (nWord) from the IO unit 20 to the main control unit 100 of the CPU unit 10 (step S128).
- the main control unit 100 of the CPU unit 10 executes an interrupt application according to the interrupt factor (the IO unit 20 to which the interrupt signal is input and the type of the interrupt signal). (Step S130), preparation for transmitting the execution result is performed (Step S132).
- the main control unit 100 of the CPU unit 10 instructs the internal bus control unit 130 to perform OUT data refresh for outputting OUT data according to the execution result (step). S134).
- the internal bus control unit 130 of the CPU unit 10 generates OUT_frame (nWord) and transmits it to the IO unit 20 that performs data output via the downlink 51 (step S136).
- OUT_frame (nWord) is transmitted to the # 5 IO unit 20.
- the IO unit 20 that has received OUT_frame (nWord) outputs OUT data from the IO module 206 in accordance with the received OUT_frame (nWord) (step S138), and also succeeds in receiving OUT_frame (nWord) via the uplink 52.
- ACK_frame shown is transmitted to the CPU unit 10 (step S140).
- the internal bus control unit 130 of the CPU unit 10 notifies the main control unit 100 of the CPU unit 10 of the completion of the OUT data refresh (step S142).
- OUT_frame may include a time stamp indicating at what timing the output should be executed in addition to the OUT data to be output.
- OUT_frame (nWord) including such a time stamp is received, the IO unit 20 outputs OUT data when the time corresponding to the designated time stamp arrives.
- the main control unit 100 of the CPU unit 10 prepares to instruct the IO unit 20 to which the interrupt signal is input to clear the interrupt factor (step). S144). That is, preparation processing is performed to clear the state value held by the IO unit 20 to which the interrupt signal is input. Subsequently, the main control unit 100 of the CPU unit 10 instructs the internal bus control unit 130 to clear the interrupt factor for the IO unit 20 (step S146). In response to this instruction, the internal bus control unit 130 of the CPU unit 10 generates OUT_frame (1W), and the IO unit 20 (in this example, # 4 in which the interrupt signal is input via the downlink 51). The data is transmitted to the IO unit 20) (step S148).
- the IO unit 20 that has received OUT_frame (1W) clears the state value indicating the interrupt factor held by itself (step S150), and also successfully receives OUT_frame (1W) via the uplink 52.
- ACK_frame shown is transmitted to the CPU unit 10 (step S152).
- the internal bus control unit 130 of the CPU unit 10 notifies the main control unit 100 of the CPU unit 10 that the clearing of the interrupt factor has been completed (step S154) and the uplink 52 Is generated and transmitted to all the IO units 20 via the downlink 51 (step S156).
- Each IO unit 20 deactivates the uplink in response to reception of PowerDown_frame.
- the main control unit 100 of the CPU unit 10 ends the interrupt task in response to the completion of the interrupt factor clear (step S158). This completes the execution of a series of interrupt processing after the interrupt signal is input.
- FIG. 10 is a time chart showing a processing procedure (second implementation example) when an interrupt signal is input in the PLC system 1 according to the present embodiment.
- the processing procedure shown in FIG. 10 is a WAKEUP_frame for changing to an active state and a TRG_frame (IRQ) including a command (trigger) for requesting an input state of an interrupt signal.
- the timing of transmission (step S122) is different. That is, in the second implementation example, when the internal bus control unit 130 of the CPU unit 10 receives the notification of the input of the interrupt signal, a frame for specifying the IO unit 20 to which the interrupt signal is input is generated ( Together with step S106), TRG_frame (IN) for collecting a time stamp from the IO unit 20 to which the interrupt signal is input is generated (step S107).
- the IO unit 20 transmits the target data to the CPU unit 10 in response to each frame (steps S112 and S126).
- FIG. 11 is a time chart showing a processing procedure (third implementation example) when an interrupt signal is input in the PLC system 1 according to the present embodiment.
- the processing procedure shown in FIG. 11 is a WAKEUP_frame for changing to an active state, TRG_frame (IRQ) including a command (trigger) for requesting an input state of an interrupt signal, IN data
- TRG_frame (IN) including a command (trigger) for executing refresh is simultaneously transmitted (step S109). That is, in the third implementation example, the internal bus control unit 130 of the CPU unit 10 responds to the notification of the input of the interrupt signal via the IRQ bus 6, and WakeUP_frame, TRG_frame (IRQ), TRG_frame (IN) Is generated (step S106), and the generated frame is transmitted via the downlink 51.
- the IO unit 20 In response to this frame, the IO unit 20 generates IRQ_frame and IN_frame and transmits them to the CPU unit 10 via the uplink 52 (step S113).
- the PLC system 1 employs a configuration in which the IRQ bus 6 is provided from the master control unit to a plurality of slave control units.
- the IO unit 20 that receives the interrupt signal is arranged at a position close to the CPU unit 10. This is to shorten the time required for transmission of the interrupt signal as much as possible. That is, the IO unit 20 that receives the interrupt signal is limited to the one close to the CPU unit 10, and the other IO units 20 do not receive the interrupt signal. In such a configuration, it is preferable to prevent the input of the interrupt signal from being erroneously notified to the IRQ bus 6 due to malfunction of noise.
- the main processing device 2 and / or the remote IO device 3 is provided with means for limiting the slave control units that can notify the master control unit of the input of the interrupt signal.
- an erroneous notification is transmitted from the (n + 1) th and subsequent IO units 20 via the IRQ bus 6. Need to be prevented.
- an interrupt notification circuit 250 (FIG. 2) having the following circuit configuration.
- FIG. 12 is a schematic diagram showing an example of a circuit configuration for preventing transmission of an erroneous notification on the IRQ bus 6 in the PLC system 1 according to the present embodiment.
- each of interrupt notification circuits 250 of IO unit 20 includes an AND circuit 252 and an OR circuit 254.
- the OR circuit 254 is inserted into the IRQ bus 6 (interrupt line), and is a logic between a signal notifying the input of the interrupt signal from the slave control unit in the previous stage and a signal notifying the input of its own interrupt signal. This corresponds to a logical sum circuit that outputs the sum as a signal for notifying the input of a new interrupt signal.
- the AND circuit 252 corresponds to a circuit for switching whether or not to output a signal notifying the input of a new interrupt signal output from the OR circuit 254 (logical sum circuit) to the subsequent slave control unit.
- the IRQ bus 6 is connected to one input terminal of the OR circuit 254 from the IO unit 20 disposed in the subsequent stage, and an interrupt factor (whether or not an interrupt signal is input) is input to the other input terminal. ing.
- the OR circuit 254 outputs a signal notifying the interrupt factor if there is at least one of notification of the input of the interrupt signal from the IO unit 20 arranged in the subsequent stage and occurrence of the interrupt factor in the own station. To do.
- the output from the OR circuit 254 is connected to one input terminal of the AND circuit 252.
- a “Wired IRQ propagation enable” signal for controlling propagation propriety on the IRQ bus 6 is input to the other input terminal of the AND circuit 252. That is, if the “Wired IRQ propagation enable” signal is not validated (activated), no valid signal is output from the AND circuit 252. That is, by disabling (inactivating) the “Wired IRQ propagation enable” signal, notification from the IO unit 20 and the IO units 20 arranged thereafter can be blocked.
- a “Wired IRQ propagation enable” signal is sent to the n IO units 20 close to the CPU unit 10. Is enabled (activated), and the “Wired IRQ propagation enable” signal is disabled (inactivated) for the other IO units 20.
- FIG. 13 is a schematic configuration diagram of a main processing apparatus 2A according to another embodiment of the present invention.
- the CPU unit 10A and the IO unit 20A are connected via a communication line (internal bus 5), but the IRQ bus 6 does not exist. Accordingly, the CPU unit 10A and the IO unit 20A have no function related to signal transmission via the IRQ bus 6.
- the IO unit 20A spontaneously sends a data frame (command) including a notification of the input of the interrupt signal. It is generated and transmitted to the CPU unit 10A via the communication line (internal bus 5).
- the CPU unit 10A can identify the transmission source IO unit 20A from this command, and requests a time stamp from the identified IO unit 20A.
- the IO unit 20A transmits the requested time stamp to the CPU unit 10A via the communication line (internal bus 5).
- the slave control unit (IO unit 20A) notifies the master control unit (CPU unit 10A) of the information indicating the input of the interrupt signal via the communication line (internal bus 5).
- a method for notifying the input of an interrupt signal from the IO unit 20A to the CPU unit 10A there is a method using polling from the CPU unit 10A. More specifically, the CPU unit 10A periodically and cyclically polls each IO unit 20A via the internal bus 5, and each IO unit 20A receives polling from the CPU unit 10A. Using this as a trigger, the interrupt signal input is notified. In other words, when each IO unit 20A receives polling from the CPU unit 10A, if it receives an interrupt signal between the previous polling and the current polling, it inputs the interrupt signal as a response to the polling. To be notified. In this way, by using polling, the CPU unit 10A can detect an input of an interrupt signal generated in any IO unit 20A.
- the master control unit (CPU unit 10A) is configured to periodically inquire the slave control unit (IO unit 20A) via the communication line (internal bus 5). If the IO unit 20A receives an interrupt signal when receiving an inquiry from the master control unit (CPU unit 10A), the IO unit 20A) sends information indicating the input of the interrupt signal to the master control unit (CPU unit 10A). Notice.
- the means for notifying the input of the interrupt signal via the communication line is not limited to the above-described method, and any method can be adopted.
- 1 PLC system 2 main processing device, 3 remote IO device, 4 field bus, 5 internal bus, 6 IRQ bus, 10 CPU unit, 12, 42 communication module, 20 IO unit, 30 power supply unit, 40 master unit, 51 down Link, 52 uplink, 100, 150 main control unit, 102, 152, 200 processor, 104, 208 non-volatile memory, 106 control program, 108 main memory, 110 fieldbus control unit, 112, 210a, 220a receiving unit, 114 , 210b, 220b transmission unit, 120 fieldbus communication controller, 122 memory controller, 124 FIFO memory, 126, 203 reception buffer, 128, 204 transmission buffer, 130 Bus control unit, 132 internal bus communication controller, 134 interrupt circuit, 136,270 counter, 142 transmission circuit, 144 reception circuit, 160 storage unit, 162, 202 shared memory, 164 reception memory, 166 transmission memory, 206 module, 212, 222 DES unit, 214, 224 repeat unit, 216, 226 SER unit, 230 reception processing unit,
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Abstract
Description
まず、本実施の形態に係るPLCシステムの全体構成について説明する。図1は、本実施の形態に係るPLCシステム1の全体構成を示す模式図である。
メイン処理装置2において、CPUユニット10は、マスター制御部に相当し、IOユニット20は、スレーブ制御部に相当する。リモートIO装置3において、マスターユニット40は、マスター制御部に相当し、IOユニット20は、スレーブ制御部に相当する。つまり、マスター制御部であるCPUユニット10およびマスターユニット40の各々は、通信ラインである内部バス5を介して少なくとも1つのIOユニット20に接続される。
次に、PLCシステム1を構成する各部のハードウェア構成について説明する。
図2は、本実施の形態に係るメイン処理装置2における接続構成を示す模式図である。なお、リモートIO装置3における接続構成についてもメイン処理装置2と同様である。以下の説明において、CPUユニット10について説明している部分は、マスターユニット40に置き換えることができる。
次に、CPUユニット10のハードウェア構成について説明する。
次に、マスターユニット40のハードウェア構成について説明する。図4は、本実施の形態に係るリモートIO装置3を構成するマスターユニット40のハードウェア構成を示す模式図である。
次に、IOユニット20のハードウェア構成について説明する。図5は、本実施の形態に係るPLCシステム1を構成するIOユニット20のハードウェア構成を示す模式図である。
上述の説明では、CPUユニット10の主制御部100、マスターユニット40の主制御部150、およびリモートIO装置3の各々について、プロセッサを用いて実現した構成例を示したが、これに限られない。例えば、プロセッサに代えて、ASIC(Application Specific Integrated Circuit)やFPGA(Field-Programmable Gate Array)などのハードウェア回路を用いて実現してもよい。逆に、一部または全部のコンポーネントをソフトウェアとして実装してもよい。
次に、図6を参照して、本実施の形態に係るPLCシステム1における割込処理の概要について説明する。図6は、本実施の形態に係るPLCシステム1における割込処理を説明するための図である。
次に、本実施の形態に係るPLCシステム1における低消費電力化について説明する。IOユニット20とCPUユニット10またはマスターユニット40との間の伝送帯域は、十分に大きくする必要があり、内部バス5のクロック周波数を高くせざるを得ない。クロック周波数が高くなることに伴って、伝送に係るコンポーネントでの消費電力が増大する。PLCシステム1においては、データの伝送方向の別に独立したリンクを含む内部バス5を採用しており、独立したリンクの構成を利用して、低消費電力化を行うための機能を実装してもよい。この低消費電力化の機能については、本発明の本質に直接関係するものではなく、採用は任意である。
次に、本実施の形態に係るPLCシステム1における割込信号が入力されたときの処理手順について説明する。
上述の第1の実装例の変形例(第2の実装例)として、第1番目および第2番目のフェーズを並列的に実行する処理手順について説明する。図10は、本実施の形態に係るPLCシステム1における割込信号が入力されたときの処理手順(第2の実装例)を示すタイムチャートである。
上述の第1の実装例の変形例(第3の実装例)として、第1番目および第2番目のフェーズに必要な遣り取りを一度の手続きで実行する処理手順について説明する。図11は、本実施の形態に係るPLCシステム1における割込信号が入力されたときの処理手順(第3の実装例)を示すタイムチャートである。
上述したように、PLCシステム1は、マスター制御部から複数のスレーブ制御部に亘ってIRQバス6を設ける構成を採用している。割込制御を実現する場合には、割込信号を受付けるIOユニット20をCPUユニット10から近い位置に配置する。これは、割込信号の伝送に要する時間を可能な限り短くするためのである。すなわち、割込信号を受付けるIOユニット20は、CPUユニット10に近いものに限られ、それ以外のIOユニット20は、割込信号を受付けない。このような構成において、IRQバス6にノイズが誤動作によって、割込信号の入力が誤って通知されることを防止することが好ましい。
上述の実施の形態においては、CPUユニット10とIOユニット20とが通信ライン(内部バス5)および割込ライン(IRQバス6)を介して接続されている構成について例示した。但し、割込信号の入力を示す情報を、割込ラインではなく、通信ラインを介して送信するようにしてもよい。以下、このような割込信号の入力を示す情報を、通信ラインを介してメイン処理装置へ送信する構成について説明する。
本実施の形態によれば、割込処理において、割込要因が発生したタイミングを知ることができるので、割込処理に係る各種のプログラムの実行タイミングなどをより適切に制御することができる。例えば、割込要因が発生してから所定時間後に何らかの信号を出力するといった制御などを容易に実現できる。
Claims (9)
- 制御システムの少なくとも一部を構成する制御装置であって、
マスター制御部と、
前記マスター制御部と少なくとも通信ラインを介して接続される少なくとも1つのスレーブ制御部とを備え、
前記スレーブ制御部は、
前記マスター制御部との間で同期された計時手段と、
割込信号を受付ける入力部と、
前記入力部を介して前記割込信号を受付けると、前記計時手段からタイミングを示す情報を取得するとともに、前記割込信号の入力を前記マスター制御部へ通知する手段と、
前記マスター制御部から前記通信ラインを介して要求を受信すると、前記取得したタイミングを示す情報を前記通信ラインを介して前記マスター制御部へ送信する手段とを含む、制御装置。 - 前記マスター制御部と前記制御部とは、さらに割込ラインを介して接続されており、
前記スレーブ制御部は、前記割込信号の入力を前記割込ラインを介して、前記マスター制御部へ通知する、請求項1に記載の制御装置。 - 前記スレーブ制御部の各々は、
前記割込ラインに介挿され、前段のスレーブ制御部からの割込信号の入力を通知する信号と、自身の割込信号の入力を通知する信号との論理和を新たな割込信号の入力を通知する信号として出力する論理和回路と、
前記論理和回路から出力される前記新たな割込信号の入力を通知する信号を後段のスレーブ制御部へ出力するか否かを切換える回路とを含む、請求項2に記載の制御装置。 - 前記スレーブ制御部は、前記割込信号の入力を示す情報を前記通信ラインを介して、前記マスター制御部へ通知する、請求項1に記載の制御装置。
- 前記マスター制御部は、前記通信ラインを介して前記スレーブ制御部へ周期的に問い合わせを行うように構成されており、
前記スレーブ制御部は、前記マスター制御部からの問い合わせを受信した際に、前記割込信号を受付けていれば、前記割込信号の入力を示す情報を前記マスター制御部へ通知する、請求項4に記載の制御装置。 - 前記通信ラインは、前記マスター制御部から前記スレーブ制御部へデータを伝送するためのダウンリンクと、前記スレーブ制御部から前記マスター制御部へデータを伝送するためのアップリンクとを含み、
前記マスター制御部は、
前記アップリンクを介した前記スレーブ制御部からのデータ送信が完了すると、前記アップリンクを非アクティブ化するための指令を、前記ダウンリンクを介して前記スレーブ制御部へ送信する手段と、
前記スレーブ制御部からの前記割込信号の入力の通知を受信すると、前記アップリンクをアクティブ化するための指令を、前記ダウンリンクを介して前記スレーブ制御部へ送信する手段とを含む、請求項1~5のいずれか1項に記載の制御装置。 - 前記制御装置は、前記スレーブ制御部を複数含んでおり、
前記制御装置は、前記割込信号の入力を前記マスター制御部へ通知可能なスレーブ制御部を制限するための手段を含む、請求項1~5のいずれか1項に記載の制御装置。 - 前記マスター制御部から前記通信ラインを介して送信される前記要求を受信するスレーブ制御部を、前記割込信号の入力の通知が可能なスレーブ制御部に制限するように構成される、請求項1~5のいずれか1項に記載の制御装置。
- マスター制御部と、前記マスター制御部と少なくとも通信ラインを介して接続される少なくとも1つのスレーブ制御部とを含む制御システムにおける制御方法であって、
前記スレーブ制御部が、入力部を介して割込信号を受付けると、前記マスター制御部との間で同期された計時手段からタイミングを示す情報を取得するとともに、前記割込信号の入力を前記マスター制御部へ通知するステップと、
前記スレーブ制御部が、前記マスター制御部から前記通信ラインを介して要求を受信すると、前記取得したタイミングを示す情報を前記通信ラインを介して前記マスター制御部へ送信するステップとを含む、制御方法。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019114085A (ja) * | 2017-12-25 | 2019-07-11 | オムロン株式会社 | 制御システムおよび制御装置 |
WO2020230412A1 (ja) * | 2019-05-16 | 2020-11-19 | オムロン株式会社 | 情報処理装置 |
JP2020187659A (ja) * | 2019-05-16 | 2020-11-19 | オムロン株式会社 | 情報処理装置 |
CN114600416A (zh) * | 2019-11-01 | 2022-06-07 | 欧姆龙株式会社 | 控制***、控制***的通信控制方法以及控制装置 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ITAN20120171A1 (it) * | 2012-12-21 | 2014-06-22 | Turbo S R L | Nodo elettrico per bus di tipo daisy-chain con trasmissione seriale dei dati e contemporanea trasmissione di energia. |
PL3107218T3 (pl) * | 2015-06-19 | 2023-10-09 | Gwf Ag | Sposób i urządzenie do transmisji danych oraz jednostka licznikowa |
DE102016214117A1 (de) | 2016-08-01 | 2018-02-01 | Siemens Aktiengesellschaft | Ermitteln einer Ausführungszeit eines Anwenderprogramms |
KR20180124340A (ko) * | 2017-05-11 | 2018-11-21 | 엘에스산전 주식회사 | 프로그래머블 논리 제어 장치 |
CN110968022B (zh) * | 2018-09-29 | 2021-09-17 | 欧姆龙(上海)有限公司 | 可编程逻辑控制器、可编程逻辑控制器***以及控制方法 |
JP7238647B2 (ja) * | 2019-07-08 | 2023-03-14 | オムロン株式会社 | 信号処理装置 |
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US11644808B2 (en) * | 2019-10-03 | 2023-05-09 | Keyence Corporation | Programable logic controller |
EP3882771A1 (en) * | 2020-03-16 | 2021-09-22 | Leica Microsystems CMS GmbH | Control system and method for operating a system |
CN112269338A (zh) * | 2020-10-23 | 2021-01-26 | 阳光电源股份有限公司 | 基于gpio的数字控制器通信方法及*** |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01217659A (ja) * | 1988-02-26 | 1989-08-31 | Fujitsu Ltd | I/o割り込み制御方式 |
JP2011086120A (ja) | 2009-10-15 | 2011-04-28 | Yaskawa Electric Corp | 制御装置 |
JP2012010216A (ja) | 2010-06-28 | 2012-01-12 | Panasonic Corp | 割込みシステム、ホスト装置、及び、周辺装置 |
WO2012081115A1 (ja) * | 2010-12-16 | 2012-06-21 | 三菱電機株式会社 | シーケンサシステムおよびその制御方法 |
WO2013136913A1 (ja) * | 2012-03-15 | 2013-09-19 | オムロン株式会社 | 制御装置および制御方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5481456A (en) * | 1990-09-04 | 1996-01-02 | Fuji Jukogyo Kabushiki Kaisha | Electronic control system having master/slave CPUs for a motor vehicle |
GB2292620B (en) * | 1994-08-16 | 1998-04-22 | Motorola Israel Ltd | Event driven programmer logic controller processor arrangement |
JPH09114541A (ja) * | 1995-10-17 | 1997-05-02 | Kokusai Electric Co Ltd | 割り込み発生時刻確認回路、処理装置 |
US5944840A (en) * | 1997-09-10 | 1999-08-31 | Bluewater Systems, Inc. | Continuous monitor for interrupt latency in real time systems |
US7080274B2 (en) * | 2001-08-23 | 2006-07-18 | Xerox Corporation | System architecture and method for synchronization of real-time clocks in a document processing system |
US20050091554A1 (en) | 2003-08-07 | 2005-04-28 | Dmitrii Loukianov | Event time-stamping |
US8266466B2 (en) | 2007-05-21 | 2012-09-11 | Cisco Technology, Inc. | Globally synchronized timestamp value counter |
CN101826000A (zh) | 2010-01-29 | 2010-09-08 | 北京龙芯中科技术服务中心有限公司 | 流水线微处理器的中断响应确定方法、装置及微处理器核 |
US9201821B2 (en) | 2012-09-27 | 2015-12-01 | Apple Inc. | Interrupt timestamping |
-
2014
- 2014-10-15 US US15/028,961 patent/US10409244B2/en active Active
- 2014-10-15 WO PCT/JP2014/077397 patent/WO2015056695A1/ja active Application Filing
- 2014-10-15 CN CN201480056471.2A patent/CN105637433B/zh active Active
- 2014-10-15 JP JP2015542628A patent/JP6037042B2/ja active Active
- 2014-10-15 EP EP14854694.8A patent/EP3045987B1/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01217659A (ja) * | 1988-02-26 | 1989-08-31 | Fujitsu Ltd | I/o割り込み制御方式 |
JP2011086120A (ja) | 2009-10-15 | 2011-04-28 | Yaskawa Electric Corp | 制御装置 |
JP2012010216A (ja) | 2010-06-28 | 2012-01-12 | Panasonic Corp | 割込みシステム、ホスト装置、及び、周辺装置 |
WO2012081115A1 (ja) * | 2010-12-16 | 2012-06-21 | 三菱電機株式会社 | シーケンサシステムおよびその制御方法 |
WO2013136913A1 (ja) * | 2012-03-15 | 2013-09-19 | オムロン株式会社 | 制御装置および制御方法 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019114085A (ja) * | 2017-12-25 | 2019-07-11 | オムロン株式会社 | 制御システムおよび制御装置 |
JP7087378B2 (ja) | 2017-12-25 | 2022-06-21 | オムロン株式会社 | 制御システムおよび制御装置 |
WO2020230412A1 (ja) * | 2019-05-16 | 2020-11-19 | オムロン株式会社 | 情報処理装置 |
JP2020187658A (ja) * | 2019-05-16 | 2020-11-19 | オムロン株式会社 | 情報処理装置 |
JP2020187659A (ja) * | 2019-05-16 | 2020-11-19 | オムロン株式会社 | 情報処理装置 |
JP7226084B2 (ja) | 2019-05-16 | 2023-02-21 | オムロン株式会社 | 情報処理装置 |
JP7259537B2 (ja) | 2019-05-16 | 2023-04-18 | オムロン株式会社 | 情報処理装置 |
US11782860B2 (en) | 2019-05-16 | 2023-10-10 | Omron Corporation | Information processing device for preventing occurrence of memory contention |
CN114600416A (zh) * | 2019-11-01 | 2022-06-07 | 欧姆龙株式会社 | 控制***、控制***的通信控制方法以及控制装置 |
CN114600416B (zh) * | 2019-11-01 | 2024-04-02 | 欧姆龙株式会社 | 控制***、控制***的通信控制方法以及控制装置 |
US12009914B2 (en) | 2019-11-01 | 2024-06-11 | Omron Corporation | Control system, communication control method of control system, and control device |
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