WO2015049852A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2015049852A1
WO2015049852A1 PCT/JP2014/004927 JP2014004927W WO2015049852A1 WO 2015049852 A1 WO2015049852 A1 WO 2015049852A1 JP 2014004927 W JP2014004927 W JP 2014004927W WO 2015049852 A1 WO2015049852 A1 WO 2015049852A1
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WIPO (PCT)
Prior art keywords
conductor film
semiconductor device
semiconductor
film
semiconductor layer
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PCT/JP2014/004927
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English (en)
French (fr)
Inventor
久雄 手島
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パナソニックＩｐマネジメント株式会社
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Application filed by パナソニックＩｐマネジメント株式会社 filed Critical パナソニックＩｐマネジメント株式会社
Priority to JP2015540375A priority Critical patent/JP6368921B2/ja
Publication of WO2015049852A1 publication Critical patent/WO2015049852A1/ja
Priority to US15/071,195 priority patent/US9966322B2/en

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Definitions

  • This disclosure relates to a semiconductor device.
  • the semiconductor device is a semiconductor device in which semiconductor elements are formed by performing processing such as diffusion and wiring on a semiconductor wafer, and further separated and packaged so as to be connected to an external circuit. Many such semiconductor devices are incorporated in electronic equipment.
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • bipolar transistors bipolar transistors
  • diodes diodes
  • a semiconductor device using such a semiconductor element has been difficult to downsize after packaging. The reason is that electrical connection is made by die bonding and wire bonding from both the upper surface side and the back surface side of the semiconductor element, and further, plastic type or ceramic type packaging is required.
  • the rewiring technique shown in Patent Document 2 is also effective for miniaturization.
  • a more three-dimensional wiring structure such as the side electrode forming technique of Patent Document 2
  • Patent Document 1 requires a through hole and a through electrode region in the semiconductor substrate, and an external terminal region electrically connected to the back surface on the upper surface of the semiconductor substrate. For this reason, the layout on the upper surface of the semiconductor substrate is restricted as compared with the conventional plastic type and ceramic type semiconductor devices, and there is a problem that the semiconductor element region having the main current path between the upper surface and the back surface becomes smaller. It was. As a result, it is difficult to lower the electrical resistance when using the circuit with respect to the area of the semiconductor substrate, which is a restriction on the design of the semiconductor device.
  • the semiconductor device shown in Patent Document 2 has a structure in which the back electrode is connected to the lead frame by solder.
  • the technique of Patent Document 2 is used in face-down mounting without using a lead frame, the height from the substrate to the upper surface of the upper surface electrode becomes lower than the height from the substrate to the upper surface of the side electrode, and connection failure occurs in the upper surface electrode. There was a problem that occurred.
  • a semiconductor device of the present disclosure includes a semiconductor layer in which a semiconductor element is formed, a first conductor film formed on the upper surface of the semiconductor layer and electrically connected to the semiconductor element, and a semiconductor A first protection film formed on a side surface of the layer and electrically connected to the semiconductor element; and a first protection film formed on the first conductor film and having an opening exposing the first conductor film.
  • the height from the upper surface of the semiconductor layer to the upper surface of the second conductor film is the same as or lower than the height from the upper surface of the semiconductor layer to the upper surface of the first conductor film.
  • both reduction of electrical resistance and securing of mechanical strength can be achieved, and face-down mounting becomes easy.
  • FIG. 1A is a plan view of the semiconductor device according to the first embodiment.
  • FIG. 1B is a cross-sectional view taken along line AA ′ in FIG.
  • FIG. 1C is a cross-sectional view of the semiconductor device according to the first embodiment mounted on a mounting substrate.
  • FIG. 1D is a plan view of the semiconductor device according to Modification 1 of the first embodiment.
  • FIG. 1E is a cross-sectional view of a semiconductor device according to Modification 2 of the first embodiment.
  • FIG. 2A is a cross-sectional view of a semiconductor device according to another modification of the first embodiment.
  • FIG. 2B is a plan view of the semiconductor device of FIG. 2A.
  • FIG. 2C is a cross-sectional view of a semiconductor device according to another modification of the first embodiment.
  • FIG. 1A is a plan view of the semiconductor device according to the first embodiment.
  • FIG. 2B is a plan view of the semiconductor device of FIG. 2A.
  • FIG. 2C is
  • FIG. 2D is a cross-sectional view of a semiconductor device according to another modification of the first embodiment.
  • FIG. 2E is a cross-sectional view of a semiconductor device according to another modification of the first embodiment.
  • FIG. 3A is a process sectional view of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 3B is a process sectional view of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 3C is a process sectional view of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 3D is a process sectional view of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 3E is a process sectional view of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 3A is a process sectional view of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 3B is a process sectional view of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 3C is a process section
  • FIG. 3F is a process sectional view of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 4A is a plan view of the semiconductor device according to the second embodiment.
  • FIG. 4B is a plan view of a state in which the semiconductor device according to the second embodiment is mounted on a mounting substrate.
  • 4C is a cross-sectional view taken along line AA ′ in FIG. 4B.
  • FIG. 4D is a plan view of a semiconductor device according to a modification of the second embodiment.
  • FIG. 5A is a plan view of the semiconductor device according to the third embodiment.
  • FIG. 5B is a cross-sectional view taken along line AA ′ in FIG. 5A.
  • FIG. 6A is a plan view of the semiconductor device according to the fourth embodiment.
  • FIG. 6B is a cross-sectional view taken along line AA ′ in FIG. 6A.
  • FIG. 6C is a cross-sectional view of the semiconductor device according to the fourth embodiment mounted on a mounting board.
  • FIG. 7A is a plan view of the semiconductor device according to the fifth embodiment.
  • FIG. 7B is a cross-sectional view taken along line AA ′ in FIG. 7A.
  • FIG. 8A is a plan view of the semiconductor device according to the sixth embodiment.
  • FIG. 8B is a cross-sectional view taken along line AA ′ in FIG. 8A.
  • FIG. 9A is a plan view of the semiconductor device according to the seventh embodiment.
  • FIG. 9B is a cross-sectional view taken along line AA ′ in FIG. 9A.
  • FIG. 9C is a cross-sectional view of the semiconductor device according to the seventh embodiment mounted on a mounting board.
  • FIG. 10A is a plan view of the semiconductor device according to the eighth embodiment.
  • FIG. 10B is a cross-sectional view taken along line AA ′ in FIG. 10A.
  • FIG. 10C is a cross-sectional view of the semiconductor device according to the eighth embodiment mounted on a mounting board.
  • FIG. 11A is a plan view of the semiconductor device according to the ninth embodiment.
  • FIG. 11B is a cross-sectional view taken along line AA ′ in FIG. 11A.
  • FIG. 11C is a cross-sectional view taken along line BB ′ in FIG. 11A.
  • FIG. 1A shows an upper surface of the semiconductor device according to the present embodiment.
  • the semiconductor device includes conductor films 102a, 102b, and 102c.
  • the conductor film 102c constitutes the side surface of the semiconductor device.
  • the conductor film 102a and the conductor film 102b are covered with a protective film 104 made of, for example, a silicon nitride film. Under the protective film 104, the conductor films 102a and 102b have a planar shape indicated by a broken line.
  • the “upper surface” means a surface to be bonded to the mounting substrate at the time of mounting
  • the “back surface” means a surface facing the “upper surface”.
  • side surface means a surface other than “upper surface” and “back surface”.
  • the protective film 104 is provided with a plurality of openings, and the conductor films 102a and 102b are exposed from each opening. Of the conductor film 102a and the conductor film 102b, each portion exposed from the opening functions as an external terminal. In the example shown in FIG. 1A, one opening 106a is formed in the protective film 104 with respect to the conductor film 102a, and three openings 106b, 106c, and 106d are formed in the protective film 104 with respect to the conductor film 102b. .
  • the side surface of the semiconductor device is composed of a conductor film 102c that functions as an external terminal. Note that in this specification, an “external terminal” of a semiconductor device means a terminal connected to a mounting substrate, typified by a gate terminal, a source terminal, a drain terminal, and the like.
  • FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. 1A.
  • FIG. 1B shows an example in which the semiconductor device is an FET.
  • the semiconductor device includes a first conductivity type semiconductor layer 110, a first conductivity type semiconductor layer 112 disposed on the semiconductor layer 110, and a second conductivity type semiconductor portion formed on the upper surface side of the semiconductor layer 112. 114 and a semiconductor portion 116 of the first conductivity type formed on the upper surface side of the semiconductor portion 114.
  • the semiconductor layer 112 and the semiconductor part 114 are made of, for example, Si.
  • the semiconductor part 114 and the semiconductor part 116 are formed by ion implantation, for example.
  • a groove 118 that penetrates the semiconductor portion 114 and the semiconductor portion 116 and reaches the semiconductor layer 112 is formed.
  • a gate electrode 122 is disposed in the trench 118 via a gate oxide film 120 made of, for example, SiO 2 .
  • the gate electrode 122 is made of, for example, polysilicon.
  • the semiconductor element included in the semiconductor device constitutes a so-called vertical MOSFET. That is, the semiconductor layer 110 constitutes a drain region, the semiconductor portion 114 constitutes a body region, the semiconductor layer 112 constitutes a drift region, and the semiconductor portion 116 constitutes a source region.
  • An insulating film 124 is disposed on a part of the upper surface of the semiconductor layer 112, and a conductive film 102a is disposed on the insulating film 124 as a gate terminal.
  • the conductor film 102a is electrically connected to the gate electrode 122.
  • the conductor film 102b is disposed as a source terminal.
  • the conductor film 102b is electrically connected to the semiconductor portion 116 that is a source region.
  • the conductor film 102b is electrically connected to the semiconductor portion 114 that is the body region.
  • the height from the upper surface of the semiconductor layer 112 to the upper surface of the conductor film 102c is the same as or lower than the height from the upper surface of the semiconductor layer 112 to the upper surfaces of the conductor film 102a and the conductor film 102b. According to this structure, connection failure is unlikely to occur in the conductor film 102a and the conductor film 102b, and face-down mounting on the mounting substrate is facilitated.
  • the upper surface of the conductor film 102a, the upper surface of the conductor film 102b, and the upper surface of the conductor film 102c are respectively located on the same plane. According to this structure, since the semiconductor device and the mounting substrate are likely to be parallel, face-down mounting on the mounting substrate is facilitated. In this specification, “same” includes a manufacturing error and means “substantially the same”.
  • the semiconductor device of FIG. 1B will be described as an Nch FET in which the first conductivity type is N-type and the second conductivity type is P-type.
  • a voltage is applied between the conductor film 102c (drain terminal) and the conductor film 102b (source terminal) and between the conductor film 102a (gate terminal) and the conductor film 102b.
  • the conductor film 102a and the conductor film 102c are electrically positive, and a channel is formed in the semiconductor portion 114 (body region).
  • a circuit current I flows from the conductor film 102c through the semiconductor layer 110 (mainly the drain region), the semiconductor layer 112, the semiconductor portion 114, the semiconductor portion 116, and the conductor film 102b.
  • each region in the path of the circuit current I desirably has as low an electrical resistance as possible in order to suppress the generation of heat.
  • the conductor film 102 c through which the circuit current I flows desirably has a thickness that is perpendicular to the side surfaces of the semiconductor layer 110 and the semiconductor layer 112. Specifically, the thickness is desirably about 10 ⁇ 1 ⁇ m or more and about 10 2 ⁇ m or less.
  • the thickness of the semiconductor layer 110 is preferably about 50 ⁇ m or more and about 200 ⁇ m or less from the viewpoint of reducing electric resistance.
  • FIG. 1C is a cross-sectional view taken along the line AA ′ in FIG. 1A when the semiconductor device is mounted on the mounting substrate 130.
  • the conductor film 102b, the conductor film 102a, and the conductor film 102c of the semiconductor device are electrically and mechanically connected to each other through a substrate pad 134 disposed on the mounting substrate 130 and a connection material 136, respectively.
  • the conductor film 102a is a gate terminal
  • the conductor film 102b is a source terminal
  • the conductor film 102c is a drain terminal.
  • the substrate pad 134 is disposed on the mounting substrate 130 and exposed from the opening of the substrate coating material 132.
  • the substrate coating material 132 is made of an insulator, and the substrate pad 134 is made of Cu, for example. Note that when the mounting substrate 130 is a flexible substrate, reliability after mounting is particularly high as compared with a conventional semiconductor device.
  • the height from the upper surface of the semiconductor layer 112 to the upper surface of the conductor film 102c is the same as or lower than the height from the upper surface of the semiconductor layer 112 to the upper surfaces of the conductor film 102a and the conductor film 102b. According to this structure, poor contact between the conductor film 102a and the conductor film 102b and the substrate pad 134 is less likely to occur. On the other hand, no connection failure occurs with respect to the conductor film 102c because the connection material 136 scoops up the side surface of the conductor film 102c. As a result, face-down mounting on the mounting substrate of the semiconductor device is facilitated.
  • the conductor film 102c may be provided with a plurality of recesses spaced from each other. According to this configuration, since the contact area between the connection material 136 and the conductor film 102c increases, the bonding strength and the mounting strength increase. As long as there is no problem in mounting, the depth and width of the plurality of recesses are not particularly limited.
  • the thermal expansion coefficients of the semiconductor layer 110 and the semiconductor layer 112 are different from the thermal expansion coefficient of the conductor film 102c, peeling may occur. This is because the semiconductor device receives stress between the semiconductor layer 110 and the semiconductor layer 112 and the conductor film 102c with respect to a change in environmental temperature including a mounting process. In order to disperse the stress that causes the separation, it is desirable to consider a stress dispersion treatment such as disposing the conductor film 102c continuously on the side surfaces of the semiconductor layers 110 and 112 without any breaks.
  • each conductor film As the material for each conductor film, metal, polysilicon with a high impurity concentration, conductive paste, or the like may be used.
  • Each conductor film is composed of a single layer film of an alloy, a single layer film of a pure element of a metal element or a metalloid element, a multilayer film of an alloy, a multilayer film of a pure element of a metal element or a semimetal element, or an alloy and a pure element. You may comprise by the laminated film of.
  • the metal element for example, Ti, W, Al, Cr, Mo, Au, Pt, Ag, Cu, Ni, Co, Pd, Sn, Pb, Bi, V may be used.
  • Sb, As, B, Si, or Ge may be used as the metalloid element.
  • nonmetallic elements such as P, C, N, and H may be used.
  • Au, Ag, Pd, Bi, and the like are generally good in wettability with a connection material such as solder, and thus are desirably disposed on the surface layer of each conductor film.
  • connection material 136 may be a solder material using any one of PbSn, AuSn, CuSn, AgSn, BiSn, AuSi, AuGe, and AuSb. As long as the mechanical strength and electrical resistance after mounting can withstand the required specifications, the material may not be a solder material.
  • a conductive paste, a conductive resin, or a brazing material in which a metal such as Ag, Cu, Au, Ni, or Al and an organic material are mixed may be used.
  • opening areas The areas of the conductor film 102a and the conductor film 102b exposed from the openings 106a to 106d provided in the protective film 104 shown in FIG. 1A (hereinafter referred to as opening areas) are preferably the same.
  • connection material 136 is printed on the substrate pad 134 of the mounting substrate 130 using a screen mask.
  • the semiconductor device is disposed on the uncured connection material 136 in a face-down manner and temporarily fixed. Thereafter, the connection material 136 is melted by reflow to bond the mounting substrate 130 and the semiconductor device.
  • the height of the connection material 136 provided in the openings after the reflow from the upper surface of the substrate pad 134 is substantially the same, and the mounting is performed with an inclination. The occurrence of mounting defects can be reduced. Furthermore, the area of the upper surface of the entire conductor film 102c may be the same as each opening area.
  • the perimeters of the openings 106a to 106d provided in the protective film 104 are preferably the same. Since surface tension is generated when the connecting material 136 is melted, an inclination is formed in the connecting material 136 on the edge side of the opening. And since the magnitude
  • each opening if the opening area is the same and the perimeter is the same, the height of the connection material 136 from the upper surface of the substrate pad 134 during mounting can be made the same with higher accuracy. Defects can be reduced.
  • Modification 1 a semiconductor device according to Modification 1 of the first embodiment will be described with reference to FIG. 1D.
  • Modification 1 differs from the semiconductor device shown in FIGS. 1A and 1B in the configuration of the conductor film 102c.
  • the conductor film 102c partially constitutes the side surface of the semiconductor device. Specifically, the conductor film 102c is formed on at least the side surface A and the opposing side surface B of the lower semiconductor layer.
  • the conductor film 102c may be formed over part of the other two side surfaces that intersect the side surface A and the side surface B.
  • the semiconductor device may include a pair of surfaces configured by the conductor film 102c and a pair of surfaces including a portion where the conductor film 102c is not disposed.
  • connection material 136 melted at the time of reflow has a surface tension and has a force to draw the conductive film 102c having good wettability.
  • the conductor film 102c may be partially formed on the side surface, and there may be a region where the conductor film 102c is not formed on the side surface. Since the wiring of the mounting substrate connected to the conductive film 102a and the conductive film 102b can be drawn through the region where the conductive film 102c is not formed, this configuration is particularly useful when the mounting substrate is a single-layer wiring. . Further, by devising the arrangement of the conductor film 102c, the wiring drawn from the mounting substrate can be thickened, so that the on-resistance can be easily reduced.
  • Modification 2 a semiconductor device according to Modification 2 of the first embodiment will be described with reference to FIG. 1E.
  • Modification 2 differs from the semiconductor device shown in FIGS. 1A and B in that a contact region 126 having a resistance lower than that of the semiconductor layer 110 is formed between the semiconductor layer 110 and the conductor film 102c.
  • the impurity concentration of the contact region 126 is desirably 1 ⁇ 10 20 [/ cm 3 ] or more. If the conductivity type of the semiconductor layer 110 is P-type, 1 ⁇ 10 19 [/ cm 3 ] or more is desirable.
  • the conductive film 102c is formed of Mo, Cr, Ti, W, Ni, Au, Pt, Al, Co or the like by using an EB (Electron Beam) vapor deposition method which is one of PVD (Physical Vapor Deposition) methods
  • EB Electro Beam
  • PVD Physical Vapor Deposition
  • a sputtering method or a CVD (Chemical Vapor Deposition) method which is another method of the PVD method, is used to form a silicide layer by applying heat treatment, or a silicide layer is formed by a sputtering method.
  • the contact region 126 can also be formed by this method.
  • the contact region 126 can be formed by additionally implanting impurities into the semiconductor layer 110 or diffusing the impurities. Further, the contact region 126 has a lower resistance by applying heat treatment after the impurity implantation to activate the impurity.
  • the contact region 126 may not be provided, and the contact surface of the semiconductor layer 110 with the conductor film 102c may be roughened. That is, since the area of the contact surface increases, the contact resistance can be lowered accordingly.
  • the electrical resistance between the semiconductor layer 110 and the conductor film 102c can be reduced, so that the semiconductor device can be downsized.
  • the description has been given using the Nch FET as the semiconductor element, but the same effect can be obtained even with the Pch FET.
  • the FET it may be realized by a diode shown in FIG. 2A, a bipolar transistor shown in FIG. 2C, a thyristor shown in FIG. 2D, and an IGBT (Insulated Gate Bipolar Transistor) shown in FIG. 2E.
  • FIG. 2A includes an N-type semiconductor layer 200, an N-type semiconductor layer 202 disposed on the semiconductor layer 200, a P-type semiconductor portion 204 formed on the semiconductor layer 202, and a semiconductor portion 204. And a conductor film 206 disposed on the substrate.
  • An insulating film 210 is formed on the semiconductor layer 202 to insulate and separate the conductive films. The conductor film 206 is exposed from the opening of the protective film 212.
  • the conductor film 206 constitutes an anode region, and the conductor film 208 constitutes a cathode region.
  • the impurity concentration of the semiconductor layer 200 is higher than the impurity concentration of the semiconductor layer 202.
  • 2B is a plan view of the diode shown in FIG. 2A and shows a structure in which four openings are formed in the conductor film 206.
  • the conductor film 208 constitutes a side surface of the semiconductor device and is electrically connected to the semiconductor layer 200 and the semiconductor layer 202. Note that when the semiconductor layer 200 and the semiconductor layer 202 are P-type and the semiconductor portion 204 is N-type, the anode region and the cathode region are interchanged.
  • the conductor film 208 may cover the insulating film 210. That is, the conductor film 208 may cover a portion where the upper surface and the side surface of the semiconductor layer intersect. In this case, it is desirable that the end portion 214 of the conductor film 208 on the insulating film 210 is covered with the protective film 212.
  • N-type semiconductor layer 220 includes an N-type semiconductor layer 220, an N-type semiconductor layer 222 disposed on the semiconductor layer 220, a P-type semiconductor portion 224 formed on the semiconductor layer 222, And an N-type semiconductor portion 226 disposed on the semiconductor portion 224.
  • the conductor film 228 electrically connected to the semiconductor portion 224 constitutes a base region, and the conductor film 230 electrically connected to the semiconductor portion 226 constitutes an emitter region.
  • the conductor film 232 constitutes a collector region.
  • Each conductor film is insulated and separated by an insulating film 234. In the opening provided in the protective film 236, the conductor film 228 and the conductor film 230 are exposed to form an external terminal. 2C is substantially the same as the structure shown in FIG. 1A.
  • the thyristor shown in FIG. 2D includes a P-type semiconductor layer 240, an N-type semiconductor layer 242 disposed on the semiconductor layer 240, a P-type semiconductor portion 244 disposed on the semiconductor layer 242, and a semiconductor And an N-type semiconductor portion 246 formed in the portion 244.
  • Each conductor film is insulated and separated by an insulating film 254. In the opening provided in the protective film 256, the conductor film 248 and the conductor film 250 are exposed to form an external terminal.
  • the conductor film 252 is electrically connected to the semiconductor layer 240 and constitutes an anode region that is an external terminal.
  • the conductor film 248 that is electrically connected to the semiconductor portion 244 constitutes a gate terminal.
  • the conductor film 250 that is electrically connected to the semiconductor portion 246 constitutes a cathode region. Note that when the semiconductor layer 240 and the semiconductor portion 244 are N-type and the semiconductor layer 242 and the semiconductor portion 246 are P-type, the anode region and the cathode region are interchanged.
  • 2D is substantially the same as the structure shown in FIG. 1A regarding the conductor film and the protective film of the thyristor shown in FIG. 2D.
  • the IGBT shown in FIG. 2E includes a P-type semiconductor layer 260, an N-type semiconductor layer 262 disposed on the semiconductor layer 260, an N-type semiconductor layer 264 disposed on the semiconductor layer 262, and a semiconductor.
  • a P-type semiconductor portion 266 formed in the layer 264 and an N-type semiconductor portion 268 formed in the semiconductor portion 266 are provided.
  • a gate oxide film 272 disposed inside a trench 270 formed so as to penetrate the semiconductor portion 268 and the semiconductor portion 266 and reach the semiconductor layer 264 is disposed.
  • a gate electrode 274 is disposed inside the gate oxide film 272. In the opening provided in the protective film 284, the conductor film 280 and the conductor film 282 are exposed to form an external terminal.
  • the conductor film 276 is electrically connected to the semiconductor layer 260 and constitutes a collector, while the semiconductor layer 262 and the semiconductor layer 264 are insulated from each other by the insulating film 278.
  • the conductor film 280 that is insulated from the semiconductor layer 264 by the insulating film 278 is electrically connected to the gate electrode 274 to form a gate terminal.
  • the conductor film 282 electrically connected to the semiconductor portion 268 constitutes an emitter.
  • the conductor film 280 and the conductor film 276 and the conductor film 282 and the conductor film 276 are insulated by the insulating film 278.
  • 2E is substantially the same as the structure shown in FIG. 1A.
  • a semiconductor element such as an FET is formed on a wafer-like semiconductor substrate 300.
  • the wafer-like semiconductor substrate 300 has an upper surface 302 and a back surface 304 facing the upper surface 302.
  • a groove 306 reaching the semiconductor layer 110 from the upper surface 302 side is formed along the outer shape of the FET.
  • Blade dicing or laser dicing can be used to form the groove 306.
  • the groove 306 can be formed by dry etching using a photoresist or a hard mask. In this case, damage caused by dicing on the semiconductor device can be reduced. Further, since the batch processing can be performed on the entire upper surface 302 of the wafer-like semiconductor substrate 300, the groove 306 can be formed in a short time. Further, it is also possible to perform processing by wet etching using a mask such as a photoresist, a silicon oxide film mask, or a metal mask.
  • an opening for forming the conductor film 102b is formed on the upper surface 302.
  • the opening can be formed by etching part of the insulating film 124 using a mask such as a photoresist.
  • the conductor film 102 a is formed on the insulating film 124, the conductor film 102 b is formed in the opening, and the conductor film 102 c is formed in the groove 306.
  • a CVD method for forming the conductor film.
  • the conductor film 102c can be easily thickened, so that the electrical resistance of the conductor film 102c can be reduced.
  • a plating method may be used.
  • a protective film 104 is formed on the upper surface 302.
  • the semiconductor device is completed by grinding from the back surface 304 of the wafer-like semiconductor substrate 300 to a position reaching the groove 306.
  • the grinding process for example, back grinding, polishing, wet etching, dry etching, or CMP (Chemical Mechanical Polishing) can be used. You may use combining these methods.
  • FIG. 4A is a plan view of the semiconductor device. A region covered by the protective film 404 disposed on the conductor films 402a and 402b is indicated by a broken line.
  • the semiconductor device includes a conductor film 402a, a conductor film 402b formed so as to be surrounded by the conductor film 402a, and a protective film 404 formed on each conductor film.
  • Two openings 406a and 406b are provided in the protective film 404 with respect to the conductor film 402a, and one opening 406c is provided in the protective film 404 with respect to the conductor film 402b.
  • the conductor films 402a and 402b and the conductor film 402c provided on the mutually opposing side surfaces of the semiconductor device each constitute an external terminal.
  • FIG. 4B is a plan view when the semiconductor device is mounted on the mounting substrate 130. It is the figure by which the part other than a conductor film in the opening part provided in the protective film 404 and the board
  • 4C is a cross-sectional view taken along line AA ′ of FIG. 4B.
  • each conductive film is connected to a substrate pad 134 provided on the mounting substrate 130 by a connection material 136.
  • the substrate pad 134 serves as a wiring for the mounting substrate 130.
  • the conductor film 402a functions as a source electrode
  • the conductor film 402b functions as a gate electrode
  • the conductor film 402c functions as a drain electrode.
  • the gate-drain capacitance is reduced by disposing the conductor film 402a serving as the source electrode between the conductor film 402b serving as the gate electrode and the conductor film 402c serving as the drain electrode. I can do it. This is because the gate-source capacitance and the source-drain capacitance are connected in series, and the gate-drain capacitance is reduced when viewed as an equivalent circuit. This makes it possible to provide a semiconductor device that excels in high-frequency driving.
  • FIG. 4D is a plan view of a semiconductor device according to a modification of the present embodiment.
  • the conductor film 402b as a gate terminal may be circular in plan view, and the conductor film 402a as a source terminal may be formed in a donut shape surrounding the conductor film 402b.
  • the conductor film 402a and the conductor film 402b are circular, the semiconductor device may rotate during face-down mounting. Therefore, in order to prevent the semiconductor device from rotating, the conductor film 402c is formed so as to constitute only the four corners of the semiconductor device.
  • the semiconductor element may be another high-speed driving semiconductor element such as a bipolar transistor or IGBT.
  • the source terminal is not limited to the case where it is connected to the ground potential, and any terminal that is supplied with the lowest potential from an external circuit among the terminals of the semiconductor element may be used.
  • FIG. 5A is a plan view of the semiconductor device.
  • FIG. 5B is a cross-sectional view of the semiconductor device taken along line AA ′ in FIG. 5A.
  • the material of the protective film 500 may be, for example, a silicon oxide film, a silicon nitride film, an organic material, a resin, silicone (silicone), a metal oxide material, or a composite material of the above materials, or a stack of the above materials. May be formed.
  • the protective film 500 may be formed by a CVD method or the like.
  • the manufacturing speed is maximized within a range suitable for the mechanical strength of the semiconductor device in order to reduce the manufacturing cost by shortening the manufacturing time per unit.
  • the manufacturing speed may have to be suppressed.
  • the conductor film 102c is covered with the protective film 500, the mechanical strength of the semiconductor device is increased. As a result, since it is not necessary to suppress the manufacturing speed, the mass productivity is improved and the cost can be reduced.
  • FIG. 6A is a plan view of the semiconductor device.
  • 6B is a cross-sectional structure diagram of the semiconductor device taken along line AA ′ in FIG. 6A.
  • FIG. 6C is a cross-sectional view taken along line AA ′ in FIG. 6A when the semiconductor device is mounted on the mounting substrate.
  • the conductor films 102a and 102b exposed from the openings 106a, 106b, 106c and 106d provided in the protective film 104, and a part of the upper surface and side surfaces of the conductor film 102c are the conductor film 600. Covered with. The entire side surface of the conductor film 102 c may be covered with the conductor film 600.
  • electroless plating is performed on the entire upper surface 302 side of the wafer-like semiconductor substrate 300. good.
  • the conductor film 600 having better wettability with respect to the connection material 136 than the conductor film 102c is formed.
  • connection material 136 is likely to creep up on the conductor film 102c, the bonding area is increased and the bonding strength is increased.
  • the thickness of the conductor film 600 can be changed as appropriate by adjusting the concentration of the electroless plating solution and the stirring speed of the plating solution during plating.
  • the conductor film 102c and the conductor film 600 may be formed of different materials.
  • the conductor film 102c is Al
  • the wettability with SnAg solder which is 1 type of the Sn containing connection material is bad.
  • electroless plating of Ni or Au with good wettability of SnAg solder can be performed.
  • the material of the conductor film 600 is not limited to Ni or Au.
  • FIG. 7A is a plan view of the semiconductor device. As shown in FIG. 7A, a plurality of grooves 700 are formed at intervals on the outer periphery of the upper surface of the semiconductor device. A conductor film 702 is formed in the groove 700.
  • FIG. 7B is a cross-sectional view of the semiconductor device taken along line AA ′ in FIG. 7A.
  • the upper surface of the conductor film 702 is flush with the conductor films 102a and 102b.
  • the height of the upper surface of the conductor film 102 c is lower than the height of the upper surface of the conductor film 702, so that a step 704 is formed between the conductor film 102 c and the conductor film 702.
  • the bonding strength with the mounting substrate is further increased.
  • the semiconductor device manufacturing method according to the present embodiment may be performed by adding the following steps to the manufacturing method of the first embodiment. For example, in the process of forming a semiconductor element, a plurality of grooves 700 are formed in the semiconductor layer 112 at intervals. A conductor film 702 is formed in the groove 700 simultaneously with the formation of the conductor films 102a and 102b. Thereafter, the semiconductor device can be realized by performing substantially the same steps as the manufacturing method according to the first embodiment.
  • the depth of the groove 700 from the upper surface of the semiconductor layer 112, the width in the side surface direction, and the number of the grooves 700 are arbitrary as long as the operation of the semiconductor element is not adversely affected. Note that the groove 700 may be formed to reach the semiconductor layer 110.
  • FIG. 8A is a plan view of the semiconductor device.
  • FIG. 8B is a cross-sectional view of the semiconductor device taken along line AA ′ in FIG. 8A.
  • the side surface of the semiconductor device is composed of a conductor film 800.
  • the height of the upper surface of the conductor film 800 is lower than the height of the upper surface of the conductor film 102c, so that a step 802 is formed between the conductor film 102c and the conductor film 800.
  • the conductor film 102c and the conductor film 800 are in contact with the bonding material. Therefore, the bonding strength with the mounting substrate is further increased.
  • the semiconductor device manufacturing method according to this embodiment may be performed by adding the following steps to the manufacturing method according to the first embodiment.
  • the semiconductor device can be obtained by holding only the back surface 304 side in an electroless plating bath and grinding the plating film while holding the top surface 302 side of the singulated semiconductor device.
  • FIG. 9A is a plan view of the semiconductor device.
  • FIG. 9B is a cross-sectional view of the semiconductor device taken along line AA ′ in FIG. 9A.
  • a groove 900 is formed on the upper surface of the protective film 104.
  • the groove 900 is formed between the conductor films.
  • the groove 900 is formed so as not to penetrate the protective film 104.
  • the groove 900 may be formed so as to penetrate the protective film 104 and expose the conductor film 102b and the insulating film 124.
  • FIG. 9C is a cross-sectional view taken along line AA ′ in FIG. 9A when the semiconductor device is mounted on the mounting substrate.
  • a capillary phenomenon occurs in the gap between the semiconductor device and the mounting substrate.
  • the connection material 136 melted by the capillary phenomenon may be connected.
  • the protective film 104 has the groove 900.
  • the groove 900 can prevent the connection materials 136 from being connected to each other by capillary action.
  • the interval between the conductor films can be narrowed, and the semiconductor device can be downsized.
  • the semiconductor device manufacturing method according to this embodiment may be performed by adding the following steps to the manufacturing method according to the first embodiment. For example, after forming the protective film 104, a groove 900 may be formed between the conductor films on the upper surface of the protective film 104 by etching.
  • a groove may be formed in the substrate coating material 132, or a groove may be formed in either the protective film 104 or the substrate coating material 132.
  • FIG. 10A is a plan view of the semiconductor device according to the eighth embodiment.
  • 10B is a cross-sectional view of the semiconductor device taken along line AA ′ in FIG. 10A.
  • FIG. 10C is a cross-sectional view taken along line AA ′ in FIG. 10A when the semiconductor device is mounted on the mounting substrate.
  • the side surface of the semiconductor device is covered with a protective film 1000.
  • the semiconductor device further includes a conductor film 1002 formed on the back surface of the semiconductor layer 110 and electrically connected to the conductor film 102c.
  • the side surface of the conductor film 102 c and the side surface and back surface of the conductor film 1002 are covered with a protective film 1000.
  • the ratio of the resistance component due to the sheet resistance of the semiconductor layer 110 may be higher than the resistance component of the entire semiconductor device.
  • the resistance component can be reduced by having the conductor film 1002.
  • the thicker the conductor film 1002 the lower the electrical resistance.
  • the thickness of the conductor film 1002 is desirably about 3 ⁇ m or more, and there is no particular upper limit value as long as mounting is not affected.
  • the mechanical strength of the semiconductor device is increased, so that the handling in the manufacturing process including mounting of the semiconductor device is facilitated.
  • the protective film 1000 preferably has insulating properties.
  • a material such as a silicon oxide film, a silicon nitride film, an organic material, a resin, silicone, a metal oxide material, a composite material thereof, or a laminated structure thereof.
  • the thickness of the conductor film 102b and the thickness of the conductor film 1002 are the same, and the thickness of the protective film 104 and the thickness of the protective film 1000 disposed on the back surface of the conductor film 1002 are the same, Since the internal stress of the semiconductor device is relieved, even when the semiconductor layer is thin, the semiconductor device is unlikely to warp and is easy to handle.
  • the semiconductor device manufacturing method according to the present embodiment may be performed by adding the following steps to the manufacturing method of the first embodiment. For example, after the back surface of the semiconductor layer 110 is ground, the conductor film 1002 is formed by sputtering or vapor deposition. Then, if the protective film 1000 is formed on the side surface of the conductor film 102c and the side surface and back surface of the conductor film 1002, a semiconductor device is obtained.
  • FIG. 11A is a plan view of the semiconductor device.
  • FIG. 11B is a cross-sectional view of the semiconductor device taken along line AA ′ in FIG. 11A.
  • FIG. 11C is a cross-sectional view of the semiconductor device taken along line BB ′ in FIG. 11A.
  • the semiconductor device includes conductor films 1100 and 1102 that form the upper surface and side surfaces of the semiconductor device, conductor film 1104 that forms the side surfaces of the semiconductor device, and protective film 1106 that covers the conductor films 1100 and 1102. With.
  • the conductor films 1100 and 1102 are disposed on the insulating film 1108.
  • the conductor film 1100 serves as a gate electrode
  • the conductor film 1102 serves as a source electrode
  • the conductor film 1104 serves as a drain electrode.
  • the conductor film 1100 and the conductor film 1102 cover the upper surface and the side surface of the semiconductor device, respectively, and are integrally formed.
  • the on-resistance increases accordingly.
  • the area can be secured by disposing the conductor film 1102 serving as the source electrode also on the side surface of the semiconductor layer, the increase in the on-resistance is suppressed, and the semiconductor device Miniaturization is possible.
  • the first to ninth embodiments and their modifications have been described as examples of the technology disclosed in the present application.
  • the technology in the present disclosure is not limited to this, and can also be applied to embodiments in which changes, replacements, additions, omissions, and the like are made.
  • the semiconductor layer may be a material having semiconductor properties such as Si, SiC, GaAs, and GaN.
  • the effect of this indication can be acquired in this structure irrespective of the polarity of a semiconductor element.
  • a cube is presented as an example of the shape of the semiconductor device, but the present disclosure also applies to a cylindrical shape, a polygonal prism shape such as a triangular prism or a hexagonal prism, or a polygonal pyramid shape such as a triangular pyramid or a hexagonal pyramid. An effect can be obtained.

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Abstract

　半導体素子が形成された半導体層と、半導体層の上面上に形成され、半導体素子と電気的に接続された第１の導体膜と、半導体層の側面上に形成され、半導体素子と電気的に接続された第２の導体膜と、第１の導体膜上に形成され、第１の導体膜を露出する開口部を有する第１の保護膜とを備え、半導体層の上面から第２の導体膜の上面までの高さは、半導体層の上面から第１の導体膜の上面までの高さと同じ、又は、低い半導体装置。

Description

半導体装置
　本開示は半導体装置に関する。
　半導体装置は、半導体ウェハに拡散・配線等の加工処理を行なって半導体素子を形成し、更に、外部回路と接続できるように個片化・パッケージングしたものである。このような半導体装置は、電子機器の中に非常に多く組み込まれている。
　半導体装置のうち、大電流を扱うＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）、バイポーラトランジスタ、ダイオード等の半導体素子では、素子の上面と裏面との間に主な電流経路を有する構造を多く採用している。このような半導体素子を用いる半導体装置は、パッケージング後の小型化が困難であった。理由は、半導体素子の上面側及び裏面側の両方からダイボンディングおよびワイヤーボンディグによって電気的接続を行なうこと、さらに、プラスチックタイプやセラミックタイプのパッケージングが必要であることである。
　これに対し近年では、特許文献１のような、ウェハ状態の組立工程において、貫通電極及び再配線の形成によって電気的接続を確保する技術であるウェハレベルＣＳＰ（Ｃｈｉｐ　Ｓｉｚｅ　Ｐａｃｋａｇｅ）技術が注目されている。
　また、特許文献２に示す再配線の技術も小型化に有効である。特許文献２の側面電極形成技術のような、より立体的な配線構造を用いることにより、半導体素子の集積度を高めながら、特性の向上を図ることができる。
特開２０１０－１２９７４９号公報 特開２００９－２２４６４１号公報
　しかし、特許文献１に示す半導体装置では、半導体基板内に貫通孔と貫通電極領域が必要であり、かつ、半導体基板の上面上に裏面と電気的に接続した外部端子領域が必要である。このため、従来のプラスチックタイプやセラミックタイプの半導体装置に比べて、半導体基板の上面上のレイアウトに制約が生じ、上面と裏面との間に主電流経路を有する半導体素子領域が小さくなる課題があった。その結果、半導体基板の面積に対する回路使用時の電気抵抗を下げることが困難となり、半導体装置の設計上の制約となっていた。
　また、従来のウェハレベルＣＳＰタイプでは、半導体装置の側面部等、表出している部分があり、機械的な外力に対して脆いという課題があった。
　また、特許文献２に示す半導体装置は、裏面電極をリードフレームにはんだで接続する構造である。リードフレームを使用しないフェースダウン実装において特許文献２の技術を用いると、基板から上面電極の上面までの高さが、基板から側面電極の上面までの高さよりも低くなり、上面電極において接続不良が発生するという課題があった。
　以上に鑑みて、本開示は、電気抵抗の削減と機械強度の確保とを両立でき、且つ、フェースダウン実装が容易な半導体装置の実現を目的とする。
　上記課題を解決するため、本開示の半導体装置は、半導体素子が形成された半導体層と、半導体層の上面上に形成され、半導体素子と電気的に接続された第１の導体膜と、半導体層の側面上に形成され、半導体素子と電気的に接続された第２の導体膜と、第１の導体膜上に形成され、第１の導体膜を露出する開口部を有する第１の保護膜とを備え、半導体層の上面から第２の導体膜の上面までの高さは、半導体層の上面から第１の導体膜の上面までの高さと同じ、又は、低い。
　本開示の半導体装置によると、電気抵抗の削減と機械強度の確保とを両立でき、且つ、フェースダウン実装が容易となる。
図１Ａは、第１の実施形態に係る半導体装置の平面図である。 図１Ｂは、図１の線分Ａ－Ａ´における断面図である。 図１Ｃは、第１の実施形態に係る半導体装置を実装基板に実装した状態の断面図である。 図１Ｄは、第１の実施形態の変形例１に係る半導体装置の平面図である。 図１Ｅは、第１の実施形態の変形例２に係る半導体装置の断面図である。 図２Ａは、第１の実施形態の他の変形例に係る半導体装置の断面図である。 図２Ｂは、図２Ａの半導体装置の平面図である。 図２Ｃは、第１の実施形態の他の変形例に係る半導体装置の断面図である。 図２Ｄは、第１の実施形態の他の変形例に係る半導体装置の断面図である。 図２Ｅは、第１の実施形態の他の変形例に係る半導体装置の断面図である。 図３Ａは、第１の実施形態に係る半導体装置の製造方法の工程断面図である。 図３Ｂは、第１の実施形態に係る半導体装置の製造方法の工程断面図である。 図３Ｃは、第１の実施形態に係る半導体装置の製造方法の工程断面図である。 図３Ｄは、第１の実施形態に係る半導体装置の製造方法の工程断面図である。 図３Ｅは、第１の実施形態に係る半導体装置の製造方法の工程断面図である。 図３Ｆは、第１の実施形態に係る半導体装置の製造方法の工程断面図である。 図４Ａは、第２の実施形態に係る半導体装置の平面図である。 図４Ｂは、第２の実施形態に係る半導体装置を実装基板に実装した状態の平面図である。 図４Ｃは、図４Ｂの線分Ａ－Ａ´における断面図である。 図４Ｄは、第２の実施形態の変形例に係る半導体装置の平面図である。 図５Ａは、第３の実施形態に係る半導体装置の平面図である。 図５Ｂは、図５Ａの線分Ａ－Ａ´における断面図である。 図６Ａは、第４の実施形態に係る半導体装置の平面図である。 図６Ｂは、図６Ａの線分Ａ－Ａ´における断面図である。 図６Ｃは、第４の実施形態に係る半導体装置を実装基板に実装した状態の断面図である。 図７Ａは、第５の実施形態に係る半導体装置の平面図である。 図７Ｂは、図７Ａの線分Ａ－Ａ´における断面図である。 図８Ａは、第６の実施形態に係る半導体装置の平面図である。 図８Ｂは、図８Ａの線分Ａ－Ａ´における断面図である。 図９Ａは、第７の実施形態に係る半導体装置の平面図である。 図９Ｂは、図９Ａの線分Ａ－Ａ´における断面図である。 図９Ｃは、第７の実施形態に係る半導体装置を実装基板に実装した状態の断面図である。 図１０Ａは、第８の実施形態に係る半導体装置の平面図である。 図１０Ｂは、図１０Ａの線分Ａ－Ａ´における断面図である。 図１０Ｃは、第８の実施形態に係る半導体装置を実装基板に実装した状態の断面図である。 図１１Ａは、第９の実施形態に係る半導体装置の平面図である。 図１１Ｂは、図１１Ａの線分Ａ－Ａ´における断面図である。 図１１Ｃは、図１１Ａの線分Ｂ－Ｂ´における断面図である。
　以下、本開示の実施の形態について、図面を参照しながら説明する。但し、既によく知られた事項の詳細説明や実質的に同一の構成に対する重複説明を省略する場合がある。本開示は以下の実施形態に限定されず本開示の技術の趣旨を逸脱しない範囲において、複数の実施形態の組み合わせや、構成要素の均等物による代替も可能である。
　（第１の実施形態）
　以下、本開示の第１の実施形態に係る半導体装置について、図１Ａ～図３Ｅを参照しながら説明する。
　図１Ａは、本実施形態に係る半導体装置の上面を示す。半導体装置は、導体膜１０２ａ、１０２ｂ及び１０２ｃを備える。導体膜１０２ｃは半導体装置の側面を構成している。導体膜１０２ａ及び導体膜１０２ｂの上は、例えば、シリコン（Ｓｉｌｉｃｏｎ）窒化膜で構成される保護膜１０４で覆われている。保護膜１０４の下において、導体膜１０２ａ及び１０２ｂは破線で示す平面形状である。
　なお、本明細書においては特に断りの無い限り、「上面」とは実装時に実装基板と接合される側の面を意味し、「裏面」とは「上面」に対向する面のことを意味する。また、「側面」とは、「上面」及び「裏面」以外の面のことを意味する。
　保護膜１０４には複数の開口部が設けられ、各開口部から導体膜１０２ａ及び１０２ｂが露出している。導体膜１０２ａ及び導体膜１０２ｂのうち、開口部から露出した箇所はそれぞれ、外部端子として機能する。図１Ａに示す例では、導体膜１０２ａに対して１つの開口部１０６ａが保護膜１０４に形成され、導体膜１０２ｂに対して３つの開口部１０６ｂ、１０６ｃ及び１０６ｄが保護膜１０４に形成されている。半導体装置の側面は、外部端子として機能する導体膜１０２ｃで構成されている。なお、本明細書において、半導体装置の「外部端子」とは、ゲート端子、ソース端子及びドレイン端子等に代表される、実装基板と接続される端子を意味する。
　図１Ｂは、図１Ａの線分Ａ－Ａ´箇所の断面図である。図１Ｂは、半導体装置がＦＥＴである場合の例である。半導体装置は、第１導電型の半導体層１１０と、半導体層１１０の上に配置された第１導電型の半導体層１１２と、半導体層１１２の上面側に形成された第２導電型の半導体部１１４と、半導体部１１４の上面側に形成された第１導電型の半導体部１１６とを備える。半導体層１１２及び半導体部１１４は、例えばＳｉで構成される。半導体部１１４及び半導体部１１６は、例えばイオン注入によって形成される。
　半導体装置には、半導体部１１４及び半導体部１１６を貫通し、半導体層１１２に到達する溝１１８が形成されている。溝１１８内には、例えばＳｉＯ２で構成されるゲート酸化膜１２０を介してゲート電極１２２が配置されている。ゲート電極１２２は例えば、ポリシリコンで構成される。
　半導体装置が備える半導体素子は、いわゆる縦型のＭＯＳＦＥＴを構成する。すなわち、半導体層１１０がドレイン領域を構成し、半導体部１１４がボディ領域を構成し、半導体層１１２がドリフト領域を構成し、半導体部１１６がソース領域を構成している。
　半導体層１１２の上面上の一部には絶縁膜１２４が配置され、絶縁膜１２４の上にはゲート端子として、導体膜１０２ａが配置されている。導体膜１０２ａは、ゲート電極１２２と電気的に接続されている。
　半導体層１１２上の絶縁膜１２４が配置されていない領域には、ソース端子として導体膜１０２ｂが配置されている。導体膜１０２ｂは、ソース領域である半導体部１１６と電気的に接続されている。また、導体膜１０２ｂは、ボディ領域である半導体部１１４と電気的に接続されている。
　半導体層１１０及び半導体層１１２の側面は、ドレイン端子としての導体膜１０２ｃに囲まれ、ドレイン領域である半導体層１１０と電気的に接続されている。導体膜１０２ｃが半導体装置の側面を構成するため、半導体装置が導体膜１０２ｃで保護され、機械的強度が増す。また、半導体素子を設計する上で、半導体層の上面以外に、ドレイン端子を形成することにより、それ以外の半導体素子領域を半導体層内および半導体層の上面に確保できる。そのため、従来技術による同一のサイズの半導体素子と比べ、実質の半導体素子の面積を大きくすることが可能となり、回路使用時の電気抵抗を下げることが容易となる。
　半導体層１１２の上面から導体膜１０２ｃの上面までの高さは、半導体層１１２の上面から導体膜１０２ａ及び導体膜１０２ｂの上面までの高さと同じ、又は、低い。この構造によれば、導体膜１０２ａ及び導体膜１０２ｂにおいて接続不良が起こりにくくなるため、実装基板へのフェースダウン実装が容易となる。
　さらには、導体膜１０２ａの上面、導体膜１０２ｂの上面、及び、導体膜１０２ｃの上面はそれぞれ、同一の平面上に位置することが望ましい。この構造によれば、半導体装置と実装基板とが平行になりやすいため、実装基板へのフェースダウン実装が容易となる。なお、本明細書において「同一」とは、製造上の誤差を含み、「実質的に同一」も含む意味である。
　以下、図１Ｂの半導体装置について、第１導電型をＮ型、第２導電型をＰ型とするＮｃｈ型ＦＥＴとして説明する。
　導体膜１０２ｃ（ドレイン端子）と導体膜１０２ｂ（ソース端子）の間、導体膜１０２ａ（ゲート端子）と導体膜１０２ｂとの間に、電圧を印加する。このとき、導体膜１０２ａ、導体膜１０２ｃが電気的にプラスになり、且つ、半導体部１１４（ボディ領域）にチャネルが形成される。電圧の印加により、導体膜１０２ｃから半導体層１１０（主にドレイン領域）、半導体層１１２、半導体部１１４、半導体部１１６、導体膜１０２ｂの経路を通って回路電流Ｉが流れる。
　なお、回路電流Ｉの経路にあるそれぞれの領域は、発熱の発生を抑制するため電気抵抗ができるだけ低いことが望ましい。例えば、回路電流Ｉが流れる導体膜１０２ｃは、半導体層１１０及び半導体層１１２の側面に垂直な方向の厚みが厚いことが望ましい。具体的には、厚みは約１０－１μｍ以上、且つ、約１０２μｍ以下が望ましい。また、半導体層１１０の厚みは、約５０μｍ以上、且つ、約２００μｍ以下の厚みであることが、電気抵抗低減の観点から望ましい。
　次に、半導体装置を実装基板１３０にフェースダウン実装した構成について説明する。
　図１Ｃは、半導体装置を実装基板１３０に実装したときの、図１Ａにおける線分Ａ－Ａ´箇所の断面図である。図１Ｃに示すように、半導体装置の導体膜１０２ｂ、導体膜１０２ａ及び導体膜１０２ｃはそれぞれ、実装基板１３０上に配置された基板パッド１３４と、接続材料１３６を介して、電気的かつ機械的に接続される。導体膜１０２ａはゲート端子、導体膜１０２ｂはソース端子、導体膜１０２ｃはドレイン端子である。基板パッド１３４は、実装基板１３０上に配置され、基板コート材１３２の開口部から露出している。基板コート材１３２は絶縁体で構成され、基板パッド１３４は、例えば、Ｃｕで構成されている。なお、実装基板１３０がフレキシブル基板の場合、従来の半導体装置に比べ、特に実装後の信頼性が高くなる。
　前述したように、半導体層１１２の上面から導体膜１０２ｃの上面までの高さは、半導体層１１２の上面から導体膜１０２ａ及び導体膜１０２ｂの上面までの高さと同じ、又は、低い。この構造によれば、導体膜１０２ａ及び導体膜１０２ｂと、基板パッド１３４との接触不良が起こりにくくなる。他方、導体膜１０２ｃに対しては、接続材料１３６が導体膜１０２ｃの側面を這い上がるため接続不良は起こらない。結果として、半導体装置の実装基板へのフェースダウン実装が容易となる。また、図示しないが、導体膜１０２ｃには、複数の凹部が互いに間隔を開けて設けられていても良い。この構成によれば、接続材料１３６と導体膜１０２ｃとの接触面積が増えるため、接合強度及び実装強度が上がる。なお、実装に問題が無い範囲であれば、これら複数の凹部の深さや幅に特に限定は無い。
　半導体層１１０及び半導体層１１２の熱膨張係数と、導体膜１０２ｃの熱膨張係数とが異なる場合、剥離が発生する恐れがある。実装工程を含む環境温度の変化に対して、半導体層１１０及び半導体層１１２と、導体膜１０２ｃとの間で半導体装置が応力を受けるためである。この剥離の原因となる応力を分散するため、導体膜１０２ｃを半導体層１１０および１１２の側面に連続して切れ目無く配置するなどの、応力分散処置を考慮することが望ましい。
　各導体膜の材料としては、金属や高不純物濃度のポリシリコンや導電性ペースト等を用いればよい。各導体膜は、合金の単層膜、金属元素や半金属元素の純元素の単層膜、合金の積層膜、金属元素や半金属元素の純元素の積層膜、又は、合金と純元素との積層膜で構成してもよい。金属元素としては、例えば、Ｔｉ、Ｗ、Ａｌ、Ｃｒ、Ｍｏ、Ａｕ、Ｐｔ、Ａｇ、Ｃｕ、Ｎｉ、Ｃｏ、Ｐｄ、Ｓｎ、Ｐｂ、Ｂｉ、Ｖを用いれば良い。半金属元素としては、例えば、Ｓｂ、Ａｓ、Ｂ、Ｓｉ、Ｇｅを用いれば良い。また、添加物としては、例えば、非金属元素であるＰ、Ｃ、Ｎ、Ｈを用いれば良い。特にＡｕ、Ａｇ、Ｐｄ、Ｂｉなどが、一般にはんだなどの接続材料との濡れ性が良いので、各導体膜の表層に配置されることが望ましい。
　接続材料１３６としては、ＰｂＳｎ、ＡｕＳｎ、ＣｕＳｎ、ＡｇＳｎ、ＢｉＳｎ、ＡｕＳｉ、ＡｕＧｅやＡｕＳｂのいずれかを用いたはんだ材であればよい。実装後の機械強度、及び、電気抵抗が要求仕様に耐える材料であれば、はんだ材でなくても構わない。例えば、Ａｇ、Ｃｕ、Ａｕ、ＮｉやＡｌなどの金属と有機材料などを混合した導電性ペーストや導電性樹脂や、ろう材でも構わない。
　図１Ａに示す、保護膜１０４に設けられた開口部１０６ａ～１０６ｄからそれぞれ露出している導体膜１０２ａ及び導体膜１０２ｂの面積（以下、開口面積という）は、同一であることが好ましい。
　例えば、フェ－スダウン実装では、実装基板１３０の基板パッド１３４上に、スクリーンマスクを用いて、接続材料１３６を印刷する。次に、未硬化の接続材料１３６の上に半導体装置をフェ－スダウンで配置し、仮固定する。その後、リフローにて、接続材料１３６を溶融し、実装基板１３０と半導体装置とを接合する。
　このように、各開口部１０６ａ～１０６ｄの面積を同一にすると、リフロー後に各開口部に設けられた接続材料１３６の基板パッド１３４の上面からの高さがほぼ同一になり、傾斜して実装されることがなく、実装不良の発生を低減できる。さらに、導体膜１０２ｃ全体の上面の面積が、各開口面積と同一であっても良い。
　保護膜１０４に設けられた各開口部１０６ａ～１０６ｄの周囲長は同一であることが好ましい。接続材料１３６の溶融時には表面張力が発生するため、開口部の縁側の接続材料１３６に傾斜が形成される。そして、各開口部の周囲長によってその表面張力の大きさが異なるため、傾斜の角度も変わる。従って、各開口部の周囲長が同一であれば、該傾斜の角度をより均一にすることができるため、実装不良を抑制することができる。
　各開口部において、開口面積が同一、且つ、周囲長が同一であれば、実装時の接続材料１３６の基板パッド１３４の上面からの高さをより高い精度で同一とすることが可能となり、実装不良を低減できる。
　（変形例１）
　以下、第１の実施形態の変形例１に係る半導体装置について、図１Ｄを参照しながら説明する。
　変形例１は、図１Ａ、図１Ｂに示す半導体装置と、導体膜１０２ｃの構成において異なる。導体膜１０２ｃは半導体装置の側面を部分的に構成している。具体的には、導体膜１０２ｃが、少なくとも下層の半導体層の側面Ａ上、及び対向する側面Ｂ上に形成されている。導体膜１０２ｃは、側面Ａ及び側面Ｂと交差する他の２つの側面上の一部に亘って形成されていても良い。言い換えると、半導体装置は、導体膜１０２ｃで構成された一対の面と、導体膜１０２ｃを配置しない部分を含む一対の面とを備えてもよい。リフロー時に溶融した接続材料１３６には表面張力が働き、濡れ性の良い導体膜１０２ｃを引き寄せる力がある。この接続材料１３６の表面張力を利用して、導体膜１０２ｃを対向する位置にのみ配置することにより、該半導体装置を実装基板１３０に仮固定した際のずれを消滅させることが可能となり、実装不良を抑制できる。
　また、導体膜１０２ｃは、側面上に部分的に形成されており、該側面上において導体膜１０２ｃが形成されていない領域があっても良い。導体膜１０２ｃが形成されていない領域を通して、導体膜１０２ａや導体膜１０２ｂと接続される実装基板の配線を引き出すことができるため、この構成は、特に実装基板が単層配線の場合に有用である。さらに、導体膜１０２ｃの配置を工夫することで、実装基板から引き出す配線を太くすることができるため、オン抵抗を容易に低減することができる。
　（変形例２）
　以下、第１の実施形態の変形例２に係る半導体装置について、図１Ｅを参照しながら説明する。
　変形例２は、図１Ａ、図Ｂに示す半導体装置と、半導体層１１０と導体膜１０２ｃとの間に、半導体層１１０よりも抵抗が低いコンタクト領域１２６が形成されている点において異なる。
　本変形例において、半導体層１１０の導電型がＮ型であれば、コンタクト領域１２６の不純物濃度は１×１０２０［／ｃｍ３］以上が望ましい。半導体層１１０の導電型がＰ型であれば、１×１０１９［／ｃｍ３］以上が望ましい。
　ＰＶＤ（Ｐｈｙｓｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法のひとつであるＥＢ（Ｅｌｅｃｔｒｏｎ　Ｂｅａｍ）蒸着法を用いて、Ｍｏ、Ｃｒ、Ｔｉ、Ｗ、Ｎｉ、Ａｕ、Ｐｔ、Ａｌ、Ｃｏ等によって導体膜１０２ｃを形成する場合は、半導体層１１０にコンタクト領域１２６が自然に形成される。ＥＢ蒸着法では、材料を蒸発させて飛散させるため、材料が熱エネルギを保持したまま、半導体層１１０に到達する。そのため、半導体材料と導体膜１０２ｃの材料とが反応することで、コンタクト領域１２６が形成される。
　また、ＰＶＤ法の他の方式の一つであるスパッタ法やＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を用いて形成し、熱処理を加えてシリサイド層を形成する方法や、シリサイド層をスパッタ法で形成するなどの方法でもコンタクト領域１２６を形成することができる。半導体層１１０に不純物を追加で注入することにより、又は、不純物を拡散することによって、コンタクト領域１２６を形成できる。また、不純物の注入後に熱処理を加え、不純物の活性化を行うことで、コンタクト領域１２６はより低抵抗となる。
　なお、コンタクト領域１２６を設けず、半導体層１１０における導体膜１０２ｃとの接触面を粗面化することで代替してもよい。すなわち、接触面の面積が増えるため、その分コンタクト抵抗を下げられる。
　この構成により、半導体層１１０と導体膜１０２ｃとの間の電気抵抗を低減できるため、半導体装置の小型化が可能となる。
　（他の変形例）
　第１の実施形態および変形例１、２では、半導体素子としてＮｃｈ型ＦＥＴを用いて説明を行ったが、Ｐｃｈ型ＦＥＴであっても同様の効果を得られる。また、ＦＥＴに限らず、図２Ａに示すダイオード、図２Ｃに示すバイポーラトランジスタ、図２Ｄに示すサイリスタ、並びに、図２Ｅに示すＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）によって実現してもよい。
　図２Ａに示すダイオードは、Ｎ型の半導体層２００と、半導体層２００の上に配置されたＮ型の半導体層２０２と、半導体層２０２に形成されたＰ型の半導体部２０４と、半導体部２０４の上に配置された導体膜２０６とを備える。半導体層２０２の上には、絶縁膜２１０が形成され、各導電膜間を絶縁分離している。保護膜２１２の開口部からは導体膜２０６が露出している。
　導体膜２０６はアノード領域を構成し、導体膜２０８はカソード領域を構成する。半導体層２００の不純物濃度は半導体層２０２の不純物濃度よりも高い。図２Ｂは図２Ａに示すダイオードの平面図であり、導体膜２０６に対して、４つの開口部が形成された構造を示す。
　導体膜２０８は、半導体装置の側面を構成し、半導体層２００及び半導体層２０２と電気的に接続されている。なお、半導体層２００及び半導体層２０２がＰ型であり、半導体部２０４がＮ型である場合は、アノード領域とカソード領域とが入れ替わる。
　導体膜２０８は、絶縁膜２１０の上を覆っていてもよい。つまり、導体膜２０８が半導体層の上面と側面とが交わる部分を覆っていてもよい。この場合、導体膜２０８の、絶縁膜２１０の上における端部２１４が保護膜２１２で覆われていることが望ましい。
　この構造によれば、応力が集中しやすい端部２１４が保護膜２１２で覆われているため、導体膜２０８と絶縁膜２１０、半導体層２０２、及び半導体層２００との剥離を防ぐことができる。この構造は、図１Ｂに示す半導体装置においても適用可能である。
　図２Ｃに示すバイポーラトランジスタは、Ｎ型の半導体層２２０と、半導体層２２０の上に配置されたＮ型の半導体層２２２と、半導体層２２２の上に形成されたＰ型の半導体部２２４と、半導体部２２４の上に配置されたＮ型の半導体部２２６とを備える。
　半導体部２２４と電気的に接続された導体膜２２８はベース領域を構成し、半導体部２２６と電気的に接続された導体膜２３０はエミッタ領域を構成する。導体膜２３２はコレクタ領域を構成する。各導体膜の間は、絶縁膜２３４によって絶縁分離されている。保護膜２３６に設けられた開口部において、導体膜２２８及び導体膜２３０が露出して外部端子を構成している。なお、図２Ｃに示すバイポーラトランジスタの導体膜及び保護膜に関する平面図は、図１Ａに示す構造と実質的に同じである。
　図２Ｄに示すサイリスタは、Ｐ型の半導体層２４０と、半導体層２４０の上に配置されたＮ型の半導体層２４２と、半導体層２４２の上に配置されたＰ型の半導体部２４４と、半導体部２４４に形成されたＮ型の半導体部２４６とを備える。各導体膜の間は絶縁膜２５４によって絶縁分離されている。保護膜２５６に設けられた開口部において、導体膜２４８及び導体膜２５０が露出して外部端子を構成している。
　導体膜２５２は、半導体層２４０と電気的に接続され、外部端子であるアノード領域を構成している。半導体部２４４と電気的に接続されている導体膜２４８はゲート端子を構成する。半導体部２４６と電気的に接続されている導体膜２５０はカソード領域を構成している。なお、半導体層２４０及び半導体部２４４がＮ型であり、半導体層２４２及び半導体部２４６がＰ型である場合は、アノード領域とカソード領域とが入れ替わる。なお、図２Ｄに示すサイリスタの導体膜及び保護膜に関する平面形状は図１Ａに示す構造と実質的に同じである。
　図２Ｅに示すＩＧＢＴは、Ｐ型の半導体層２６０と、半導体層２６０の上に配置されたＮ型の半導体層２６２と、半導体層２６２の上に配置されたＮ型の半導体層２６４と、半導体層２６４に形成されたＰ型の半導体部２６６と、半導体部２６６に形成されたＮ型の半導体部２６８とを備える。半導体部２６８、半導体部２６６を貫通し、半導体層２６４に到達するように形成された溝２７０の内部に配置されたゲート酸化膜２７２が配置されている。ゲート酸化膜２７２の内部にゲート電極２７４が配置されている。保護膜２８４に設けられた開口部において、導体膜２８０及び導体膜２８２が露出して外部端子を構成している。
　導体膜２７６は、半導体層２６０と電気的に接続され、コレクタを構成する一方、半導体層２６２及び半導体層２６４とは絶縁膜２７８によって絶縁されている。絶縁膜２７８によって半導体層２６４と絶縁された導体膜２８０は、ゲート電極２７４と電気的に接続され、ゲート端子を構成する。半導体部２６８と電気的に接続する導体膜２８２はエミッタを構成する。導体膜２８０と導体膜２７６との間、及び、導体膜２８２と導体膜２７６との間は絶縁膜２７８によって絶縁されている。なお、図２Ｅに示すＩＧＢＴの導体膜及び保護膜に関する平面図は図１Ａに示す構造と実質的に同じである。
　（製造方法）
　次に、本開示の第１の実施形態に係る半導体装置の製造方法について、図３Ａ～図３Ｆの工程断面図を参照しながら説明する。
　図３Ａに示すように、まず、ＦＥＴ等の半導体素子をウェハ状半導体基板３００に形成する。ウェハ状半導体基板３００は上面３０２と、上面３０２と対向する裏面３０４とを有する。
　次に、図３Ｂに示すように、ＦＥＴの外形に沿って、上面３０２側から半導体層１１０に到達する溝３０６を形成する。溝３０６の形成には、ブレードダイシングやレーザダイシングを用いることが可能である。
　溝３０６の形成には、フォトレジストやハードマスクを用いて、ドライエッチングで処理することも可能である。この場合、半導体装置に対するダイシングによるダメージを低減できる。さらに、ウェハ状半導体基板３００の上面３０２の全面において一括処理できるため、短時間で溝３０６を形成できる。また、フォトレジストやシリコン酸化膜マスクやメタルマスクなどのマスクを用いて、ウェットエッチングで処理することも可能である。
　次に、図３Ｃに示すように、上面３０２に導体膜１０２ｂを形成するための開口部を形成する。開口部は、フォトレジストなどのマスクを用いて、絶縁膜１２４の一部をエッチングして形成できる。
　次に、図３Ｄに示すように、絶縁膜１２４上に導体膜１０２ａ、及び、開口部に導体膜１０２ｂを形成し、溝３０６に、導体膜１０２ｃを形成する。導体膜の形成には、ＣＶＤ法を使うのが望ましい。例えば、ＴｉやＷのＣＶＤ膜を使用することにより、導体膜１０２ｃは容易に厚膜化できるため、導体膜１０２ｃの電気抵抗を低減できる。導体膜１０２ｃの形成においては、めっき法を用いても良い。
　次に、図３Ｅに示すように、上面３０２に保護膜１０４を形成する。
　最後に、図３Ｆに示すように、ウェハ状半導体基板３００の裏面３０４から溝３０６に達する位置まで研削することにより、半導体装置が完成する。研削工程においては、例えば、バックグラインド、ポリッシュ、ウェットエッチング、ドライエッチングやＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）を用いることが可能である。これらの方法を組み合わせて使っても良い。
　（第２の実施形態）
　以下、本開示の第２の実施形態に係る半導体装置について、図４Ａ～図４Ｄを参照しながら説明する。
　図４Ａは、半導体装置の平面図である。導体膜４０２ａ及び４０２ｂの上に配置された保護膜４０４により覆われている領域は、破線で示している。
　図４Ａに示すように、半導体装置は、導体膜４０２ａと、導体膜４０２ａに囲まれるように形成された導体膜４０２ｂと、各導体膜の上に形成された保護膜４０４とを備える。導体膜４０２ａに対して保護膜４０４には２つの開口部４０６ａ及び４０６ｂが設けられ、導体膜４０２ｂに対して保護膜４０４には１つの開口部４０６ｃが設けられている。導体膜４０２ａ、４０２ｂ、及び、半導体装置の互いに対向する側面上に設けられた導体膜４０２ｃがそれぞれ、外部端子を構成する。
　図４Ｂは、半導体装置を実装基板１３０に実装した際の平面図である。保護膜４０４に設けられた開口部における導体膜以外の部分、及び、後述する基板コート材１３２が透視された図である。図４Ｃは、図４ＢのＡ－Ａ´線における断面図である。
　図４Ｂ及び図４Ｃに示すように、各導体膜はそれぞれ、実装基板１３０の上に設けられた基板パッド１３４と接続材料１３６によって接続されている。導体膜４０２ｃが形成されていない領域を通して、導体膜４０２ａおよび導体膜４０２ｂと接続される基板パッド１３４を引き出すことができる。基板パッド１３４は、実装基板１３０の配線として働く。
　例えば、半導体装置に設けられた半導体素子が電界効果型トランジスタ（ＦＥＴ）である場合、導体膜４０２ａがソース電極として働き、導体膜４０２ｂがゲート電極として働き、導体膜４０２ｃがドレイン電極として働く。ゲート・ドレイン間の容量が大きくなると、高周波のスイッチング動作でＦＥＴの入力のオン・オフを繰り返しても、出力のオン・オフへの追随性が悪くなる。
　しかし、本実施形態のように、ゲート電極として働く導体膜４０２ｂとドレイン電極として働く導体膜４０２ｃとの間に、ソース電極として働く導体膜４０２ａを配置することにより、ゲート・ドレイン間容量を小さくすることが出来る。これは、ゲート・ソース間容量及びソース・ドレイン間容量の直列接続になるため、等価回路としてみた場合、ゲート・ドレイン間容量は小さくなるためである。これにより高周波駆動に優れる半導体装置の提供が可能となる。
　図４Ｄは、本実施形態の変形例に係る半導体装置の平面図である。
　図４Ｄのように、平面視においてゲート端子である導体膜４０２ｂが円状であり、ソース端子である導体膜４０２ａが導体膜４０２ｂを囲うドーナツ状に形成されていても良い。この場合、導体膜４０２ａ及び導体膜４０２ｂが円状であるため、フェースダウン実装時に半導体装置が回転する可能性がある。そこで、半導体装置が回転することを防ぐため、導体膜４０２ｃが半導体装置の四隅のみを構成するように形成している。
　なお、半導体素子はバイポーラトランジスタやＩＧＢＴなどの他の高速駆動半導体素子であっても良い。なお、ソース端子はグランド電位に接続された場合に限らず、半導体素子の端子中、外部回路から最も低い電位が供給される端子であればよい。
　（第３の実施形態）
　以下、本開示の第３の実施形態に係る半導体装置について、図５Ａ及び図５Ｂを参照しながら説明する。図５Ａは、半導体装置の平面図である。図５Ｂは、図５Ａの線分Ａ－Ａ´における半導体装置の断面図である。
　半導体装置の側面、すなわち導体膜１０２ｃ上に保護膜５００が形成された構成である。保護膜５００は絶縁性を有していることが望ましい。保護膜５００の材料は、例えば、シリコン酸化膜、シリコン窒化膜、有機材料、樹脂、シリコーン（Ｓｉｌｉｃｏｎｅ）、金属酸化材料、又は、前記材料の複合材料であっても良いし、前記材料を積層して形成しても良い。保護膜５００は、ＣＶＤ法などにより形成すれば良い。
　半導体装置の実装を含む製造工程では、１個当たりの製造時間を短縮することにより製造コストを削減するため、半導体装置の機械強度に適合する範囲内で製造スピードを最大化している。しかしながら、半導体装置の機械強度の観点から、製造スピードを抑制せざるを得ないことがある。
　この構成によれば、導体膜１０２ｃが保護膜５００で覆われているため、半導体装置の機械強度が増している。その結果、製造スピードを抑制しなくても済むため、量産性が向上し、低コスト化が可能となる。
　（第４の実施形態）
　以下、本開示の第４の実施形態に係る半導体装置について、図６Ａ及び図６Ｂを参照しながら説明する。図６Ａは、半導体装置の平面図である。図６Ｂは、図６Ａの線分Ａ－Ａ´における半導体装置の断面構造図である。図６Ｃは、半導体装置を実装基板に実装した際の、図６Ａにおける線分Ａ－Ａ´箇所の断面図である。
　図６Ａ及び図６Ｂのように、保護膜１０４に設けられた開口部１０６ａ、１０６ｂ、１０６ｃ及び１０６ｄから露出する導体膜１０２ａ及び１０２ｂ、並びに、導体膜１０２ｃの上面及び側面の一部は導体膜６００で覆われている。導体膜１０２ｃは、側面の全体が導体膜６００により覆われていても良い。
　本実施形態に係る半導体装置の製造方法としては、例えば、図３Ｃに示す溝３０６に、導体膜１０２ｃを形成した後、ウェハ状半導体基板３００の上面３０２側の全面に無電解めっきを実施すれば良い。無電解めっきによって、導体膜１０２ｃよりも接続材料１３６に対する濡れ性が良い導体膜６００が形成される。
　この構成によれば、接続材料１３６が、導体膜１０２ｃに這い上がりやすくなるため、接合面積が増え、接合強度が上がる。
　なお、導体膜６００の厚さは、無電解めっき液の濃度や、めっき中のめっき液の攪拌スピードを調整することで適宜変更できる。導体膜１０２ｃと導体膜６００とは異なる材料で形成されていても良い。なお、導体膜１０２ｃがＡｌである場合、Ｓｎ含有の接続材料の１種であるＳｎＡｇはんだとの濡れ性が悪い。この場合、ＳｎＡｇはんだの濡れ性が良いＮｉやＡｕの無電解めっきを行うことが出来る。導体膜６００の材料はＮｉやＡｕに限らない。
　（第５の実施形態）
　以下、本開示の第５の実施形態に係る半導体装置について、図７Ａ及び図７Ｂを参照しながら説明する。
　図７Ａは、半導体装置の平面図である。図７Ａに示すように、半導体装置の上面の外周に、複数の溝７００が互いに間隔を置いて形成されている。そして、溝７００には導体膜７０２が形成されている。
　図７Ｂは、図７Ａの線分Ａ－Ａ´箇所の半導体装置の断面図である。図７Ｂに示すように、導体膜７０２の上面は導体膜１０２ａ及び１０２ｂと同一平面上にある。さらに、半導体装置の裏面を基準としたとき、導体膜１０２ｃの上面の高さは、導体膜７０２の上面の高さよりも低いため、導体膜１０２ｃと導体膜７０２とは段差７０４を形成する。
　この構造によれば、半導体装置の側面において導体膜１０２ｃのみと接合材料が接触する第１の実施形態に係る半導体装置と比較して、導体膜１０２ｃ及び導体膜７０２と接合材料とが接触する面積が大きいため、実装基板との接合強度がさらに増す。
　本実施形態に係る半導体装置の製造方法は、第１の実施形態の製造方法に以下の工程を追加すれば良い。例えば、半導体素子の形成過程において、半導体層１１２に複数の溝７００を互いに間隔を空けて形成する。溝７００に、導体膜１０２ａ及び１０２ｂの形成と同時に、導体膜７０２を形成する。その後は、第１の実施形態に係る製造方法とほぼ同じ工程を行うことで、半導体装置が実現できる。
　なお、溝７００の半導体層１１２の上面からの深さや、側面方向の幅や、溝７００の数は、半導体素子の動作に悪影響がない範囲において任意である。なお、溝７００は半導体層１１０に至るように形成されていても構わない。
　（第６の実施形態）
　以下、本開示の第６の実施形態に係る半導体装置について、図８Ａ及び図８Ｂを参照しながら説明する。図８Ａは、半導体装置の平面図である。また、図８Ｂは、図８Ａの線分Ａ－Ａ´箇所における半導体装置の断面図である。
　図８Ａに示すように、半導体装置の側面は導体膜８００により構成されている。図８Ｂに示すように、半導体装置の裏面を基準としたとき、導体膜８００の上面の高さは、導体膜１０２ｃの上面の高さよりも低いため、導体膜１０２ｃと導体膜８００とは段差８０２を形成する。
　この構造によれば、半導体装置の側面において導体膜１０２ｃのみと接合材料が接触する第１の実施形態に係る半導体装置と比較して、導体膜１０２ｃ及び導体膜８００と接合材料とが接触する面積が大きいため、実装基板との接合強度がさらに増す。
　本実施形態に係る半導体装置の製造方法は第１の実施形態の製造方法に以下の工程を追加すれば良い。例えば、個片化された半導体装置の上面３０２側を保持した状態で、裏面３０４側のみを無電解めっき槽にめっき浴し、めっき膜を研削することで半導体装置が得られる。
　（第７の実施形態）
　以下、本開示の第７の実施形態に係る半導体装置について、図９Ａ～図９Ｃを参照しながら説明する。図９Ａは、半導体装置の平面図である。図９Ｂは、図９Ａの線分Ａ－Ａ´箇所における半導体装置の断面図である。図９Ａに示すように、溝９００が保護膜１０４の上面に形成されている。溝９００は各導体膜の間に形成されている。図９Ｂに示すように、溝９００は保護膜１０４を貫通しないように形成されている。なお、溝９００は保護膜１０４を貫通し、導体膜１０２ｂ及び絶縁膜１２４が露出するように形成されていても良い。
　図９Ｃは、半導体装置を実装基板に実装した時の、図９Ａの線分Ａ－Ａ´箇所における断面図である。半導体装置を実装基板に実装するリフロー時には、半導体装置と実装基板との間の隙間に対して毛細管現象が起こる。そして半導体装置の小型化に伴い、各導体膜間の間隔が狭くなると、毛細管現象により溶融した接続材料１３６同士が繋がってしまうことがある。
　しかし、本実施の形態では、保護膜１０４が溝９００を有している。この構造によれば、図９Ｃに示すように、溝９００によって、毛細管現象により接続材料１３６同士が繋がることを防止できる。
　その結果、各導体膜間の間隔を狭くすることが可能となるため、半導体装置を小型にできる。
　本実施形態に係る半導体装置の製造方法は第１の実施形態の製造方法に以下の工程を追加すれば良い。例えば、保護膜１０４を形成後に、エッチングにより保護膜１０４の上面において各導体膜の間に溝９００を形成すれば良い。
　なお、保護膜１０４に溝９００を形成するのではなく、基板コート材１３２に溝を形成しても良いし、保護膜１０４及び基板コート材１３２のどちらにも溝を形成しても良い。
　（第８の実施形態）
　以下、本開示の第８の実施形態に係る半導体装置について、図１０Ａ～図１０Ｃを参照しながら説明する。図１０Ａは、第８の実施形態に係る半導体装置の平面図である。図１０Ｂは、図１０Ａの線分Ａ－Ａ´箇所における半導体装置の断面図である。図１０Ｃは、半導体装置を実装基板に実装した時の、図１０Ａの線分Ａ－Ａ´箇所における断面図である。
　図１０Ａに示すように、半導体装置の側面は保護膜１０００で覆われている。図１０Ｂに示すように、半導体装置は、半導体層１１０の裏面上に形成され、導体膜１０２ｃと電気的に接続された導体膜１００２をさらに備えている。導体膜１０２ｃの側面及び導体膜１００２の側面及び裏面は保護膜１０００によって覆われている。
　半導体装置全体の抵抗成分に対して、半導体層１１０のシート抵抗による抵抗成分が占める割合が高くなる場合がある。しかし、上記構造によれば導体膜１００２を有することにより、抵抗成分を低下させることができる。また、導体膜１００２の厚みが厚い程、電気抵抗は低減できる。例えば、導体膜１００２の厚みは約３μｍ以上が望ましく、実装等に影響がない限り上限値は特にない。また、この構造によれば、電気抵抗の低減のみならず、半導体装置の機械強度が増すため、半導体装置の実装を含む製造工程上の扱いが容易になる。
　保護膜１０００によって導体膜１０２ｃ及び導体膜１００２が覆われているため、半導体装置の機械強度が増す。なお、保護膜１０００は絶縁性を有していることが望ましい。例えば、シリコン酸化膜、シリコン窒化膜、有機材料、樹脂、シリコーン、金属酸化材料などの材料、および、それらの複合材料やそれらの積層構造などで形成されていることが望ましい。また、導体膜１０２ｂの厚みと導体膜１００２の厚みとが同一であり、且つ、保護膜１０４の厚みと、導体膜１００２の裏面上に配置された保護膜１０００の厚みとが同一である場合、半導体装置の内部応力が緩和されるため、半導体層の厚みが薄くなっても、半導体装置が反りにくく、取扱いが容易となる。
　本実施形態に係る半導体装置の製造方法は、第１の実施形態の製造方法に以下の工程を追加すれば良い。例えば、半導体層１１０の裏面を研削した後、導体膜１００２をスパッタや蒸着等で形成する。その後、導体膜１０２ｃの側面及び導体膜１００２の側面及び裏面に保護膜１０００を形成すれば、半導体装置が得られる。
　（第９の実施形態）
　以下、本開示の第９の実施形態に係る半導体装置について、図１１Ａ及び図１１Ｂを参照しながら説明する。図１１Ａは、半導体装置の平面図である。図１１Ｂは、図１１Ａの線分Ａ－Ａ´箇所における半導体装置の断面図である。図１１Ｃは、図１１Ａの線分Ｂ－Ｂ´箇所における半導体装置の断面図である。
　図１１Ａに示されるように、半導体装置は、半導体装置の上面及び側面を構成する導体膜１１００及び１１０２と、半導体装置の側面を構成する導体膜１１０４と、導体膜１１００及び１１０２を覆う保護膜１１０６とを備える。導体膜１１００及び１１０２は、絶縁膜１１０８上に配置される。導体膜１１００はゲート電極として働き、導体膜１１０２はソース電極として働き、導体膜１１０４はドレイン電極として働く。図１１Ｂに示されるように、導体膜１１００及び導体膜１１０２はそれぞれ、半導体装置の上面及び側面を覆い、一体的に形成されている。
　第１～第８の実施形態に係る半導体装置を小型化する場合、装置表面において、ソース電極として働く導体膜１０２ｂが占める面積が小さくなれば、その分、オン抵抗が増大してしまう。
　しかし、本実施形態によれば、ソース電極として働く導体膜１１０２を半導体層の側面上にも配置することによって、面積を確保することができるため、オン抵抗の増大を抑制しつつ、半導体装置の小型化が可能となる。
　以上のように、本出願において開示する技術の例示として、第１～第９の実施形態とそれらの変形例を説明した。しかしながら、本開示における技術は、これに限定されず、変更、置き換え、付加、省略などを行った実施形態にも適用可能である。また、上記第１～第９の実施形態と変形例で説明した各構成要素を組み合わせて、新たな実施形態とすることも可能である。
　本明細書で開示された実施形態において、半導体層はＳｉ、ＳｉＣ、ＧａＡｓ、ＧａＮなど半導体の性質を持つ材料であれば良い。
　なお、半導体素子の極性に関係なく、本構成において、本開示の効果を得ることができる。なお、以下の例では半導体装置の形状において立方体を例として提示しているが、円筒形状や、三角柱や六角柱などの多角柱形状や、三角錐や六角錐などの多角錐形状でも本開示の効果を得ることができる。
　また、上述の実施形態は、本開示における技術を例示するためのものであるから、特許請求の範囲またはその均等の範囲において種々の変更、置き換え、付加、省略などを行うことができる。
１０２ａ，１０２ｂ，１０２ｃ，２０６，２０８，２２８，２３０，２３２，２４８，２５０，２５２，２７６，２８０，２８２，４０２ａ，４０２ｂ，４０２ｃ，６００，７０２，８００，１００２，１１００，１１０２，１１０４　　導体膜
１０４，２１２，２３６，２５６，２８４，４０４，５００，１０００，１１０６　　保護膜
１０６ａ，１０６ｂ，１０６ｃ，１０６ｄ，４０６ａ，４０６ｂ，４０６ｃ　　開口部
１１０，１１２，２００，２０２，２２０，２２２，２４０，２４２，２６０，２６２，２６４　　半導体層
１１４，１１６，２０４，２２４，２２６，２４４，２４６，２６６，２６８　　半導体部
１１８，２７０，３０６，７００，９００　　溝
１２０，２７２　　ゲート酸化膜
１２２，２７４　　ゲート電極
１２４，２１０，２３４，２５４，２７８，１１０８　　絶縁膜
１２６　　コンタクト領域
１３０　　実装基板
１３２　　基板コート材
１３４　　基板パッド
１３６　　接続材料
３００　　ウェハ状半導体基板
３０２　　上面
３０４　　裏面
５００　　保護膜
７０４，８０２　　段差

Claims (20)

  1. 　半導体素子が形成された半導体層と、
    　前記半導体層の上面上に形成され、前記半導体素子と電気的に接続された第１の導体膜と、
    　前記半導体層の側面上に形成され、前記半導体素子と電気的に接続された第２の導体膜と、
    　前記第１の導体膜上に形成され、前記第１の導体膜を露出する開口部を有する第１の保護膜とを備え、
    　前記半導体層の前記上面から前記第２の導体膜の上面までの高さは、前記半導体層の前記上面から前記第１の導体膜の上面までの高さと同じ、又は、低い
    　半導体装置。
  2. 　前記開口部は、第１の開口部及び第２の開口部を含み、
    　前記第１の開口部の面積と前記第２の開口部の面積とが同一である
    　請求項１に記載の半導体装置。
  3. 　前記第１の開口部の周囲長と前記第２の開口部の周囲長とが同一である
    　請求項２に記載の半導体装置。
  4. 　前記開口部は、第１の開口部及び第２の開口部を含み、
    　前記第１の開口部の周囲長と前記第２の開口部の周囲長とが同一である
    　請求項１に記載の半導体装置。
  5. 前記第２の導体膜には、複数の凹部が、互いに間隔を開けて設けられている
    請求項１から４のいずれかに記載の半導体装置。
  6. 　前記第２の導体膜上に形成された第３の導体膜を備え、
    　前記第２の導体膜と前記第３の導体膜とは段差を形成している
    　請求項１から５のいずれかに記載の半導体装置。
  7. 　前記第３の導体膜は、前記第１の導体膜及び前記第２の導体膜よりも、実装基板と前記半導体装置とを接続する接続材料に対する濡れ性が良い
    　請求項６に記載の半導体装置。
  8. 　前記半導体層の前記側面は、第１の側面及び前記第１の側面と対向する第２の側面を有し、
    　前記第２の導体膜は、少なくとも前記第１の側面上及び前記第２の側面上に形成されている
    　請求項１から７のいずれかに記載の半導体装置。
  9. 　前記第２の導体膜は、前記側面上に部分的に形成されており、
    　前記半導体層の前記側面において、前記第２の導体膜が配置されていない領域がある
    　請求項１から８のいずれかに記載の半導体装置。
  10. 前記半導体素子は、電界効果型トランジスタであり、
    前記半導体層の前記上面上に形成され、前記半導体素子と電気的に接続された第４の導体膜をさらに備え、
    　前記第１の導体膜は、ソース電極として働き、前記第２の導体膜は、ドレイン電極として働き、前記第４の導体膜は、ゲート電極として働き、
    前記第１の導体膜は、前記第２の導体膜と前記第４の導体膜との間に配置されている
    　請求項１から９のいずれかに記載の半導体装置。
  11. 前記第１の導体膜は、前記第４の導体膜を囲っている
    　請求項１０に記載の半導体装置。
  12. 　前記半導体層と前記第２の導体膜との間に形成され、且つ、前記半導体層よりも抵抗が低いコンタクト領域をさらに備える
    　請求項１から１１のいずれかに記載の半導体装置。
  13. 　前記第１の保護膜には溝が形成されている
    　請求項１から１２のいずれかに記載の半導体装置。
  14. 　前記第１の導体膜は、前記半導体層の前記側面上にも配置されている
    請求項１から１３のいずれかに記載の半導体装置。
  15. 　前記第１の導体膜の上面及び前記第２の導体膜の上面は同一の平面状に位置する
    　請求項１から１４のいずれかに記載の半導体装置。
  16. 　前記半導体層の裏面上に形成され、前記第２の導体膜と電気的に接続された第５の導体膜をさらに備える
    　請求項１から１５のいずれかに記載の半導体装置。
  17. 　前記第５の導体膜の裏面を覆う第３の保護膜をさらに備える
    　請求項１６に記載の半導体装置。
  18. 　前記第１の導体膜の厚みと、前記第５の導体膜の厚みとは同一であり、
    前記第１の保護膜の厚みと、前記第３の保護膜の厚みとは同一である
    　請求項１７に記載の半導体装置。
  19. 　前記半導体装置は、さらに、前記第２の導体膜を覆う第２の保護膜を備える
    　請求項１から１８のいずれかに記載の半導体装置。
  20. 前記第２の導体膜は、前記半導体層の前記上面と前記側面とが交わる部分を覆い、
    　前記上面上における前記第２の導体膜の端部は、前記第１の保護膜で覆われている
    　請求項１から１９のいずれかに記載の半導体装置。
PCT/JP2014/004927 2013-10-01 2014-09-26 半導体装置 WO2015049852A1 (ja)

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