WO2015033476A1 - スイッチング素子、半導体装置、半導体装置の製造方法 - Google Patents
スイッチング素子、半導体装置、半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2015033476A1 WO2015033476A1 PCT/JP2013/074284 JP2013074284W WO2015033476A1 WO 2015033476 A1 WO2015033476 A1 WO 2015033476A1 JP 2013074284 W JP2013074284 W JP 2013074284W WO 2015033476 A1 WO2015033476 A1 WO 2015033476A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gate pad
- switching element
- substrate
- gate
- resistance
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000000523 sample Substances 0.000 claims description 12
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 description 34
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 34
- 238000000034 method Methods 0.000 description 20
- 238000005259 measurement Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1602—Diamond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a switching element that switches between conduction and interruption of a current by a control signal from the outside, a semiconductor device provided with the switching element, and a method for manufacturing the semiconductor device.
- Patent Document 1 discloses a switching element having a built-in gate resistor. This switching element has a plurality of resistance regions under the gate pad portion. Then, in the final step of the wafer process, a plurality of resistance regions and gates are appropriately connected to obtain a desired gate resistance.
- a semiconductor device with a rated current of several tens to several thousand amperes may be manufactured by connecting a plurality of switching elements in parallel.
- the switching speed and the conduction current value also vary. This causes oscillation or deterioration of the switching element. Therefore, it is desirable to configure a switching element with a built-in gate resistance so that it can be confirmed that the gate resistance value conforms to the standard.
- the number of parallel mounting of switching elements increases when the rated current is large, and the number of parallel mounting switching elements decreases when the rated current is small. If the number of switching elements mounted in parallel changes, the optimum value of the gate resistance value for suppressing gate oscillation or reducing the unbalance of the control signal changes. Therefore, it is desirable that the gate resistance can be selected after completion of the built-in gate resistance type switching element so that the switching element can be used for a plurality of types.
- the present invention has been made in order to solve the above-described problem.
- a switching element capable of measuring a gate resistance value and selecting a gate resistance after completion of a switching element with a built-in gate resistance, and a semiconductor device having the switching element And a method of manufacturing a semiconductor device having the switching element.
- the switching element according to the present invention includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, the first gate pad formed on the substrate, and the A first resistance portion for connecting the second gate pad and a cell region formed on the substrate and connected to the first gate pad are provided.
- a semiconductor device includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, the first gate pad formed on the substrate, and the A first switching element comprising: a first resistor for connecting a second gate pad; and a cell region formed on the substrate and connected to the first gate pad; and the same structure as the first switching element A second switching element connected in parallel with the first switching element, the first gate pad of the first switching element and the first gate pad of the second switching element, or of the first switching element And a wire for supplying a control signal connected to the second gate pad and the second gate pad of the second switching element.
- a method of manufacturing a semiconductor device includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, and the first gate formed on the substrate.
- a step of manufacturing a switching element comprising: a first resistance portion connecting the pad and the second gate pad; and a cell region formed on the substrate and connected to the first gate pad;
- the gate resistance value can be measured and the gate resistance can be selected after the gate resistance built-in type switching element is completed.
- a switching element, a semiconductor device, and a method for manufacturing the semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
- the same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.
- FIG. 1 is a plan view schematically showing a switching element 10 according to Embodiment 1 of the present invention.
- the switching element 10 is an IGBT.
- the switching element 10 includes a substrate 11.
- a first gate pad 12 and a second gate pad 14 are formed on the substrate 11.
- the substrate 11 is formed with a first resistance portion 16 that connects the first gate pad 12 and the second gate pad 14.
- the first resistance unit 16 is a gate resistor built in the switching element 10.
- the first resistance unit 16 includes a high resistance layer formed by a wafer process.
- the gate resistance built in the switching element is sometimes called an on-chip resistance. In the drawing, the first resistance portion 16 is indicated by a circuit symbol.
- a cell region 18 is formed on the substrate 11.
- the cell region 18 has a gate wiring portion that receives a control signal.
- the gate wiring portion of the cell region 18 is connected to the first gate pad 12 by the wiring 20.
- the switching element 10 is manufactured by a wafer process.
- a probe (measurement terminal) is applied to the first gate pad 12 and the second gate pad 14, and the resistance value of the first resistance unit 16 is measured.
- the switching element 10 is mounted on the module.
- an aluminum wire that is used for the gate wiring and transmits a control signal from the outside is fixed to the first gate pad 12 or the second gate pad 14.
- the switching element 10 is discarded without mounting the switching element 10 on the module. Therefore, it is found that the resistance value of the first resistance portion 16 does not conform to the standard after the switching element 10 is mounted, and the amount of damage can be reduced compared to the case where the entire semiconductor device is discarded.
- the resistance value of the first resistance unit 16 can be measured by bringing the probe into contact with both the first gate pad 12 and the second gate pad 14. it can. Therefore, it can be confirmed that the resistance value of the first resistance portion 16 conforms to the standard.
- the semiconductor device can be stably operated without current concentration on any of the plurality of switching elements.
- the number of parallel switching elements in the semiconductor device is large, or when the semiconductor device is switched at a high frequency, it is necessary to align the gate resistance values of the switching elements in the semiconductor device with high accuracy. In this case, it is preferable to select switching elements having a gate resistance value within a desired range based on the gate resistance value of each element measured as described above and mount them on one semiconductor device.
- a plurality of switching elements are manufactured, their resistance values are measured, switching elements whose resistance values are within a desired range among the plurality of switching elements are selected, and the selected switching elements are mounted on one semiconductor device. . This makes it possible to efficiently obtain a high-performance semiconductor device.
- FIG. 2 is a plan view showing the aluminum wire 22 fixed to the second gate pad 14.
- the first resistor 16 can be used as an on-chip resistor.
- FIG. 3 is a plan view showing the aluminum wire 24 fixed to the first gate pad 12. When the aluminum wire 24 is connected to the first gate pad 12, a switching element having no on-chip resistance can be obtained.
- the switching element 10 can be made compatible with a plurality of types. That is, by appropriately selecting the gate resistance, the switching element 10 can be used for a plurality of types having different numbers of parallel mounting. Therefore, manufacturing management can be simplified and productivity can be improved.
- FIG. 4 is a plan view of a switching element according to a modification.
- the first gate pad 26 is formed in the cell region 18. Specifically, the first gate pad 26 is formed at the corner of the cell region 18. The first gate pad 26 is preferably provided immediately above the gate wiring portion in the cell region 18.
- FIG. 5 is a plan view of a switching element including a resistance portion 40 as a connection portion.
- the connection part is formed by a resistance part 40.
- the resistor portion 40 can be used as an on-chip resistor by fixing an aluminum wire to the first gate pad 12.
- the series resistance of the first resistance portion 16 and the resistance portion 40 can be used as an on-chip resistance.
- Switching element 10 is not limited to an IGBT.
- the switching element may be formed of a power MOSFET.
- the substrate 11 may be formed of a wide band gap semiconductor.
- the wide band gap semiconductor include silicon carbide, gallium nitride-based materials, and diamond.
- the switching element may be formed of a wide band gap semiconductor.
- the semiconductor device can be stably operated by confirming that the gate resistance values of the plurality of switching elements are aligned by the above method.
- FIG. 6 is a plan view of the switching element 30 according to the second embodiment of the present invention.
- the switching element 30 includes a third gate pad 32 formed on the substrate 11.
- the second gate pad 14 and the third gate pad 32 are connected by a second resistor portion 34 formed on the substrate 11.
- a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. First, the switching element 30 is manufactured. Next, a probe is applied to the first gate pad 12 and the second gate pad 14 to measure the resistance value of the first resistance unit 16. Next, a probe is applied to the second gate pad 14 and the third gate pad 32 to measure the resistance value of the second resistance unit 34. Next, a probe is applied to the first gate pad 12 and the third gate pad 32, and the series resistance value of the first resistance unit 16 and the second resistance unit 34 is measured.
- the switching element 30 is mounted on the module. Then, an aluminum wire is fixed to any one of the first gate pad 12, the second gate pad 14, and the third gate pad 32.
- the resistance value of the first resistance unit 16 is R1
- the resistance value of the second resistance unit 34 is R2.
- the second resistor portion 34 and the first resistor portion 16 can be used as on-chip resistors.
- the gate resistance value at this time is R1 + R2.
- the first resistor portion 16 can be used as an on-chip resistor.
- the gate resistance value at this time is R1.
- a switching element having no on-chip resistance can be obtained. Therefore, a desired gate resistance value can be selected from the three gate resistance values.
- a probe is applied to the gate pad to provide three resistance values (the resistance value of the first resistance unit 16, the resistance value of the second resistance unit 34, the first resistance unit 16 and the second resistance unit 34). Series resistance value).
- the measurement of the resistance value may be omitted for the resistance portion that is known not to be used in advance.
- FIG. 7 is a plan view of the switching element 50 according to Embodiment 3 of the present invention.
- the switching element 50 includes a first additional gate pad 52 formed on the substrate 11.
- the first additional gate pad 52 and the first gate pad 12 are connected by a first additional resistance portion 54 formed on the substrate 11.
- a method for manufacturing a semiconductor device will be described. First, the switching element 50 is manufactured. Next, a probe is applied to the first gate pad 12 and the second gate pad 14 to measure the resistance value of the first resistance unit 16. Next, a probe is applied to the first gate pad 12 and the first additional gate pad 52, and the resistance value of the first additional resistance unit 54 is measured. Further, a probe is applied to the first gate pad 12, the second gate pad 14, and the first additional gate pad 52, and the parallel resistance values of the first resistance unit 16 and the first additional resistance unit 54 are measured.
- the switching element 50 is mounted on the module. Then, an aluminum wire is fixed to the first gate pad 12, the second gate pad 14, the first additional gate pad 52, or both the second gate pad 14 and the first additional gate pad 52.
- the resistance value of the first resistance unit 16 is R1
- the resistance value of the first additional resistance unit 54 is R A 1.
- the first resistor portion 16 can be used as an on-chip resistor.
- the gate resistance value at this time is R1.
- the first additional resistor portion 54 can be used as an on-chip resistor.
- the gate resistance value at this time is R A 1.
- the first resistor 16 and the first additional resistor 54 connected in parallel as on-chip resistors can be used.
- the gate resistance value at this time is (R1 ⁇ R A 1) / (R1 + R A 1). Therefore, a desired gate resistance value can be selected from four gate resistance values simply by selecting the connection method of the aluminum wires.
- FIG. 8 is a plan view of the switching element 56 according to the fourth embodiment of the present invention.
- the switching element 56 includes a second additional gate pad 60 formed on the substrate 11.
- the second additional gate pad 60 and the first additional gate pad 52 are connected by a second additional resistor portion 62 formed on the substrate 11.
- the switching element described in the third embodiment can provide four gate resistance values
- the switching element 56 according to the fourth embodiment provides five gate resistance values in addition to these four gate resistance values. It can. Assuming that the resistance value of the second resistance unit 34 is R2 and the resistance value of the second additional resistance unit 62 is R A 2, the five new gate resistance values are as follows.
- the gate resistance value is R1 + R2.
- the gate resistance value is R A 1 + R A 2.
- the gate resistance value is ((R2 + R1) ⁇ (R A 2 + R A 1)) / ((R2 + R1) + (R A 2 + R A 1)).
- the gate resistance value is ((R2 + R1) ⁇ R A 1) / ((R2 + R1) + R A 1).
- the gate resistance value is (R1 ⁇ (R A 2 + R A 1)) / (R1 + (R A 2 + R A 1)). It is.
- the switching element 56 is completed, the above nine resistance values are measured.
- the switching element 56 is mounted on the module.
- the aluminum wire is fixed to the gate pad so as to realize one of nine resistance values. Therefore, a desired gate resistance value can be selected from nine gate resistance values simply by selecting a connection method of aluminum wires.
- FIG. 9 is a plan view of the switching element 70 according to the fifth embodiment of the present invention.
- the switching element 70 is characterized in that a plurality of gate pads including the first gate pad 12 and the second gate pad 14 are formed so as to surround the cell region 18.
- the switching element 70 has a quadrangular shape having a first side 11a, a second side 11b, a third side 11c, and a fourth side 11d in plan view.
- First to third gate pads 12, 14, and 32 are formed along the first side 11a.
- Fourth to sixth gate pads 72, 74, and 76 are formed along the second side 11b.
- Seventh to ninth gate pads 78, 80, and 82 are formed along the third side 11c.
- Tenth to twelfth gate pads 84, 86, and 88 are formed along the fourth side 11d.
- Adjacent two gate pads are connected by a resistor. That is, as shown in FIG. 9, the first to eleventh resistance portions 16, 34, 90, 92, 94, 96, 98, 100, 102, 104, 106 are formed. However, the sixth gate pad 76 and the twelfth gate pad 88 are not connected. A gate wiring including a gate resistance portion from the sixth gate pad 76 to the first gate pad 12 and a gate wiring including a gate resistance portion from the twelfth gate pad 88 to the first gate pad 12 are connected in parallel. After confirming that the resistance values of the first to eleventh resistor portions 16, 34, 90, 92, 94, 96, 98, 100, 102, 104, 106 conform to the standard, the switching element 70 is mounted on the package. .
- An aluminum wire is fixed to the gate pad for each of the two gate wirings connected in parallel.
- a desired gate resistance value can be selected from 78 gate resistance values simply by setting the resistance values of the respective resistance portions to different values and selecting an aluminum wire connection method.
- the number of gate pads, the arrangement method, the number of resistance portions, and the arrangement method can be adjusted as appropriate. By adjusting these appropriately, a desired set of gate resistance values can be prepared. That is, the number and arrangement method of the plurality of resistance portions are particularly limited as long as the plurality of gate pads are connected so that all of the plurality of gate pads are electrically connected to the first gate pad. Not.
- FIG. 10 is a circuit diagram of a semiconductor device according to the sixth embodiment of the present invention.
- This semiconductor device includes a first switching element 10A and a second switching element 10B.
- the first switching element 10A and the second switching element 10B have the same configuration as the switching element 10 according to the first embodiment.
- the first switching element 10A and the second switching element 10B are connected in parallel.
- the aluminum wire is fixed to the second gate pad 14 of the first switching element 10A and the second gate pad 14 of the second switching element 10B, so that the gate driving circuit 200 is connected to them.
- the control signal is transmitted from the gate driving circuit 200 to the cell region of the first switching element 10A via the first resistor 16 of the first switching element 10A.
- a similar control signal is transmitted from the gate drive circuit 200 to the cell region of the second switching element 10B via the first resistance portion 16 of the second switching element 10B.
- the resistance value of the first resistance part 16 of the first switching element 10A and the resistance value of the first resistance part 16 of the second switching element 10B conform to the standard. Therefore, current imbalance can be avoided.
- the gate resistance of the switching element can be adjusted by selecting whether the aluminum wire is connected to the first gate pad 12 or the second gate pad 14. Therefore, whether the control signal is supplied to the first gate pad 12 of the first switching element 10A and the second switching element 10B, or to the second gate pad 14 of the first switching element 10A and the second switching element 10B, By selecting either of these, you can handle a wide variety of products.
- the first switching element 10A and the second switching element 10B are not limited to the switching element 10 of the first embodiment, and any one of the above switching elements may be adopted. Further, the number of parallel switching elements is not limited to two and may be larger. In this case, the wires are respectively connected to the first gate pads or the second gate pads of the plurality of switching elements as described above. The effects of the present invention may be enhanced by appropriately combining the characteristics of the switching elements according to the above embodiments.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
図1は、本発明の実施の形態1に係るスイッチング素子10を模式的に示す平面図である。スイッチング素子10はIGBTである。スイッチング素子10は基板11を備えている。基板11には第1ゲートパッド12と第2ゲートパッド14が形成されている。基板11には第1ゲートパッド12と第2ゲートパッド14を接続する第1抵抗部16が形成されている。第1抵抗部16は、スイッチング素子10に内蔵されたゲート抵抗である。第1抵抗部16はウエハプロセスで形成された高抵抗層を備えている。スイッチング素子に内蔵されたゲート抵抗はオンチップ抵抗と呼ばれることもある。なお、図面においては、第1抵抗部16は回路記号で示す。
本発明の実施の形態2に係るスイッチング素子、半導体装置、及び半導体装置の製造方法は、実施の形態1と共通点が多いので、実施の形態1との相違点を中心に説明する。図6は、本発明の実施の形態2に係るスイッチング素子30の平面図である。スイッチング素子30は、基板11に形成された第3ゲートパッド32を備えている。第2ゲートパッド14と第3ゲートパッド32は、基板11に形成された第2抵抗部34により接続されている。
本発明の実施の形態3に係るスイッチング素子、半導体装置、及び半導体装置の製造方法は、実施の形態1と共通点が多いので、実施の形態1との相違点を中心に説明する。図7は、本発明の実施の形態3に係るスイッチング素子50の平面図である。スイッチング素子50は、基板11に形成された第1付加ゲートパッド52を備えている。第1付加ゲートパッド52と第1ゲートパッド12は、基板11に形成された第1付加抵抗部54により接続されている。
本発明の実施の形態4に係るスイッチング素子、半導体装置、及び半導体装置の製造方法は、実施の形態3と共通点が多いので、実施の形態3との相違点を中心に説明する。図8は、本発明の実施の形態4に係るスイッチング素子56の平面図である。スイッチング素子56は基板11に形成された第2付加ゲートパッド60を備えている。第2付加ゲートパッド60と第1付加ゲートパッド52は、基板11に形成された第2付加抵抗部62により接続されている。
本発明の実施の形態5に係るスイッチング素子、半導体装置、及び半導体装置の製造方法は、実施の形態2との相違点を中心に説明する。図9は、本発明の実施の形態5に係るスイッチング素子70の平面図である。スイッチング素子70は、第1ゲートパッド12及び第2ゲートパッド14を含む複数のゲートパッドが、セル領域18を囲むように形成されたことが特徴である。
図10は、本発明の実施の形態6に係る半導体装置の回路図である。この半導体装置は、第1スイッチング素子10Aと第2スイッチング素子10Bを備えている。第1スイッチング素子10Aと第2スイッチング素子10Bは、実施の形態1に係るスイッチング素子10と同じ構成を有している。第1スイッチング素子10Aと第2スイッチング素子10Bは並列に接続されている。
Claims (14)
- 基板と、
前記基板に形成された第1ゲートパッドと、
前記基板に形成された第2ゲートパッドと、
前記基板に形成された、前記第1ゲートパッドと前記第2ゲートパッドを接続する第1抵抗部と、
前記基板に形成され、前記第1ゲートパッドと接続されたセル領域と、を備えたことを特徴とするスイッチング素子。 - 前記基板に形成された第3ゲートパッドと、
前記基板に形成された、前記第2ゲートパッドと前記第3ゲートパッドを接続する第2抵抗部と、を備えたことを特徴とする請求項1に記載のスイッチング素子。 - 前記基板に形成された第1付加ゲートパッドと、
前記基板に形成された、前記第1ゲートパッドと前記第1付加ゲートパッドを接続する第1付加抵抗部と、を備えたことを特徴とする請求項1又は2に記載のスイッチング素子。 - 前記基板に形成された第2付加ゲートパッドと、
前記基板に形成された、前記第2付加ゲートパッドと前記第1付加ゲートパッドを接続する第2付加抵抗部と、を備えたことを特徴とする請求項3に記載のスイッチング素子。 - 前記第1ゲートパッドは、前記セル領域の外側にあり、
前記基板に形成され、前記第1ゲートパッドと前記セル領域を接続する接続部を備えたことを特徴とする請求項1乃至4のいずれか1項に記載のスイッチング素子。 - 前記接続部は配線で形成されたことを特徴とする請求項5に記載のスイッチング素子。
- 前記接続部は抵抗部分で形成されたことを特徴とする請求項5に記載のスイッチング素子。
- 前記第1ゲートパッド、及び前記第2ゲートパッドを含む複数のゲートパッドと、
前記複数のゲートパッドの全てが前記第1ゲートパッドと電気的に接続されるように、前記複数のゲートパッドを接続する、前記第1抵抗部を含む複数の抵抗部と、を備え、
前記複数のゲートパッドは前記セル領域を囲むように形成されたことを特徴とする請求項1乃至7のいずれか1項に記載のスイッチング素子。 - 前記第1ゲートパッドは前記セル領域内に形成されたことを特徴とする請求項1乃至4のいずれか1項に記載のスイッチング素子。
- 前記基板は、ワイドバンドギャップ半導体で形成されたことを特徴とする請求項1乃至9のいずれか1項に記載のスイッチング素子。
- 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料、又はダイヤモンドであることを特徴とする請求項10に記載のスイッチング素子。
- 基板と、前記基板に形成された第1ゲートパッドと、前記基板に形成された第2ゲートパッドと、前記基板に形成された、前記第1ゲートパッドと前記第2ゲートパッドを接続する第1抵抗部と、前記基板に形成され、前記第1ゲートパッドと接続されたセル領域と、を備えたスイッチング素子を複数備え、
複数の前記スイッチング素子の前記第1ゲートパッド、又は前記第2ゲートパッドにそれぞれ接続された、制御信号を供給する複数のワイヤを備えたことを特徴とする半導体装置。 - 基板と、前記基板に形成された第1ゲートパッドと、前記基板に形成された第2ゲートパッドと、前記基板に形成された、前記第1ゲートパッドと前記第2ゲートパッドを接続する第1抵抗部と、前記基板に形成され、前記第1ゲートパッドと接続されたセル領域と、を備えたスイッチング素子を製造する工程と、
前記第1ゲートパッドと前記第2ゲートパッドにプローブをあてて、前記第1抵抗部の抵抗値を測定する工程と、
前記抵抗値が規格に適合する場合、前記スイッチング素子をモジュールに搭載する工程と、を備えたことを特徴とする半導体装置の製造方法。 - 基板と、前記基板に形成された第1ゲートパッドと、前記基板に形成された第2ゲートパッドと、前記基板に形成された、前記第1ゲートパッドと前記第2ゲートパッドを接続する第1抵抗部と、前記基板に形成され、前記第1ゲートパッドと接続されたセル領域と、を備えたスイッチング素子を複数製造する工程と、
複数の前記スイッチング素子のそれぞれについて、前記第1ゲートパッドと前記第2ゲートパッドにプローブをあてて、前記第1抵抗部の抵抗値を測定する工程と、
複数の前記スイッチング素子のうち、前記抵抗値が所望範囲内であるスイッチング素子を選別し、選別されたスイッチング素子を1つの半導体装置に搭載する工程と、を備えたことを特徴とする半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201380079465.4A CN105531814A (zh) | 2013-09-09 | 2013-09-09 | 开关元件、半导体装置、半导体装置的制造方法 |
CN202110510096.6A CN113224150A (zh) | 2013-09-09 | 2013-09-09 | 开关元件、半导体装置、半导体装置的制造方法 |
PCT/JP2013/074284 WO2015033476A1 (ja) | 2013-09-09 | 2013-09-09 | スイッチング素子、半導体装置、半導体装置の製造方法 |
JP2015535278A JP6020733B2 (ja) | 2013-09-09 | 2013-09-09 | スイッチング素子、半導体装置、半導体装置の製造方法 |
DE112013007417.6T DE112013007417B4 (de) | 2013-09-09 | 2013-09-09 | Schaltelement, Halbleiteranordnung und Verfahren zum Herstellen einer Halbleiteranordnung |
US14/897,797 US9553084B2 (en) | 2013-09-09 | 2013-09-09 | Switching element, semiconductor device, and semiconductor device manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2013/074284 WO2015033476A1 (ja) | 2013-09-09 | 2013-09-09 | スイッチング素子、半導体装置、半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015033476A1 true WO2015033476A1 (ja) | 2015-03-12 |
Family
ID=52627981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2013/074284 WO2015033476A1 (ja) | 2013-09-09 | 2013-09-09 | スイッチング素子、半導体装置、半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9553084B2 (ja) |
JP (1) | JP6020733B2 (ja) |
CN (2) | CN113224150A (ja) |
DE (1) | DE112013007417B4 (ja) |
WO (1) | WO2015033476A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170062412A1 (en) * | 2015-08-25 | 2017-03-02 | Mitsubishi Electric Corporation | Transistor element and semiconductor device |
US20170352600A1 (en) * | 2016-06-03 | 2017-12-07 | Mitsubishi Electric Corporation | Semiconductor device and method for producing the same |
JP2020047675A (ja) * | 2018-09-14 | 2020-03-26 | 富士電機株式会社 | 半導体装置 |
JP2021005925A (ja) * | 2019-06-25 | 2021-01-14 | 株式会社デンソー | 並列スイッチング回路 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111684582B (zh) * | 2018-06-19 | 2022-05-10 | 新唐科技日本株式会社 | 半导体装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758293A (ja) * | 1993-08-18 | 1995-03-03 | Hitachi Ltd | 絶縁ゲート型半導体装置およびそれを用いた駆動回路装置ならびに電子システム |
JP2007273931A (ja) * | 2006-03-07 | 2007-10-18 | Toshiba Corp | 電力用半導体素子、その製造方法及びその駆動方法 |
JP2008147785A (ja) * | 2006-12-06 | 2008-06-26 | Denso Corp | プルアップ抵抗遮断用mosトランジスタの駆動回路 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03179779A (ja) | 1989-09-29 | 1991-08-05 | Fuji Electric Co Ltd | 絶縁ゲート型半導体装置 |
JP2800566B2 (ja) * | 1991-07-23 | 1998-09-21 | 日本電気株式会社 | 電界効果トランジスタおよび高周波信号発振器および周波数変換回路 |
US5592006A (en) | 1994-05-13 | 1997-01-07 | International Rectifier Corporation | Gate resistor for IGBT |
JP3311166B2 (ja) | 1994-10-18 | 2002-08-05 | 株式会社東芝 | 絶縁ゲート型半導体装置 |
JP2746172B2 (ja) * | 1995-02-02 | 1998-04-28 | 日本電気株式会社 | 半導体集積回路装置 |
JPH10150142A (ja) * | 1996-11-20 | 1998-06-02 | Fuji Electric Co Ltd | 半導体装置 |
JP3318928B2 (ja) | 1999-04-12 | 2002-08-26 | 日本電気株式会社 | 半導体装置 |
JP2005032736A (ja) | 2002-06-10 | 2005-02-03 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
DE10246960B4 (de) | 2002-10-09 | 2004-08-19 | Infineon Technologies Ag | Feldeffektleistungstransistor |
JP4342826B2 (ja) * | 2003-04-23 | 2009-10-14 | 株式会社半導体エネルギー研究所 | 半導体素子の作製方法 |
JP2005228851A (ja) * | 2004-02-12 | 2005-08-25 | Mitsubishi Electric Corp | Igbtモジュール |
KR20090026657A (ko) * | 2007-09-10 | 2009-03-13 | 주식회사 하이닉스반도체 | 반도체 소자의 테스트 패턴 |
US8531226B2 (en) * | 2011-03-22 | 2013-09-10 | Fairchild Semiconductor Corporation | Bridge circuit providing a polarity insensitive power connection |
JP6111130B2 (ja) * | 2013-04-22 | 2017-04-05 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
-
2013
- 2013-09-09 DE DE112013007417.6T patent/DE112013007417B4/de active Active
- 2013-09-09 CN CN202110510096.6A patent/CN113224150A/zh active Pending
- 2013-09-09 US US14/897,797 patent/US9553084B2/en active Active
- 2013-09-09 WO PCT/JP2013/074284 patent/WO2015033476A1/ja active Application Filing
- 2013-09-09 CN CN201380079465.4A patent/CN105531814A/zh active Pending
- 2013-09-09 JP JP2015535278A patent/JP6020733B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758293A (ja) * | 1993-08-18 | 1995-03-03 | Hitachi Ltd | 絶縁ゲート型半導体装置およびそれを用いた駆動回路装置ならびに電子システム |
JP2007273931A (ja) * | 2006-03-07 | 2007-10-18 | Toshiba Corp | 電力用半導体素子、その製造方法及びその駆動方法 |
JP2008147785A (ja) * | 2006-12-06 | 2008-06-26 | Denso Corp | プルアップ抵抗遮断用mosトランジスタの駆動回路 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170062412A1 (en) * | 2015-08-25 | 2017-03-02 | Mitsubishi Electric Corporation | Transistor element and semiconductor device |
US20170352600A1 (en) * | 2016-06-03 | 2017-12-07 | Mitsubishi Electric Corporation | Semiconductor device and method for producing the same |
US10074578B2 (en) * | 2016-06-03 | 2018-09-11 | Mitsubishi Electric Corporation | Semiconductor device and method for producing the same |
JP2020047675A (ja) * | 2018-09-14 | 2020-03-26 | 富士電機株式会社 | 半導体装置 |
JP7172328B2 (ja) | 2018-09-14 | 2022-11-16 | 富士電機株式会社 | 半導体装置 |
JP2021005925A (ja) * | 2019-06-25 | 2021-01-14 | 株式会社デンソー | 並列スイッチング回路 |
JP7205402B2 (ja) | 2019-06-25 | 2023-01-17 | 株式会社デンソー | 並列スイッチング回路 |
Also Published As
Publication number | Publication date |
---|---|
DE112013007417B4 (de) | 2024-01-04 |
US9553084B2 (en) | 2017-01-24 |
CN113224150A (zh) | 2021-08-06 |
US20160148927A1 (en) | 2016-05-26 |
CN105531814A (zh) | 2016-04-27 |
JPWO2015033476A1 (ja) | 2017-03-02 |
DE112013007417T5 (de) | 2016-06-02 |
JP6020733B2 (ja) | 2016-11-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6020733B2 (ja) | スイッチング素子、半導体装置、半導体装置の製造方法 | |
US10446498B2 (en) | Isolation between semiconductor components | |
TWI769202B (zh) | 半導體裝置 | |
TWI463640B (zh) | 半導體裝置及電子機器 | |
JP6062565B1 (ja) | 半導体装置およびその製造方法 | |
TWI648831B (zh) | Semiconductor device and method of manufacturing same | |
JP5001872B2 (ja) | 半導体装置 | |
TW201413895A (zh) | 多晶片封裝結構及其封裝方法 | |
US10643930B2 (en) | Semiconductor device with semiconductor chips of different sizes and manufacturing method threreof | |
JP2013125848A (ja) | パワーモジュール半導体装置およびその製造方法 | |
TWI354357B (en) | Semiconductor intergrated circuit and leadframe fo | |
CN102195602B (zh) | 振动片基板及音叉型振动片 | |
JP2003243576A (ja) | 半導体装置 | |
CN104247027A (zh) | 功率晶体管模块 | |
JP2005101097A (ja) | 半導体装置及びその製造方法 | |
KR100396344B1 (ko) | 모니터용 저항 소자 및 저항 소자의 상대적 정밀도의 측정방법 | |
JP5218087B2 (ja) | 半導体装置 | |
JP5811803B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
WO2020129788A1 (ja) | 方向性結合器及び高周波モジュール | |
JP2023069756A (ja) | 半導体装置 | |
CN104485323A (zh) | 引线框架和半导体封装体 | |
JP2004119819A (ja) | 半導体装置 | |
JP5017485B2 (ja) | システムインパッケージ | |
JP6299388B2 (ja) | 半導体装置及びこれを用いた電力変換装置 | |
JP2945488B2 (ja) | リードフレーム及び半導体装置のバーンイン方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201380079465.4 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13893072 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2015535278 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14897797 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112013007417 Country of ref document: DE Ref document number: 1120130074176 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 13893072 Country of ref document: EP Kind code of ref document: A1 |