WO2015019771A1 - 酸化物半導体層及びその製造方法、並びに酸化物半導体の前駆体、酸化物半導体層、半導体素子、及び電子デバイス - Google Patents
酸化物半導体層及びその製造方法、並びに酸化物半導体の前駆体、酸化物半導体層、半導体素子、及び電子デバイス Download PDFInfo
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- WO2015019771A1 WO2015019771A1 PCT/JP2014/067960 JP2014067960W WO2015019771A1 WO 2015019771 A1 WO2015019771 A1 WO 2015019771A1 JP 2014067960 W JP2014067960 W JP 2014067960W WO 2015019771 A1 WO2015019771 A1 WO 2015019771A1
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- Prior art keywords
- oxide semiconductor
- temperature
- precursor
- layer
- semiconductor layer
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Images
Classifications
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- C—CHEMISTRY; METALLURGY
- C01—INORGANIC CHEMISTRY
- C01G—COMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
- C01G15/00—Compounds of gallium, indium or thallium
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02104—Forming layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02483—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
Definitions
- the present invention relates to an oxide semiconductor layer, a manufacturing method thereof, a precursor of an oxide semiconductor, an oxide semiconductor layer, a semiconductor element, and an electronic device.
- a polycrystalline silicon film or an amorphous silicon film has been mainly used as a channel layer of a thin film transistor.
- the electron mobility is limited due to electron scattering or the like occurring at the interface between crystal grains, resulting in variations in transistor characteristics.
- an amorphous silicon film there is a problem that the reliability of the element is lowered because the electron mobility is very low and the element is easily deteriorated with time.
- oxide semiconductors having higher electron mobility than amorphous silicon films and less variation in transistor characteristics than polycrystalline silicon films.
- Patent Documents 1 to 3 attempts have been made to produce a coated flexible electronic device using a conductive polymer or an organic semiconductor.
- a layer formed by a printing method which is a typical example of a low energy manufacturing process
- the thickness of a layer required for a semiconductor element is generally very thin.
- a paste or solution used in a low energy manufacturing process for example, a precursor of an oxide semiconductor in which a metal compound that becomes an oxide semiconductor when oxidized is dispersed in a solution containing a binder
- the viscosity is adjusted by adding a binder.
- a layer typically an oxide semiconductor layer
- patterning is performed using a paste or solution to which a binder is added, and then the binder is removed as much as possible.
- the layer must be thinned.
- cracks occur during the thinning process.
- the binder is decomposed to some extent by firing to form this oxide semiconductor layer, a certain amount still remains in the paste or solution as impurities.
- residual impurities such as carbon impurities cause a deterioration in electrical characteristics of the semiconductor with high accuracy if the amount exceeds a certain value. Therefore, many technical problems still remain in the manufacture of semiconductor devices using low energy manufacturing processes.
- a desired thin oxide semiconductor layer is formed by firing a film on a substrate formed by a low energy manufacturing process, and a semiconductor element including the oxide semiconductor layer is manufactured. Will make great progress towards solving the above-mentioned problems.
- the present invention solves at least one of the above-described problems, thereby reducing the generation of cracks (or cracks, hereinafter collectively referred to as “cracks”), and having excellent electrical characteristics and stability.
- the present invention greatly contributes to the provision of a semiconductor element and an electronic device including the layer and the oxide semiconductor layer.
- Inventors of the present application are conducting various researches on the formation of various oxide semiconductor layers from a liquid material, and in detail analyzing the process from the liquid to the gel film and the process from the gel film to solidification or sintering in a multifaceted manner. Went.
- a material that can solidify or sinter the oxide semiconductor precursor material from the gel film at a temperature that can be differentiated from the temperature at which the binder is almost completely decomposed, It was found that it can be solved.
- the binder and the solvent are removed by heat treatment, but a metal compound (for example, a distribution) that becomes an oxide semiconductor when oxidized.
- a metal complex having a ligand is not decomposed.
- the above-mentioned “process from gel film to solidification or sintering” is a typical example.
- the above-mentioned ligand is decomposed and oxidized, it is formed between the metal that becomes an oxide semiconductor and oxygen. A situation where the bond is substantially completed.
- the inventors of the present application form a film from a material in which a precursor of a specific oxide semiconductor is dispersed in a solution in a binder made of an aliphatic polycarbonate.
- a film can be easily formed by a low energy manufacturing process.
- the present invention has been created based on the above viewpoints and numerous analyses.
- One method of manufacturing an oxide semiconductor layer according to the present invention includes an oxidation in which a metal compound that becomes an oxide semiconductor when oxidized is dispersed in a solution containing a binder (which may contain inevitable impurities) made of an aliphatic polycarbonate.
- a firing step of firing the layer is performed in which a metal compound that becomes an oxide semiconductor when oxidized is dispersed in a solution containing a binder (which may contain inevitable impurities) made of an aliphatic polycarbonate.
- the binder made of aliphatic polycarbonate is heated at the first temperature at which 90% by weight or more of the above-mentioned binder is decomposed, whereby the binder is substantially decomposed. Then, the temperature is higher than the first temperature and is a temperature at which the metal that becomes an oxide semiconductor and oxygen when combined are oxidized, and the heat generation in the differential thermal analysis (DTA) of the precursor of the oxide semiconductor.
- DTA differential thermal analysis
- a metal compound that becomes an oxide semiconductor when oxidized is dispersed in a solution containing a binder (which may contain inevitable impurities) made of an aliphatic polycarbonate.
- a first oxide semiconductor precursor that is a temperature at which the metal and oxygen are bonded to each other and is lower than a second temperature that is an exothermic peak value in differential thermal analysis (DTA) of the precursor. It is a precursor whose binder is decomposed by 90 wt% or more depending on the temperature.
- the first temperature for decomposing the binder is preferably a temperature for decomposing the binder by 95 wt% or more. More preferably, the temperature is 99% by weight or more.
- One oxide semiconductor layer of the present invention includes an oxide in which a metal compound that becomes an oxide semiconductor when oxidized is dispersed in a solution containing a binder (which may contain inevitable impurities) made of an aliphatic polycarbonate.
- the semiconductor precursor layer is formed by firing at a temperature at which the metal and oxygen are bonded to each other and at or above a second temperature that is an exothermic peak value in differential thermal analysis (DTA) of the precursor,
- the binder is an oxide semiconductor layer in which the binder is decomposed by 90 wt% or more by a first temperature lower than the second temperature.
- the first temperature for decomposing the binder is preferably a temperature for decomposing the binder by 95 wt% or more. More preferably, the temperature is 99% by weight or more.
- the “substrate” in the present application is not limited to the foundation of the plate-like body, but includes other forms of foundations or base materials.
- the “layer” in the present application is a concept including not only a layer but also a film.
- the “film” in the present application is a concept including not only a film but also a layer.
- “application” refers to forming a layer on a substrate by a low energy manufacturing process, that is, a printing method or an application method.
- one oxide semiconductor layer of the present invention it is possible to accurately suppress the remaining of impurities typified by carbon impurities in the manufactured oxide semiconductor layer. As a result, generation of cracks can be reduced, and a semiconductor element or electronic device having excellent electrical characteristics and stability can be realized.
- a low energy manufacturing process can be realized.
- an oxide semiconductor layer in which the remaining of impurities represented by carbon impurities can be suppressed with high accuracy can be formed. Further, according to one oxide semiconductor layer of the present invention, the remaining of impurities represented by carbon impurities in the oxide semiconductor layer can be suppressed with high accuracy. Therefore, according to one oxide semiconductor precursor or oxide semiconductor layer of the present invention, it is possible to reduce the generation of cracks and realize a semiconductor element or electronic device having excellent electrical characteristics and stability. it can.
- 6 is a graph showing Vg-Id characteristics of a channel of a thin film transistor in an example corresponding to the first embodiment of the present invention. 6 is a graph showing Vg-Id characteristics of a channel of a thin film transistor in an example corresponding to a modification of the first embodiment of the present invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 2nd Embodiment of this invention.
- FIGS. 1 to 8 are schematic cross-sectional views showing one process of a method of manufacturing a thin film transistor 100 which is an example of a semiconductor element.
- FIG. 9 is a schematic cross-sectional view showing one process and the entire configuration of the method of manufacturing the thin film transistor 100 according to this embodiment.
- the gate electrode 20, the gate insulating layer 34, the channel 44, the source electrode 58, and the drain electrode 56 are stacked in this order on the substrate 10 from the lower layer.
- provision or realization of an electronic device for example, a portable terminal, an information home appliance, or other known electrical appliances
- an electronic device for example, a portable terminal, an information home appliance, or other known electrical appliances
- the thin film transistor 100 employs a so-called bottom gate structure, but this embodiment is not limited to this structure. Therefore, a person skilled in the art can form a top gate structure by changing the order of the steps by referring to the description of the present embodiment with ordinary technical common sense.
- the temperature display in the present application represents the set temperature in the case of a heater that contacts the substrate, and the temperature near the surface of the heating object in the case of a heater that does not contact the substrate. Represents. Further, in order to simplify the drawing, description of patterning of the extraction electrode from each electrode is omitted.
- the substrate 10 of the present embodiment is not particularly limited, and a substrate generally used for a semiconductor element is used.
- a substrate generally used for a semiconductor element is used.
- high heat resistant glass SiO 2 / Si substrate (that is, a substrate in which a silicon oxide film is formed on a silicon substrate), alumina (Al 2 O 3 ) substrate, STO (SrTiO) substrate, SiO 2 on the surface of Si substrate
- Various insulating base materials including a semiconductor substrate (for example, a Si substrate, a SiC substrate, a Ge substrate, etc.) such as an insulating substrate in which an STO (SrTiO) layer is formed via a layer and a Ti layer can be applied.
- the insulating substrate is made of materials such as polyesters such as polyethylene terephthalate and polyethylene naphthalate, polyolefins, cellulose triacetate, polycarbonate, polyamide, polyimide, polyamideimide, polysulfone, aramid, and aromatic polyamide. Film or sheet is included. Further, the thickness of the substrate is not particularly limited, but is, for example, 3 ⁇ m to 300 ⁇ m. Further, the substrate may be hard or flexible.
- the material of the gate electrode 20 is, for example, a metal material such as refractory metal such as platinum, gold, silver, copper, aluminum, molybdenum, palladium, ruthenium, iridium, tungsten, or an alloy thereof.
- a conductive metal oxide containing ruthenium oxide, a p + -silicon layer, or an n + -silicon layer can be applied.
- the gate electrode 20 is formed on a SiO 2 / Si substrate (hereinafter also simply referred to as “substrate”) 10 as a base material by a known sputtering method or CVD method. .
- the gate insulating layer 34 is a precursor for a gate insulating layer having a precursor containing silicon (Si) (for example, polysilazane) as a solute.
- Si silicon
- a silicon oxide starting from a body solution (however, it may contain unavoidable impurities. The same applies to oxides of other materials as well as oxides of this material).
- the organic solvent employed in the solution containing the binder is not particularly limited as long as the organic solvent can dissolve the aliphatic polycarbonate.
- the organic solvent include diethylene glycol monoethyl ether acetate, ⁇ -terpineol, ⁇ -terpineol, N-methyl-2-pyrrolidone, isopropyl alcohol, diethylene glycol monobutyl ether acetate, diethylene glycol monobutyl ether, toluene, cyclohexane, methyl ethyl ketone, dimethyl carbonate , Diethyl carbonate, propylene carbonate and the like.
- the set temperature in this firing step is a temperature at which the metal and oxygen are bonded after the ligand of the metal compound is decomposed in the formation process of the oxide semiconductor, and differential thermal analysis (DTA) described later.
- a temperature equal to or higher than the temperature of the exothermic peak value (second temperature) is selected.
- the second temperature is higher by 10 ° C. or more than the first temperature is more accurate, and is a preferable embodiment from the viewpoint of suppressing the remaining impurities typified by carbon impurities in the oxide semiconductor layer after the main baking. It is.
- the second temperature is higher than the first temperature by 50 ° C. or more, it is possible to suppress the remaining of such impurities with higher accuracy.
- the second temperature is higher than the first temperature by 100 ° C. or more. Is the most preferred example.
- the maximum difference between the second temperature and the first temperature is not particularly limited.
- the heating method is not particularly limited in any of the first pre-baking step, the second pre-baking step, and the main baking (baking step).
- a conventional heating method using a thermostat or an electric furnace may be used, but in particular, when the substrate is vulnerable to heat, the oxide semiconductor layer is heated by ultraviolet heating, electromagnetic wave heating, or lamp heating so that the heat is not transmitted to the substrate. It is preferable to use a method of heating only.
- aliphatic polycarbonate is at least one selected from the group consisting of polyethylene carbonate and polypropylene carbonate from the viewpoint of high oxygen content and decomposition into a low molecular weight compound at a relatively low temperature. It is preferable.
- ethylene oxide and propylene oxide are preferably used from the viewpoint of high polymerization reactivity with carbon dioxide.
- each above-mentioned epoxide may be used individually, respectively, and can also be used in combination of 2 or more type.
- the number average molecular weight of the above-mentioned aliphatic polycarbonate is preferably from 5,000 to 1,000,000, more preferably from 10,000 to 500,000.
- the number average molecular weight of the aliphatic polycarbonate is less than 5000, the effect as a binder is not sufficient, and cracks may be generated in the oxide semiconductor layer, or the adhesion between the substrate and the oxide semiconductor layer may be reduced.
- the number average molecular weight of an aliphatic polycarbonate exceeds 1000000, since the solubility to the organic solvent of an aliphatic polycarbonate falls, handling may become difficult.
- the numerical value of the above-mentioned number average molecular weight is the value measured by the method shown in the below-mentioned Example.
- the amount of the metal catalyst used for the polymerization reaction is preferably 0.001 to 20 parts by mass, more preferably 0.01 to 10 parts by mass with respect to 100 parts by mass of the epoxide. .
- the usage-amount of a metal catalyst is less than 0.001 mass part, there exists a possibility that a polymerization reaction may become difficult to advance.
- the usage-amount of a metal catalyst exceeds 20 mass parts, there exists a possibility that there may be no effect corresponding to a usage-amount and it may become economical.
- the reaction solvent used as needed in the above polymerization reaction is not particularly limited.
- Various organic solvents can be applied as the reaction solvent.
- this organic solvent are: Aliphatic hydrocarbon solvents such as pentane, hexane, octane, decane and cyclohexane; Aromatic hydrocarbon solvents such as benzene, toluene, xylene; Chloromethane, methylene dichloride, chloroform, carbon tetrachloride, 1,1-dichloroethane, 1,2-dichloroethane, ethyl chloride, trichloroethane, 1-chloropropane, 2-chloropropane, 1-chlorobutane, 2-chlorobutane, 1-chloro-2 -Halogenated hydrocarbon solvents such as methylpropane, chlorobenzene, bromobenzene; And carbonate solvents such as dimethyl carbonate, diethyl carbonate,
- the amount of the reaction solvent used is preferably 500 parts by mass or more and 10000 parts by mass or less with respect to 100 parts by mass of the epoxide from the viewpoint of facilitating the reaction.
- the method of reacting epoxide and carbon dioxide in the presence of a metal catalyst is not particularly limited.
- a method may be employed in which the above epoxide, metal catalyst, and reaction solvent as required are charged into an autoclave and mixed, and then carbon dioxide is injected to react.
- the polymerization reaction temperature in the above polymerization reaction is not particularly limited. Typically, the temperature is preferably 30 to 100 ° C, more preferably 40 to 80 ° C. When the polymerization reaction temperature is less than 30 ° C., the polymerization reaction may take a long time. On the other hand, when the polymerization reaction temperature exceeds 100 ° C., side reactions occur and the yield may decrease. Although the polymerization reaction time varies depending on the polymerization reaction temperature, it cannot be generally stated, but it is typically preferably 2 to 40 hours.
- an aliphatic polycarbonate can be obtained by filtering off by filtration or the like, washing with a solvent if necessary, and drying.
- the channel 44 it is possible to control the final thickness of the channel 44 by changing the weight ratio of the metal compound that becomes an oxide semiconductor when oxidized and the binder. This has been confirmed by the inventors' research. For example, it has been found that a channel 44 having a thickness of 10 nm to 50 nm, which is a very thin layer, can be formed without generating cracks. It should be noted that not only the aforementioned thin layer but also a layer having a thickness of 50 nm or more can be formed relatively easily by appropriately adjusting the thickness of the channel precursor layer 42, the aforementioned weight ratio, and the like. .
- the oxide semiconductor precursor of the present embodiment is employed, even if an oxide semiconductor precursor layer having a considerably thick film (for example, 10 ⁇ m or more) is initially formed, a binder or the like may be formed by a subsequent baking step. Is decomposed with high accuracy, the thickness of the layer after firing can be very thin (eg, 10 nm to 100 nm). Furthermore, it is worthy of special mention that even such a thin layer will not cause cracks or be suppressed with high accuracy. Therefore, the oxide semiconductor precursor and the oxide semiconductor layer of this embodiment, which can sufficiently secure the initial thickness and can finally form an extremely thin layer, are described in a low-energy manufacturing process or described later. It was found that it is very suitable for the process by stamping. In addition, the use of an oxide semiconductor layer in which even such an extremely thin layer does not generate cracks or is suppressed with high accuracy greatly enhances the stability of the thin film transistor 100 of this embodiment.
- a binder or the like may be formed by a subsequent baking step. Is decomposed with high accuracy,
- the electrical characteristics and stability of the oxide semiconductor layer forming the channel can be improved by appropriately adjusting the type and combination of the above-described metal compounds and the mixing ratio with the binder. it can.
- Source Electrode and Drain Electrode Further, as shown in FIG. 6, after a resist film 90 patterned by a known photolithography method is formed on the channel 44, the channel 44 and the resist film 90 are formed. Then, the ITO layer 50 is formed by a known sputtering method.
- the target material of the present embodiment is, for example, ITO containing 5 wt% tin oxide (SnO 2 ), and is formed under conditions of room temperature to 100 ° C. Thereafter, when the resist film 90 is removed, the drain electrode 56 and the source electrode 58 made of the ITO layer 50 are formed on the channel 44 as shown in FIG.
- Example> Specific examples using examples of a semiconductor element (a thin film transistor in this embodiment) including an oxide semiconductor layer, together with manufacturing examples, examples, and comparative examples of oxide semiconductor precursors and oxide semiconductor layers
- the embodiments described above are not limited to these examples.
- the obtained polypropylene carbonate could be identified from the following physical properties. IR (KBr) absorption peak: 1742, 1456, 1381, 1229, 1069, 787 (both units are cm -1 ) Moreover, the number average molecular weight of the obtained polypropylene carbonate was 52,000.
- the polypropylene carbonate obtained in Production Example 2 was dissolved in diethylene glycol monoethyl ether acetate to obtain 10 g of a polypropylene carbonate solution (6.25 wt%).
- the above-described indium-zinc-containing solution was gradually added to the polypropylene carbonate solution to obtain an oxide semiconductor precursor having a weight ratio of 10: 2.
- a gate insulating layer precursor layer 32 starting from a gate insulating layer precursor solution containing polysilazane as a solute is formed on the gate electrode 20 by a known spin coating method. Thereafter, the gate insulating layer precursor layer 32 is heated in the atmosphere as in the first embodiment, whereby the gate insulating layer 34 that is a silicon oxide layer is formed on the gate electrode 20.
- the gate insulating layer 34 had a thickness of about 109 nm.
- the gate insulating layer 34 Thereafter, three types of (a) to (c) shown in Production Example 3 and modifications thereof are printed on the gate insulating layer 34 by printing methods (specifically, screen printing, letterpress reverse printing, imprinting method, etc.). A precursor layer of the oxide semiconductor is formed.
- the first preliminary firing step, the second preliminary firing step, and the firing step (main firing) are all the same as in the first embodiment.
- the channel 44 has a thickness of about 20 nm.
- the precursor layers of the three types of oxide semiconductors (a) to (c) shown in Production Example 3 and modifications thereof are subjected to a firing step (main firing), Using the low-pressure mercury lamp shown in the modification of the first embodiment, Production Example 4 (three types (a) to (c)) irradiated with ultraviolet rays for 30 minutes was also produced.
- the oxide semiconductor precursor layer was heated to 500 ° C. in 0.3 minutes and heated, and further held at that temperature for 10 minutes. Then, the oxide semiconductor precursor layer was air-cooled to 25 ° C. to obtain an oxide semiconductor layer.
- FIG. 10 is a graph showing changes in the thickness of the oxide semiconductor layer.
- FIG. 11 is an optical micrograph of the surface of the oxide semiconductor layer in Production Example (3) described above.
- FIG. 12 is an optical micrograph of the surface of the oxide semiconductor layer in Comparative Example (1) described above.
- thermogravimetry in FIG. 13, a significant decrease in weight, which is considered to be evaporation of the solvent, was observed near 120 ° C. Further, as shown in (X) of FIG. 13, an exothermic peak in the differential thermal measurement graph of the InZn solution was confirmed at around 330 ° C. Therefore, it is confirmed that indium and zinc are bonded to oxygen at around 330 ° C. Therefore, this 330 ° C. corresponds to the second temperature in the first embodiment.
- FIG. 16 is a diagram of a thin film transistor of an example corresponding to the first embodiment (Production Example 3 and (b) in a modification of Production Example 3). It is a graph which shows the Vg-Id characteristic of a channel. Further, the measurement of this characteristic and the measurement of the Vg-Id characteristic shown in FIG. 17 to be described later were performed using a simple Vg-Id characteristic measurement system shown in FIG. Note that Vg in FIG. 15 is a terminal for applying a voltage corresponding to the gate voltage, and Vd and Vs are terminals for detecting a current value as electrodes corresponding to the drain electrode and the source electrode, respectively.
- the characteristics indicating that the channel of the thin film transistor employing the oxide semiconductor layer of this example (Production Example 3) is a semiconductor were confirmed. Therefore, it was confirmed that the thin film transistor employing the oxide semiconductor layer of this example (Production Example 3) also has good electrical characteristics as a transistor.
- the examples of the mixing ratio other than (b) in the manufacturing example 3 and the modified example of the manufacturing example 3, that is, (a) and (c) switching characteristics as a thin film transistor could not be confirmed at present.
- FIG. 17 shows three examples corresponding to the modification of the first embodiment ((a) to (a) in Manufacturing Example 4).
- FIG. 17C is a graph showing the Vg-Id characteristic corresponding to FIG.
- the channel of the thin film transistor employing the three types of oxide semiconductor layers of this example is a semiconductor. Therefore, by performing an irradiation step of irradiating ultraviolet rays after the baking step (main baking), at least in the range shown in Production Example 3, it is not dependent on the weight ratio of the polypropylene carbonate (PPC) and the InZn solution and is good. It was confirmed that electrical characteristics can be obtained. This is because the oxide semiconductor layer after the firing step is irradiated with ultraviolet rays, thereby further promoting the decomposition or evaporation of impurities considered to be trace amounts represented by carbon impurities in the oxide semiconductor layer. This is probably because the impurities can be further reduced or the impurities can be eliminated.
- FIGS. 18 to 21 are schematic cross-sectional views illustrating one process of the manufacturing method of the thin film transistor 200.
- FIG. FIG. 22 is a schematic cross-sectional view showing one process and the entire configuration of the method of manufacturing the thin film transistor 200 in the present embodiment.
- the description of the patterning of the extraction electrode from each electrode is omitted.
- the description which overlaps with 1st Embodiment is abbreviate
- the gate electrode 20 is formed on the substrate 10 by a known sputtering method, photolithography method, and etching method. Note that the material of the gate electrode 20 of the present embodiment is platinum (Pt).
- a precursor solution for a gate insulating layer containing polysilazane as a solute by a low energy manufacturing process is formed on the substrate 10 and the gate electrode 20, as in the first embodiment.
- preliminary firing is performed by heating to 80 ° C. or more and less than 250 ° C. in the air (including water vapor).
- plasma is irradiated under atmospheric pressure to etch the entire channel precursor layer 42.
- a power of 500 W is applied.
- the channel precursor layer 42 is etched by the plasma formed under the applied conditions.
- the channel precursor layer 42 in the region where the pattern is not formed is removed, while the channel precursor layer 42 in the region where the pattern is formed leaves a certain thickness or more. Patterning becomes possible.
- a firing step main firing
- a channel 44 is formed as shown in FIG.
- performing the above-described plasma etching under the atmospheric pressure after the second pre-baking step removes the remaining film (unnecessary portion) of the channel precursor layer 42 that has been embossed.
- This is a preferred embodiment from the viewpoint of high accuracy and easy realization.
- the final thinning of the channel 44 (for example, about 10 nm to 30 nm) is realized with higher accuracy.
- a process of etching the channel precursor layer 42 as a whole is also performed.
- the stamping process is performed on the precursor layer having a high plastic deformation ability.
- the pressure applied when performing the die pressing process is a low pressure of 0.1 MPa or more and 20 MPa or less
- each precursor layer comes to deform following the surface shape of the die, and the desired die
- the push structure can be formed with high accuracy.
- the pressure in a low pressure range of 1 MPa or more and 20 MPa or less the mold becomes difficult to be damaged when performing the stamping process, and it is advantageous for increasing the area.
- the reason why the pressure is within the range of “0.1 MPa to 20 MPa” is as follows. First, if the pressure is less than 0.1 MPa, the pressure may be too low to emboss each precursor layer. When polypropylene carbonate is used as the binder, since the polypropylene carbonate is a relatively soft material, even if the pressure is about 0.1 MPa, the stamping process can be performed. On the other hand, if the pressure is 20 MPa, the precursor layer can be sufficiently embossed, so that it is not necessary to apply more pressure. From the viewpoint described above, it is more preferable that the embossing process is performed at a pressure within the range of 0.5 MPa or more and 10 MPa or less in the embossing process in the second embodiment.
- a mold release process is performed on the surface of each precursor layer to which the mold pressing surface comes into contact and / or a mold release process is performed on the mold pressing surface of the mold in advance. Then, it is preferable to perform an embossing process on each precursor layer. By performing such treatment, it is possible to reduce the frictional force between each precursor layer and the mold, and therefore it is possible to perform the stamping process with higher accuracy on each precursor layer.
- the release agent that can be used for the release treatment include surfactants (for example, fluorine surfactants, silicon surfactants, nonionic surfactants, etc.), fluorine-containing diamond-like carbon, and the like. can do.
- each of the above-described embodiments is not limited to the structure.
- a thin film transistor having a staggered structure but also a thin film transistor having a so-called planar structure in which a source electrode, a drain electrode, and a channel are arranged on the same plane can achieve the effects of the above-described embodiments. The same effect can be achieved.
- the channel (that is, the oxide semiconductor layer) of each of the above embodiments is formed over a substrate.
- the number of peaks indicated by (X) indicating the second temperature is one, but there is one exothermic peak in the differential heat measurement graph. Not necessarily. If the solute contained in the solution constituting the oxide semiconductor precursor of each of the above-described embodiments, that is, the material of the precursor is different, two or more exothermic peaks in the differential thermal measurement graph can be formed. However, in this case, since the second temperature must be higher than at least the first temperature, it is preferable to set the temperature indicated by the lower temperature side peak among the plurality of exothermic peaks as the second temperature.
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Abstract
Description
20 ゲート電極
32 ゲート絶縁層用前駆体層
34 ゲート絶縁層
42 チャネル用前駆体層
44 チャネル
50 ITO層
56 ドレイン電極
58 ソース電極
90 レジスト膜
100,200 薄膜トランジスタ
M1 チャネル用型
1.本実施形態の薄膜トランジスタの全体構成
図1乃至図8は、それぞれ、半導体素子の一例である薄膜トランジスタ100の製造方法の一過程を示す断面模式図である。また、図9は、本実施形態における薄膜トランジスタ100の製造方法の一過程及び全体構成を示す断面模式図である。図9に示すように、本実施形態における薄膜トランジスタ100においては、基板10上に、下層から、ゲート電極20、ゲート絶縁層34、チャネル44、ソース電極58及びドレイン電極56の順序で積層されている。なお、この半導体素子を備える電子デバイス(例えば、携帯端末や情報家電、あるいはその他の公知の電化製品)の提供ないし実現は、本実施形態の半導体素子を理解する当業者であれば特に説明を要せず十分に理解され得る。
ゲート電極20の材料には、例えば、白金、金、銀、銅、アルミ、モリブデン、パラジウム、ルテニウム、イリジウム、タングステン、などの高融点金属、又はその合金等の金属材料、ルテニウム酸化物を含む導電性の金属酸化物、あるいはp+-シリコン層やn+-シリコン層が適用できる。本実施形態では、図1に示すように、ゲート電極20が、公知のスパッタリング法やCVD法により基材であるSiO2/Si基板(以下、単に「基板」ともいう)10上に形成される。
また、本実施形態における薄膜トランジスタ100においては、ゲート絶縁層34が、シリコン(Si)を含む前駆体(例えば、ポリシラザン(polysilazane))を溶質とするゲート絶縁層用前駆体溶液を出発材とするシリコン酸化物(但し、不可避不純物を含み得る。以下、この材料の酸化物に限らず他の材料の酸化物についても同じ。)である。
本実施形態のチャネル44は、酸化されたときに酸化物半導体となる金属の化合物(「金属化合物」ともいう)を脂肪族ポリカーボネートからなるバインダー(不可避不純物を含み得る。以下、同じ)を含む溶液中に分散させた酸化物半導体の前駆体の層(以下、「酸化物半導体の前駆体層」又は「前駆体層」ともいう)を焼成することによって形成される。
グリセリン、ソルビタン等の多価アルコールエステル;
ジエチレングリコール、トリエチレングリコール、ジプロピレングリコール、トリプロピレングリコール、ポリエチレングリコール、ポリプロピレングリコール等のポリエーテルポリオール;ポリエチレンイミン等のアミン;
ポリアクリル酸、ポリメタクリル酸等の(メタ)アクリル樹脂;
イソブチレンまたはスチレンと無水マレイン酸との共重合体、及びそのアミン塩など
である。
酢酸亜鉛、ジエチル亜鉛、ジブチル亜鉛等の有機亜鉛触媒;あるいは、
一級アミン、2価のフェノール、2価の芳香族カルボン酸、芳香族ヒドロキシ酸、脂肪族ジカルボン酸、脂肪族モノカルボン酸等の化合物と亜鉛化合物とを反応させることにより得られる有機亜鉛触媒など
である。
これらの有機亜鉛触媒の中でも、より高い重合活性を有することから、亜鉛化合物と、脂肪族ジカルボン酸と、脂肪族モノカルボン酸とを反応させて得られる有機亜鉛触媒を採用することは好適な一態様である。
ペンタン、ヘキサン、オクタン、デカン、シクロヘキサン等の脂肪族炭化水素系溶媒;
ベンゼン、トルエン、キシレン等の芳香族炭化水素系溶媒;
クロロメタン、メチレンジクロリド、クロロホルム、四塩化炭素、1,1-ジクロロエタン、1,2-ジクロロエタン、エチルクロリド、トリクロロエタン、1-クロロプロパン、2-クロロプロパン、1-クロロブタン、2-クロロブタン、1-クロロ-2-メチルプロパン、クロルベンゼン、ブロモベンゼン等のハロゲン化炭化水素系溶媒;
ジメチルカーボネート、ジエチルカーボネート、プロピレンカーボネート等のカーボネート系溶媒など
である。
さらにその後、図6に示すように、チャネル44上に、公知のフォトリソグラフィー法によってパターニングされたレジスト膜90が形成された後、チャネル44及びレジスト膜90上に、公知のスパッタリング法により、ITO層50を形成する。本実施形態のターゲット材は、例えば、5wt%酸化錫(SnO2)を含有するITOであり、室温~100℃の条件下において形成される。その後、レジスト膜90が除去されると、図7に示すように、チャネル44上に、ITO層50によるドレイン電極56及びソース電極58が形成される。
本実施形態の薄膜トランジスタは、第1の実施形態におけるチャネルの焼成工程(本焼成)後に、さらに紫外線を照射する照射工程が行われている点を除き、第1の実施形態の薄膜トランジスタ100の製造工程及び構成と同様である。従って、第1の実施形態と重複する説明は省略する。
以下に、酸化物半導体の前駆体及び酸化物半導体層の製造例、実施例、及び比較例とともに、酸化物半導体層を備えた半導体素子(本実施例では薄膜トランジスタ)の実施例を用いて具体例を説明するが、上述の各実施形態はこれら実施例に限定されるものではない。
攪拌機、窒素ガス導入管、温度計、還流冷却管を備えた300mL容の四つ口フラスコに、酸化亜鉛8.1g(100ミリモル)、グルタル酸12.7g(96ミリモル)、酢酸0.1g(2ミリモル)、及びトルエン130g(150mL)を仕込んだ。次に、反応系内を窒素雰囲気に置換した後、そのフラスコを55℃まで昇温し、同温度で4時間攪拌することにより、前述の各材料の反応処理を行った。その後、110℃まで昇温し、さらに同温度で4時間攪拌して共沸脱水させ、水分のみを除去した。その後、そのフラスコを室温まで冷却することにより、有機亜鉛触媒を含む反応液を得た。
攪拌機、ガス導入管、温度計を備えた1L容のオートクレーブの系内をあらかじめ窒素雰囲気に置換した後、製造例1と同様の方法により得られた有機亜鉛触媒を含む反応液8.0mL(有機亜鉛触媒を1.0g含む)、ヘキサン131g(200mL)、及びプロピレンオキシド46.5g(0.80モル)を仕込んだ。次に、攪拌しながら二酸化炭素を加えることによって反応系内を二酸化炭素雰囲気に置換し、反応系内が1.5MPaとなるまで二酸化炭素を充填した。その後、そのオートクレーブを60℃に昇温し、反応により消費される二酸化炭素を補給しながら6時間重合反応を行った。
IR(KBr)の吸収ピーク:1742,1456,1381,1229,1069,787(いずれも単位はcm-1)
また、得られたポリプロピレンカーボネートの数平均分子量は、52000であった。
50mL容のナス型フラスコに、インジウムアセチルアセトナート2.06g及びプロピオン酸7.94gを仕込むことにより、10gの第1溶液を得た(0.5mol/kg)。同様にして、50mL容のナス型フラスコに、塩化亜鉛0.68g及び2-メトキシエタノールを仕込むことにより、10gの第2溶液を得た(0.5mol/kg)。その後、第1溶液と第2溶液を、撹拌しながら徐々に混合することにより、最終的にインジウム-亜鉛酸化物となる、インジウム-亜鉛含有溶液を得た。
次に、そのポリプロピレンカーボネートの溶液中に、上述のインジウム-亜鉛含有溶液を徐々に加え、重量比10:2の酸化物半導体の前駆体を得た。
なお、酸化物半導体の前駆体層(第1の実施形態におけるチャネル用前駆体層42)におけるポリプロピレンカーボネート(PPC)とインジウム-亜鉛含有溶液(本願では、「InZn溶液」ともいう)との重量比を異ならせた変形例を製造した。
具体的には、上記の製造例3の例と併せて、以下の(a)~(c)に示す3種類の重量比を製造した。
(a)PPC:InZnO=10:1.5
(b)PPC:InZnO=10:2
(c)PPC:InZnO=10:1
製造例3において、ポリプロピレンカーボネートを用いなかったことを除き、製造例3と同様に処理することにより、比較用の酸化物半導体の前駆体を得た。
本製造例においては、まず、基板10の上にゲート電極20として、p+-シリコン層を形成した。p+-シリコン層は、公知のCVD法により形成された。本製造例では、基板10は、SiO2/Si基板であり、SiO2上に約10nm厚のTiOX膜(図示しない)を備えている。なお、基板10がp+-シリコン基板である場合は、この基板10がゲート電極の役割を果たし得る。
上述の各製造例により得られた脂肪族ポリカーボネートの数平均分子量、並びに、製造例及び比較例により得られたバインダー及び酸化物半導体の前駆体層の厚みおよび特性を以下の方法により測定し、評価した。
上述の脂肪族ポリカーボネート(製造例2におけるポリプロピレンカーボネート)濃度が0.5質量%のクロロホルム溶液を調製し、高速液体クロマトグラフを用いて測定した。測定後、同一条件で測定した数平均分子量が既知のポリスチレンと比較することにより、分子量を算出した。また、測定条件は、以下の通りである。
機種:HLC-8020
カラム:GPCカラム
(東ソー株式会社の商品名:TSK GEL Multipore HXL-M)
カラム温度:40℃
溶出液:クロロホルム
流速:1mL/分
一例として、母材となる基板である熱酸化膜付きシリコン基板(幅:20mm、長さ:20mm、厚み:0.7mm)に対して、アセトンを用いて表面を洗浄した。その後、UV処理装置(SAMCO社製)を用いて、その熱酸化膜付きシリコン基板の表面処理を行い、試験用基板を作製した。
上述の(a)~(c)に示す3種類について、上記処理によって得られた酸化物半導体層の厚みの変化を、エリプソメトリ法を用いて測定した。図10は、酸化物半導体層の厚みの変化の示すグラフである。
酸化物半導体層の表面を、光学顕微鏡を用いて観察することにより、クラックの有無が調べられた。ここで、クラックが視認されないものを「丸印(良好)」と評価し、クラックが顕著に認められるものを「NG」と評価した。評価結果を、以下の表1並びに図11及び図12に示す。なお、図11は、上述の製造例(3)における酸化物半導体層の表面の光学顕微鏡写真である。また、図12は、上述の比較例(1)における酸化物半導体層の表面の光学顕微鏡写真である。
また、図13は、本実施例における薄膜トランジスタのチャネルを形成するための酸化物半導体の前駆体を構成するインジウム-亜鉛含有溶液(製造例3のInZn溶液)のTG-DTA特性を示すグラフである。また、図14は、本実施例(製造例3)における薄膜トランジスタのチャネル部を形成するためのバインダー溶液(製造例3におけるポリプロピレンカーボネート溶液)のTG-DTA特性を示すグラフである。なお、図13及び図14に示すように、各図中の実線は、熱重量(TG)測定結果であり、図中の点線は示差熱(DTA)測定結果である。
上述の各製造例により得られた酸化物半導体の前駆体層をチャネルに採用した薄膜トランジスタの特性が調べられた。
図16は、第1の実施形態に相当する実施例(製造例3及び製造例3の変形例における(b))の薄膜トランジスタのチャネルのVg-Id特性を示すグラフである。また、この特性の測定及び後述する図17に示すVg-Id特性の測定は、図15に示す簡易的なVg-Id特性測定システムを用いて行われた。なお、図15におけるVgはゲート電圧に相当する電圧を印加する端子であり、Vd及びVsはそれぞれドレイン電極及びソース電極に相当する電極として、電流値を検出するための端子である。
また、図17は、第1の実施形態の変形例に相当する3つの実施例(製造例4における(a)~(c))の、図16に相当するVg-Id特性を示すグラフである。
1.薄膜トランジスタ200の製造方法
図18乃至図21は、それぞれ、薄膜トランジスタ200の製造方法の一過程を示す断面模式図である。また、図22は、本実施形態における薄膜トランジスタ200の製造方法の一過程及び全体構成を示す断面模式図である。なお、図面を簡略化するため、各電極からの引き出し電極のパターニングについての記載は省略する。また、第1の実施形態と重複する説明は省略する。
まず、図18に示すように、ゲート電極20が、公知のスパッタリング法、フォトリソグラフィー法、及びエッチング法により基板10上に形成される。なお、本実施形態のゲート電極20の材料は、白金(Pt)である。
次に、基板10及びゲート電極20上に、第1の実施形態と同様に、低エネルギー製造プロセスにより、ポリシラザン(polysilazane)を溶質とするゲート絶縁層用前駆体溶液を出発材とするゲート絶縁層用前駆体層を形成した後、大気中(水蒸気を含む)で、80℃以上250℃未満に加熱することにより、予備焼成が行われる。
第1の実施形態における第2予備焼成工程を行ったチャネル用前駆体層42に対して、型押し加工を施す。まず、ゲート絶縁層34及び基板10上に、第1の実施形態と同様にチャネル用前駆体層42を形成する。その後、第1の実施形態と同様に第1予備焼成工程及び第2予備焼成工程を行う。
次に、第1の実施形態と同様、チャネル44上に、公知のフォトリソグラフィー法によってパターニングされたレジスト膜が形成された後、チャネル44及びレジスト膜上に、公知のスパッタリング法により、ITO層を形成する。その後、レジスト膜が除去されると、図22に示すように、チャネル44上に、ITO層によるドレイン電極56及びソース電極58が形成される。
上述の第2の実施形態における型押し工程において、予め、型押し面が接触することになる各前駆体層の表面に対する離型処理及び/又はその型の型押し面に対する離型処理を施しておき、その後、各前駆体層に対して型押し加工を施すことが好ましい。そのような処理を施すことにより、各前駆体層と型との間の摩擦力を低減することができるため、各前駆体層に対してより一層精度良く型押し加工を施すことが可能となる。なお、離型処理に用いることができる離型剤としては、界面活性剤(例えば、フッ素系界面活性剤、シリコン系界面活性剤、ノニオン系界面活性剤等)、フッ素含有ダイヤモンドライクカーボン等を例示することができる。
Claims (16)
- 酸化されたときに酸化物半導体となる金属の化合物を脂肪族ポリカーボネートからなるバインダー(不可避不純物を含み得る)を含む溶液中に分散させた酸化物半導体の前駆体を、基板上又はその上方に層状に形成する前駆体層の形成工程と、
前記前駆体層を、前記バインダーを90wt%以上分解させる第1温度によって加熱した後、前記第1温度よりも高く、かつ前記金属と酸素とが結合する温度であって、前記前駆体の示差熱分析法(DTA)における発熱ピーク値である第2温度以上の温度によって前記前駆体層を焼成する焼成工程と、を含む、
酸化物半導体層の製造方法。 - 前記第2温度が、前記第1温度よりも10℃以上高い、
請求項1に記載の酸化物半導体層の製造方法。 - 前記第2温度が、前記第1温度よりも50℃以上高い、
請求項1に記載の酸化物半導体層の製造方法。 - 前記焼成工程の後、さらに紫外線を照射する照射工程を含む、
請求項1乃至請求項3のいずれか1項に記載の酸化物半導体層の製造方法。 - 前記脂肪族ポリカーボネートが、エポキシドと二酸化炭素とを重合させた脂肪族ポリカーボネートである、
請求項1乃至請求項3のいずれか1項に記載の酸化物半導体層の製造方法。 - 前記脂肪族ポリカーボネートが、ポリエチレンカーボネート、及びポリプロピレンカーボネートからなる群より選ばれる少なくとも1種である、
請求項1乃至請求項3のいずれか1項に記載の酸化物半導体層の製造方法。 - 酸化されたときに酸化物半導体となる金属の化合物を脂肪族ポリカーボネートからなるバインダー(不可避不純物を含み得る)を含む溶液中に分散させた酸化物半導体の前駆体であって、かつ、
前記金属と酸素とが結合する温度であって、前記前駆体の示差熱分析法(DTA)における発熱ピーク値である第2温度よりも低い第1温度によって前記バインダーが90wt%以上分解される、
酸化物半導体の前駆体。 - 前記第2温度が、前記第1温度よりも10℃以上高い、
請求項7に記載の酸化物半導体の前駆体。 - 前記第2温度が、前記第1温度よりも50℃以上高い、
請求項7に記載の酸化物半導体の前駆体。 - 前記脂肪族ポリカーボネートが、エポキシドと二酸化炭素とを重合させた脂肪族ポリカーボネートである、
請求項7乃至請求項9のいずれか1項に記載の酸化物半導体の前駆体。 - 前記脂肪族ポリカーボネートが、ポリエチレンカーボネート、及びポリプロピレンカーボネートからなる群より選ばれる少なくとも1種である、
請求項7乃至請求項9のいずれか1項に記載の酸化物半導体の前駆体。 - 酸化されたときに酸化物半導体となる金属の化合物を脂肪族ポリカーボネートからなるバインダー(不可避不純物を含み得る)を含む溶液中に分散させた酸化物半導体の前駆体の層を、前記金属と酸素とが結合する温度であって、前記前駆体の示差熱分析法(DTA)における発熱ピーク値である第2温度以上で焼成することにより形成され、かつ、前記第2温度よりも低い第1温度によって前記バインダーが90wt%以上分解される、
酸化物半導体層。 - 前記第2温度が、前記第1温度よりも10℃以上高い、
請求項12に記載の酸化物半導体層。 - 前記第2温度が、前記第1温度よりも50℃以上高い、
請求項12に記載の酸化物半導体層。 - 請求項12乃至請求項14のいずれか1項に記載の酸化物半導体層を備えた、
半導体素子。 - 請求項15に記載の半導体素子を備えた、
電子デバイス。
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KR20190094099A (ko) | 2018-02-02 | 2019-08-12 | 스미토모 세이카 가부시키가이샤 | 폴리프로필렌 카보네이트 함유층 및 그 제조방법, 및 폴리프로필렌 카보네이트 함유층을 구비하는 기재 |
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JP5749411B1 (ja) * | 2013-08-09 | 2015-07-15 | 国立大学法人北陸先端科学技術大学院大学 | 酸化物半導体層及びその製造方法、並びに酸化物半導体の前駆体、酸化物半導体層、半導体素子、及び電子デバイス |
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JP7238847B2 (ja) * | 2020-04-16 | 2023-03-14 | トヨタ自動車株式会社 | 半導体素子の製造方法 |
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JPWO2015019771A1 (ja) | 2017-03-02 |
KR20160041947A (ko) | 2016-04-18 |
TW201813109A (zh) | 2018-04-01 |
CN105474372B (zh) | 2018-08-03 |
US20170117393A1 (en) | 2017-04-27 |
KR102147816B1 (ko) | 2020-08-25 |
EP3032576A1 (en) | 2016-06-15 |
TWI639240B (zh) | 2018-10-21 |
US9552985B2 (en) | 2017-01-24 |
JP5749411B1 (ja) | 2015-07-15 |
TW201511291A (zh) | 2015-03-16 |
CA2920490C (en) | 2021-04-20 |
US9842916B2 (en) | 2017-12-12 |
CA2920490A1 (en) | 2015-02-12 |
TWI614902B (zh) | 2018-02-11 |
CN105474372A (zh) | 2016-04-06 |
EP3032576A4 (en) | 2017-03-15 |
US20160181098A1 (en) | 2016-06-23 |
CN108878267A (zh) | 2018-11-23 |
SG11201600622WA (en) | 2016-02-26 |
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