WO2015010431A1 - 一种阵列基板及其制作方法、显示装置 - Google Patents
一种阵列基板及其制作方法、显示装置 Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Definitions
- a Thin-Film Transistor Liquid Crystal Display includes a color filter substrate, an array substrate, and a liquid crystal layer between the color filter substrate and the array substrate.
- the array substrate includes a transparent substrate, and a plurality of mutually parallel gate lines located inside the transparent substrate and a plurality of data lines vertically intersecting and electrically insulated from the gate lines, wherein the plurality of gate lines and the plurality of lines The data line defines a plurality of pixel units.
- Each of the pixel units includes a pixel electrode, a storage capacitor (Cs), a liquid crystal capacitor (Clc), and a thin film transistor (TFT) as a switching device.
- Cs and Ck are connected in parallel to the pixel electrode, and the pixel electrode is connected to the TFT.
- the TFT 10 of the pixel unit includes a source 11 , a gate 12 , and a drain 13 .
- the source 11 is electrically connected to the pixel electrode 20 , and the gate 12 and the gate line 30 .
- the drain 13 is connected to the data line 40, the gate line 30 and the gate 12 are located in the first metal layer, the data line 40, the drain 13 and the source 11 are located in the second metal layer, and the source is II overlaps the gate 12.
- the source overlaps the gate, thereby forming a parasitic capacitance (Cgs) between the source and the gate, wherein the size of Cgs is related to the overlap area of the source and the gate.
- Cgs parasitic capacitance
- a voltage jump variable Cgs_Cs + Ck - on the pixel electrode wherein A Vg is the difference between the turn-on voltage and the turn-off voltage applied on the gate.
- a misalignment occurs, which causes a change in the overlap area between the source and the gate of the pixel unit. If the amount of misalignment between the first metal layer and the second metal layer of the adjacent pixel unit is different, the amount of change in the overlapping area between the source and the gate of the adjacent pixel unit is different, thereby causing adjacent pixels.
- the amount of change in the parasitic capacitance Cgs of the cell is different, and the parasitic capacitance Cgs of the adjacent pixel unit is different after the misalignment occurs between the first metal layer and the second metal layer (the parasitic capacitance Cgs of the adjacent pixel unit is in the first metal)
- the layer is identical to the second metal layer before the misalignment occurs. If the parasitic capacitance Cgs of the adjacent pixel units are different, the voltage jump variables on the pixel electrodes of the adjacent pixel units are different, so that the gray scales of the adjacent pixels are not uniform, thereby causing poor picture quality, for example, Flicker appears. ) and Mura (uneven grayscale of the screen).
- the current TFT CD has a problem of poor picture quality when the amount of misalignment between the first metal layer and the second metal layer of the adjacent pixel unit is different.
- the embodiment of the present invention provides an array substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that the amount of misalignment between the first metal layer and the second metal layer of the adjacent pixel unit is different when the TFTXCD existing in the prior art is different. There will be problems with poor picture quality.
- an array substrate including a thin film transistor TFT, the TFT includes a source, a gate, and a drain, the gate is located at a first metal layer, the source and The drain is located in the second metal layer, wherein
- the shape of the source and the gate are satisfied: in a case where a misalignment occurs between the first metal layer and the second metal layer, an overlapping area of the source and the gate is constant.
- the overlapping area of the source and the gate of the pixel unit is constant, and thus each The overlapping area of the source and the gate of each pixel unit is the same (the amount of change is 0), thereby ensuring the source of the adjacent pixel unit after the misalignment occurs between the first metal layer and the second metal layer.
- the overlap area of the gate and the gate are the same, and the parasitic capacitance Cgs of the adjacent pixel unit is the same, thereby achieving a certain degree of uniformity of the gray level of the adjacent pixels, and avoiding or reducing the problem of poor picture quality.
- the source includes an overlapping region with the gate and a direction parallel to the gate line a first partial region and a second partial region respectively located on both sides of the gate;
- the increase/decrease bottom area of the first partial region is equal to the decrease/enhancement area of the second partial region.
- the source and the gate are ensured.
- the overlap area is constant.
- the pattern of the first partial region, the second partial region, and the overlapping region with the gate includes a U-shaped pattern in which the opening faces in a direction parallel to the gate line and a closure with the " ⁇ -shaped pattern" Connected to the horizontally placed " ⁇ "-shaped pattern;
- first partial region is located at a position where the one side of the "U” shape extends out of the gate, or at a position where the two sides of the "U” shape extend out of the gate
- second partial region is located at a position where the "L"-shaped pattern extends out of the gate.
- the pattern of the first partial region, the second partial region and the overlapping region with the gate is a pattern resembling a "shi" shape
- first partial region is located at a position where the first side and/or the second side of the "shi"-shaped pattern extends out of the gate in a first direction parallel to the gate line;
- the second partial region is located at a position where the first side and/or the second side of the "shi"-shaped pattern extends out of the gate in a second direction opposite to the first direction, the first side Parallel to the second side.
- the specific structure of the source included in the TFT is provided, so that the technical solution of the present invention can be easily implemented by those skilled in the art. It should be noted that the specific source structures in the embodiments of the present invention are only used to explain the present invention, and are not intended to limit the present invention. Other structures that can be used to implement the technical solutions of the present invention are also within the protection scope of the present invention. Inside.
- the array substrate further includes a data line connected to the drain, and a minimum distance value between the first partial area and the second partial area and the data line is not less than a set value, for example , 5 ⁇ - 10 ⁇ .
- the gate includes a first partial region and a second partial region separated from each other, the source includes a third partial region overlapping the first partial region and overlapping with the second partial region Part IV area;
- the increase/decrease bottom area of the third partial region is equal to the decrease/enhancement bottom area of the fourth partial region.
- the source and the gate are ensured.
- the overlap area of the poles is constant.
- the pattern of the source is a T-like pattern composed of the third partial region, the fourth partial region, and a region between the first partial region and the second partial region;
- the third partial region is located at a position where the inverted "T" shape overlaps the first partial region in a first direction parallel to the gate line, and the fourth partial region is located at the inverted "T"
- the glyph is at a position overlapping the second partial region in a second direction opposite to the first direction.
- a display device comprising the array substrate.
- the display device since the array substrate included in the display device can ensure the gray level of adjacent pixels to a certain extent, the display device can avoid or reduce the occurrence of poor picture quality to some extent.
- a method for fabricating the array substrate including:
- An active layer and a source and a drain on the active layer are sequentially formed on the gate insulating layer, wherein the source and the drain are located in the second metal layer; Wherein, in a case where a misalignment occurs between the first metal layer and the second metal layer, an overlapping area of the source and the gate is constant.
- the overlapping area of the source and the gate of the pixel unit is constant, and thus each pixel
- the amount of change in the overlap area between the source and the gate of the cell is the same (the amount of change is 0), which can ensure that the gray level of adjacent pixels is uniform to a certain extent, and the problem of poor picture quality is avoided or reduced.
- the solution of the embodiment of the present invention is such that when a misalignment occurs between the first metal layer and the second metal layer, even if the first metal layer and the second metal layer of the adjacent pixel unit
- the amount of misalignment generated is different, and the overlapping area of the gate and the source of the adjacent pixel unit can be the same, so that the parasitic capacitance Cgs of the adjacent pixel unit is the same, thereby ensuring the voltage jump variable on the pixel electrode of the adjacent pixel unit.
- the gray scale of adjacent pixels is uniform, and thus the problem of poor picture quality such as Flicker and Mura is avoided or reduced to some extent.
- FIG. 1 is a schematic structural view of a pixel unit in the prior art
- FIG. 2 is a schematic view showing a first structure of a pixel unit included in an array substrate according to an embodiment of the present invention
- FIG. 3 is a schematic view showing a second structure of a pixel unit included in an array substrate according to an embodiment of the present invention.
- FIG. 4 is a schematic view showing a third structure of a pixel unit included in the array substrate of the embodiment of the present invention.
- FIG. 5 is a fourth structural diagram of a pixel unit included in an array substrate according to an embodiment of the present invention.
- FIG. 6 is a fifth structural diagram of a pixel unit included in an array substrate according to an embodiment of the present invention.
- a sixth structural diagram of a pixel unit included in the array substrate of the embodiment of the present invention is shown.
- FIG. 8 is a schematic flow chart of a method for fabricating an array substrate according to the embodiment
- 9A-9H are structural diagrams of pixel units included in an array substrate during fabrication of an array substrate according to an embodiment of the invention.
- An array substrate includes a TFT, the TFT includes a source, a gate and a drain, the gate is located at the first metal layer, the source and the drain are located at the second metal layer, and the first metal layer and the first metal layer In the case where a misalignment occurs between the two metal layers, the overlap area of the source and the gate is constant.
- the overlapping area of the source and the gate of the adjacent pixel unit is the same before the misalignment occurs between the first metal layer and the second metal layer, after the misalignment occurs between the first metal layer and the second metal layer, The amount of change in the overlapping area of the source and the gate of the adjacent pixel unit is different, and the overlapping area of the source and the gate of the adjacent pixel unit after the misalignment between the first metal layer and the second metal layer is recognized different.
- the structure of the array substrate according to the embodiment of the present invention can ensure that the overlapping area of the source and the gate is constant in the case where a misalignment occurs between the first metal layer and the second metal layer, that is, according to the present invention
- the array substrate of the embodiment can ensure that after the dislocation between the first metal layer and the second metal layer, the overlapping area of the source and the gate of the adjacent pixel unit is the same, so that the first metal layer and the second layer After the misalignment between the metal layers, the overlapping areas of the source and the gate of the adjacent pixel unit are the same, thereby ensuring that the gray level of the adjacent pixels is uniform to a certain extent, and the problem of poor picture quality is avoided or reduced.
- An embodiment of the present invention provides an array substrate, including a TFT, the TFT includes a source, a gate, and a drain, the gate is located in the first metal layer, and the source and the drain are located in the second metal layer, where
- the shape of the source and the gate are satisfied: in the case where a misalignment occurs between the first metal layer and the second metal layer, the overlapping area of the source and the gate is constant.
- the array substrate includes a plurality of pixel units, each of the pixel units includes one TFT, and the implementation manner of the TFT in each pixel unit included in the array substrate provided by the embodiment of the present invention is described.
- the embodiment of the present invention will be described below by taking an embodiment of a pixel unit included in the array substrate of the embodiment of the present invention as an example.
- the pixel unit of the array substrate provided by the embodiment of the invention includes a TFT
- the TFT includes a source, a gate and a drain
- the gate is located in the first metal layer
- the source and the drain are located in the second metal layer. among them,
- the shape of the source and the gate are satisfied: in the case where a misalignment occurs between the first metal layer and the second metal layer, the overlapping area of the source and the gate is constant.
- the gate is the bottom gate as an example.
- the implementation of other types of gates eg., top gates, etc.
- the implementation of the bottom gate is similar and will not be described here.
- the amount of misalignment generated between the first metal layer and the second metal layer due to natural factors such as process instability is generally small, that is, within a preset misalignment amount ranging from ⁇ 2 ⁇ m to ⁇ 5 ⁇ m ⁇ .
- the lower limit value of the preset misalignment amount range may be 0, that is, no misalignment occurs between the first metal layer and the second metal layer.
- the source and/or the gate need to be improved.
- the source and/or the gate need to be improved. The following will be introduced separately.
- the overlap area of the source and the gate is constant when the source is misaligned between the first metal layer and the second metal layer.
- the source (or the lateral cross-sectional pattern of the source) includes an overlap region with the gate (or a lateral cross-sectional pattern of the gate) and a gate at a direction parallel to the gate line (or , a transverse cross-sectional pattern of the gate) a first partial region and a second partial region on both sides;
- the increased bottom area (or the reduced/increased area) of the first partial region and the reduced/increased bottom area of the second partial region is equal.
- the source and drain of the thin film transistor (TFT) of the array substrate (pixel unit) of the embodiment of the present invention are the same, and the names can be interchanged; the drain connected to the data line can be connected to the pixel electrode. As the source; vice versa.
- the array substrate (pixel unit) of the embodiment of the present invention further includes a gate line vertically connected to the gate, and a data line vertically connected to the drain, and a direction parallel to the gate line is a horizontal direction and a direction parallel to the data line. It is in the vertical direction.
- the direction parallel to the gate line 30 is water.
- the direction parallel to the data line 40 is a vertical direction.
- the bottom area (or area) of the first partial region on the side of the gate (or the lateral cross-sectional pattern of the gate) according to the embodiment of the present invention is opposite to the gate (or the lateral cross-sectional pattern of the gate) The misalignment occurs between the first metal layer and the second metal layer.
- the bottom portion area of the first partial region (opposite gate) on the gate side is A, between the first metal layer and the second metal layer.
- the bottom area of the first partial region (relative to the gate) on the side of the gate changes to B.
- the embodiment of the second partial region on the other side of the gate (or the lateral cross-sectional pattern of the gate) according to an embodiment of the present invention is similar to the embodiment of the first partial region according to the embodiment of the present invention, This will not be repeated here.
- the first partial region and the second partial region are regions respectively located on opposite sides of the gate in a direction parallel to the gate line, and a misalignment occurs between the first metal layer and the second metal layer.
- the increase/decrease bottom area of the first partial region is equal to the decrease/enhancement bottom area of the second partial region, thereby ensuring a constant area of the overlap region of the source and the gate, ensuring the source and the gate.
- the overlap area is constant.
- the area of the first portion region is increased (reduced), that is, the source and the gate
- the parasitic capacitance Cgs between them is reduced (increased), and accordingly, the area of the second partial region is reduced (increased), that is, the parasitic capacitance Cgs between the source and the gate is increased (reduced). Since the increase/decrease area of the first partial region can be compensated by the reduced/increased area of the second partial region, the total parasitic capacitance Cgs between the source and the gate is ensured to be constant, avoiding the occurrence of Flkker and Miira.
- the second metal layer is misaligned (ie, dislocated in the vertical direction) with respect to the first metal layer, due to the source (or the lateral cross-sectional pattern of the source) and the gate (or, the lateral direction of the gate)
- the overlap between the overlap region of the cross-sectional pattern and the edge of the gate (or the lateral cross-sectional pattern of the gate) is relatively large, so that the overlap area of the source and the gate is not affected.
- the offset of the angle may be decomposed into a misalignment in a direction parallel to the gate line and a misalignment in a direction perpendicular to the gate line, and parallel to the gate line.
- Embodiments in which the misalignment in the direction and the misalignment in the direction perpendicular to the gate line are similar to the above-described embodiment in which the misalignment in the direction parallel to the gate line and the misalignment in the direction perpendicular to the gate line are This will not be repeated here.
- the shape of the overlapping region of the source and the gate may be any shape that ensures the electrical properties of the TFT.
- the shape of the overlapping region of the source and the gate may be designed as needed or empirically, for example, according to the shape of the source included in the TFT.
- the shape of the first partial region and the second partial region may be any shape (for example, circular, rectangular or elliptical), and only needs to satisfy the case where a misalignment occurs between the first metal layer and the second metal layer.
- the increase/decrease area of the first partial region is equal to the reduced/increased area of the second partial region.
- the shape of the first partial region and the second partial region may be designed according to needs or experience. It should be noted that any overlap region including the gate (or the lateral cross-sectional pattern of the gate) and the two sides of the gate (or the lateral cross-sectional pattern of the gate) are respectively located in the direction parallel to the gate line.
- the pixel unit includes a TFT 10, a pixel electrode 20, a gate line 30, and a data line 40.
- the TFT I0 includes a source 11, a gate 12, and a drain 13, a source II and a pixel electrode. 20 is electrically connected to the via 50, the gate 12 is connected to the gate line 30, and the drain 13 is connected to the data line 40.
- the gate 12 and the gate line 30 are located in the first metal layer, the source II and the drain. 13 and data line 40 are located in the second metal layer.
- the source 11 (or the lateral cross-sectional pattern of the source 11) includes an overlap region lia with the gate electrode 12 (or a lateral cross-sectional pattern of the gate electrode 12), and is located at the gate electrode 12 in a direction parallel to the gate line, respectively. (Or, the transverse cross-sectional pattern of the gate electrode 12) the first partial region l ib and the second partial region iic on both sides.
- a pattern of the first partial region I lb , the second partial region lie and the overlapping region lia with the gate electrode 12 (or the lateral cross-sectional pattern of the gate electrode 12), including the opening "U” in a direction parallel to the gate line A glyph pattern and an "L” shaped pattern that is connected to the closed edge of the "U” shape and placed laterally.
- the first partial region lib is located at a position where one side of the "U" shape extends out of the gate 12 (or a lateral cross-sectional pattern of the gate 12), or on both sides of the "U" shape
- the second partial region lie is located at the "L"-shaped extension of the gate 12 (or the lateral cross-sectional pattern of the gate 12) Location.
- the U-shaped opening may face the drain or may face away from the drain.
- the U-shaped opening faces the drain.
- the first partial region l ib is located on a side of the "U" shape extending away from the through hole 50, or as shown in FIG. 5, located in the "U" shape away from the pass.
- the two sides extending in the direction of the hole 50, the drain 13 (or the transverse cross-sectional pattern of the drain 13) are located between the two sides of the " ⁇ " shape, and the horizontally placed "L"-shaped pattern is rotated to the left.
- the 45-degree "L" shape, the second partial region Uc is electrically connected to the pixel electrode 20 through the via 50.
- the implementation manner of the source of the U-shaped opening facing away from the drain is similar to the implementation of the source of the U-shaped opening toward the drain, except that the glyph opening is back-drained.
- the "L"-shaped pattern placed in the horizontal direction is a "L" shape rotated 45 degrees to the left and vertically inverted, and the drain (or the transverse cross-sectional pattern of the drain) is parallel to the horizontally placed "L"-shaped pattern. .
- the "U"-shaped side and the closed side of the gate overlap, that is, the intersection with the gate (or the transverse cross-sectional pattern of the gate)
- the shape of the side and the closed side of the stacking area can be designed according to needs or experience.
- the closed side of the "U” shape is rectangular, as shown in FIG. 3, the "U"
- the shape of the closed edge of the glyph is curved.
- the shape of the first partial region and the second partial region may be a regular shape or an irregular shape.
- the shape of the first partial area l ib is a rectangle
- the shape of the second partial area lie is a horizontally placed "L" shape.
- the shape of the second partial region may be deformed from the "L" shape to another shape as needed.
- the rectangle is deformed to be perpendicular to the closed side of the "U" shape, i.e., the shape of the second partial region is "one".
- the size requirements of the first partial regions may be the same or different, so as to achieve a misalignment between the first metal layer and the second metal layer, the first partial region
- the increase/decrease area is equal to the decrease/enlargement area of the second partial area.
- the first partial region lib is located on one side of the "U" shape (close to Gate! The upper edge of the upper and lower edges of 2, wherein the lower edge of the gate 12 is in contact with the gate line 30, the upper edge of the gate 12 is away from the gate line 30, and the upper edge of the gate 12 extends parallel to the lower edge of the gate 12)
- the second partial region lie is located at a position where the "L"-shaped shape extends out of the cross-sectional pattern of the gate electrode i.
- the shape of the second partial region 11c is The "L" shape placed horizontally.
- the amounts of change of the lengths of the first partial region lib and the second partial region lie are equal, and thus, in order to realize the first metal layer and the second metal layer
- the increase/decrease area of the first partial area lib is equal to the decrease/enlargement area of the second partial area lie
- the width of the first partial area lib is required to be equal to the width of the rectangular area of the horizontal area of the second partial area lie.
- the width value of the first partial region lib ranges from 5 ⁇ m to 10 ⁇ m.
- the first partial region lib is located at one side of the "U" shape (near the lower edge in the upper and lower edges of the gate 12) and extends at a position of the cross-sectional pattern of the gate 12 and the first partial region
- the shape of lib is a rectangle
- the second partial region 11c is located at a position where the "L" shape extends out of the cross-sectional pattern of the gate 12 and the shape of the second partial region lie is a horizontally placed "L" shape.
- the amounts of change of the lengths of the first partial region lib and the second partial region lie are equal, and thus, in order to realize the first metal layer and the second metal layer
- the increase/decrease area of the first partial region lib is equal to the decrease/enlargement area of the second partial region lie
- the width of the first partial region lib is required to be equal to the width of the rectangular region of the horizontal region of the second partial region 11c ( The embodiment of the widths of the first partial region lib and the second partial region 11c in FIGS. 2 and 4 is similar).
- the first partial region lib is located at a position where the two sides of the "U" shape extend out of the cross-sectional pattern of the gate 12 and the shape of the first partial region lib is a rectangle, and the second partial region lie is located.
- the "L" shape extends at a position of the cross-sectional pattern of the gate electrode 12 and the shape of the second partial portion 11c is a horizontally placed "L" shape.
- the amounts of change of the lengths of the first partial region lib and the second partial region lie are equal, and thus, in order to realize the first metal layer and the second metal layer
- the increase/decrease area of the first partial region lib is equal to the decrease/enlargement area of the second partial region lie, and is required to be respectively located on both sides of the "IT glyph”.
- the sum of the width values of the first partial regions 1 ib at the position of the cross-sectional pattern of the gate electrode 12 is equal to the width of the rectangular portion of the horizontal region of the second partial region 11c.
- the width of the rectangle of the horizontal area of the second partial region is in the range of 5 ⁇ . ⁇ .
- the width of the first portion of the region can also be set as needed or empirically, e.g., based on pixel cell design experience.
- the amount of misalignment between the first metal layer and the second metal layer due to natural factors such as process instability is within a predetermined amount of misalignment, and thus the first metal layer and the second metal layer are implemented.
- the increase/decrease area of the first partial region is equal to the subtraction/increasing area of the second partial region, and the minimum distance between the source and the two edges of the gate (left and right edges)
- the value is not less than the upper limit value of the preset misalignment amount range, and is described below by taking FIG. 2 as an example.
- the shape of the first partial area l ib is a rectangle
- the shape of the second partial area is a horizontally placed "L" shape.
- the length value of the first partial region l ib (ie, the value of the first partial region l ib from the left edge of the gate 12) is a first distance value
- the length of the rectangular portion of the horizontal region of the second partial region 1 ie is a second distance a value
- the glyph being parallel to a side of the first partial region 1 ib and a value of a distance from a left edge of the gate 12, the closed edge of the "U" shaped being a distance from the right edge of the gate 12
- the fourth distance value is not less than an upper limit value of the preset misalignment amount range.
- the first distance value may be set according to needs or experience.
- the first distance value ranges from ⁇ ⁇ - 5 ⁇ .
- the larger the value of the first distance value, the second distance value, the third distance value, and the fourth distance value is, the larger the upper limit value of the preset misalignment amount range is, and the larger the preset misalignment amount range is. The lower the probability of occurrence of FUckeir and Mura.
- the first distance value, the second distance value, the third distance value, and the fourth distance value are equal.
- the first distance value, the second distance value, the third distance value, and the fourth distance value are equal, not only can the upper limit value of the preset misalignment amount range be large, but also the TFT can be ensured. Good electrical performance.
- the minimum distance value between the first partial region and the second partial region and the data line (or the transverse cross-sectional pattern of the data line) is not less than a predetermined distance value threshold.
- the distance The value threshold can be set as needed or empirically, for example, based on pixel unit design experience.
- the distance value threshold has a value ranging from 5 ⁇ to 10 ⁇ .
- the minimum distance between the first partial region and the second partial region and the data line (or the transverse cross-sectional pattern of the data line) is not less than the distance threshold, and the short circuit between the source and the data line can be prevented.
- the minimum distance between the upper edge and the source of the gate is not less than the spacing threshold.
- the spacing threshold can be set as needed or empirically.
- the spacing threshold ranges from 3 ⁇ to 5 ⁇
- the pattern of the first partial region 11b, the second partial region 11c, and the overlapping region l ia with the gate electrode 12 is similar to "s".
- the pattern of the glyphs In order to achieve a misalignment between the first metal layer and the second metal layer, the overlapping area of the source and the gate is constant, and the first partial region and the second partial region are implemented in various forms.
- the first partial region is located at a position where the first side and/or the second side of the "shi" shape extends in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate) And the second partial region is located on the first side and/or the second side of the "shi" shape extending in a second direction opposite to the first direction (or a transverse cross-sectional pattern of the gate) At the position, the first side and the second side are parallel to each other.
- the first partial region l ib is located on the first side of the "s" shape and extends out of the gate 12 in a first direction parallel to the gate line (or the lateral cross section of the gate 12 At a position of the pattern), the second partial region lie is located on the first side of the "shi" shape and extends out of the gate 12 in a second direction opposite to the first direction (or a transverse cross-sectional pattern of the gate 12) The location.
- the width of the first partial region l ib is equal to the width of the second partial region lie.
- the implementation of the width of the first partial area ib and the second partial area is similar to the implementation of the width of the first partial area ib in FIG. 2, and details are not described herein again.
- the minimum distance between the source II and the two edges of the gate 12 (left and right edges)
- the value is not less than the upper limit of the range of the preset misalignment.
- the first partial region l ib has a rectangular shape
- the second partial region l i e has a rectangular shape.
- the length values of the first partial region 1 ib and the second partial region 11 c (ie, the value of the first partial region l ib from the left edge of the gate ! 2, and the second partial region 1 ie the value from the right edge of the gate 12) a first distance value, a value of a distance from a left edge of the gate 12 in the "shi" shape completely overlapping the cross-sectional pattern of the gate 12) is a second distance value, wherein the first distance value and The minimum value of the second distance values is not less than the upper limit value of the preset misalignment amount range.
- the implementation manners of the first distance value and the second distance value are similar to the implementation manners of the first distance value and the second distance value in the first embodiment, and details are not described herein again.
- the first partial region is located at a position where the second side of the "Shi" shape extends in a first direction parallel to the gate line and extends out of the gate (or a lateral cross-sectional pattern of the gate), and the second partial region A second side of the "shi" shape extends at a position of the gate (or a lateral cross-sectional pattern of the gate) in a second direction opposite to the first direction.
- the first partial region is located at a position where the first side of the "shi" shape extends in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate), and the second partial region A second side of the "shi" shape extends at a position of the gate (or a lateral cross-sectional pattern of the gate) in a second direction opposite to the first direction.
- the first partial region is located at a position where the second side of the "shi" shape extends in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate), and the second partial region A first side of the "shi" shape extends at a position of the gate (or a lateral cross-sectional pattern of the gate) in a second direction opposite to the first direction.
- the embodiment of the second embodiment to the fourth embodiment is similar to the embodiment of the first embodiment, and details are not described herein again.
- the first partial region is located at a position where the first side and the second side of the "shi" shape extend in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate).
- the second partial region is located at a position where the first side or the second side of the "shi" shape extends in a second direction opposite to the first direction (or a lateral cross-sectional pattern of the gate).
- the sum of the widths of the first partial regions is equal to the width of the second partial regions.
- the implementation manner of the widths of the first partial region and the second partial region is similar to the implementation of the widths of the first partial region 1 ib and the second partial region 11c in FIG. 5 , and details are not described herein again.
- the minimum distance between the two edges (left and right edges) of the source and the gate is not less than the upper limit of the range of the preset misalignment.
- Embodiment 1 of the embodiment of the present invention Implementation.
- the first partial region is located at a position where the first side or the second side of the "Shi" shape extends in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate)
- the second partial region is located at a position where the first side and the second side of the "shi" shape extend in a second direction opposite to the first direction (or a lateral cross-sectional pattern of the gate).
- the sum of the widths of the second partial regions is equal to the width of the first partial regions.
- the implementation of the width of the first partial region and the second partial region is similar to the implementation of the widths of the first partial region ib and the second partial region ies in FIG. 5, and details are not described herein again.
- the minimum distance between the two edges (left and right edges) of the source and the gate is not less than the upper limit of the range of the preset misalignment.
- Embodiment 1 of the embodiment of the present invention Implementation.
- the first partial region is located at a position where the first side and the second side of the "shi" shape extend in a first direction from a gate (or a lateral cross-sectional pattern of the gate), and the second partial region is located at a position The first side and the second side of the "shi" shape extend at a position of the gate (or a lateral cross-sectional pattern of the gate) in a second direction opposite to the first direction.
- the sum of the widths of the second partial regions is equal to the sum of the widths of the first partial regions.
- the implementation of the width of the first partial region and the second partial region is similar to the implementation of the width of the first partial region ib in FIG. 5, and details are not described herein again.
- the first partial area and the second partial area are rectangular in shape, and the length values of the first partial area and the second partial area are first distance values, and the upper limit of the preset misalignment range is the first 5 Giant j3 ⁇ 4 '(i_.
- the minimum distance value between the first partial region and the second partial region and the data line (or the transverse cross-sectional pattern of the data line) is not less than the distance value threshold.
- the distance value threshold It can be set according to needs or experience, for example, based on pixel unit design experience.
- the distance value threshold has a value ranging from 5 ⁇ to 10 ⁇ .
- the minimum distance between the first partial region and the second partial region and the data line (or the transverse cross-sectional pattern of the data line) is not less than the distance threshold, and the short circuit between the source and the data line can be prevented.
- the minimum distance between the upper edge and the source of the gate is not less than the spacing threshold.
- the spacing threshold can be set as needed or empirically.
- the spacing threshold ranges from 3 ⁇ to 5 ⁇
- the above two embodiments are only two preferred embodiments of the improved source of the embodiment of the present invention, and the source structure in the embodiment of the present invention is simply deformed to make the source after the deformation.
- the structure satisfies the case where the misalignment occurs between the first metal layer and the second metal layer, the overlapping area of the source and the gate is constant, or the other can satisfy the generation between the first metal layer and the second metal layer.
- the source structure in which the overlap area of the source and the gate are constant is within the protection range of the embodiment of the present invention.
- the gap between the source and the gate is constant when the gate is misaligned between the first metal layer and the second metal layer.
- the gate (or the lateral cross-sectional pattern of the gate) includes a first partial region and a second partial region.
- the amount of decrease/increase in the overlap area of the source (or the lateral cross-sectional pattern of the source) and the first partial region is equal to the source (or , the lateral cross-sectional pattern of the source) is increased/decreased by the overlap area of the second partial region.
- any scheme for ensuring that the overlap area between the source and the gate is constant in the case where the gate structure is modified to ensure that a misalignment occurs between the first metal layer and the second metal layer is applicable to Embodiments of the invention.
- the overlapping area of the source (or the lateral cross-sectional pattern of the source) and the first partial region may be increased (or reduced) by the source (or the lateral cross-sectional pattern of the source) and the second partial region.
- the reduction (or increase) of the overlap area is compensated to ensure that the total parasitic capacitance Cgs between the source and the gate is constant, avoiding the occurrence of Flicker and Mura.
- the overlapping area of the source and the gate is constant.
- the gate (or the lateral cross-sectional pattern of the gate) includes a first partial region and a second partial region separated from each other, and the source (or the lateral cross-sectional pattern of the source) includes a portion overlapping the first partial region a three-part area and a fourth part area overlapping the second part area;
- the increase/decrease area (or area) of the third partial region is equal to the decrease/enlargement area (or area) of the fourth partial region.
- any increase or decrease in the bottom area (or area) of the third partial region is achieved by improving the source and the gate to ensure that a misalignment occurs between the first metal layer and the second metal layer.
- the scheme in which the reduction/enhancement area (or area) of the fourth partial region is equal to ensure that the overlap area of the source and the gate is constant is applicable to the embodiment of the present invention.
- the increase/decrease bottom area (or area) of the third partial region can be compensated by the reduced/increased bottom area (or area) of the fourth partial region, thereby ensuring the total between the source and the gate.
- the parasitic capacitance Cgs is constant, avoiding the occurrence of Flicker and Mura.
- the gate electrode 12 (or the lateral cross-sectional pattern of the gate electrode 12) includes a first partial region I 2a and a second partial region i2b separated from each other, and the source 11 (or source II)
- the transverse cross-sectional pattern includes a third partial region i la overlapping the first partial region 12a and a fourth partial region I lb overlapping the second partial region 12b.
- the source 11 (or the lateral cross-sectional pattern of the source) is a similar inverted shape composed of the first partial area I ia , the fourth partial area l ib , and the area ie between the first partial area I2a and the second partial area 12 b picture of.
- the third partial region I la is located at a position where the inverted "T" shape overlaps the first partial region 12a in a first direction parallel to the gate line
- the fourth partial region l ib is located at the inverted "T”
- the glyph is at a position overlapping the second partial region 12b in a second direction opposite to the first direction.
- the shapes of the third partial area i ia and the fourth partial area l ib may be set as needed or empirically, preferably, as shown in FIG. 7 , the third partial area i la and the fourth partial area l ib The shape is a rectangle.
- the width of the third partial region 11a is equal to the width of the fourth partial region l ib .
- the upper limit value of the predetermined misalignment amount range is a length value of the third partial region i la .
- a display device includes the array substrate.
- the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.
- a method for fabricating an array substrate including:
- Step 801 forming a gate on the base substrate, wherein the gate is located on the first metal layer; Step 802, forming a gate insulating layer covering the gate on the base substrate; Step 803, An active layer and a source and a drain on the active layer are sequentially formed on the gate insulating layer, wherein the source and the drain are located in the second metal layer.
- an overlapping area of the source and the gate is constant.
- step 801 forming a gate on the base substrate comprises:
- the embodiment of the base substrate is similar to the embodiment of the base substrate in the prior art.
- the base substrate is a glass substrate, a quartz substrate, or a flexible substrate.
- the implementation of the gate metal layer is similar to the implementation of the gate metal layer of the prior art.
- the gate metal layer is at least one film composed of a metal or alloy of Cr (chromium), Ti (titanium), Ta (barium), Mo (molybdenum), A1 (aluminum), and Cii (copper).
- the thickness of the gate metal layer ranges from 50 ⁇ ⁇ to 400 ⁇ ⁇ .
- the gate metal layer is etched, a different shape of the gate is etched away from the mask using different patterns.
- the gate can be formed by a photolithography process including: coating a photoresist, exposing, developing, etching, and stripping the photoresist using a mask.
- the gate metal layer may be etched as needed while forming a gate line.
- FIG. 9A a plan view of forming a gate electrode and a gate line on a base substrate is shown in FIG. 9A, and - A cross-sectional view in FIG. 9A is shown in FIG. 9B. Shown.
- a gate insulating layer covering the gate is formed on the base substrate, and the package is A gate insulating layer covering the gate is formed on the base substrate by a plasma enhanced chemical vapor deposition (PECVD) method.
- PECVD plasma enhanced chemical vapor deposition
- the gate insulating layer covers both the gate and the gate line.
- the reaction gas corresponding to the gate insulating layer may be a mixed gas of SiH 4 (silane), NH 3 (ammonia gas) and 13 ⁇ 4, and the material of the gate insulating layer includes one of an oxide, a nitride and an oxygen-nitrogen compound.
- the thickness of the gate insulating layer ranges from 1000A to 4000A.
- an active layer and a source and a drain on the active layer are sequentially formed on the gate insulating layer, including: depositing an active layer on the gate insulating layer by a PECVD method And depositing a source/drain metal layer on the active layer by sputtering or thermal evaporation; and etching the active layer and the source/drain metal layer to form an active layer, and a source and a source on the active layer Drain.
- the implementation of the active layer is similar to the implementation of the active layer in the prior art.
- the thickness of the active layer ranges from 1000 ⁇ to 4000 ⁇ .
- the active layer comprises a semiconductor layer and a cryptic semiconductor layer (ie, an ohmic contact layer) having a thickness ranging from 1000 ⁇ to 3,000 ⁇ , and a miscellaneous semiconductor layer having a thickness ranging from 300 ⁇ to 600 ⁇ .
- the reactive gas corresponding to the active layer comprises a mixed gas of SiH 4 and 3 ⁇ 4, and a mixed gas of SiH 2 Cl 2 (dichlorosilane) and 3 ⁇ 4.
- the embodiment of the source-drain metal layer is similar to the prior art source-drain metal layer.
- the source/drain metal layer has a thickness in the range of 500A to 2500A.
- the material of the source/drain metal layer comprises one of a metal or an alloy of Cr, W, Ti, Ta, Mo, Al and Cu.
- the corresponding active layer region between the source and the drain is a corresponding region of the TFT channel pattern, and when the etching process is performed, the doped semiconductor layer of the corresponding region of the TFT channel pattern is completely better.
- the source/drain metal layer is etched, different shapes of the source and the drain are etched by using masks of different patterns.
- the source/drain metal layer may be etched as needed to form a data line.
- a plan view of forming source, drain, and data lines on the active layer is shown in FIG. 9C, in which the drain is a linear electrode, the source The pole includes a U-shaped electrode and a linear electrode, a branch of the linear electrode and the U-shaped electrode extends beyond the gate edge, and a cross-sectional view taken along line B- in Fig. 9C is shown in Fig. 9D.
- the method further includes:
- Step 804 forming a passivation layer including a via hole on the second metal layer
- Step 805 Form a pixel electrode electrically connected to the source through the via hole on the passivation layer.
- step 804 forming a passivation layer including via holes on the second metal layer, comprising: depositing a passivation layer on the second metal layer by a PECVD method;
- the passivation layer corresponding to the source is etched away to form a via that exposes the source.
- the implementation of the passivation layer is similar to the implementation of the passivation layer of the prior art.
- the thickness of the passivation layer ranges from 700A to 2000A.
- the passivation layer corresponding to the reaction gas may be Si3 ⁇ 4, ⁇ ⁇ ⁇ ⁇ mixed gas, or a Si3 ⁇ 4Cl 2, ⁇ ⁇ ⁇ ⁇ 2 mixed gas, the material of the passivation layer comprises an oxide, nitride, or One of oxygen and nitrogen compounds.
- FIG. 9A a plan view of forming a passivation layer including via holes on the second metal layer is as shown in FIG. 9A, wherein the source is electrically connected to the pixel electrode and the pixel electrode. Connected, and the cross section of CC ' in Figure 9 is shown in Figure 9F.
- a pixel electrode electrically connected to the source via the via is formed on the passivation layer, including: depositing a transparent conductive layer on the passivation layer by sputtering or thermal evaporation; And etching the transparent conductive layer to form a pixel electrode electrically connected to the source through the via hole in the pixel region.
- the embodiment of the transparent conductive layer is similar to the implementation of the transparent conductive layer in the prior art.
- the thickness of the transparent conductive layer ranges from 300 ⁇ to 600 ⁇ .
- the material of the transparent conductive layer comprises one or more of indium tin oxide, copper zinc oxide and aluminum zinc oxide.
- FIG. 9G a plan view of a pixel electrode formed on the passivation layer and electrically connected to the source via the via is shown in FIG. 9G, and the D-D' direction in FIG. 9G The sectional view is shown in Figure 9 ⁇ .
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US14/361,883 US9219082B2 (en) | 2013-07-23 | 2013-12-19 | Array substrate and method for manufacturing the same, and display device |
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CN103412449B (zh) * | 2013-07-23 | 2015-11-18 | 合肥京东方光电科技有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN104460149B (zh) * | 2014-12-03 | 2017-09-15 | 深圳市华星光电技术有限公司 | 一种阵列基板、显示装置 |
KR102500662B1 (ko) * | 2015-06-25 | 2023-02-17 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판 |
CN105140300B (zh) * | 2015-10-20 | 2019-01-18 | 重庆京东方光电科技有限公司 | 薄膜晶体管及其制作方法、阵列基板和显示装置 |
CN205067935U (zh) * | 2015-11-05 | 2016-03-02 | 京东方科技集团股份有限公司 | 一种阵列基板及显示装置 |
CN105826396A (zh) * | 2016-05-31 | 2016-08-03 | 京东方科技集团股份有限公司 | 薄膜晶体管、显示基板及显示装置 |
JP6802653B2 (ja) * | 2016-07-15 | 2020-12-16 | 株式会社ジャパンディスプレイ | 表示装置 |
CN106206746B (zh) * | 2016-09-28 | 2020-07-24 | 京东方科技集团股份有限公司 | 薄膜晶体管、goa电路、显示基板和显示装置 |
CN106950771B (zh) | 2017-03-31 | 2019-12-24 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板及显示装置 |
CN106992215B (zh) | 2017-05-05 | 2019-12-31 | 京东方科技集团股份有限公司 | 一种薄膜晶体管、阵列基板及显示装置 |
WO2020045296A1 (ja) * | 2018-08-30 | 2020-03-05 | 凸版印刷株式会社 | 薄膜トランジスタアレイ |
CN110620154A (zh) * | 2019-08-22 | 2019-12-27 | 合肥鑫晟光电科技有限公司 | 薄膜晶体管及其制备方法、阵列基板、显示面板及装置 |
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US20150129882A1 (en) | 2015-05-14 |
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