WO2014194539A1 - 显示面板的测试线路及其测试方法 - Google Patents

显示面板的测试线路及其测试方法 Download PDF

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Publication number
WO2014194539A1
WO2014194539A1 PCT/CN2013/077793 CN2013077793W WO2014194539A1 WO 2014194539 A1 WO2014194539 A1 WO 2014194539A1 CN 2013077793 W CN2013077793 W CN 2013077793W WO 2014194539 A1 WO2014194539 A1 WO 2014194539A1
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Prior art keywords
gate
sub
charge
test
test pad
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PCT/CN2013/077793
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English (en)
French (fr)
Inventor
徐亮
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深圳市华星光电技术有限公司
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Priority to US13/981,350 priority Critical patent/US9159259B2/en
Publication of WO2014194539A1 publication Critical patent/WO2014194539A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • This invention relates to the field of liquid crystal displays. More specifically, it relates to a test circuit for a display panel and a test method therefor.
  • the display panel produced is generally subjected to a power-on lighting test before crimping COF (Chip on Film) and PCB (Printed Circuit Board).
  • COF Chip on Film
  • PCB Printed Circuit Board
  • the advantages of this mode are: The number of probes on the Probe is basically the same as the number of pins in the terminal area of the display panel (about one thousand to several thousand). The waveform comes directly from the same generator as the module PCB. Therefore, the results of the inspection are the best in terms of brightness and darkness (Mura), point defects and line defects, and can also display many special inspection pictures.
  • the disadvantage of this mode is that the probe is expensive, and is easily damaged during the production process, and needs to be replaced frequently. At the same time, when the lamp is turned on, the alignment of the probe and the display panel is very high, and the production efficiency is difficult to increase.
  • Shorting Bar (Shorting Bar) Power-on mode This mode is to short the pins of the gate terminal together, usually the pins of the odd-numbered gate terminals are short-circuited together to form the first test pad, even-numbered row gate
  • the sub-pins are short-circuited together to form a second test pad; the data lines connecting the red sub-pixels are short-circuited together to form a third test pad, and the data lines connecting the green sub-pixels are short-circuited together to form a fourth test pad, which will connect the blue
  • the data lines of the color sub-pixels are shorted together to form a fifth test pad.
  • the advantage of this mode is that the probe's terminals are significantly reduced, so the cost of the Probe is greatly reduced.
  • each test pad is much larger than the size of the Probe's terminals, so the alignment requirements for the Probe and the display panel are very low. high productivity.
  • the shortcomings of this mode are: It can only display some specific pictures, and the signal provided by Probe and the signal provided by Module PCB board are very different, so the accuracy is relatively low. 3.
  • One Gate one Date Power-on mode This mode uses flexible conductive tape or conductive adhesive on the Probe. After the probe is pressed into the terminal area of the display panel, all the scan lines are short-circuited, all The data lines are also shorted together, and the display panel is equivalent to a sub-pixel (Sub Pixel).
  • the advantages of this mode are: The price is lower than the Full Contact mode, but higher than the Shorting Bar mode, and is generally used as a supplementary detection method after the circuit of the Shorting Bar mode is interrupted.
  • the disadvantage of this mode is that the graphics displayed are the least and the detection accuracy is the worst.
  • the liquid crystal display adopts the vertical alignment display mode the color shift becomes serious at a large viewing angle.
  • various methods have been proposed in the industry, such as the coupling capacitance method (also known as the CC method), the dual TFT driving method (also known as the TT method), and the charge sharing method (Charge Sharing).
  • each method has its own advantages and disadvantages, but they have one thing in common: they all divide the original sub-pixel (Sub P el) into two parts, part called Main The area, which is called the Sub area, is generally smaller than the Sub area.
  • This design is generally referred to as the 8-domain design.
  • each sub-pixel is driven by a double gate line, one of which is a charge-filled gate line C and the other is a charge-sharing gate line S. As shown in FIG.
  • the gates of the transistor switches T1 and ⁇ 2 of the sub-pixel are all coupled to the Charging gate line C, and the sources of the transistor switches T1 and ⁇ 2 are all coupled to the data line D, and the transistor switches T1 and ⁇ 2 are
  • the drains are respectively coupled to the electrodes of the Main region and the Sub region; the gate, the source and the drain of the transistor switch T3 are respectively coupled to the SHARING gate line S, the source of the transistor switch T2, and one end of the capacitor Cdown, and the capacitor Cdown The other end is connected to the common voltage Vcom.
  • the sub-pixel shown in FIG. 1 may represent any one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • one pixel formed by the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a matrix on the display panel, wherein the m-th sub-pixel will be connected
  • the Sharing gate line S is short-circuited with the Charging gate line C coupled to the m+2nth row of sub-pixels, and m and n are both positive integers.
  • the Charging gate lines C coupled with the odd-numbered sub-pixels are short-circuited and coupled to the first gate test pad, even rows.
  • the pixel-coupled Charging gate lines C are shorted together and coupled to the second gate test pads.
  • the Charging gate line C and the SHARING gate line S coupled to the odd row sub-pixels are all coupled to the first The gate test pad, the even-numbered row sub-pixel coupled Charging gate line C and the SHARING gate line S are all coupled to the second gate test pad.
  • the Charging gate line C and the Sharing gate line S coupled to the same row of sub-pixels are simultaneously at a high potential or a low potential, but the transistor switch T3 and the transistor switches T1 and ⁇ 2 are turned on at different times, and there is a The time difference, the difference in the display of each sub-pixel within this time difference (ie, the point defect of the display panel) cannot be detected, resulting in missed or false detection of the point defect.
  • the point defects commonly seen in the display panel are classified into three types: a dead point, a bright point, and a dark point.
  • dots that are pure black under white screen conditions or dots that are pure white under black screen conditions are collectively referred to as dead pixels; red, green, and blue dots that are presented under black screen conditions are collectively referred to as bright dots; Simple red, green, and blue dots are collectively referred to as dark spots. Therefore, the number of point defects is an important indicator of the quality of the display panel.
  • an object of the present invention is to provide a test circuit for a display panel, the display panel comprising a plurality of sub-pixels arranged in an array, each sub-pixel being composed of a Charging gate line and a SHARING gate
  • the test circuit includes: a first data test pad electrically coupled to the plurality of red sub-pixels; a second data test pad electrically coupled to the plurality of green sub-pixels; a third data test pad, electrical a plurality of blue sub-pixels are coupled; a SHARING-coupled SHARING gate line of the m-th row of the display panel is coupled to a Charging gate line coupled to the m+2n-row sub-pixel, wherein a positive integer, II is a positive integer not less than 2; k gate test pads, wherein, when the number of rows of sub-pixels of any row is divided by k, the remainder is q, and the qth gate test pad is electrical
  • the sub-pixel includes at least two transistor switches electrically connected to one of the Charging gate lines and one of the data lines, wherein a Charging gate line electrically connected to any of the gate test pads is turned on When the signal is applied, the transistor switch electrically coupled to the Charging gate line is turned on, and the Charging gate line electrically connected to the gate test pad other than the gate test pad is turned on the cutoff signal; When each data line is input with a data signal, the sub-pixel controlled by any of the gate test pads displays a color.
  • the sub-pixel further includes at least one transistor switch electrically connected to one of the SHARING gate lines, wherein the gate electrode electrically controlled by any one of the gate test pads is electrically coupled to the Charging gate line and The potential of the Sharing gate line is different.
  • Another object of the present invention is to provide a test method for a display panel, the test method comprising: electrically connecting the data lines coupled to the red sub-pixels and electrically coupling the first data test pad;
  • the pixel-coupled data lines are electrically connected to each other and electrically coupled to the second data test pad; the data lines coupled to the blue sub-pixels are electrically connected together and electrically coupled to the third data test pad;
  • the sub-pixel-coupled SHARING gate line of the m-th row of the display panel is electrically connected to the Charging gate line of the m+2n-th row of sub-pixels, where m is a positive integer and n is not less than A positive integer of 2; a remainder q is obtained by dividing the number of rows in which the sub-pixels of any row are divided by k, and the Charging gate lines coupled to the sub-pixels of the remaining row corresponding to q are electrically connected and electrically coupled Connected to the qth gate test pad, k and q
  • the k is not more than 2n. Further, the k is 3, and the n is 2.
  • the transistor switch electrically coupled to the Charging gate line is turned on, except for any of the gate test pads.
  • the Charging gate lines electrically connected to the other gate test pads are turned on by the cut-off signal; when the data lines are connected to the data signals, the sub-pixels controlled by any of the gate test pads display colors.
  • the potentials of the Charging gate lines and the Sharing gate lines electrically coupled to the sub-pixels controlled by any of the gate test pads are different.
  • the test circuit and the test method of the display panel of the present invention can enable the display panel to display any gate signal to the gate test pad during the display test, and the Charging gate of each row of sub-pixels controlled by the gate test pad is coupled.
  • the difference between the pole line and the Sharing gate line is better, and the point defect can be better detected, especially due to the difference between the transistor switch T3 and the transistor switching time T1, ⁇ 2.
  • FIG. 1 is a structural diagram of a drive circuit of a sub-pixel of a conventional display panel.
  • 2 is a schematic structural view of a test line of a display panel according to an embodiment of the present invention.
  • FIG. 3 is a signal waveform diagram displayed on the display panel shown in FIG. 2.
  • the display panel includes a pixel P, a charge charging gate line C and a charge sharing gate line S, a data line Dn, and k gate test pads G(1), G ( 2), ..., G(k) and three data test pads Dr, Dg and Db.
  • the pixels P are distributed on the display panel in a matrix arrangement manner, and one pixel P includes three sub-pixels as shown in FIG. 1, that is, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.
  • the data lines Dn coupled to the red sub-pixels R are connected together and electrically coupled to the first data test pad Dr.
  • the data lines Dn coupled to the green sub-pixels G are connected together and electrically coupled to the second data test pad Dg.
  • the data lines Dn coupled to the blue sub-pixel B are connected together and electrically coupled to the third data test pad Db.
  • the first data test pad Dr controls the display of all the red sub-pixels R
  • the second data test pad Dg controls the display of all the green sub-pixels G
  • the third data test pad Db controls the display of all the blue sub-pixels B.
  • a Charging gate in which a sub-pixel coupled to a sub-pixel of the m-th row is coupled to a sub-pixel of the m+2n-th row is viewed in a sub-pixel arrangement manner.
  • the pole lines C are connected together; the number of rows in which the sub-pixels of each row are divided by k, wherein a row of sub-pixels coupled with a remainder of 1 is coupled to the Charging gate line C and electrically coupled to the first gate test Pad G(l), a row of sub-pixels coupled with a remainder of 2 is coupled to the Charging gate line C and electrically coupled to the second gate test pad G(2), and so on, the remainder is k (also The remaining number of sub-pixels coupled to the Charging gate line C are connected together and electrically coupled to the kth gate test pad G(k); wherein m is a positive integer and n is not less than 2 A positive integer, k is a positive integer, and 2 ⁇ is not divisible by k.
  • k is not more than 2n.
  • the first gate test pad G(1) controls the display of a row of sub-pixels corresponding to a remainder of 1
  • the second gate test pad G(2) controls the display of a row of sub-pixels corresponding to a remainder of 2
  • the kth gate test pad G(k) controls the display of the corresponding row of sub-pixels with k (ie, the remainder is zero).
  • the display panel When the display panel displays the test, the first data signal d1, the second data signal d2, the third data signal d3, the first gate signal g(l), the second gate signal g(2), ..., Kth gate signal g(k) is passed to the first data test pad Dr, the second data test pad Dg, the third data test pad Db, the first gate test pad G(1), the second gate test pad G(2), ..., the kth gate test pad G(k), the display panel can display the red of the red sub-pixel R, the green of the green sub-pixel G, and the blue of the blue sub-pixel B.
  • any gate signal is given to the gate
  • the potentials of the Charging gate line C and the SHARING gate line S coupled to each row of sub-pixels controlled by the gate test pad are different, so that the point defects can be better detected, especially due to the transistor switch.
  • the display panel shown in FIG. 2 is provided to the display panel during the display test to provide the display panel with color, thereby achieving the test purpose, the present invention also provides a test method for the display panel. Please refer to Figure 3, and please refer to Figure 2 at the same time.
  • the method for testing the point defect of the display panel is to use the first data signal d1, the second data signal d2, the third data signal d3, the first gate signal g(1), the second gate signal g(2), ... ..., the kth gate signal g(k) is respectively connected to the first data test pad Dr, the second data test pad Dg, the third data test pad Db, the first gate test pad G(l), and the second gate Pole test pad G (2), ..., kth gate test pad G (k).
  • the first data signal d1, the second data signal d2, the third data signal d3, the first gate signal g(1), the second gate signal g(2), ..., the kth gate signal g ( k) is, for example, a periodic signal having the same period t.
  • the first gate signal g(1), the second gate signal g(2), ..., the kth gate signal g(k) are periodic signals having a periodic convex wave 300, and the convex wave
  • the voltage of 300 is such that the transistor switches T1 to T3 connected to the first gate test pad G(1), the second gate test pad G(2), ..., and the kth gate test pad G(k) are turned on. .
  • the transistor switch T1 T3 is indicated. cutoff.
  • any of the gate test pads is turned on, that is, when the Charging gate line C electrically connected to any of the gate test pads is turned on, the turn-on signal is turned on.
  • the transistor switches T1 and T2 coupled to the Charging gate line C are turned on, and the other gate test pads are turned on, because the tracking gate line S of the sub-pixel controlled by the gate test pad is controlled.
  • the gate line S coupled to the sub-pixel controlled by any of the gate test pads is turned on, so that the sub-pixels controlled by any of the gate test pads are controlled.
  • the coupled Charging gate line C and the Sharing gate line S are at different potentials. Since the display mechanism of the display panel is not the focus of the present invention, only the color development mechanism of the display panel will be briefly described herein. When the transistor switches T1 and T2 of the sub-pixel are turned off, the sub-pixel does not display color, and when the transistor switches T1 and T2 of the sub-pixel are turned on, the sub-pixel displays color. Specifically, please refer to FIG. 2 and FIG. 3.
  • the first data signal d1, the second data signal d2, the third data signal d3, the first gate signal g(l), the second gate signal g(2), ..., the kth gate signal g will be separately discussed.
  • (k) In the case of periods t1, t2, ..., tk. At the beginning of the period t1, all sub-pixels are not lit.
  • the Charging gate line C and the SHAS gate line S electrically connected to the first gate test pad G(1) are at a high potential, and The transistor switches T1 and T2 coupled to the Charging gate line C electrically connected to the gate test pad G(1) are turned on, the first data test pad Dr, the second data test pad Dg, and the third data test pad.
  • Db applies the first data signal d1, the second data signal d2, and the third data signal d3 to each of the data lines D and then to the sub-pixels in which the transistor switches T1 and ⁇ 2 are turned on, that is, the first gate test at this time.
  • the sub-pixel controlled by the pad G(l) displays a color; and since the second gate signal g(2), ..., the kth gate signal g(k) does not show the convex wave 300, that is, the second gate test respectively Pad G(2), ..., the kth gate test pad G(k) is electrically connected to the Charging gate line C and the Sharing gate line S is at a low potential, so the first gate test pad G(l) leads The Sharing gate line S coupled to each row of sub-pixels is also at a low potential. At the beginning of period t2, all sub-pixels are not lit.
  • the Charging gate line C and the SHAS gate line S electrically connected to the second gate test pad G(2) are at a high potential, and
  • the transistor switch T1, ⁇ 2 coupled to the Charging gate line C electrically connected to the second gate test pad G(2) is turned on, the first data test pad Dr, the second data test pad Dg, and the third data test pad Db respectively passes the first data signal d1, the second data signal d2, and the third data signal d3 into the sub-pixels in which the transistor switches T1 and ⁇ 2 are turned on, that is, the sub-gate test pad G(2) controls the sub-pixel.
  • the Sharing gate line S coupled to each row of sub-pixels in which the test pad G(2) is turned on is also at a low potential.
  • the Charging gate electrically connected to the kth gate test pad G(k) is indicated.
  • the line C and the tracking gate line S are at a high potential, and the transistor switches T1 and ⁇ 2 coupled to the Charging gate line C electrically connected to the kth gate test pad G(k) are turned on, the first data test pad Dr, the second data test pad Dg, and the third data test pad Db respectively pass the first data signal d1, the second data signal d2, and the third data signal d3 into the sub-pixels in which the transistor switches T1 and ⁇ 2 are turned on, that is,
  • the sub-pixel controlled by the kth gate test pad G(k) displays color; and the first gate signal g(1), the second gate signal g(2), ..., the k-1th gate signal g(kl) does not appear as a convex wave, that is, respectively, with the first gate test pad G(1), the second gate test pad G(2), ...
  • n 2 k is 3, that is, the sub-m row
  • the pixel-coupled Sharing gate line S is connected to the Charging gate line C to which the sub-pixels of the m+4th row are coupled; the number of rows in which the sub-pixels of each row are divided by 3, wherein the remainder is a row corresponding to ⁇
  • the sub-pixel-coupled Charging gate lines C are connected together and electrically coupled to the first gate test pad G(1), and the remainder of the corresponding row of sub-pixels coupled to the Charging gate lines C are connected together and electrically
  • the second gate test pad G(2) is coupled to the second gate test C.
  • the remainder of the row is 3 (that is, the remainder is zero).
  • the corresponding row of sub-pixels coupled to the Charging gate line C are connected together and electrically coupled to the third gate test.
  • Pad G3 controls the display of the corresponding row of sub-pixels with a remainder of 3 (ie, the remainder is zero).
  • the test circuit and the test method of the display panel of the present invention can enable the display panel to display any row of sub-pixels controlled by the gate test pad when any gate signal is applied to the gate test pad during the display test.
  • the coupled Charging gate line C and the Sharing gate line S are at different potentials, the point defects can be better detected, especially due to the difference in opening time of the transistor switch T3 and the transistor switches T1 and ⁇ 2. Point defect.

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  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
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Abstract

一种显示面板的测试电路及其测试方法。该显示面板包括阵列排布的多个子像素，每个子像素由电荷充入栅极线（C）和电荷共享栅极线（S）控制，测试电路包括：第一、第二和第三数据测试垫（Dr，Dg，Db）分别电性耦接多个红色子像素、多个绿色子像素和多个蓝色子像素；显示面板的第m行的子像素耦接的电荷共享栅极线与第m+2n行的子像素耦接的电荷充入栅极线连接，其中m为正整数，n为不小于2的正整数；k个栅极测试垫（G（k）），当任一行的子像素所在的行数除以k后余数为q，第q栅极测试垫电性连接该行子像素耦接的电荷充入栅极线，k和q均为正整数；2n不能被k整除。由于任意子像素耦接的电荷充入栅极线和电荷共享栅极线所处的点位不同，所以可以更好地检测出显示面板的点缺陷。

Description

显示面板的测试线路及其测试方法 技术领域
本发明涉及液晶显示领域。 更具体地讲， 涉及一种显示面板的测试线路及 其测试方法。
背景技术 在液晶显示器的实际生产过程中， 生产出来的显示面板在压接 COF (Chip on Film, 膜片上芯片封装）和 PCB (印刷电路板）之前， 一般都会进行一次加 电点亮的测试。 根据其使用的加电测试器 （Probe) 的不同， 一般分为以下三 种类型：
1、 全接触 （Full Contact) 加电模式 这种模式的优点是： 在 Probe上的探针数量和显示面板端子区的引脚数量 基本相同 （约一千到几千个）， 其使用的电波形直接来自和模块印刷电路板 (Module PCB ) 相同的发生器。 所以其检查的结果在亮暗不均 （Mura)、 点缺 陷和线缺陷上的可信度最好， 也可以显示出很多特殊检查画面。 但是这种模式 的缺点是： Probe 的造价高， 且在生产过程中容易损坏， 需要经常更换， 同时 在点灯时， Probe和显示面板的对位要求非常高， 生产效率难以提高。
2、 短路棒 （Shorting Bar) 加电模式 这种模式是将栅极端子的引脚在***短路在一起，通常奇数行栅极端子的 引脚短路在一起形成第一测试垫， 偶数行栅极端子的引脚短路在一起形成第二 测试垫； 将连接红色子像素的数据线短路在一起形成第三测试垫， 将连接绿色 子像素的数据线短路在一起形成第四测试垫，将连接蓝色子像素的数据线短路 在一起形成第五测试垫。 该模式的优点是： Probe的端子明显减少， 所以 Probe 的造价大幅度降低， 另外每个测试垫的尺寸远远大于 Probe的端子的尺寸， 所 以对 Probe和显示面板的对位要求就很低，生产效率高。但是该模式的缺点是: 其只能显示一些特定的画面， 同时 Probe提供的信号和 Module PCB板提供的 信号有很大的差异， 所以准确性相对较低。 3、 一个扫描行一个数据行 （One Gate one Date) 加电模式 这种模式是在 Probe上使用柔性导电胶带或者导电胶， Probe压在显示面 板端子区后， 所有的扫描线短路在一起， 所有的数据线也短路在一起， 这时该 显示面板相当于一个子像素（Sub Pixel)。这种模式的优点是： 价格相对于 Full Contact模式低， 但比 Shorting Bar模式高， 一般作为 Shorting Bar模式的回路 被打断后的一个补充检测方法。 这种模式的缺点是显示的图形最少， 检测准确 度最差。 在液晶显示器采用垂直配向显示模式时， 在大视角情况下， 色差 （Color shift) 会变得严重。 针对这个问题， 行业里面提出了各种各样的方法， 比如耦 合电容法 （也被称为 CC方法）、 双 TFT驱动法 （也被称为 TT法）、 电荷分享 法 （Charge Sharing)。 所有这些方法都有一定的效果， 并且每种方法都有各自 的优缺点， 但是它们有一个共同点： 都是将原来的一个子像素 （Sub P el) 分 为两个部分， 一部分称为 Main区， 一部分称为 Sub区， 一般 Main区的大小要 小于 Sub区。 这种设计一般都统称为 8畴 （8 Domain) 设计。 在显示面板中的像素采用 8 Domain设计时， 每个子像素采用双栅极线驱 动， 其中一条为电荷充入（Charging)栅极线 C, 另一条为电荷共享（Sharing) 栅极线 S, 具体如图 1 所示， 子像素的晶体管开关 Tl、 Τ2 的栅极均耦接至 Charging栅极线 C， 晶体管幵关 Tl、 Τ2的源极均耦接至数据线 D, 晶体管开 关 Tl、 Τ2的漏极分别耦接至 Main区、 Sub区的电极； 晶体管开关 T3的栅极、 源极及漏极分别耦接 Sharing栅极线 S、晶体管开关 T2的源极及电容器 Cdown 的一端， 电容器 Cdown的另一端连接到公共电压 Vcom。 图 1所示的子像素可代表红色子像素、 绿色子像素、 蓝色子像素中的任意 一个。 在显示面板的制作过程中， 可将由红色子像素、 绿色子像素和蓝色子像 素形成的一个像素以矩阵排列的方式排布在显示面板上，其中，将与第 m行子 像素稱接的 Sharing栅极线 S和与第 m+2n行子像素耦接的 Charging栅极线 C 短路在一起， m和 n均为正整数。
在对制作好的显示面板以短路棒（Shorting Bar)加电模式进行测试时， 将 奇数行子像素耦接的 Charging栅极线 C短路在一起并耦接第一栅极测试垫， 偶数行子像素耦接的 Charging栅极线 C短路在一起并耦接第二栅极测试垫。 这样，奇数行子像素耦接的 Charging栅极线 C和 Sharing栅极线 S均耦接第一 栅极测试垫，偶数行子像素耦接的 Charging栅极线 C和 Sharing栅极线 S均耦 接第二栅极测试垫。那么在进行测试时， 同一行子像素耦接的 Charging栅极线 C和 Sharing栅极线 S同时处于高电位或低电位，然而晶体管开关 T3和晶体管 开关 Tl、 Τ2打开的时间不同， 会存在一个时间差， 在这个时间差内各个子像 素显示的差异（即显示面板的点缺陷）无法检测出，造成点缺陷的漏检或误检。 在这里， 需要说明的是， 显示面板常见的点缺陷分为坏点、 亮点和暗点三种。 其中， 在白屏条件下为纯黑色的点或在黑屏条件下为纯白色的点统称为坏点； 在黑屏条件下呈现的红、 绿、 蓝点统称为亮点； 在白屏条件下呈现非单纯红、 绿、 蓝点统称为暗点。 因此， 点缺陷的数量是衡量显示面板质量的一项重要指 标。
发明内容 为了解决上述现有技术存在的问题，本发明的目的在于提供一种显示面板 的测试线路， 所述显示面板包括阵列排布的多个子像素， 每个子像素由 Charging栅极线和 Sharing栅极线控制， 所述测试电路包括： 第一数据测试垫， 电性耦接多个红色子像素； 第二数据测试垫， 电性耦接多个绿色子像素； 第三 数据测试垫， 电性耦接多个蓝色子像素；所述显示面板的第 m行的子像素耦接 的 Sharing栅极线与第 m+2n行的子像素耦接的 Charging栅极线连接在一起， 其中， m为正整数， II为不小于 2的正整数； k个栅极测试垫， 其中， 当任一 行的子像素所在的行数除以 k后余数为 q, 第 q栅极测试垫电性连接该行子像 素耦接的 Charging栅极线， k和 q均为正整数； 其中， 2η不能被 k整除。 进一步地， 所述 k不大于 2n。 进一步地， 所述 k为 3, 所述 n为 2。 此外，所述子像素包括至少两个电性连接 Charging栅极线之一及数据线之 一的晶体管开关，其中， 当任一栅极测试垫电性连接的 Charging栅极线被通入 导通信号时， 与该 Charging栅极线电性耦接的晶体管开关被导通， 除该任一栅 极测试垫以外的其它栅极测试垫电性连接的 Charging栅极线被通入截止信号； 当各条数据线被通入数据信号时， 该任一栅极测试垫控制的子像素显示颜色。 此外， 所述子像素还包括至少一个电性连接 Sharing栅极线之一的晶体管 开关，其中，所述任一栅极测试垫控制的子像素电性耦接的 Charging栅极线和 Sharing栅极线所处的电位不相同。 本发明的另一目的还在于提供一种显示面板的测试方法， 该测试方法包 括- 将红色子像素耦接的数据线电性连接在一起并电性耦接第一数据测试垫； 将绿色子像素耦接的数据线电性连接在一起并电性耦接第二数据测试垫； 将蓝 色子像素耦接的数据线电性连接在一起并电性耦接第三数据测试垫；将所述显 示面板的第 m行的子像素耦接的 Sharing栅极线与第 m+2n行的子像素耦接的 Charging栅极线电性连接在一起， 其中， m为正整数， n为不小于 2的正整数； 以任一行的子像素所在的行数除以 k后得到余数 q, 将余数为 q对应的该任一 行子像素耦接的 Charging栅极线电性连接在一起并电性耦接第 q栅极测试垫， k和 q均为正整数； 其中， 2n不能被 k整除。 进一步地， 所述 k不大于 2n。 进一步地， 所述 k为 3， 所述 n为 2。 此外， 在任一栅极测试垫电性连接的 Charging栅极线被通入导通信号时， 与该 Charging栅极线电性耦接的晶体管开关被导通，除该任一栅极测试垫以外 的其它栅极测试垫电性连接的 Charging栅极线被通入截止信号；当各条数据线 被通入数据信号时， 该任一栅极测试垫控制的子像素显示颜色。 此外， 所述任一栅极测试垫控制的子像素电性耦接的 Charging栅极线和 Sharing栅极线所处的电位不相同。 本发明的显示面板的测试线路及测试方法， 可使显示面板在显示测试时， 在给出任一栅极信号到栅极测试垫时， 该栅极测试垫控制的各行子像素耦接的 Charging栅极线和 Sharing栅极线所处的电位不同， 则可以更好地检测出点缺 陷， 特别是由于晶体管开关 T3和晶体管幵关 Tl、 Τ2打幵时间的不同而漏检 的点缺陷。
附图说明 图 1是现有的显示面板的子像素的驱动电路结构图。 图 2是本发明的实施例的显示面板的测试线路的结构示意图。
图 3是图 2所示显示面板显示的信号波形图。 具体实施方式 现在对本发明的实施例进行详细的描述， 其示例表示在附图中， 其中， 相 同的标号始终表示相同部件。下面通过参照附图对实施例进行描述以解释本发 明。 在附图中， 为了清晰起见， 可以夸大层和区域的厚度。 在下面的描述中， 为了避免公知结构和 /或功能的不必要的详细描述所导致的本发明构思的混淆， 可省略公知结构和 /或功能的不必要的详细描述。 图 2是本发明的实施例的显示面板的测试线路的结构示意图。 如图 2所示， 显示面板包括像素 P、 电荷充入 （Charging) 栅极线 C和电 荷共享（Sharing)栅极线 S、数据线 Dn以及 k个栅极测试垫 G(l)、 G(2)、……、 G(k)和三个数据测试垫 Dr、 Dg和 Db。其中， 像素 P是以矩阵排列的方式分布 在显示面板上，并且一个像素 P包括三个图 1所示的子像素，即红色子像素 R、 绿色子像素 G和蓝色子像素 B。红色子像素 R耦接的数据线 Dn连接在一起并 电性耦接第一数据测试垫 Dr，绿色子像素 G耦接的数据线 Dn连接在一起并电 性耦接第二数据测试垫 Dg, 蓝色子像素 B耦接的数据线 Dn连接在一起并电 性耦接第三数据测试垫 Db。则第一数据测试垫 Dr控制所有红色子像素 R的显 示， 第二数据测试垫 Dg控制所有绿色子像素 G的显示， 第三数据测试垫 Db 控制所有蓝色子像素 B的显示。 在像素 P排列而成的像素 P矩阵中， 以子像素排列的方式来看， 将第 m 行的子像素耦接的 Sharing栅极线 S与第 m+2n行的子像素耦接的 Charging栅 极线 C连接在一起； 以各行子像素所在的行数除以 k， 其中， 余数为 1对应的 一行子像素耦接的 Charging栅极线 C连接在一起并电性耦接第一栅极测试垫 G(l),余数为 2对应的一行子像素耦接的 Charging栅极线 C连接在一起并电性 耦接第二栅极测试垫 G(2)， 依此类推， 余数为 k (也就是余数为零）对应的一 行子像素耦接的 Charging栅极线 C 连接在一起并电性耦接第 k栅极测试垫 G(k); 其中， m为正整数， n为不小于 2的正整数， k为正整数， 并且 2η不被 k整除。 为了节省栅极测试垫的使用数量， 进而节省成本， 优选地， k不大于 2n。 这样， 第一栅极测试垫 G(l )控制余数为 1对应的一行子像素的显示， 第二 栅极测试垫 G(2)控制余数为 2对应的一行子像素的显示， 依此类推， 第 k栅极 测试垫 G(k)控制余数为 k (也就是余数为零） 对应的一行子像素的显示。 在显示面板显示测试时， 分别将第一数据信号 dl、 第二数据信号 d2、 第 三数据信号 d3、 第一栅极信号 g(l)、 第二栅极信号 g(2)、 ……、 第 k栅极信号 g(k)通入到第一数据测试垫 Dr、 第二数据测试垫 Dg、 第三数据测试垫 Db、 第 一栅极测试垫 G(l)、 第二栅极测试垫 G(2)、 ……、 第 k栅极测试垫 G(k), 就 可以让显示面板显示红色子像素 R的红色、 绿色子像素 G的绿色和蓝色子像 素 B的蓝色。 由于第一栅极信号 g(l)、 第二栅极信号 g(2)、 ……、 第 k栅极信 号 g(k)被分别依次给出， 因此， 在给出任一栅极信号到栅极测试垫时， 该栅极 测试垫控制的各行子像素耦接的 Charging栅极线 C和 Sharing栅极线 S所处的 电位不同， 则可以更好地检测出点缺陷， 特别是由于晶体管开关 T3和晶体管 幵关 Tl、 Τ2打开时间的不同而漏检的点缺陷。 由于图 2所示的显示面板在显示测试时， 通过提供适当的信号给予显示面 板， 以使显示面板显示出色彩， 进而达到测试目的， 所以本发明还提供一种显 示面板的测试方法。 请参照图 3 , 并请同时参照图 2。 图 3是图 2所示显示面 板显示的信号波形图。 其中， 横向代表时间变化， 而纵向表示电压变化。 此显示面板的点缺陷的测试方法是将第一数据信号 dl、第二数据信号 d2、 第三数据信号 d3、 第一栅极信号 g(l)、 第二栅极信号 g(2)、 ……、 第 k栅极信 号 g(k)分别通入到第一数据测试垫 Dr、 第二数据测试垫 Dg、 第三数据测试垫 Db、第一栅极测试垫 G(l)、第二栅极测试垫 G(2)、……、第 k栅极测试垫 G(k)。 其中， 第一数据信号 dl、 第二数据信号 d2、 第三数据信号 d3、 第一栅极信号 g(l)、第二栅极信号 g(2)、 ……、第 k栅极信号 g(k)是例如具有相同周期 t的周 期性信号。 此外， 第一栅极信号 g(l)、 第二栅极信号 g(2)、 ……、 第 k栅极信 号 g(k)是具有一周期性凸波 300的周期性信号， 且凸波 300的电压是使与第一 栅极测试垫 G(l)、 第二栅极测试垫 G(2)、 ……和第 k栅极测试垫 G(k)相连的 晶体管开关 T1~T3导通。 当第一栅极信号 g(l)、 第二栅极测试垫 g(2)、 ……和 第 k栅极测试垫 g(k)在无凸波 300出现的时候，即表示晶体管开关 T1 T3截止。 换言之， 当任一栅极测试垫被通入导通信号时， 即与该任一栅极测试垫电性连 接的 Charging栅极线 C被通入导通信号时， 与被通入导通信号的 Charging栅 极线 C耦接的晶体管开关 Tl、 T2被导通，其它的栅极测试垫被通入截止信号， 由于该任一栅极测试垫控制的子像素耦接的 Sharing栅极线 S电性连接于其它 的栅极测试垫， 因此该任一栅极测试垫控制的子像素耦接的 Sharing栅极线 S 被通入截止信号， 这样使得该任一栅极测试垫控制的子像素耦接的 Charging 栅极线 C和 Sharing栅极线 S所处的电位不同。 由于显示面板的显示机制并不是本发明的重点， 所以在此仅简略叙述显示 面板的显色机制。当子像素的晶体管开关 T1和 T2截止时， 该子像素是不显示 颜色的， 当子像素的晶体管开关 T1和 T2导通时， 该子像素显示颜色。 具体而言， 请参照图 2及图 3。 将分别讨论第一数据信号 dl、 第二数据信 号 d2、 第三数据信号 d3、 第一栅极信号 g(l)、 第二栅极信号 g(2)、 ……、 第 k 栅极信号 g(k)在周期 tl、 t2、 ……、 tk的情形。 在周期 tl 的初始时， 所有子像素是不亮的。 待第一栅极信号 g(l)的凸波 300 出现时， 表示与第一栅极测试垫 G(l)电性连接的 Charging栅极线 C 和 Sharing栅极线 S处于高电位， 与第一栅极测试垫 G(l)电性连接的 Charging栅 极线 C耦接的晶体管开关 Tl、 T2才会导通， 第一数据测试垫 Dr、第二数据测 试垫 Dg、 第三数据测试垫 Db分别将第一数据信号 dl、 第二数据信号 d2、 第 三数据信号 d3施加到各条数据线 D 进而通入晶体管开关 Tl、 Τ2导通的子 像素中， 即此时第一栅极测试垫 G(l)控制的子像素显示颜色； 而由于第二栅极 信号 g(2)、 ……、 第 k栅极信号 g(k)未出现凸波 300, 即分别与第二栅极测试 垫 G(2)、 ……、 第 k栅极测试垫 G(k)电性连接的 Charging栅极线 C和 Sharing 栅极线 S 处于低电位， 因此第一栅极测试垫 G(l )导通的各行子像素耦接的 Sharing栅极线 S也处于低电位。 在周期 t2 的初始时， 所有子像素是不亮的。 待第二栅极信号 g(2)的凸波 300 出现时， 表示与第二栅极测试垫 G(2)电性连接的 Charging栅极线 C 和 Sharing栅极线 S处于高电位， 与第二栅极测试垫 G(2)电性连接的 Charging栅 极线 C耦接的晶体管开关 Tl、 Τ2才会导通， 第一数据测试垫 Dr、 第二数据测 试垫 Dg、 第三数据测试垫 Db分别将第一数据信号 dl、 第二数据信号 d2、 第 三数据信号 d3通入晶体管开关 Tl、 Τ2导通的子像素中， 即此时第二栅极测试 垫 G(2)控制的子像素显示颜色； 而由于第一栅极信号 g(2)、 第三栅极信号 g3、 ……、第 k栅极信号 g(k)未出现凸波 300， 即分别与第一栅极测试垫 G(l)、 第三栅极测试垫 G3、 ……、 第 k栅极测试垫 G(k)电性连接的 Charging栅极线 C和 Sharing栅极线 S处于低电位， 因此第二栅极测试垫 G(2)导通的各行子像 素耦接的 Sharing栅极线 S也处于低电位。 类推下去， 在周期 tk的初始时， 所有子像素是不亮的。 待第 k栅极信号 g(k)的凸波 300出现时，表示与第 k栅极测试垫 G(k)电性连接的 Charging栅极 线 C和 Sharing栅极线 S 处于高电位， 与第 k栅极测试垫 G(k)电性连接的 Charging栅极线 C耦接的晶体管开关 Tl、 Τ2才会导通， 第一数据测试垫 Dr、 第二数据测试垫 Dg、 第三数据测试垫 Db分别将第一数据信号 dl、 第二数据 信号 d2、 第三数据信号 d3通入晶体管开关 Tl、 Τ2导通的子像素中， 即此时 第 k栅极测试垫 G(k)控制的子像素显示颜色； 而由于第一栅极信号 g(l)、第二 栅极信号 g(2)、 ……、 第 k-1栅极信号 g(k-l)未出现凸波， 即分别与第一栅极 测试垫 G(l)、 第二栅极测试垫 G(2)、 ……、 第 k-1栅极测试垫 G(k-l)电性连接 的 Charging栅极线 C和 Sharing栅极线 S处于低电位， 因此第 k栅极测试垫 G(k)导通的各行子像素耦接的 Sharing栅极线 S也处于低电位。 此外， 在实际应用中， 由于栅极测试垫较为昂贵， 因此在本发明中， 为了 节省成本， 以及简化测试线路的连接， 优选地， 使 n为 2， k为 3， 即将第 m 行的子像素耦接的 Sharing栅极线 S与第 m+4行的子像素耦接的 Charging栅极 线 C连接在一起； 以各行子像素所在的行数除以 3， 其中， 余数为〗对应的一 行子像素耦接的 Charging栅极线 C 连接在一起并电性耦接第一栅极测试垫 G(l),余数为 2对应的一行子像素耦接的 Charging栅极线 C连接在一起并电性 耦接第二栅极测试垫 G(2), 余数为 3 (也就是余数为零）对应的一行子像素耦 接的 Charging栅极线 C连接在一起并电性耦接第三栅极测试垫 G3。 这样， 第 一栅极测试垫 G(l)控制余数为 1 对应的一行子像素的显示， 第二栅极测试垫 G(2)控制余数为 2对应的一行子像素的显示， 第 3栅极测试垫 G3控制余数为 3 (也就是余数为零） 对应的一行子像素的显示。 综上所述， 本发明的显示面板的测试线路及测试方法， 可使显示面板在显 示测试时， 在给出任一栅极信号到栅极测试垫时， 该栅极测试垫控制的各行子 像素耦接的 Charging栅极线 C和 Sharing栅极线 S所处的电位不同，则可以更 好地检测出点缺陷， 特别是由于晶体管开关 T3和晶体管开关 Tl、 Τ2打开时 间的不同而漏检的点缺陷。
尽管己经参照其示例性实施例具体显示和描述了本发明， 但是本领域的技 术人员应该理解， 在不脱离权利要求所限定的本发明的精神和范围的情况下， 可以对其进行形式和细节上的各种改变。

Claims

权利要求书
1、 一种显示面板的测试线路， 所述显示面板包括阵列排布的多个子像素， 每个子像素由电荷充入栅极线和电荷共享栅极线控制， 其中， 所述测试电路包 括： 第一数据测试垫， 电性耦接多个红色子像素； 第二数据测试垫， 电性耦接多个绿色子像素； 第三数据测试垫， 电性耦接多个蓝色子像素； 所述显示面板的第 m行的子像素耦接的电荷共享栅极线与第 m+2n行的子 像素耦接的电荷充入栅极线连接， 其中， m为正整数， n为不小于 2的正整数; k个栅极测试垫， 其中， 当任一行的子像素所在的行数除以 k后余数为 q， 第 q栅极测试垫电性连接该行子像素耦接的电荷充入栅极线， k和 q均为正整 数； 其中， 2n不能被 k整除。
2、 根据权利要求 1所述的测试电路， 其中， 所述 k不大于 2n。
3、 根据权利要求 1所述的测试电路， 其中， 所述 k为 3， 所述 n为 2。
4、 根据权利要求 2所述的测试电路， 其中， 所述 k为 3， 所述 n为 2。
5、 根据权利要求 1所述的测试电路， 其中， 所述子像素包括至少两个电 性连接电荷充入栅极线之一及数据线之一的晶体管开关， 其中， 当任一栅极测试垫电性连接的电荷充入栅极线被通入导通信号时， 与该电荷充入栅极线电性耦接的晶体管开关被导通， 除该任一栅极测试垫以外 的其它栅极测试垫电性连接的电荷充入栅极线被通入截止信号； 当各条数据线 被通入数据信号时， 该任一栅极测试垫控制的子像素显示颜色。
6、 根据权利要求 4所述的测试电路， 其中， 所述子像素还包括至少一个 电性连接电荷共享栅极线之一的晶体管开关， 其中， 所述任一栅极测试垫控制的子像素电性耦接的电荷充入栅极线和电 荷共享栅极线所处的电位不相同。
7、 一种显示面板的测试方法， 其中， 包括： 将红色子像素耦接的数据线电性连接在一起并电性耦接第一数据测试垫； 将绿色子像素耦接的数据线电性连接在一起并电性耦接第二数据测试垫； 将蓝色子像素耦接的数据线电性连接在一起并电性耦接第三数据测试垫； 将所述显示面板的第 m行的子像素耦接的电荷共享栅极线与第 m+2n行的 子像素耦接的电荷充入栅极线电性连接在一起， 其中， m为正整数， n为不小 于 2的正整数； 以任一行的子像素所在的行数除以 k后得到余数 q， 将余数为 q对应的该 任一行子像素耦接的电荷充入栅极线电性连接在一起并电性耦接第 q栅极测试 垫， k和 q均为正整数； 其中， 2n不能被 k整除。
8、 根据权利要求 7所述的测试方法， 其中， 所述 k不大于 2n。
9、 根据权利要求 7所述的测试方法， 其中， 所述 k为 3， 所述 n为 2。
10、 根据权利要求 8所述的测试方法， 其中， 所述 k为 3， 所述 n为 2。
11、 根据权利要求 7所述的测试方法， 其中， 在任一栅极测试垫电性连接 的电荷充入栅极线被通入导通信号时， 与该电荷充入栅极线电性耦接的晶体管 开关被导通， 除该任一栅极测试垫以外的其它栅极测试垫电性连接的电荷充入 栅极线被通入截止信号； 当各条数据线被通入数据信号时， 该任一栅极测试垫 控制的子像素显示颜色。
12、 根据权利要求 11 所述的测试方法， 其中， 所述任一栅极测试垫控制 的子像素电性耦接的电荷充入栅极线和电荷共享栅极线所处的电位不相同。
PCT/CN2013/077793 2013-06-06 2013-06-24 显示面板的测试线路及其测试方法 WO2014194539A1 (zh)

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