WO2014181509A1 - Multilayer substrate and electronic device using same, and method for manufacturing electronic device - Google Patents

Multilayer substrate and electronic device using same, and method for manufacturing electronic device Download PDF

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Publication number
WO2014181509A1
WO2014181509A1 PCT/JP2014/002248 JP2014002248W WO2014181509A1 WO 2014181509 A1 WO2014181509 A1 WO 2014181509A1 JP 2014002248 W JP2014002248 W JP 2014002248W WO 2014181509 A1 WO2014181509 A1 WO 2014181509A1
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WO
WIPO (PCT)
Prior art keywords
layer
mold
land
multilayer substrate
electronic device
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PCT/JP2014/002248
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French (fr)
Japanese (ja)
Inventor
俊浩 中村
正英 辰己
英二 藪田
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株式会社デンソー
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Publication of WO2014181509A1 publication Critical patent/WO2014181509A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1316—Moulded encapsulation of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present disclosure relates to a land on which electronic components are mounted and a multilayer substrate having a surface pattern electrically connected to an external circuit, an electronic device using the same, and a method for manufacturing the electronic device.
  • Patent Document 1 an electronic device in which an electronic component is mounted on one side of a substrate has been proposed (see, for example, Patent Document 1). Specifically, in this electronic device, a surface pattern that is electrically connected to lands and external circuits is formed on one surface of the substrate, and a solder resist that covers the surface pattern is formed. The solder resist has an opening for exposing a portion of the surface pattern that is connected to an external circuit. The electronic component is mounted on the land via solder or the like. In addition, one surface side of the substrate including the electronic component is sealed with a mold resin so that at least a portion of the surface pattern connected to the external circuit is exposed.
  • Such an electronic device is manufactured as follows. That is, first, a land and a surface pattern are formed on one surface of the substrate. And after forming the solder resist which covers a surface pattern, the opening part which exposes a part of surface pattern to a solder resist is formed. Next, the electronic component is mounted on the land via solder or the like. Subsequently, a mold having a recess formed on one surface is prepared, and one surface of the mold is pressed against one surface of the substrate so that the electronic component is disposed in the recess. Thereafter, the space between the substrate and the concave portion of the mold is filled with mold resin, whereby the electronic device in which one surface side of the substrate including the electronic component is sealed is manufactured.
  • the height of the portion of the solder resist that covers the surface pattern from the substrate surface is higher than the height of the portion of the solder resist that does not cover the surface pattern from the substrate surface. That is, the height of the solder resist from the substrate surface is different in each part in the part not sealed with the mold resin.
  • the one surface of the mold contacts with a portion of the solder resist that covers the surface pattern, and does not contact with a portion of the solder resist that does not cover the surface pattern.
  • a gap may be formed between one surface of the mold and a portion of the solder resist that does not cover the surface pattern. Therefore, when the gap and the space between the substrate and the concave portion of the mold communicate with each other, the mold resin flows out of the gap when the space between the substrate and the concave portion of the mold is filled with the mold resin. May end up. And the part exposed from a soldering resist among surface patterns may be covered with mold resin.
  • This disclosure is intended to provide a multilayer substrate capable of suppressing the surface pattern from being covered with a mold resin, an electronic device using the same, and a method for manufacturing the electronic device.
  • the multilayer substrate includes a core layer having a surface, an inner layer wiring formed on the surface of the core layer, and a buildup disposed in a state of covering the inner layer wiring on the surface of the core layer.
  • the layer is formed on one side of the build-up layer opposite to the core layer, and is formed on one side of the build-up layer and the land on which the electronic component is mounted, and is electrically connected to the land via the inner layer wiring.
  • a surface pattern that is electrically connected to an external circuit, and a protective film that covers the surface pattern and has an opening that exposes a part of the surface pattern are formed.
  • one surface of the build-up layer is insulated from the land and the surface pattern, surrounds the land and is formed between the land and the surface pattern, and a protective covering the surface layer conductor.
  • a height of the protective film from one side of the build-up layer on the mold step is a height from one side of the build-up layer of the protective film covering the surface pattern. More than that.
  • the mold step is always pressed against the mold.
  • the mold step is formed in a frame shape surrounding the land and is formed between the land and the surface pattern. Therefore, the mold resin can be prevented from flowing out of the space between the multilayer substrate and the mold, and the portion of the surface pattern exposed from the opening of the protective film can be prevented from being covered with the mold resin.
  • an electronic device seals the multilayer substrate according to the first aspect, the electronic component mounted on the land, and the inner edge side of the protective film in the electronic component, the land, and the mold step part. And a mold resin to be stopped.
  • the manufacturing method includes preparing a multilayer substrate, mounting electronic components on lands in the multilayer substrate, Forming a mold resin for sealing the inner edge side of the protective film in the electronic component, the land, and the mold step portion.
  • a mold resin for sealing the inner edge side of the protective film in the electronic component, the land, and the mold step portion.
  • a mold having a recess formed on one surface is prepared, and after pressing one surface of the mold against the mold step so that an electronic component is placed in the recess, the multilayer substrate and the recess Fill the space between the mold resin.
  • the mold resin can be prevented from flowing out from the space between the multilayer substrate and the concave portion of the mold, and the opening of the protective film in the surface pattern It can suppress that the part exposed from is covered with mold resin.
  • FIG. 1 is a cross-sectional view of an electronic device according to a first embodiment of the present disclosure. It is a top view of the electronic device shown in FIG.
  • FIG. 7 is a cross-sectional view showing a manufacturing process of the electronic device shown in FIG. 1.
  • FIG. 4 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 3.
  • FIG. 5 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 4.
  • FIG. 6 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 5. It is an enlarged view of the electronic device in a 2nd embodiment of this indication.
  • a first embodiment of the present disclosure will be described. Note that the electronic device of the present embodiment is preferably mounted on a vehicle such as an automobile, for example, and applied to drive various electronic devices for the vehicle.
  • the electronic device includes a multilayer substrate 10 having one surface 10a and another surface 10b, and electronic components 121 to 123 mounted on the one surface 10a of the multilayer substrate 10.
  • the electronic device is configured by sealing the one surface 10a side of the multilayer substrate 10 together with the electronic components 121 to 123 with the mold resin 150.
  • the multilayer substrate 10 includes a core layer 20 as an insulating resin layer, a build-up layer 30 on the surface 20a side disposed on the surface 20a of the core layer 20, and a back surface 20b side disposed on the back surface 20b side of the core layer 20.
  • the core layer 20 and the buildup layers 30 and 40 are composed of a prepreg formed by sealing both surfaces of a glass cloth with a resin, and examples of the prepreg resin include an epoxy resin.
  • the prepreg resin may contain a filler having excellent electrical insulation and heat dissipation, such as alumina and silica, as necessary.
  • a patterned surface-side inner layer wiring 51 (hereinafter simply referred to as an inner layer wiring 51) is formed at the interface between the core layer 20 and the buildup layer 30.
  • a patterned back side inner layer wiring 52 (hereinafter simply referred to as an inner layer wiring 52) is formed.
  • patterned surface side surface wirings 61 to 63 are formed on the surface 30a of the build-up layer 30, patterned surface side surface wirings 61 to 63 (hereinafter simply referred to as surface layer wirings 61 to 63) are formed.
  • the surface wirings 61 to 63 are bonding lands 61 on which the electronic components 121 to 123 are mounted and the bonding components 141 and 142 that are electrically connected to the electronic components 121 and 122 via the bonding wires 141 and 142.
  • the land 62 is a surface pattern 63 that is electrically connected to an external circuit.
  • patterned back surface side wirings 71 and 72 are formed on the front surface 40a of the buildup layer 40.
  • the surface layer wirings 71 and 72 are a back surface pattern 71 connected to the inner layer wiring 52 through a filled via described later, a heat sink pattern 72 provided with a heat sink for heat dissipation (hereinafter simply referred to as an HS pattern 72). ).
  • the surface 30 a of the buildup layer 30 is one surface of the buildup layer 30 opposite to the core layer 20, and is a surface that becomes the one surface 10 a of the multilayer substrate 10.
  • the surface 40 a of the buildup layer 40 is one surface of the buildup layer 40 opposite to the core layer 20, and is a surface that becomes the other surface 10 b of the multilayer substrate 10.
  • the inner layer wirings 51 and 52, the surface layer wirings 61 to 63, and the surface layer wirings 71 and 72, which will be specifically described later, are configured by appropriately laminating metal foil such as copper or metal plating.
  • the inner layer wiring 51 and the inner layer wiring 52 are electrically and thermally connected through a through via 81 provided through the core layer 20.
  • the through via 81 is configured such that a through electrode 81b such as copper is formed on the wall surface of the through hole 81a penetrating the core layer 20 in the thickness direction, and a filler 81c is filled in the through hole 81a. Has been.
  • the inner layer wiring 51 and the surface layer wirings 61 to 63, and the inner layer wiring 52 and the surface layer wirings 71 and 72 pass through the filled vias 91 and 101 provided through the respective buildup layers 30 and 40 in the thickness direction as appropriate. Connected electrically and thermally. Accordingly, the lands 61 and 62 and the surface layer wiring 63 are appropriately electrically connected via the inner layer wirings 51 and 52, the back surface pattern 71, the through via 81, and the filled vias 91 and 101.
  • the filled vias 91 and 101 are configured such that through holes 91a and 101a penetrating the build-up layers 30 and 40 in the thickness direction are filled with through electrodes 91b and 101b such as copper.
  • the filler 81c is made of resin, ceramic, metal, or the like, but is an epoxy resin in this embodiment.
  • the through electrodes 81b, 91b, 101b are configured by metal plating such as copper.
  • the solder resist 110 that covers the front surface pattern 63 and the back surface pattern 71 is formed on the front surfaces 30a and 40a of the buildup layers 30 and 40, respectively.
  • the solder resist 110 that covers the surface pattern 63 is formed with an opening 110a that exposes a portion of the surface pattern 63 that is connected to an external circuit.
  • the solder resist 110 that covers the surface pattern 63 corresponds to a protective film.
  • the electronic components 121 to 123 include a power element 121 that generates a large amount of heat, such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a control element 122 such as a microcomputer, a passive such as a chip capacitor or a resistor. Element 123.
  • the electronic components 121 to 123 are mounted on the land 61 via the solder 130 and are electrically and mechanically connected to the land 61.
  • the power element 121 and the control element 122 are also electrically connected to the land 62 formed in the periphery via bonding wires 141 and 142 such as aluminum and gold.
  • the power element 121, the control element 122, and the passive element 123 are described as examples of the electronic components 121 to 123, but the electronic components 121 to 123 are not limited to these.
  • the mold resin 150 seals the lands 61 and 62 and the electronic components 121 to 123, and a general mold material such as an epoxy resin is formed by a transfer molding method using a mold, a compression molding method, or the like. Is.
  • the mold resin 150 is formed only on the one surface 10a of the multilayer substrate 10. That is, the electronic device of this embodiment has a so-called half mold structure. Further, on the other surface 10 b side of the multilayer substrate 10, although not particularly shown, a heat sink is provided on the HS pattern 72 via heat dissipation grease or the like.
  • the mold step part 64 is formed in the surface 30a of the buildup layer 30.
  • FIG. 1 the structure of the type
  • the mold step portion 64 is a portion to which a mold constituting the outer shape of the mold resin 150 is pressed when the mold resin 150 is formed, and a surface layer conductor 64 a formed on the surface 30 a of the buildup layer 30, and a surface layer conductor
  • the solder resist 110 covers the 64a.
  • the surface conductor 64 a has a frame shape surrounding the lands 61 and 62, and is formed between the lands 61 and 62 and the surface pattern 63. Further, the surface layer conductor 64 a is insulated from the lands 61 and 62 and the surface pattern 63. That is, the surface layer conductor 64a is a so-called dummy pattern for adjusting the height of the mold step 64.
  • the surface conductor 64a is completely covered with the solder resist 110 that covers the surface pattern 63. That is, the height of the solder resist 110 from the surface 30a of the buildup layer 30 in the mold step 64 is constant in the circumferential direction.
  • the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is set to be equal to or higher than the height from the surface 30a of the build-up layer 30 in the part covering the surface pattern 63 in the solder resist 110.
  • the film thickness of the surface pattern 63 and the surface layer conductor 64a is made equal, and the film thickness of each part of the solder resist 110 is also made equal.
  • the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is made equal to the height from the surface 30a of the build-up layer 30 in the part of the solder resist 110 that covers the surface pattern 63. ing.
  • the mold resin 150 seals the inner edge side portion of the solder resist 110 constituting the mold step portion 64 while exposing the outer edge side portion of the solder resist 110 constituting the die step portion 64. That is, it can be said that the mold step 64 is formed at the interface between the portion sealed with the mold resin 150 and the portion not sealed on the one surface 10 a of the multilayer substrate 10.
  • the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is, in other words, the build-up layer 30 from the surface opposite to the surface layer conductor 64a in the solder resist 110 covering the surface layer conductor 64a. It is the length to the surface 30a.
  • the surface pattern 63 and the surface layer conductor 64a are covered with the same solder resist 110.
  • the solder resist 110 that covers the surface pattern 63 and the solder resist 110 that covers the surface layer conductor 64a are separated. Good.
  • FIGS. 3 to 5 are cross-sectional views in the vicinity of a portion of the multilayer substrate 10 where the power element 121 is mounted.
  • FIG. 3 (a) a structure in which metal foils 161 and 162 such as copper foil are arranged on the front surface 20 a and the back surface 20 b of the core layer 20 is prepared. Then, as shown in FIG. 3B, a through hole 81a penetrating the metal foil 161, the core layer 20, and the metal foil 162 is formed by a drill or the like.
  • electroless plating or electroplating is performed to form a metal plating 163 such as copper on the wall surface of the through hole 81a and the metal foils 161 and 162.
  • a through electrode 81b composed of the metal plating 163 is formed on the wall surface of the through hole 81a.
  • catalysts such as palladium.
  • a filler 81 c is arranged in a space surrounded by the metal plating 163.
  • the through via 81 having the through hole 81a, the through electrode 81b, and the filler 81c is formed.
  • lid plating is performed by electroless plating, electroplating, or the like, and metal plating 164, 165 such as copper is formed on the metal plating 163 and the filler 81c.
  • a resist (not shown) is disposed on the metal platings 164 and 165. Then, wet etching or the like is performed using the resist as a mask, and the metal plating 164, the metal plating 163, and the metal foil 161 are appropriately patterned to form the inner layer wiring 51, and the metal plating 165, the metal plating 163, and the metal foil 162 are appropriately formed.
  • the inner layer wiring 52 is formed by patterning. That is, in this embodiment, the inner layer wiring 51 is configured by laminating the metal foil 161, the metal plating 163, and the metal plating 164, and the inner layer wiring 52 is configured by laminating the metal foil 162, the metal plating 163, and the metal plating 165. It is configured.
  • the metal foil 161, the metal plating 163, the metal plating 164, the metal foil 162, the metal plating 163, and the metal plating 165 are collectively shown as one layer.
  • a buildup layer 30 and a metal plate 166 such as copper are laminated on the inner layer wiring 51 on the surface 20a side of the core layer 20. Then, as shown in FIG. Further, the buildup layer 40 and a metal plate 167 such as copper are laminated on the inner layer wiring 52 on the back surface 20 b side in the core layer 20. In this way, a stacked body 168 is configured in which the metal plate 166, the buildup layer 30, the inner layer wiring 51, the core layer 20, the inner layer wiring 52, the buildup layer 30, and the metal plate 167 are sequentially stacked from the top.
  • the laminate 168 is integrated by heating while pressing from the lamination direction of the laminate 168. Specifically, by pressurizing the laminate 168, the resin constituting the buildup layer 30 is caused to flow to embed between the inner layer wirings 51, and the resin constituting the buildup layer 40 is caused to flow to cause the inner layer wirings 52 to flow. Embed between. And the buildup layers 30 and 40 are hardened by heating the laminated body 168, and the laminated body 168 is integrated.
  • a through hole 91a that penetrates the metal plate 166 and the buildup layer 30 and reaches the inner layer wiring 51 is formed by a laser or the like.
  • a through hole 101 a that penetrates the metal plate 167 and the buildup layer 40 and reaches the inner layer wiring 52 is formed in a cross section different from FIG.
  • the through electrode 91b and the through electrode 101b shown in FIG. 1 are configured by the metal plating 169 embedded in the through holes 91a and 101a formed in the buildup layers 30 and 40. Further, filled vias 91 and 101 in which through electrodes 91b and 101b are embedded in the through holes 91a and 101a are formed.
  • the metal plate 166 and the metal plating 169 are collectively shown as one layer.
  • a resist (not shown) is placed on the metal plate 166. Then, wet etching or the like is performed using the resist as a mask to pattern the metal plate 166, thereby forming the surface layer wirings 61 to 63 and the surface layer conductor 64a. For this reason, the surface layer wirings 61 to 63 and the surface layer conductor 64a have the same height from the surface 30a of the buildup layer 30.
  • a resist (not shown) is arranged on the metal plate 167, and the metal plate 167 is patterned by performing wet etching or the like using the resist as a mask, thereby forming the surface layer wirings 71 and 72.
  • the surface layer wirings 61 to 63 are configured to have the metal plate 166 and the metal plating 169, and the surface layer wirings 71 and 72 are configured to include the metal plate 167 and the metal plating 169.
  • the surface layer conductor 64 a is not electrically connected to the inner layer wiring 51, and the filled via 91 is not formed between the inner layer wiring 51, and thus is constituted only by the metal plate 166.
  • the solder resist 110 is disposed on the surfaces 30a and 40a of the buildup layers 30 and 40, respectively, and patterned appropriately.
  • the multilayer substrate 10 in which the mold step 64 is formed by the surface layer conductor 64a and the solder resist 110 is manufactured.
  • the mold step portion 64 is such that the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is a part of the build-up layer that covers the surface pattern 63 in the solder resist 110. 30 is equal to the height from the surface 30a.
  • the electronic components 121 to 123 are mounted on the land 61 via the solder 130. Then, wire bonding is performed between the power element 121 and the control element 122 and the land 62, and the power element 121 and the control element 122 and the land 62 are electrically connected.
  • a molding resin 150 is formed by a transfer molding method using a mold or a compression molding method so that the lands 61 and 62 and the electronic components 121 to 123 are sealed. To do.
  • a mold 200 is prepared in which a recess 201 constituting the outer shape of the mold resin 150 is formed on one surface 200a, and the surface 200a is multilayered so that the electronic components 121 to 123 are disposed in the recess 201.
  • the substrate 10 is in pressure contact with the one surface 10a side.
  • the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is from the surface 30a of the build-up layer 30 that covers the surface pattern 63 in the solder resist 110. Is equal to the height. For this reason, the mold step 64 is pressed against the mold 200. Moreover, since the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is constant in the circumferential direction, no gap is formed between the mold step 64 and the mold 200. .
  • the said electronic device is manufactured by filling the space between the multilayer substrate 10 and the recessed part 201 of the metal mold
  • the height from the surface 30 a of the buildup layer 30 is set to be equal to or higher than the height from the surface 30 a of the buildup layer 30 in the part of the solder resist 110 that covers the surface pattern 63.
  • the mold step 64 is formed. For this reason, when the one surface 200 a of the mold 200 is pressed against the one surface 10 a side of the multilayer substrate 10, the mold step 64 is always pressed against the mold 200.
  • the mold step 64 has a frame shape surrounding the lands 61 and 62 and is formed between the lands 61 and 62 and the surface pattern 63.
  • the surface conductor 64a of the present embodiment has a rounded corner on the opposite side to the buildup layer 30 side in the cross section in the thickness direction.
  • the lands 61 and 62 and the surface pattern 63 are portions for electrically connecting the electronic components 121 to 123 and the external circuit, and it is preferable to increase the current capacity. Therefore, as shown in FIG.
  • the cross section in the thickness direction is rectangular. That is, the lands 61 and 62 and the surface pattern 63 have a right-angled corner in the cross section opposite to the buildup layer 30 side in the cross section in the thickness direction.
  • FIG. 7 is an enlarged view corresponding to the area A in FIG.
  • the core layer 20 and the buildup layers 30 and 40 are illustrated as being composed of a single prepreg layer. It is good also as what is comprised from.
  • mold step part 64 is made from the surface 30a of the buildup layer 30 of the part which covers the surface pattern 63 among the solder resists 110.
  • the following may be performed.
  • metal plating or the like may be formed only on the surface layer conductor 64a.
  • the mold step 64 has been described in which the height from the surface 30a of the buildup layer 30 is constant in the circumferential direction. That is, even if a depression is formed in the solder resist 110 constituting the mold step 64, the height of the portion where the depression is formed in the mold depression 64 is slightly lower than the height of the other portions. Good. According to this, when forming mold resin 150, the void which may be generated in mold resin 150 can be discharged from a hollow part. In the case where such a mold step portion 64 is configured, even if the mold resin 150 flows out of the recess portion, a portion of the surface pattern 63 exposed from the solder resist 110 is not covered with the mold resin 150. It is preferable to form a depression.

Abstract

A multilayer substrate, wherein a mold foot (64) is provided on one face (30a) of a build-up layer (30), the mold foot (64) having a frame-shaped surface layer conductor (64a) insulated from a land (61) and a surface pattern (63), surrounding the land (61), and being formed between the land (61) and the surface pattern (63), and a protective film (110) for covering the surface layer conductor (64a). The height of the protective film (110) of the mold foot (64) from the one face (30a) of the build-up layer (30) is equal to or greater than the height of a portion of the protective film (110) covering the surface pattern (63) from the one face (30a) of the build-up layer (30). A molded resin can thereby be restricted from covering the surface pattern.

Description

多層基板およびこれを用いた電子装置、電子装置の製造方法Multilayer substrate, electronic device using the same, and method for manufacturing electronic device 関連出願の相互参照Cross-reference of related applications
　本開示は、２０１３年５月６日に出願された日本出願番号２０１３－９７２２７号に基づくもので、ここにその記載内容を援用する。 This disclosure is based on Japanese Application No. 2013-97227 filed on May 6, 2013, the contents of which are incorporated herein.
　本開示は、電子部品が搭載されるランドおよび外部回路と電気的に接続される表面パターンを有する多層基板およびこれを用いた電子装置、電子装置の製造方法に関するものである。 The present disclosure relates to a land on which electronic components are mounted and a multilayer substrate having a surface pattern electrically connected to an external circuit, an electronic device using the same, and a method for manufacturing the electronic device.
　従来より、基板の一面側に電子部品が搭載された電子装置が提案されている（例えば、特許文献１参照）。具体的には、この電子装置では、基板の一面には、ランドおよび外部回路と電気的に接続される表面パターンが形成されていると共に表面パターンを覆うソルダーレジストが形成されている。なお、ソルダーレジストには、表面パターンのうち外部回路と接続される部分を露出させる開口部が形成されている。そして、電子部品は、ランド上にはんだ等を介して搭載されている。また、電子部品を含む基板の一面側は、表面パターンのうち少なくとも外部回路と接続される部分が露出されるように、モールド樹脂によって封止されている。 Conventionally, an electronic device in which an electronic component is mounted on one side of a substrate has been proposed (see, for example, Patent Document 1). Specifically, in this electronic device, a surface pattern that is electrically connected to lands and external circuits is formed on one surface of the substrate, and a solder resist that covers the surface pattern is formed. The solder resist has an opening for exposing a portion of the surface pattern that is connected to an external circuit. The electronic component is mounted on the land via solder or the like. In addition, one surface side of the substrate including the electronic component is sealed with a mold resin so that at least a portion of the surface pattern connected to the external circuit is exposed.
　このような電子装置は、次のように製造される。すなわち、まず、基板の一面にランドおよび表面パターンを形成する。そして、表面パターンを覆うソルダーレジストを形成した後、ソルダーレジストに表面パターンの一部を露出させる開口部を形成する。次に、電子部品をランド上にはんだ等を介して搭載する。続いて、一面に凹部が形成された金型を用意し、電子部品が凹部内に配置されるように、金型の一面を基板の一面側に圧接する。その後、基板と金型の凹部との間の空間にモールド樹脂を充填することにより、電子部品を含む基板の一面側が封止された上記電子装置が製造される。 Such an electronic device is manufactured as follows. That is, first, a land and a surface pattern are formed on one surface of the substrate. And after forming the solder resist which covers a surface pattern, the opening part which exposes a part of surface pattern to a solder resist is formed. Next, the electronic component is mounted on the land via solder or the like. Subsequently, a mold having a recess formed on one surface is prepared, and one surface of the mold is pressed against one surface of the substrate so that the electronic component is disposed in the recess. Thereafter, the space between the substrate and the concave portion of the mold is filled with mold resin, whereby the electronic device in which one surface side of the substrate including the electronic component is sealed is manufactured.
特開平７－２２５３８号公報Japanese Patent Laid-Open No. 7-22538
　しかしながら、このような電子装置の製造方法では、ソルダーレジストのうち表面パターンを覆う部分の基板表面からの高さがソルダーレジストのうち表面パターンを覆わない部分の基板表面からの高さより高くなる。つまり、モールド樹脂で封止されない部分において、ソルダーレジストの基板表面からの高さが各部分で異なる。 However, in such a method for manufacturing an electronic device, the height of the portion of the solder resist that covers the surface pattern from the substrate surface is higher than the height of the portion of the solder resist that does not cover the surface pattern from the substrate surface. That is, the height of the solder resist from the substrate surface is different in each part in the part not sealed with the mold resin.
　このため、金型の一面を基板の一面側に圧接した際、金型の一面はソルダーレジストのうち表面パターンを覆う部分と当接し、ソルダーレジストのうち表面パターンを覆わない部分とは当接しないことがある。つまり、金型の一面とソルダーレジストのうち表面パターンを覆わない部分との間には隙間が形成されることがある。したがって、当該隙間と、基板と金型の凹部との間の空間とが連通した場合には、基板と金型の凹部との間の空間にモールド樹脂を充填したときにモールド樹脂が隙間から流出してしまうことがある。そして、表面パターンのうちソルダーレジストから露出する部分がモールド樹脂にて覆われてしまう可能性がある。 For this reason, when one surface of the mold is pressed against one surface of the substrate, the one surface of the mold contacts with a portion of the solder resist that covers the surface pattern, and does not contact with a portion of the solder resist that does not cover the surface pattern. Sometimes. That is, a gap may be formed between one surface of the mold and a portion of the solder resist that does not cover the surface pattern. Therefore, when the gap and the space between the substrate and the concave portion of the mold communicate with each other, the mold resin flows out of the gap when the space between the substrate and the concave portion of the mold is filled with the mold resin. May end up. And the part exposed from a soldering resist among surface patterns may be covered with mold resin.
　本開示は、表面パターンがモールド樹脂に覆われることを抑制できる多層基板およびこれを用いた電子装置、および電子装置の製造方法を提供することを目的とする。 This disclosure is intended to provide a multilayer substrate capable of suppressing the surface pattern from being covered with a mold resin, an electronic device using the same, and a method for manufacturing the electronic device.
　本開示の第一の態様によれば、多層基板は、表面を有するコア層と、コア層の表面に形成された内層配線と、コア層の表面に内層配線を覆う状態で配置されたビルドアップ層と、ビルドアップ層のうちコア層と反対側の一面に形成され、電子部品が搭載されるランドと、ビルドアップ層の一面に形成され、内層配線を介してランドと電気的に接続されると共に外部回路と電気的に接続される表面パターンと、表面パターンを覆うと共に、表面パターンの一部を露出させる開口部が形成された保護膜とを備える。 According to the first aspect of the present disclosure, the multilayer substrate includes a core layer having a surface, an inner layer wiring formed on the surface of the core layer, and a buildup disposed in a state of covering the inner layer wiring on the surface of the core layer. The layer is formed on one side of the build-up layer opposite to the core layer, and is formed on one side of the build-up layer and the land on which the electronic component is mounted, and is electrically connected to the land via the inner layer wiring. In addition, a surface pattern that is electrically connected to an external circuit, and a protective film that covers the surface pattern and has an opening that exposes a part of the surface pattern are formed.
　さらに、上記多層基板において、ビルドアップ層の一面には、ランドおよび表面パターンと絶縁され、ランドを囲むと共にランドと表面パターンとの間に形成された枠状の表層導体と、表層導体を覆う保護膜と、を有する型踏み部が形成されており、型踏み部における保護膜のビルドアップ層の一面からの高さは、保護膜のうち表面パターンを覆う部分のビルドアップ層の一面からの高さ以上とされている。 Further, in the above multilayer board, one surface of the build-up layer is insulated from the land and the surface pattern, surrounds the land and is formed between the land and the surface pattern, and a protective covering the surface layer conductor. And a height of the protective film from one side of the build-up layer on the mold step is a height from one side of the build-up layer of the protective film covering the surface pattern. More than that.
　このような多層基板では、ランドに電子部品を搭載した後、金型を多層基板の一面側に圧接してモールド樹脂を備える電子装置を製造する場合、型踏み部が必ず金型に圧接される。そして、型踏み部は、ランドを囲む枠状とされていると共にランドと表面パターンとの間に形成されている。したがって、多層基板と金型との間の空間からモールド樹脂が流出することを抑制でき、表面パターンのうち保護膜の開口部から露出する部分がモールド樹脂で覆われることを抑制できる。 In such a multilayer substrate, after mounting electronic components on a land, when manufacturing an electronic device including a mold resin by pressing a mold against one side of the multilayer substrate, the mold step is always pressed against the mold. . The mold step is formed in a frame shape surrounding the land and is formed between the land and the surface pattern. Therefore, the mold resin can be prevented from flowing out of the space between the multilayer substrate and the mold, and the portion of the surface pattern exposed from the opening of the protective film can be prevented from being covered with the mold resin.
　本開示の第二の態様によれば、電子装置は、第一の態様にかかる多層基板と、ランドに搭載された電子部品と、電子部品、ランドおよび型踏み部における保護膜の内縁側を封止するモールド樹脂とを備える。 According to the second aspect of the present disclosure, an electronic device seals the multilayer substrate according to the first aspect, the electronic component mounted on the land, and the inner edge side of the protective film in the electronic component, the land, and the mold step part. And a mold resin to be stopped.
　本開示の第三の態様によれば、第二の態様にかかる電子装置の製造方法に関し、該製造方法は、多層基板を用意することと、多層基板におけるランドに電子部品を搭載することと、電子部品、ランドおよび型踏み部における保護膜の内縁側を封止するモールド樹脂を形成することとを有する。モールド樹脂を形成することでは、一面に凹部が形成された金型を用意し、凹部内に電子部品が配置されるように金型の一面を型踏み部に圧接した後、多層基板と凹部との間の空間にモールド樹脂を充填する。 According to a third aspect of the present disclosure, with respect to a method for manufacturing an electronic device according to the second aspect, the manufacturing method includes preparing a multilayer substrate, mounting electronic components on lands in the multilayer substrate, Forming a mold resin for sealing the inner edge side of the protective film in the electronic component, the land, and the mold step portion. In forming the mold resin, a mold having a recess formed on one surface is prepared, and after pressing one surface of the mold against the mold step so that an electronic component is placed in the recess, the multilayer substrate and the recess Fill the space between the mold resin.
　これによれば、型踏み部が必ず金型に圧接されるため、多層基板と金型の凹部との間の空間からモールド樹脂が流出することを抑制でき、表面パターンのうち保護膜の開口部から露出する部分がモールド樹脂で覆われることを抑制できる。 According to this, since the mold step is always pressed against the mold, the mold resin can be prevented from flowing out from the space between the multilayer substrate and the concave portion of the mold, and the opening of the protective film in the surface pattern It can suppress that the part exposed from is covered with mold resin.
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。図面において、
本開示の第１実施形態における電子装置の断面図である。 図１に示す電子装置の平面図である。 図１に示す電子装置の製造工程を示す断面図である。 図３に続く電子装置の製造工程を示す断面図である。 図４に続く電子装置の製造工程を示す断面図である。 図５に続く電子装置の製造工程を示す断面図である。 本開示の第２実施形態における電子装置の拡大図である。 The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawing
1 is a cross-sectional view of an electronic device according to a first embodiment of the present disclosure. It is a top view of the electronic device shown in FIG. FIG. 7 is a cross-sectional view showing a manufacturing process of the electronic device shown in FIG. 1. FIG. 4 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 3. FIG. 5 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 4. FIG. 6 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 5. It is an enlarged view of the electronic device in a 2nd embodiment of this indication.
　以下、本開示の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.
　（第１実施形態）
　本開示の第１実施形態について説明する。なお、本実施形態の電子装置は、例えば、自動車等の車両に搭載され、車両用の各種電子装置を駆動するために適用されると好適である。 (First embodiment)
A first embodiment of the present disclosure will be described. Note that the electronic device of the present embodiment is preferably mounted on a vehicle such as an automobile, for example, and applied to drive various electronic devices for the vehicle.
　図１に示されるように、電子装置は、一面１０ａおよび他面１０ｂを有する多層基板１０と、多層基板１０の一面１０ａ上に搭載された電子部品１２１～１２３と、を備えている。そして、多層基板１０の一面１０ａ側を電子部品１２１～１２３と共にモールド樹脂１５０で封止することにより、電子装置が構成されている。 As shown in FIG. 1, the electronic device includes a multilayer substrate 10 having one surface 10a and another surface 10b, and electronic components 121 to 123 mounted on the one surface 10a of the multilayer substrate 10. The electronic device is configured by sealing the one surface 10a side of the multilayer substrate 10 together with the electronic components 121 to 123 with the mold resin 150.
　多層基板１０は、絶縁樹脂層としてのコア層２０と、コア層２０の表面２０ａに配置された表面２０ａ側のビルドアップ層３０と、コア層２０の裏面２０ｂ側に配置された裏面２０ｂ側のビルドアップ層４０とを備える積層基板である。 The multilayer substrate 10 includes a core layer 20 as an insulating resin layer, a build-up layer 30 on the surface 20a side disposed on the surface 20a of the core layer 20, and a back surface 20b side disposed on the back surface 20b side of the core layer 20. A multilayer substrate including a build-up layer 40.
　なお、コア層２０およびビルドアップ層３０、４０は、ガラスクロスの両面を樹脂で封止してなるプリプレグ等で構成され、プリプレグの樹脂としては、エポキシ樹脂等が挙げられる。また、プレプレグの樹脂には、必要に応じて、アルミナやシリカ等の電気絶縁性かつ放熱性に優れたフィラーが含有されていてもよい。 The core layer 20 and the buildup layers 30 and 40 are composed of a prepreg formed by sealing both surfaces of a glass cloth with a resin, and examples of the prepreg resin include an epoxy resin. In addition, the prepreg resin may contain a filler having excellent electrical insulation and heat dissipation, such as alumina and silica, as necessary.
　そして、コア層２０とビルドアップ層３０との界面には、パターニングされた表面側内層配線５１（以下では、単に内層配線５１という）が形成されている。同様に、コア層２０とビルドアップ層４０との界面には、パターニングされた裏面側内層配線５２（以下では、単に内層配線５２という）が形成されている。 A patterned surface-side inner layer wiring 51 (hereinafter simply referred to as an inner layer wiring 51) is formed at the interface between the core layer 20 and the buildup layer 30. Similarly, at the interface between the core layer 20 and the buildup layer 40, a patterned back side inner layer wiring 52 (hereinafter simply referred to as an inner layer wiring 52) is formed.
　また、ビルドアップ層３０の表面３０ａには、パターニングされた表面側表層配線６１～６３（以下では、単に表層配線６１～６３という）が形成されている。本実施形態では、表層配線６１～６３は、電子部品１２１～１２３が搭載される搭載用のランド６１、電子部品１２１、１２２とボンディングワイヤ１４１、１４２を介して電気的に接続されるボンディング用のランド６２、外部回路と電気的に接続される表面パターン６３とされている。 Further, on the surface 30a of the build-up layer 30, patterned surface side surface wirings 61 to 63 (hereinafter simply referred to as surface layer wirings 61 to 63) are formed. In the present embodiment, the surface wirings 61 to 63 are bonding lands 61 on which the electronic components 121 to 123 are mounted and the bonding components 141 and 142 that are electrically connected to the electronic components 121 and 122 via the bonding wires 141 and 142. The land 62 is a surface pattern 63 that is electrically connected to an external circuit.
　ビルドアップ層４０の表面４０ａには、パターニングされた裏面側表層配線７１、７２（以下では、単に表層配線７１、７２という）が形成されている。本実施形態では、表層配線７１、７２は、後述するフィルドビアを介して内層配線５２と接続される裏面パターン７１、放熱用のヒートシンクが備えられるヒートシンク用パターン７２（以下では、単にＨＳ用パターン７２という）とされている。 On the front surface 40a of the buildup layer 40, patterned back surface side wirings 71 and 72 (hereinafter simply referred to as surface wirings 71 and 72) are formed. In the present embodiment, the surface layer wirings 71 and 72 are a back surface pattern 71 connected to the inner layer wiring 52 through a filled via described later, a heat sink pattern 72 provided with a heat sink for heat dissipation (hereinafter simply referred to as an HS pattern 72). ).
　なお、ビルドアップ層３０の表面３０ａとは、ビルドアップ層３０のうちコア層２０と反対側の一面のことであり、多層基板１０の一面１０ａとなる面のことである。また、ビルドアップ層４０の表面４０ａとは、ビルドアップ層４０のうちコア層２０と反対側の一面のことであり、多層基板１０の他面１０ｂとなる面のことである。そして、内層配線５１、５２、表層配線６１～６３、表層配線７１、７２は、具体的には後述するが、銅等の金属箔や金属メッキが適宜積層されて構成されている。 Note that the surface 30 a of the buildup layer 30 is one surface of the buildup layer 30 opposite to the core layer 20, and is a surface that becomes the one surface 10 a of the multilayer substrate 10. Further, the surface 40 a of the buildup layer 40 is one surface of the buildup layer 40 opposite to the core layer 20, and is a surface that becomes the other surface 10 b of the multilayer substrate 10. The inner layer wirings 51 and 52, the surface layer wirings 61 to 63, and the surface layer wirings 71 and 72, which will be specifically described later, are configured by appropriately laminating metal foil such as copper or metal plating.
　内層配線５１と内層配線５２とは、コア層２０を貫通して設けられた貫通ビア８１を介して電気的および熱的に接続されている。具体的には、貫通ビア８１は、コア層２０を厚さ方向に貫通する貫通孔８１ａの壁面に銅等の貫通電極８１ｂが形成され、貫通孔８１ａの内部に充填材８１ｃが充填されて構成されている。 The inner layer wiring 51 and the inner layer wiring 52 are electrically and thermally connected through a through via 81 provided through the core layer 20. Specifically, the through via 81 is configured such that a through electrode 81b such as copper is formed on the wall surface of the through hole 81a penetrating the core layer 20 in the thickness direction, and a filler 81c is filled in the through hole 81a. Has been.
　また、内層配線５１と表層配線６１～６３、および内層配線５２と表層配線７１、７２とは、適宜各ビルドアップ層３０、４０を厚さ方向に貫通して設けられたフィルドビア９１、１０１を介して電気的および熱的に接続されている。これにより、ランド６１、６２と表層配線６３とは、内層配線５１、５２、裏面パターン７１、貫通ビア８１、フィルドビア９１、１０１を介して適宜電気的に接続されている。 Further, the inner layer wiring 51 and the surface layer wirings 61 to 63, and the inner layer wiring 52 and the surface layer wirings 71 and 72 pass through the filled vias 91 and 101 provided through the respective buildup layers 30 and 40 in the thickness direction as appropriate. Connected electrically and thermally. Accordingly, the lands 61 and 62 and the surface layer wiring 63 are appropriately electrically connected via the inner layer wirings 51 and 52, the back surface pattern 71, the through via 81, and the filled vias 91 and 101.
　なお、フィルドビア９１、１０１は、各ビルドアップ層３０、４０を厚さ方向に貫通する貫通孔９１ａ、１０１ａが銅等の貫通電極９１ｂ、１０１ｂにて充填された構成とされている。また、充填材８１ｃは、樹脂、セラミック、金属等が用いられるが、本実施形態では、エポキシ樹脂とされている。そして、貫通電極８１ｂ、９１ｂ、１０１ｂは、銅等の金属メッキにて構成されている。 The filled vias 91 and 101 are configured such that through holes 91a and 101a penetrating the build-up layers 30 and 40 in the thickness direction are filled with through electrodes 91b and 101b such as copper. The filler 81c is made of resin, ceramic, metal, or the like, but is an epoxy resin in this embodiment. The through electrodes 81b, 91b, 101b are configured by metal plating such as copper.
　そして、各ビルドアップ層３０、４０の表面３０ａ、４０ａには、表面パターン６３、および裏面パターン７１を覆うソルダーレジスト１１０が形成されている。なお、表面パターン６３を覆うソルダーレジスト１１０には、表面パターン６３のうち外部回路と接続される部分を露出させる開口部１１０ａが形成されている。また、本実施形態では、表面パターン６３を覆うソルダーレジスト１１０が保護膜に相当している。 The solder resist 110 that covers the front surface pattern 63 and the back surface pattern 71 is formed on the front surfaces 30a and 40a of the buildup layers 30 and 40, respectively. The solder resist 110 that covers the surface pattern 63 is formed with an opening 110a that exposes a portion of the surface pattern 63 that is connected to an external circuit. In the present embodiment, the solder resist 110 that covers the surface pattern 63 corresponds to a protective film.
　電子部品１２１～１２３は、ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）等の発熱が大きいパワー素子１２１、マイコン等の制御素子１２２、チップコンデンサや抵抗等の受動素子１２３である。そして、各電子部品１２１～１２３は、はんだ１３０を介してランド６１上に搭載されてランド６１と電気的、機械的に接続されている。また、パワー素子１２１および制御素子１２２は、周囲に形成されているランド６２ともアルミニウムや金等のボンディングワイヤ１４１、１４２を介して電気的に接続されている。 The electronic components 121 to 123 include a power element 121 that generates a large amount of heat, such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a control element 122 such as a microcomputer, a passive such as a chip capacitor or a resistor. Element 123. The electronic components 121 to 123 are mounted on the land 61 via the solder 130 and are electrically and mechanically connected to the land 61. The power element 121 and the control element 122 are also electrically connected to the land 62 formed in the periphery via bonding wires 141 and 142 such as aluminum and gold.
　なお、ここでは、電子部品１２１～１２３としてパワー素子１２１、制御素子１２２、受動素子１２３を例に挙げて説明したが、電子部品１２１～１２３はこれらに限定されるものではない。 Here, the power element 121, the control element 122, and the passive element 123 are described as examples of the electronic components 121 to 123, but the electronic components 121 to 123 are not limited to these.
　モールド樹脂１５０は、ランド６１、６２および電子部品１２１～１２３を封止するものであり、エポキシ樹脂等の一般的なモールド材料が金型を用いたトランスファーモールド法やコンプレッションモールド法等により形成されたものである。 The mold resin 150 seals the lands 61 and 62 and the electronic components 121 to 123, and a general mold material such as an epoxy resin is formed by a transfer molding method using a mold, a compression molding method, or the like. Is.
　なお、本実施形態では、モールド樹脂１５０は、多層基板１０の一面１０ａのみに形成されている。つまり、本実施形態の電子装置は、いわゆるハーフモールド構造とされている。また、多層基板１０の他面１０ｂ側には、特に図示していないが、ＨＳ用パターン７２に放熱グリス等を介してヒートシンクが備えられている。 In the present embodiment, the mold resin 150 is formed only on the one surface 10a of the multilayer substrate 10. That is, the electronic device of this embodiment has a so-called half mold structure. Further, on the other surface 10 b side of the multilayer substrate 10, although not particularly shown, a heat sink is provided on the HS pattern 72 via heat dissipation grease or the like.
　以上が本実施形態における電子装置の基本的な構成である。そして、本実施形態の電子装置では、ビルドアップ層３０の表面３０ａに型踏み部６４が形成されている。以下に、本実施形態の特徴点である型踏み部６４の構成について図１および図２を参照しつつ説明する。なお、図２では、理解をし易くするために、ソルダーレジスト１１０を省略して示してある。また、図１は、図２中のI-I断面に相当している。 The above is the basic configuration of the electronic device in the present embodiment. And in the electronic device of this embodiment, the mold step part 64 is formed in the surface 30a of the buildup layer 30. FIG. Below, the structure of the type | mold tread part 64 which is the feature point of this embodiment is demonstrated, referring FIG. 1 and FIG. In FIG. 2, the solder resist 110 is omitted for easy understanding. 1 corresponds to a cross section taken along line II in FIG.
　型踏み部６４は、モールド樹脂１５０を形成する際にモールド樹脂１５０の外形を構成する金型が圧接される部分であり、ビルドアップ層３０の表面３０ａに形成された表層導体６４ａと、表層導体６４ａを覆うソルダーレジスト１１０によって構成されている。 The mold step portion 64 is a portion to which a mold constituting the outer shape of the mold resin 150 is pressed when the mold resin 150 is formed, and a surface layer conductor 64 a formed on the surface 30 a of the buildup layer 30, and a surface layer conductor The solder resist 110 covers the 64a.
　具体的には、表層導体６４ａは、図１および図２に示されるように、ランド６１、６２を囲む枠状とされ、ランド６１、６２と表面パターン６３との間に形成されている。また、表層導体６４ａは、ランド６１、６２および表面パターン６３とは絶縁されている。すなわち、表層導体６４ａは、いわゆるダミーパターンであり、型踏み部６４の高さを調整するためのものである。 Specifically, as shown in FIGS. 1 and 2, the surface conductor 64 a has a frame shape surrounding the lands 61 and 62, and is formed between the lands 61 and 62 and the surface pattern 63. Further, the surface layer conductor 64 a is insulated from the lands 61 and 62 and the surface pattern 63. That is, the surface layer conductor 64a is a so-called dummy pattern for adjusting the height of the mold step 64.
　そして、表層導体６４ａは、表面パターン６３を覆うソルダーレジスト１１０によって完全に覆われている。つまり、型踏み部６４におけるソルダーレジスト１１０のビルドアップ層３０の表面３０ａからの高さは、周方向において一定とされている。 The surface conductor 64a is completely covered with the solder resist 110 that covers the surface pattern 63. That is, the height of the solder resist 110 from the surface 30a of the buildup layer 30 in the mold step 64 is constant in the circumferential direction.
　また、型踏み部６４におけるソルダーレジスト１１０のビルドアップ層３０の表面３０ａからの高さは、ソルダーレジスト１１０のうち表面パターン６３を覆う部分のビルドアップ層３０の表面３０ａからの高さ以上とされている。本実施形態では、表面パターン６３および表層導体６４ａの膜厚が等しくされ、ソルダーレジスト１１０の部分毎の膜厚も等しくされている。このため、型踏み部６４におけるソルダーレジスト１１０のビルドアップ層３０の表面３０ａからの高さは、ソルダーレジスト１１０のうち表面パターン６３を覆う部分のビルドアップ層３０の表面３０ａからの高さと等しくされている。 Moreover, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is set to be equal to or higher than the height from the surface 30a of the build-up layer 30 in the part covering the surface pattern 63 in the solder resist 110. ing. In this embodiment, the film thickness of the surface pattern 63 and the surface layer conductor 64a is made equal, and the film thickness of each part of the solder resist 110 is also made equal. For this reason, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is made equal to the height from the surface 30a of the build-up layer 30 in the part of the solder resist 110 that covers the surface pattern 63. ing.
　そして、モールド樹脂１５０は、型踏み部６４を構成するソルダーレジスト１１０の外縁側の部分を露出させつつ、型踏み部６４を構成するソルダーレジスト１１０の内縁側の部分を封止している。つまり、型踏み部６４は、多層基板１０の一面１０ａにおいて、モールド樹脂１５０で封止される部分と封止されない部分との間の界面に形成されているともいえる。 The mold resin 150 seals the inner edge side portion of the solder resist 110 constituting the mold step portion 64 while exposing the outer edge side portion of the solder resist 110 constituting the die step portion 64. That is, it can be said that the mold step 64 is formed at the interface between the portion sealed with the mold resin 150 and the portion not sealed on the one surface 10 a of the multilayer substrate 10.
　なお、型踏み部６４におけるソルダーレジスト１１０のビルドアップ層３０の表面３０ａからの高さとは、言い換えると、表層導体６４ａを覆うソルダーレジスト１１０のうち表層導体６４ａと反対側の面からビルドアップ層３０の表面３０ａまでの長さのことである。また、図１では、表面パターン６３および表層導体６４ａが同じソルダーレジスト１１０にて覆われているが、表面パターン６３を覆うソルダーレジスト１１０と表層導体６４ａを覆うソルダーレジスト１１０とが分離されていてもよい。 In addition, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is, in other words, the build-up layer 30 from the surface opposite to the surface layer conductor 64a in the solder resist 110 covering the surface layer conductor 64a. It is the length to the surface 30a. In FIG. 1, the surface pattern 63 and the surface layer conductor 64a are covered with the same solder resist 110. However, the solder resist 110 that covers the surface pattern 63 and the solder resist 110 that covers the surface layer conductor 64a are separated. Good.
　以上が本実施形態における電子装置の構成である。次に、上記電子装置の製造方法について図３～図６を参照しつつ説明する。なお、図３～図５は、多層基板１０のうちパワー素子１２１が搭載される部分近傍の断面図である。 The above is the configuration of the electronic device in the present embodiment. Next, a method for manufacturing the electronic device will be described with reference to FIGS. 3 to 5 are cross-sectional views in the vicinity of a portion of the multilayer substrate 10 where the power element 121 is mounted.
　まず、図３（ａ）に示されるように、コア層２０の表面２０ａおよび裏面２０ｂに銅箔等の金属箔１６１、１６２が配置されたものを用意する。そして、図３（ｂ）に示されるように、ドリル等によって金属箔１６１、コア層２０、金属箔１６２を貫通する貫通孔８１ａを形成する。 First, as shown in FIG. 3 (a), a structure in which metal foils 161 and 162 such as copper foil are arranged on the front surface 20 a and the back surface 20 b of the core layer 20 is prepared. Then, as shown in FIG. 3B, a through hole 81a penetrating the metal foil 161, the core layer 20, and the metal foil 162 is formed by a drill or the like.
　その後、図３（ｃ）に示されるように、無電解メッキや電気メッキを行い、貫通孔８１ａの壁面および金属箔１６１、１６２上に銅等の金属メッキ１６３を形成する。これにより、貫通孔８１ａの壁面に、金属メッキ１６３にて構成される貫通電極８１ｂが形成される。なお、無電解メッキおよび電気メッキを行う場合には、パラジウム等の触媒を用いて行うことが好ましい。 Thereafter, as shown in FIG. 3C, electroless plating or electroplating is performed to form a metal plating 163 such as copper on the wall surface of the through hole 81a and the metal foils 161 and 162. As a result, a through electrode 81b composed of the metal plating 163 is formed on the wall surface of the through hole 81a. In addition, when performing electroless plating and electroplating, it is preferable to carry out using catalysts, such as palladium.
　続いて、図３（ｄ）に示されるように、金属メッキ１６３で囲まれる空間に充填材８１ｃを配置する。これにより、貫通孔８１ａ、貫通電極８１ｂ、充填材８１ｃを有する上記貫通ビア８１が形成される。 Subsequently, as shown in FIG. 3 (d), a filler 81 c is arranged in a space surrounded by the metal plating 163. Thus, the through via 81 having the through hole 81a, the through electrode 81b, and the filler 81c is formed.
　その後、図４（ａ）に示されるように、無電解メッキおよび電気メッキ等でいわゆる蓋メッキを行い、金属メッキ１６３および充填材８１ｃ上に銅等の金属メッキ１６４、１６５を形成する。 Thereafter, as shown in FIG. 4A, so-called lid plating is performed by electroless plating, electroplating, or the like, and metal plating 164, 165 such as copper is formed on the metal plating 163 and the filler 81c.
　次に、図４（ｂ）に示されるように、金属メッキ１６４、１６５上に図示しないレジストを配置する。そして、当該レジストをマスクとしてウェットエッチング等を行い、金属メッキ１６４、金属メッキ１６３、金属箔１６１を適宜パターニングして内層配線５１を形成すると共に、金属メッキ１６５、金属メッキ１６３、金属箔１６２を適宜パターニングして内層配線５２を形成する。つまり、本実施形態では、内層配線５１は、金属箔１６１、金属メッキ１６３、金属メッキ１６４が積層されて構成され、内層配線５２は、金属箔１６２、金属メッキ１６３、金属メッキ１６５が積層されて構成されている。 Next, as shown in FIG. 4B, a resist (not shown) is disposed on the metal platings 164 and 165. Then, wet etching or the like is performed using the resist as a mask, and the metal plating 164, the metal plating 163, and the metal foil 161 are appropriately patterned to form the inner layer wiring 51, and the metal plating 165, the metal plating 163, and the metal foil 162 are appropriately formed. The inner layer wiring 52 is formed by patterning. That is, in this embodiment, the inner layer wiring 51 is configured by laminating the metal foil 161, the metal plating 163, and the metal plating 164, and the inner layer wiring 52 is configured by laminating the metal foil 162, the metal plating 163, and the metal plating 165. It is configured.
　なお、次の図４（ｃ）以降では、金属箔１６１、金属メッキ１６３、金属メッキ１６４、および金属箔１６２、金属メッキ１６３、金属メッキ１６５をまとめて１層として示してある。 In FIG. 4C and subsequent figures, the metal foil 161, the metal plating 163, the metal plating 164, the metal foil 162, the metal plating 163, and the metal plating 165 are collectively shown as one layer.
　その後、図４（ｃ）に示されるように、コア層２０における表面２０ａ側において、内層配線５１上にビルドアップ層３０および銅等の金属板１６６を積層する。また、コア層２０における裏面２０ｂ側において、内層配線５２上にビルドアップ層４０および銅等の金属板１６７を積層する。このようにして、上から順に、金属板１６６、ビルドアップ層３０、内層配線５１、コア層２０、内層配線５２、ビルドアップ層３０および金属板１６７が順に積層された積層体１６８を構成する。 4C, a buildup layer 30 and a metal plate 166 such as copper are laminated on the inner layer wiring 51 on the surface 20a side of the core layer 20. Then, as shown in FIG. Further, the buildup layer 40 and a metal plate 167 such as copper are laminated on the inner layer wiring 52 on the back surface 20 b side in the core layer 20. In this way, a stacked body 168 is configured in which the metal plate 166, the buildup layer 30, the inner layer wiring 51, the core layer 20, the inner layer wiring 52, the buildup layer 30, and the metal plate 167 are sequentially stacked from the top.
　続いて、図４（ｄ）に示されるように、積層体１６８の積層方向から加圧しつつ加熱することにより積層体１６８を一体化する。具体的には、積層体１６８を加圧することにより、ビルドアップ層３０を構成する樹脂を流動させて内層配線５１の間を埋め込むと共に、ビルドアップ層４０を構成する樹脂を流動させて内層配線５２の間を埋め込む。そして、積層体１６８を加熱することにより、ビルドアップ層３０、４０を硬化して積層体１６８を一体化する。 Subsequently, as shown in FIG. 4D, the laminate 168 is integrated by heating while pressing from the lamination direction of the laminate 168. Specifically, by pressurizing the laminate 168, the resin constituting the buildup layer 30 is caused to flow to embed between the inner layer wirings 51, and the resin constituting the buildup layer 40 is caused to flow to cause the inner layer wirings 52 to flow. Embed between. And the buildup layers 30 and 40 are hardened by heating the laminated body 168, and the laminated body 168 is integrated.
　次に、図５（ａ）に示されるように、レーザ等により、金属板１６６、ビルドアップ層３０を貫通して内層配線５１に達する貫通孔９１ａを形成する。同様に、図５（ａ）とは別断面において、図１に示されるように、金属板１６７、ビルドアップ層４０を貫通して内層配線５２に達する貫通孔１０１ａを形成する。 Next, as shown in FIG. 5A, a through hole 91a that penetrates the metal plate 166 and the buildup layer 30 and reaches the inner layer wiring 51 is formed by a laser or the like. Similarly, as shown in FIG. 1, a through hole 101 a that penetrates the metal plate 167 and the buildup layer 40 and reaches the inner layer wiring 52 is formed in a cross section different from FIG.
　そして、図５（ｂ）に示されるように、無電解メッキや電気メッキ等でいわゆるフィルドメッキを行い、貫通孔９１ａ、１０１ａを金属メッキ１６９で埋め込む。これにより、ビルドアップ層３０、４０に形成された貫通孔９１ａ、１０１ａに埋め込まれた金属メッキ１６９にて貫通電極９１ｂおよび図１に示した貫通電極１０１ｂが構成される。また、貫通孔９１ａ、１０１ａに貫通電極９１ｂ、１０１ｂが埋め込まれたフィルドビア９１、１０１が形成される。なお、次の図５（ｃ）以降では、金属板１６６および金属メッキ１６９をまとめて１層として示してある。 Then, as shown in FIG. 5B, so-called filled plating is performed by electroless plating, electroplating, or the like, and the through holes 91a and 101a are embedded with metal plating 169. Thus, the through electrode 91b and the through electrode 101b shown in FIG. 1 are configured by the metal plating 169 embedded in the through holes 91a and 101a formed in the buildup layers 30 and 40. Further, filled vias 91 and 101 in which through electrodes 91b and 101b are embedded in the through holes 91a and 101a are formed. In FIG. 5C and subsequent figures, the metal plate 166 and the metal plating 169 are collectively shown as one layer.
　続いて、図５（ｃ）に示されるように、金属板１６６上に図示しないレジストを配置する。そして、レジストをマスクとしてウェットエッチング等を行って金属板１６６をパターニングすることにより、表層配線６１～６３および表層導体６４ａを形成する。このため、表層配線６１～６３と表層導体６４ａとは、ビルドアップ層３０の表面３０ａからの高さが等しくなる。 Subsequently, as shown in FIG. 5C, a resist (not shown) is placed on the metal plate 166. Then, wet etching or the like is performed using the resist as a mask to pattern the metal plate 166, thereby forming the surface layer wirings 61 to 63 and the surface layer conductor 64a. For this reason, the surface layer wirings 61 to 63 and the surface layer conductor 64a have the same height from the surface 30a of the buildup layer 30.
　同様に、金属板１６７上に図示しないレジストを配置し、レジストをマスクとしてウェットエッチング等を行って金属板１６７をパターニングすることにより、表層配線７１、７２を形成する。 Similarly, a resist (not shown) is arranged on the metal plate 167, and the metal plate 167 is patterned by performing wet etching or the like using the resist as a mask, thereby forming the surface layer wirings 71 and 72.
　つまり、本実施形態では、表層配線６１～６３は、金属板１６６および金属メッキ１６９を有する構成とされ、表層配線７１、７２は、金属板１６７および金属メッキ１６９を有する構成とされている。なお、表層導体６４ａは、内層配線５１と電気的に接続されるものではなく、内層配線５１との間にフィルドビア９１が形成されないため、金属板１６６のみで構成されている。 That is, in the present embodiment, the surface layer wirings 61 to 63 are configured to have the metal plate 166 and the metal plating 169, and the surface layer wirings 71 and 72 are configured to include the metal plate 167 and the metal plating 169. Note that the surface layer conductor 64 a is not electrically connected to the inner layer wiring 51, and the filled via 91 is not formed between the inner layer wiring 51, and thus is constituted only by the metal plate 166.
　次に、図６（ａ）に示されるように、ビルドアップ層３０、４０の表面３０ａ、４０ａにそれぞれソルダーレジスト１１０を配置して適宜パターニングする。これにより、表層導体６４ａおよびソルダーレジスト１１０にて型踏み部６４が形成された多層基板１０が製造される。なお、型踏み部６４は、上記のように、型踏み部６４におけるソルダーレジスト１１０のビルドアップ層３０の表面３０ａからの高さが、ソルダーレジスト１１０のうち表面パターン６３を覆う部分のビルドアップ層３０の表面３０ａからの高さと等しくされている。 Next, as shown in FIG. 6A, the solder resist 110 is disposed on the surfaces 30a and 40a of the buildup layers 30 and 40, respectively, and patterned appropriately. Thereby, the multilayer substrate 10 in which the mold step 64 is formed by the surface layer conductor 64a and the solder resist 110 is manufactured. Note that, as described above, the mold step portion 64 is such that the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is a part of the build-up layer that covers the surface pattern 63 in the solder resist 110. 30 is equal to the height from the surface 30a.
　続いて、図６（ｂ）に示されるように、はんだ１３０を介して電子部品１２１～１２３をランド６１に搭載する。そして、パワー素子１２１および制御素子１２２とランド６２との間でワイヤボンディングを行い、パワー素子１２１および制御素子１２２とランド６２とを電気的に接続する。 Subsequently, as shown in FIG. 6B, the electronic components 121 to 123 are mounted on the land 61 via the solder 130. Then, wire bonding is performed between the power element 121 and the control element 122 and the land 62, and the power element 121 and the control element 122 and the land 62 are electrically connected.
　その後、図６（ｃ）に示されるように、ランド６１、６２および電子部品１２１～１２３が封止されるように、金型を用いたトランスファーモールド法やコンプレッションモールド法等によってモールド樹脂１５０を形成する。 Thereafter, as shown in FIG. 6C, a molding resin 150 is formed by a transfer molding method using a mold or a compression molding method so that the lands 61 and 62 and the electronic components 121 to 123 are sealed. To do.
　具体的には、一面２００ａにモールド樹脂１５０の外形を構成する凹部２０１が形成されている金型２００を用意し、凹部２０１内に電子部品１２１～１２３が配置されるように、一面２００ａを多層基板１０の一面１０ａ側に圧接する。 Specifically, a mold 200 is prepared in which a recess 201 constituting the outer shape of the mold resin 150 is formed on one surface 200a, and the surface 200a is multilayered so that the electronic components 121 to 123 are disposed in the recess 201. The substrate 10 is in pressure contact with the one surface 10a side.
　このとき、上記のように、型踏み部６４におけるソルダーレジスト１１０のビルドアップ層３０の表面３０ａからの高さは、ソルダーレジスト１１０のうち表面パターン６３を覆う部分のビルドアップ層３０の表面３０ａからの高さと等しくされている。このため、型踏み部６４が金型２００に圧接される。また、型踏み部６４におけるソルダーレジスト１１０のビルドアップ層３０の表面３０ａからの高さは、周方向において一定とされているため、型踏み部６４と金型２００との間に隙間は形成されない。 At this time, as described above, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is from the surface 30a of the build-up layer 30 that covers the surface pattern 63 in the solder resist 110. Is equal to the height. For this reason, the mold step 64 is pressed against the mold 200. Moreover, since the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is constant in the circumferential direction, no gap is formed between the mold step 64 and the mold 200. .
　そして、多層基板１０と金型２００の凹部２０１との間の空間にモールド樹脂１５０を充填することにより、上記電子装置が製造される。 And the said electronic device is manufactured by filling the space between the multilayer substrate 10 and the recessed part 201 of the metal mold | die 200 with the mold resin 150. FIG.
　なお、金型２００の一面２００ａを多層基板１０の一面１０ａ側に圧接した際、ソルダーレジスト１１０のうち表面パターン６３を覆う部分も金型２００に圧接されることになるが、特に問題はない。 Note that when the one surface 200a of the mold 200 is pressed against the one surface 10a side of the multilayer substrate 10, the portion of the solder resist 110 covering the surface pattern 63 is also pressed into the mold 200, but there is no particular problem.
　以上説明したように、多層基板１０には、ビルドアップ層３０の表面３０ａからの高さがソルダーレジスト１１０のうち表面パターン６３を覆う部分のビルドアップ層３０の表面３０ａからの高さ以上とされている型踏み部６４が形成されている。このため、金型２００の一面２００ａを多層基板１０の一面１０ａ側に圧接した際、型踏み部６４が必ず金型２００に圧接される。そして、型踏み部６４は、ランド６１、６２を囲む枠状とされていると共にランド６１、６２と表面パターン６３との間に形成されている。したがって、多層基板１０と金型２００の凹部２０１との間の空間からモールド樹脂１５０が流出することを抑制でき、表面パターン６３のうちソルダーレジスト１１０の開口部１１０ａから露出する部分がモールド樹脂１５０で覆われることを抑制できる。 As described above, in the multilayer substrate 10, the height from the surface 30 a of the buildup layer 30 is set to be equal to or higher than the height from the surface 30 a of the buildup layer 30 in the part of the solder resist 110 that covers the surface pattern 63. The mold step 64 is formed. For this reason, when the one surface 200 a of the mold 200 is pressed against the one surface 10 a side of the multilayer substrate 10, the mold step 64 is always pressed against the mold 200. The mold step 64 has a frame shape surrounding the lands 61 and 62 and is formed between the lands 61 and 62 and the surface pattern 63. Therefore, it is possible to suppress the mold resin 150 from flowing out of the space between the multilayer substrate 10 and the concave portion 201 of the mold 200, and the portion of the surface pattern 63 exposed from the opening 110 a of the solder resist 110 is the mold resin 150. It can suppress being covered.
　（第２実施形態）
　本開示の第２実施形態について説明する。本実施形態は、第１実施形態に対して表層導体６４ａの形状を変更したものであり、その他に関しては第１実施形態と同様であるため、ここでは説明を省略する。 (Second Embodiment)
A second embodiment of the present disclosure will be described. In the present embodiment, the shape of the surface conductor 64a is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment, and thus the description thereof is omitted here.
　図７に示されるように、本実施形態の表層導体６４ａは、厚さ方向における断面において、ビルドアップ層３０側と反対側の角部が丸められている。これに対し、ランド６１、６２および表面パターン６３は、電子部品１２１～１２３と外部回路とを電気的に接続する部分であり、電流容量を大きくすることが好ましいため、図１に示されるように、厚さ方向における断面が矩形状とされている。つまり、ランド６１、６２および表面パターン６３は、厚さ方向における断面において、ビルドアップ層３０側と反対側の断面の角部が直角とされている。なお、図７は、図１中の領域Ａに相当する拡大図である。 As shown in FIG. 7, the surface conductor 64a of the present embodiment has a rounded corner on the opposite side to the buildup layer 30 side in the cross section in the thickness direction. On the other hand, the lands 61 and 62 and the surface pattern 63 are portions for electrically connecting the electronic components 121 to 123 and the external circuit, and it is preferable to increase the current capacity. Therefore, as shown in FIG. The cross section in the thickness direction is rectangular. That is, the lands 61 and 62 and the surface pattern 63 have a right-angled corner in the cross section opposite to the buildup layer 30 side in the cross section in the thickness direction. FIG. 7 is an enlarged view corresponding to the area A in FIG.
　これによれば、図６（ｃ）の工程において、金型２００の一面２００ａを型踏み部６４に圧接したとき、表層導体６４ａの角部に応力が集中することを抑制できる。このため、ソルダーレジスト１１０にクラックが発生することを抑制できる。 According to this, when the one surface 200a of the mold 200 is pressed against the mold step 64 in the process of FIG. 6C, it is possible to suppress stress concentration on the corners of the surface conductor 64a. For this reason, generation | occurrence | production of a crack in the soldering resist 110 can be suppressed.
　（他の実施形態）
　本開示は上記した実施形態に限定されるものではなく、請求の範囲に記載した範囲内において適宜変更が可能である。 (Other embodiments)
The present disclosure is not limited to the above-described embodiment, and can be appropriately changed within the scope described in the claims.
　例えば、上記各実施形態において、コア層２０およびビルドアップ層３０、４０として、プリプレグの単層から構成されるものを図示しているが、コア層２０およびビルドアップ層３０、４０をプリプレグの多層から構成されるものとしてもよい。 For example, in each of the above embodiments, the core layer 20 and the buildup layers 30 and 40 are illustrated as being composed of a single prepreg layer. It is good also as what is comprised from.
　また、上記各実施形態において、型踏み部６４におけるソルダーレジスト１１０のビルドアップ層３０の表面３０ａからの高さをソルダーレジスト１１０のうち表面パターン６３を覆う部分のビルドアップ層３０の表面３０ａからの高さ以上とする場合には、次のようにすればよい。例えば、図５（ｃ）の工程において、表面パターン６３および表層導体６４ａをパターニングする際、表層導体６４ａ上のみに金属メッキ等を形成すればよい。 Moreover, in each said embodiment, the height from the surface 30a of the buildup layer 30 of the solder resist 110 in the type | mold step part 64 is made from the surface 30a of the buildup layer 30 of the part which covers the surface pattern 63 among the solder resists 110. When the height is to be exceeded, the following may be performed. For example, when the surface pattern 63 and the surface layer conductor 64a are patterned in the step of FIG. 5C, metal plating or the like may be formed only on the surface layer conductor 64a.
　また、上記各実施形態では、型踏み部６４は、ビルドアップ層３０の表面３０ａからの高さが周方向において一定とされているものを説明したが、次のようにしてもよい。すなわち、型踏み部６４を構成するソルダーレジスト１１０に窪み部を形成し、型踏み部６４のうち窪み部が形成されている部分の高さが他の部分の高さより僅かに低くされていてもよい。これによれば、モールド樹脂１５０を形成する際にモールド樹脂１５０中に生成する可能性があるボイドを窪み部から排出することができる。なお、このような型踏み部６４を構成する場合には、窪み部からモールド樹脂１５０が流出したとしても、表面パターン６３のうちソルダーレジスト１１０から露出する部分がモールド樹脂１５０で覆われない場所に窪み部を形成することが好ましい。 Further, in each of the above embodiments, the mold step 64 has been described in which the height from the surface 30a of the buildup layer 30 is constant in the circumferential direction. That is, even if a depression is formed in the solder resist 110 constituting the mold step 64, the height of the portion where the depression is formed in the mold depression 64 is slightly lower than the height of the other portions. Good. According to this, when forming mold resin 150, the void which may be generated in mold resin 150 can be discharged from a hollow part. In the case where such a mold step portion 64 is configured, even if the mold resin 150 flows out of the recess portion, a portion of the surface pattern 63 exposed from the solder resist 110 is not covered with the mold resin 150. It is preferable to form a depression.
　上記のように、本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 As described above, the present disclosure has been described based on the embodiments, but it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims (4)

  1. 　表面（２０ａ）を有するコア層（２０）と、
    　前記コア層の前記表面に形成された内層配線（５１）と、
    　前記コア層の前記表面に前記内層配線を覆う状態で配置されたビルドアップ層（３０）と、
    　前記ビルドアップ層のうち前記コア層と反対側の一面（３０ａ）に形成され、電子部品（１２１～１２３）が搭載されるランド（６１）と、
    　前記ビルドアップ層の前記一面に形成され、前記内層配線を介して前記ランドと電気的に接続されると共に外部回路と電気的に接続される表面パターン（６３）と、
    　前記表面パターンを覆うと共に、前記表面パターンの一部を露出させる開口部（１１０ａ）が形成された保護膜（１１０）と、を有する多層基板において、
    　前記ビルドアップ層の前記一面には、前記ランドおよび前記表面パターンと絶縁され、前記ランドを囲むと共に前記ランドと前記表面パターンとの間に形成された枠状の表層導体（６４ａ）と、前記表層導体を覆う前記保護膜と、を有する型踏み部（６４）が形成されており、
    　前記型踏み部における前記保護膜の前記ビルドアップ層の前記一面からの高さは、前記保護膜のうち前記表面パターンを覆う部分の前記ビルドアップ層の前記一面からの高さ以上とされている多層基板。     A core layer (20) having a surface (20a);
    An inner wiring (51) formed on the surface of the core layer;
    A buildup layer (30) disposed in a state of covering the inner layer wiring on the surface of the core layer;
    A land (61) formed on one side (30a) of the buildup layer opposite to the core layer, on which electronic components (121 to 123) are mounted;
    A surface pattern (63) formed on the one surface of the build-up layer, electrically connected to the land via the inner layer wiring and electrically connected to an external circuit;
    A multilayer substrate having a protective film (110) that covers the surface pattern and has an opening (110a) that exposes a part of the surface pattern.
    The one surface of the build-up layer is insulated from the land and the surface pattern, surrounds the land and is formed between the land and the surface pattern, and a frame-shaped surface conductor (64a), and the surface layer A mold step (64) having the protective film covering the conductor is formed,
    The height of the protective film from the one surface of the build-up layer in the stepping portion is equal to or higher than the height of the part of the protective film covering the surface pattern from the one surface of the build-up layer. Multilayer board.
  2. 　前記表層導体は、前記表層導体の厚さ方向における断面において、前記ビルドアップ層側と反対側の角部が丸められており、
    　前記ランドおよび前記表面パターンは、前記ランドおよび前記表面パターンの厚さ方向における断面において、前記ビルドアップ層側と反対側の角部が直角とされている請求項１に記載の多層基板。     In the surface layer conductor, in the cross section in the thickness direction of the surface layer conductor, the corner on the opposite side to the buildup layer side is rounded,
    2. The multilayer substrate according to claim 1, wherein the land and the surface pattern have a right-angle corner on the opposite side to the buildup layer side in a cross section in the thickness direction of the land and the surface pattern.
  3. 　請求項１または２に記載の多層基板と、
    　前記ランドに搭載された前記電子部品と、
    　前記電子部品、前記ランドおよび前記型踏み部における前記保護膜の内縁側を封止するモールド樹脂（１５０）と、を備える電子装置。     The multilayer substrate according to claim 1 or 2,
    The electronic component mounted on the land;
    An electronic device comprising: a mold resin (150) for sealing an inner edge side of the protective film in the electronic component, the land, and the stepping portion.
  4. 　請求項３に記載の電子装置の製造方法において、
    　前記多層基板を用意することと、
    　前記多層基板における前記ランドに前記電子部品を搭載することと、
    　前記電子部品、前記ランドおよび前記型踏み部における前記保護膜の内縁側を封止する前記モールド樹脂を形成することと、を有し、
    　前記モールド樹脂を形成することでは、一面（２００ａ）に凹部（２０１）が形成された金型（２００）を用意し、前記凹部内に前記電子部品が配置されるように前記金型の一面を前記型踏み部に圧接した後、前記多層基板と前記凹部との間の空間に前記モールド樹脂を充填する電子装置の製造方法。     In the manufacturing method of the electronic device according to claim 3,
    Providing the multilayer substrate;
    Mounting the electronic component on the land in the multilayer substrate;
    Forming the mold resin that seals an inner edge side of the protective film in the electronic component, the land, and the mold step portion, and
    In forming the mold resin, a mold (200) having a recess (201) formed on one surface (200a) is prepared, and the one surface of the mold is arranged so that the electronic component is disposed in the recess. A method of manufacturing an electronic device, wherein the mold resin is filled in a space between the multilayer substrate and the recess after being pressed against the mold step.
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