WO2014174863A1 - Field effect transistor - Google Patents

Field effect transistor Download PDF

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Publication number
WO2014174863A1
WO2014174863A1 PCT/JP2014/051817 JP2014051817W WO2014174863A1 WO 2014174863 A1 WO2014174863 A1 WO 2014174863A1 JP 2014051817 W JP2014051817 W JP 2014051817W WO 2014174863 A1 WO2014174863 A1 WO 2014174863A1
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basic
transistor
field effect
effect transistor
transistors
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PCT/JP2014/051817
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French (fr)
Japanese (ja)
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弘善 伊奈
佳宏 上溪
大佑 栗田
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the present invention relates to a field effect transistor, and more particularly to a heterojunction field effect transistor having a gallium nitride (GaN) -based heterojunction.
  • GaN gallium nitride
  • GaN-based semiconductors used as field effect transistors have characteristics such as a large band gap, a high breakdown electric field, and a high electron saturation drift velocity. It is also possible to use a two-dimensional electron gas generated at the heterojunction interface. Therefore, GaN-based semiconductors are attracting attention as materials for realizing semiconductor devices that are excellent in terms of high-temperature operation, high-speed switching operation, high-power operation, and the like.
  • GaN-based semiconductors are more expensive and costly than conventional Si. Therefore, conventionally, efforts have been made to reduce costs by epitaxially growing GaN on Si substrates.
  • heterojunction field effect transistors using GaN-based semiconductors have been developed, and various devices have been made to obtain high transistor characteristics.
  • the inventor has eagerly developed a field effect transistor using a GaN-on-Si substrate in which GaN is epitaxially grown on an Si wafer, and a device in which a plurality of basic transistors are formed in a high-current device. It was found that the basic transistor located outside the chip is vulnerable to off-bias testing.
  • a device for large current is usually formed by arranging a plurality of basic transistors as a basic configuration in parallel, but when an off-bias life test was performed using the created device chip, in most field effect transistors, Breakage marks due to dielectric breakdown were observed in the portion located near the outer periphery of the element chip.
  • a GaN-on-Si substrate obtained by epitaxially growing GaN with different lattice constants on a Si wafer after forming a field effect transistor, the Si wafer is diced into chips, so that the GaN is formed at a portion near the chip edge.
  • the life of the dielectric breakdown is shortened due to a change in transistor characteristics due to a change in how stress is applied.
  • Patent Document 1 in order to ensure a sufficient life even at a portion close to the chip end, a heat treatment exceeding 1000 ° C. is necessary, and there is a problem that it is difficult to produce a stable transistor by a heat treatment equivalent to that during crystal growth. is there.
  • Patent Document 2 in order to ensure a sufficient life even at a portion close to the end of the chip, the impurity concentration is increased, but there is a problem that the crystallinity of GaN is lowered.
  • an object of the present invention is to provide a field effect transistor capable of extending the lifetime of the entire device by increasing the insulation resistance of the basic transistor at the outer periphery of the chip.
  • the field effect transistor of the present invention is A substrate, A channel layer formed on the substrate and on which carriers run; A carrier supply layer formed on the channel layer and supplying the carrier to the channel layer; A source electrode joined to at least the carrier supply layer of the carrier supply layer or the channel layer; A drain electrode disposed opposite to the source electrode and joined to at least the carrier supply layer of the carrier supply layer or the channel layer; A gate electrode disposed between the source electrode and the drain electrode for controlling the traveling of the carriers in the channel layer; A plurality of basic transistors are formed by the channel layer, the carrier supply layer, the source electrode, the drain electrode, and the gate electrode, Of the plurality of basic transistors, the outermost basic transistor has a higher insulation resistance than the other basic transistors.
  • the outermost basic transistor has higher insulation resistance than the other basic transistors by increasing the distance between the gate electrode and the drain electrode.
  • the outermost basic transistor of the plurality of basic transistors is a diode-connected transistor in which the gate electrode and the source electrode of another basic transistor are connected.
  • the outermost basic transistor serving as the diode-connected transistor has higher insulation resistance than the other basic transistors by increasing the distance between the gate electrode and the drain electrode.
  • the substrate is an Si substrate.
  • the basic transistor is a heterojunction field effect transistor.
  • the lifetime of the entire element can be extended by increasing the insulation resistance of the outermost basic transistor of the plurality of basic transistors as compared with the other basic transistors.
  • a field effect transistor can be realized.
  • FIG. 1 is a plan view of a field effect transistor according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the main part of the field effect transistor.
  • FIG. 3 is a plan view of a field effect transistor according to the second embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of the main part of the outermost periphery of the field effect transistor.
  • FIG. 1 shows a plan view of a field effect transistor 1 according to a first embodiment of the present invention.
  • the field effect transistor 1 of the first embodiment includes a nitride semiconductor layer (not shown) stacked on a substrate (not shown), and substantially parallel to and spaced from each other.
  • the plurality of linear drain electrodes 2 provided, the plurality of gate electrodes 3 provided so as to surround the outer sides of the drain electrodes 2, and the intervals so as to surround the outer sides of the gate electrodes 3.
  • an open source electrode 4 Further, in the field effect transistor 1, the drain electrode 2 is connected to the drain pad 21 via a drain wiring (not shown), and the source electrode 4 is connected to the source pad 41 via a source wiring (not shown). ing.
  • the field effect transistor 1 is a single basic transistor surrounded by a dotted line 5 and has a structure in which a plurality of basic transistors are connected in parallel to handle a large current.
  • FIG. 2 shows a cross-sectional view of the main part of the basic transistor of the field effect transistor.
  • a buffer layer 102 made of undoped AlGaN, a channel layer 103 made of undoped GaN, and a carrier supply layer 104 made of undoped AlGaN are formed on an Si substrate 101.
  • 2DEG two-dimensional electron gas
  • the source electrode 4 and the drain electrode 2 are formed on the carrier supply layer 104 with a space therebetween.
  • a gate electrode 3 is formed on the carrier supply layer 104 between the source electrode 4 and the drain electrode 2 and on the source electrode 4 side.
  • the source electrode 4 and the drain electrode 2 are ohmic electrodes, and the gate electrode 3 is a Schottky electrode.
  • an HFET Hetero-junction field
  • Effect Transistor Heterojunction field effect transistor
  • the active region is a carrier between the source electrode 4 and the drain electrode 2 due to a voltage applied to the gate electrode 3 disposed between the source electrode 4 and the drain electrode 2 on the carrier supply layer 104.
  • This is a region of the nitride semiconductor layer (channel layer 103, carrier supply layer 104) through which flows.
  • An insulating film 105 made of SiO 2 is formed on the carrier supply layer 104 excluding the region where the source electrode 4, the drain electrode 2, and the gate electrode 3 are formed in order to protect the carrier supply layer 104.
  • a channel is formed by generating a two-dimensional electron gas (2DEG) formed at the interface between the channel layer 103 and the carrier supply layer 104.
  • This channel is controlled by applying a voltage to the gate electrode 3 to turn on and off the HFET having the source electrode 4, the drain electrode 2, and the gate electrode 3.
  • 2DEG two-dimensional electron gas
  • This HFET when a negative voltage is applied to the gate electrode 3, a depletion layer is formed in the channel layer 103 under the gate electrode 3 and the OFF state is set, while the gate electrode 3 is turned off when the voltage of the gate electrode 3 is zero.
  • 3 is a normally-on type transistor in which the depletion layer disappears in the lower channel layer 103 and is turned on.
  • the distance Lgd between the gate electrode 3 and the drain electrode 2 of the basic transistor is 10 ⁇ m.
  • the basic transistor located on the outermost side (the portion surrounded by the dotted line 6 in FIG. 1) has a gate electrode 3 and a drain electrode 2 which are more than the other basic transistors.
  • the above basic transistor was subjected to a bias test at a temperature of 150 ° C., a source electrode of 0 V, a substrate potential of 0 V, a drain electrode of 600 V, and a gate electrode of ⁇ 10 V.
  • the life of the basic transistor at the outermost periphery is made relatively long, so that it can be prevented from being destroyed quickly, thereby realizing a long-lived high-current element. be able to.
  • the outermost basic transistor surrounded by the dotted line 6 among the plurality of basic transistors is configured to have higher insulation resistance than other basic transistors. The lifetime of the entire device can be extended.
  • the insulation distance can be increased and the insulation resistance can be improved.
  • the cost can be suppressed by using a GaN-on-Si substrate in which GaN is epitaxially grown on a Si wafer.
  • the generation of the two-dimensional electron gas (2DEG) formed at the heterojunction interface between the channel layer 103 and the carrier supply layer 104 can realize the field effect transistor 1 having high electron mobility and capable of high speed operation. .
  • FIG. 3 is a plan view of a field effect transistor 100 according to the second embodiment of the present invention.
  • the field effect transistor 100 of the second embodiment has the same configuration as the field effect transistor 1 of the first embodiment except for the basic transistor located outside.
  • the field effect transistor 100 of the second embodiment is one basic transistor in a portion surrounded by a dotted line 5 and has a structure in which a plurality of basic transistors are connected in parallel so as to handle a large current. .
  • the outermost basic transistor (portion surrounded by the dotted line 106) among the plurality of basic transistors is a diode-connected transistor in which the gate electrode 30 is connected to the source electrode 4 of the adjacent basic transistor. Yes.
  • the gate electrode 30 of the basic transistor surrounded by the dotted line 106 is in Schottky junction with the AlGaN layer 104 and is formed to be a Schottky diode.
  • the gate electrode 30 is not connected to a wiring for applying a gate voltage. In FIG. 3, the wiring between the gate electrode 30 of the outermost basic transistor and the source electrode 4 of another basic transistor is not shown.
  • FIG. 4 is a cross-sectional view of the main part of the outermost basic transistor of the field effect transistor.
  • the recess 40 is provided on the left side of the gate electrode 3 so that the two-dimensional electron gas (2DEG) of the outermost basic transistor is not connected to the source electrode of another basic transistor.
  • the drain-gate distance Lgd in the outermost basic transistor surrounded by the dotted line 106 can be made wider than in the case of other basic transistors surrounded by the dotted line 5. Therefore, the breakdown voltage can be increased.
  • the distance between the drain and the gate is relatively increased in the outermost peripheral portion (the outermost basic transistor surrounded by the dotted line 106), thereby quickly breaking down. Since this can be prevented, a long-life high-current element can be realized. Further, the change in the manufacturing process is small and can be realized only by changing the photoetching mask.
  • the GaN FET when a high voltage is applied to the source electrode 4, it becomes possible to flow a current to the drain electrode 2 side, and the function similar to that of the body diode seen in Si-IGBT (insulated gate bipolar transistor) is achieved. It is possible to have it.
  • the field effect transistor 100 of the second embodiment has the same effect as the field effect transistor 1 of the first embodiment.
  • the outermost basic transistor to be the diode-connected transistor has a longer insulation distance by increasing the distance between the gate electrode 3 and the drain electrode 2 than the other basic transistors, thereby increasing the insulation resistance. it can.
  • the substrate of the field effect transistor according to the present invention includes Si.
  • the substrate is not limited to a sapphire substrate or SiC substrate, a nitride semiconductor layer may be grown on the sapphire substrate or SiC substrate, or an AlGaN layer is grown on the GaN substrate.
  • a nitride semiconductor layer may be grown on a semiconductor substrate.
  • a buffer layer may be formed between the substrate and the nitride semiconductor layer, or a hetero improvement layer may be formed between the first semiconductor layer and the second semiconductor layer of the nitride semiconductor layer.
  • the HFET having the recess structure in which the ohmic electrode reaches the GaN layer has been described.
  • the ohmic electrode that becomes the source electrode and the drain electrode is formed on the undoped AlGaN layer without forming the recess.
  • the present invention may be applied to the formed HFET.
  • the nitride semiconductor device of the present invention is not limited to an HFET using 2DEG, but has a field effect of other configurations such as a MIS (Metal Insulator Semiconductor) FET, a MOS (Metal Oxide Semiconductor) FET, and a MES (Metal Semiconductor) FET. Even if it is a transistor, the same effect is acquired.
  • a MIS-HFET structure having an insulating film between the gate electrode and the semiconductor may be used.
  • the normally-on type HFET has been described.
  • the present invention may be applied to a normally-off type nitride semiconductor device.
  • the field effect transistor using the channel layer 103 made of undoped GaN and the carrier supply layer 104 made of undoped AlGaN is described.
  • the channel layer using other semiconductor materials It may be a carrier supply layer, for example, a nitride semiconductor represented by Al x In y Ga 1-xy N (x ⁇ 0, y ⁇ 0, 0 ⁇ x + y ⁇ 1).
  • the field effect transistor of this invention is A substrate 101; A channel layer 103 formed on the substrate 101 and carrying carriers, A carrier supply layer 104 formed on the channel layer 103 and supplying the carriers to the channel layer 103; A source electrode 4 bonded to at least the carrier supply layer 104 of the carrier supply layer 104 or the channel layer 103; A drain electrode 2 disposed opposite to the source electrode 4 and joined to at least the carrier supply layer 104 of the carrier supply layer 104 or the channel layer 103; A gate electrode 3, 30 disposed between the source electrode 4 and the drain electrode 2 for controlling the carrier travel of the channel layer 103; A plurality of basic transistors are formed by the channel layer 103, the carrier supply layer 104, the source electrode 4, the drain electrode 2, and the gate electrodes 3, 30. Among the plurality of basic transistors, the outermost basic transistor has a structure with higher insulation resistance than the other basic transistors.
  • the lifetime of the entire element can be extended by configuring the outermost basic transistor of the plurality of basic transistors to have higher insulation resistance than the other basic transistors.
  • the outermost basic transistor has a higher insulation resistance by increasing the distance between the gate electrodes 3 and 30 and the drain electrode 2 than the other basic transistors. Yes.
  • the outermost basic transistor of the plurality of basic transistors has a longer insulation distance than the other basic transistors by increasing the distance between the gate electrodes 3 and 30 and the drain electrode 2. It can be expanded to increase insulation resistance.
  • the outermost basic transistor of the plurality of basic transistors is a diode-connected transistor in which the gate electrode 30 and the source electrode 4 of another basic transistor are connected.
  • the outermost basic transistor of the plurality of basic transistors is a diode-connected transistor in which the gate electrode 30 and the source electrode 4 of another basic transistor are connected to each other. When a high voltage is applied, current can flow to the drain electrode 2 side.
  • the outermost basic transistor serving as the diode-connected transistor has higher insulation resistance than the other basic transistors by increasing the distance between the gate electrode 30 and the drain electrode 2.
  • the outermost basic transistor serving as a diode-connected transistor is made longer by increasing the distance between the gate electrode 3 and the drain electrode 2 than the other basic transistors, thereby increasing the resistance. Insulation can be enhanced.
  • the substrate is the Si substrate 101.
  • the cost is reduced by using the GaN-on-Si substrate in which GaN is epitaxially grown on the Si wafer. Can be suppressed.
  • the basic transistor is a heterojunction field effect transistor.
  • a field effect transistor that has high electron mobility and can operate at high speed by generating a two-dimensional electron gas (2DEG) formed at the heterojunction interface between the channel layer 103 and the carrier supply layer 104. Can be realized.
  • 2DEG two-dimensional electron gas

Abstract

Using a channel layer, a carrier supply layer, a source electrode (4), drain electrodes (2), and gate electrodes (3), a plurality of basic transistors are formed. The outermost basic transistor surrounded by a dotted line (6) among the plurality of basic transistors is configured to be of a higher insulation resistance than the other basic transistors. As a result, by increasing insulation resistance of the basic transistor on the chip outer peripheral portion, a field effect transistor is provided that is capable of extending the life of the entire element

Description

電界効果トランジスタField effect transistor
　この発明は、電界効果トランジスタに関し、詳しくは、窒化ガリウム(ＧaＮ)系のヘテロ接合を有するヘテロ接合電界効果トランジスタなどに関する。 The present invention relates to a field effect transistor, and more particularly to a heterojunction field effect transistor having a gallium nitride (GaN) -based heterojunction.
　電界効果トランジスタとして用いられるＧaＮ系半導体は、バンドギャップが大きく、絶縁破壊電界が高く、電子の飽和ドリフト速度が大きいといった特性がある。また、ヘテロ接合界面に発生する２次元電子ガスを利用することが可能である。そのため、ＧaＮ系半導体は、高温動作、高速スイッチング動作、大電力動作等の点で優れる半導体素子を実現する材料として期待を集めている。 GaN-based semiconductors used as field effect transistors have characteristics such as a large band gap, a high breakdown electric field, and a high electron saturation drift velocity. It is also possible to use a two-dimensional electron gas generated at the heterojunction interface. Therefore, GaN-based semiconductors are attracting attention as materials for realizing semiconductor devices that are excellent in terms of high-temperature operation, high-speed switching operation, high-power operation, and the like.
　その一方で、従来用いられているＳiに比べてＧaＮ系半導体は高価であり、コストがかかることが分かっている。そのため、従来より、Ｓi基板上にＧaＮをエピタキシャル成長させることでコストを抑える取り組みがなされている。 On the other hand, it has been found that GaN-based semiconductors are more expensive and costly than conventional Si. Therefore, conventionally, efforts have been made to reduce costs by epitaxially growing GaN on Si substrates.
　そして、ＧaＮ系半導体を用いたヘテロ接合電界効果トランジスタの開発が行われ、高いトランジスタ特性を得るため、いろいろな工夫がなされている。 And, heterojunction field effect transistors using GaN-based semiconductors have been developed, and various devices have been made to obtain high transistor characteristics.
　例えば、従来の第１の電界効果トランジスタとしては、ドレイン電極付近のチャネル層のｎ型不純物濃度をドレイン電極直下より低くすることで絶縁破壊しにくい構造としたものがある(例えば、特開２０１１－７１３０７号公報(特許文献１)参照)。 For example, as a conventional first field effect transistor, there is a structure in which an n-type impurity concentration in a channel layer near the drain electrode is made lower than that immediately below the drain electrode so that dielectric breakdown is difficult (for example, Japanese Patent Laid-Open No. 2011-2011 No. 71307 (see Patent Document 1).
　また、従来の第２の電界効果トランジスタとしては、バッファ層に炭素を添加して高抵抗化することで絶縁破壊しにくい構造としたものがある(例えば、特開２００７－２５１１４４号公報(特許文献２)参照)。 In addition, as a conventional second field effect transistor, there is a transistor which has a structure in which dielectric breakdown is difficult by adding carbon to the buffer layer to increase resistance (for example, Japanese Patent Application Laid-Open No. 2007-251144 (Patent Document). 2)).
特開２０１１－７１３０７号公報JP 2011-71307 A 特開２００７－２５１１４４号公報JP 2007-251144 A
　こうしたＳiウェハ上にＧaＮをエピタキシャル成長させたＧaＮ-on-Ｓi基板を用いた電界効果トランジスタの開発を本発明者が鋭意行っていたところ、大電流用素子において、複数の基本トランジスタが形成された素子チップの外側に位置する基本トランジスタがオフバイアス試験に対して弱いことを見出した。 The inventor has eagerly developed a field effect transistor using a GaN-on-Si substrate in which GaN is epitaxially grown on an Si wafer, and a device in which a plurality of basic transistors are formed in a high-current device. It was found that the basic transistor located outside the chip is vulnerable to off-bias testing.
　大電流用素子は、通常、基本構成となる基本トランジスタを複数並列に配置することで形成されるが、作成した素子チップを用いてオフバイアス寿命試験を実施したところ、大半の電界効果トランジスタにおいて、素子チップの外周付近に位置する部分で絶縁破壊による破壊痕が見られた。 A device for large current is usually formed by arranging a plurality of basic transistors as a basic configuration in parallel, but when an off-bias life test was performed using the created device chip, in most field effect transistors, Breakage marks due to dielectric breakdown were observed in the portion located near the outer periphery of the element chip.
　これは、同一の基本トランジスタを並列に形成した電界効果トランジスタにおいて、破壊した外周部分はそれ以外の部分に比べ相対的に寿命が短いということである。 This means that in a field effect transistor in which the same basic transistors are formed in parallel, the destroyed outer peripheral portion has a relatively short life compared to other portions.
　Ｓiウェハ上に格子定数の異なるＧaＮをエピ成長させたＧaＮ-on-Ｓi基板では、電界効果トランジスタを形成した後、Ｓiウェハをダイシングしてチップ化することで、チップ端に近い部分でＧaＮに対して応力のかかり方が変わるために、トランジスタ特性が変化して絶縁破壊に対する寿命が短くなったと考えられる。 In a GaN-on-Si substrate obtained by epitaxially growing GaN with different lattice constants on a Si wafer, after forming a field effect transistor, the Si wafer is diced into chips, so that the GaN is formed at a portion near the chip edge. On the other hand, it is considered that the life of the dielectric breakdown is shortened due to a change in transistor characteristics due to a change in how stress is applied.
　上記特許文献１や特許文献２に係る電界効果トランジスタの構造では、チップ内の複数の基本トランジスタを均一に形成することになり、チップ端に近い部分の絶縁破壊に対する寿命が短いという問題は残ってしまう。 In the structure of the field effect transistor according to Patent Document 1 or Patent Document 2 described above, a plurality of basic transistors in the chip are uniformly formed, and there remains a problem that the life against dielectric breakdown near the chip end is short. End up.
　また、上記特許文献１においてチップ端に近い部分でも十分な寿命を確保するには、１０００℃を超える熱処理が必要となり、結晶成長時と同等の熱処理により安定したトランジスタ作製が困難になるという問題がある。 Further, in Patent Document 1, in order to ensure a sufficient life even at a portion close to the chip end, a heat treatment exceeding 1000 ° C. is necessary, and there is a problem that it is difficult to produce a stable transistor by a heat treatment equivalent to that during crystal growth. is there.
　また、上記特許文献２においてチップ端に近い部分でも十分な寿命を確保するためには、不純物濃度を高めることになるが、ＧaＮの結晶性が低下するという問題がある。 Further, in Patent Document 2, in order to ensure a sufficient life even at a portion close to the end of the chip, the impurity concentration is increased, but there is a problem that the crystallinity of GaN is lowered.
　そこで、この発明の課題は、チップ外周部分での基本トランジスタの耐絶縁性を高めることによって、素子全体での寿命を長くできる電界効果トランジスタを提供することにある。 Therefore, an object of the present invention is to provide a field effect transistor capable of extending the lifetime of the entire device by increasing the insulation resistance of the basic transistor at the outer periphery of the chip.
　上記課題を解決するため、この発明の電界効果トランジスタは、
　基板と、
　上記基板上に形成され、キャリアが走行するチャネル層と、
　上記チャネル層上に形成され、上記チャネル層に上記キャリアを供給するキャリア供給層と、
　上記キャリア供給層または上記チャネル層のうちの少なくとも上記キャリア供給層に接合されたソース電極と、
　上記ソース電極に対向して配置され、上記キャリア供給層または上記チャネル層のうちの少なくとも上記キャリア供給層に接合されたドレイン電極と、
　上記ソース電極と上記ドレイン電極との間に配置され、上記チャネル層の上記キャリアの走行を制御するためのゲート電極と
を備え、
　上記チャネル層、上記キャリア供給層、上記ソース電極、上記ドレイン電極および上記ゲート電極で複数の基本トランジスタが形成されており、
　上記複数の基本トランジスタのうちの最外周の基本トランジスタは、それ以外の基本トランジスタよりも耐絶縁性を高くした構成をしていることを特徴とする。 In order to solve the above problems, the field effect transistor of the present invention is
A substrate,
A channel layer formed on the substrate and on which carriers run;
A carrier supply layer formed on the channel layer and supplying the carrier to the channel layer;
A source electrode joined to at least the carrier supply layer of the carrier supply layer or the channel layer;
A drain electrode disposed opposite to the source electrode and joined to at least the carrier supply layer of the carrier supply layer or the channel layer;
A gate electrode disposed between the source electrode and the drain electrode for controlling the traveling of the carriers in the channel layer;
A plurality of basic transistors are formed by the channel layer, the carrier supply layer, the source electrode, the drain electrode, and the gate electrode,
Of the plurality of basic transistors, the outermost basic transistor has a higher insulation resistance than the other basic transistors.
　また、一実施形態の電界効果トランジスタでは、
　上記複数の基本トランジスタのうちの最外周の基本トランジスタは、それ以外の基本トランジスタよりも上記ゲート電極と上記ドレイン電極との間の距離を長くすることにより耐絶縁性を高くしている。 In the field effect transistor of one embodiment,
Of the plurality of basic transistors, the outermost basic transistor has higher insulation resistance than the other basic transistors by increasing the distance between the gate electrode and the drain electrode.
　また、一実施形態の電界効果トランジスタでは、
　上記複数の基本トランジスタのうちの最外周の基本トランジスタは、上記ゲート電極と他の基本トランジスタのソース電極とが接続されたダイオード接続トランジスタとした。 In the field effect transistor of one embodiment,
The outermost basic transistor of the plurality of basic transistors is a diode-connected transistor in which the gate electrode and the source electrode of another basic transistor are connected.
　また、一実施形態の電界効果トランジスタでは、
　上記ダイオード接続トランジスタとなる上記最外周の基本トランジスタは、それ以外の基本トランジスタよりも上記ゲート電極と上記ドレイン電極との間の距離を長くすることにより耐絶縁性を高くしている。 In the field effect transistor of one embodiment,
The outermost basic transistor serving as the diode-connected transistor has higher insulation resistance than the other basic transistors by increasing the distance between the gate electrode and the drain electrode.
　また、一実施形態の電界効果トランジスタでは、
　上記基板はＳi基板である。 In the field effect transistor of one embodiment,
The substrate is an Si substrate.
　また、一実施形態の電界効果トランジスタでは、
　上記基本トランジスタはヘテロ接合電界効果トランジスタである。 In the field effect transistor of one embodiment,
The basic transistor is a heterojunction field effect transistor.
　以上より明らかなように、この発明によれば、複数の基本トランジスタのうちの最外周の基本トランジスタを、それ以外の基本トランジスタよりも耐絶縁性を高めることによって、素子全体での寿命を長くできる電界効果トランジスタを実現することができる。 As apparent from the above, according to the present invention, the lifetime of the entire element can be extended by increasing the insulation resistance of the outermost basic transistor of the plurality of basic transistors as compared with the other basic transistors. A field effect transistor can be realized.
図１はこの発明の第１実施形態の電界効果トランジスタの平面図である。FIG. 1 is a plan view of a field effect transistor according to a first embodiment of the present invention. 図２は上記電界効果トランジスタの要部の断面図である。FIG. 2 is a cross-sectional view of the main part of the field effect transistor. 図３はこの発明の第２実施形態の電界効果トランジスタの平面図である。FIG. 3 is a plan view of a field effect transistor according to the second embodiment of the present invention. 図４は上記電界効果トランジスタの最外周の要部の断面図である。FIG. 4 is a cross-sectional view of the main part of the outermost periphery of the field effect transistor.
　以下、この発明の電界効果トランジスタを図示の実施の形態により詳細に説明する。 Hereinafter, the field effect transistor of the present invention will be described in detail with reference to the illustrated embodiments.
　〔第１実施形態〕
　図１はこの発明の第１実施形態の電界効果トランジスタ１の平面図を示している。 [First Embodiment]
FIG. 1 shows a plan view of a field effect transistor 1 according to a first embodiment of the present invention.
　この第１実施形態の電界効果トランジスタ１は、図１に示すように、基板(図示せず)上に積層された窒化物半導体層(図示せず)上に、互いに略平行にかつ間隔をあけて設けられた直線状の複数のドレイン電極２と、ドレイン電極２夫々の外側を囲むように間隔をあけて設けられた複数のゲート電極３と、ゲート電極３夫々の外側を囲むように間隔をあけて設けられたソース電極４とを備える。さらに、上記電界効果トランジスタ１は、ドレイン電極２をドレインパッド２１にドレイン配線(図示せず)を介して接続し、ソース電極４をソースパッド４１にソース配線(図示せず)を介して接続している。 As shown in FIG. 1, the field effect transistor 1 of the first embodiment includes a nitride semiconductor layer (not shown) stacked on a substrate (not shown), and substantially parallel to and spaced from each other. The plurality of linear drain electrodes 2 provided, the plurality of gate electrodes 3 provided so as to surround the outer sides of the drain electrodes 2, and the intervals so as to surround the outer sides of the gate electrodes 3. And an open source electrode 4. Further, in the field effect transistor 1, the drain electrode 2 is connected to the drain pad 21 via a drain wiring (not shown), and the source electrode 4 is connected to the source pad 41 via a source wiring (not shown). ing.
　また、上記電界効果トランジスタ１は、点線５で囲われた部分で1つの基本トランジスタとなっており、大電流を扱えるように複数の基本トランジスタが並列に接続された構造となっている。 The field effect transistor 1 is a single basic transistor surrounded by a dotted line 5 and has a structure in which a plurality of basic transistors are connected in parallel to handle a large current.
　図２は上記電界効果トランジスタの基本トランジスタの要部の断面図を示している。 FIG. 2 shows a cross-sectional view of the main part of the basic transistor of the field effect transistor.
　この半導体装置は、図２に示すように、Ｓi基板１０１上に、アンドープＡlＧaＮからなるバッファ層１０２と、アンドープＧaＮからなるチャネル層１０３と、アンドープＡlＧaＮからなるキャリア供給層１０４を形成している。このチャネル層１０３とキャリア供給層１０４との界面に２ＤＥＧ(２次元電子ガス)が発生する。 In this semiconductor device, as shown in FIG. 2, a buffer layer 102 made of undoped AlGaN, a channel layer 103 made of undoped GaN, and a carrier supply layer 104 made of undoped AlGaN are formed on an Si substrate 101. 2DEG (two-dimensional electron gas) is generated at the interface between the channel layer 103 and the carrier supply layer 104.
　また、キャリア供給層１０４上に、互いに間隔をあけてソース電極４とドレイン電極２とを形成している。また、キャリア供給層１０４上に、ソース電極４とドレイン電極２との間かつソース電極４側にゲート電極３を形成している。ソース電極４とドレイン電極２はオーミック電極であり、ゲート電極３はショットキー電極である。上記ソース電極４と、ドレイン電極２と、ゲート電極３と、そのソース電極４,ドレイン電極２,ゲート電極３が形成されたチャネル層１０３,キャリア供給層１０４の活性領域でＨＦＥＴ(Hetero-junction Field Effect Transistor；ヘテロ接合電界効果トランジスタ)を構成している。 Also, the source electrode 4 and the drain electrode 2 are formed on the carrier supply layer 104 with a space therebetween. A gate electrode 3 is formed on the carrier supply layer 104 between the source electrode 4 and the drain electrode 2 and on the source electrode 4 side. The source electrode 4 and the drain electrode 2 are ohmic electrodes, and the gate electrode 3 is a Schottky electrode. In the active region of the source electrode 4, the drain electrode 2, the gate electrode 3, the source electrode 4, the drain electrode 2, the channel layer 103 in which the gate electrode 3 is formed, and the carrier supply layer 104, an HFET (Hetero-junction field) Effect Transistor (heterojunction field effect transistor).
　ここで、活性領域とは、キャリア供給層１０４上のソース電極４とドレイン電極２との間に配置されたゲート電極３に印加される電圧によって、ソース電極４とドレイン電極２との間でキャリアが流れる窒化物半導体層(チャネル層１０３,キャリア供給層１０４)の領域である。 Here, the active region is a carrier between the source electrode 4 and the drain electrode 2 due to a voltage applied to the gate electrode 3 disposed between the source electrode 4 and the drain electrode 2 on the carrier supply layer 104. This is a region of the nitride semiconductor layer (channel layer 103, carrier supply layer 104) through which flows.
　そして、ソース電極４とドレイン電極２とゲート電極３が形成された領域を除くキャリア供給層１０４上に、キャリア供給層１０４を保護するため、ＳiＯ２からなる絶縁膜１０５を形成している。 An insulating film 105 made of SiO 2 is formed on the carrier supply layer 104 excluding the region where the source electrode 4, the drain electrode 2, and the gate electrode 3 are formed in order to protect the carrier supply layer 104.
　上記電界効果トランジスタでは、チャネル層１０３とキャリア供給層１０４との界面に形成された２次元電子ガス(２ＤＥＧ)が発生してチャネルが形成される。このチャネルをゲート電極３に電圧を印加することにより制御して、ソース電極４とドレイン電極２とゲート電極３を有するＨＦＥＴをオンオフさせる。このＨＦＥＴは、ゲート電極３に負電圧が印加されているときにゲート電極３下のチャネル層１０３に空乏層が形成されてオフ状態となる一方、ゲート電極３の電圧がゼロのときにゲート電極３下のチャネル層１０３に空乏層がなくなってオン状態となるノーマリーオンタイプのトランジスタである。 In the field effect transistor, a channel is formed by generating a two-dimensional electron gas (2DEG) formed at the interface between the channel layer 103 and the carrier supply layer 104. This channel is controlled by applying a voltage to the gate electrode 3 to turn on and off the HFET having the source electrode 4, the drain electrode 2, and the gate electrode 3. In this HFET, when a negative voltage is applied to the gate electrode 3, a depletion layer is formed in the channel layer 103 under the gate electrode 3 and the OFF state is set, while the gate electrode 3 is turned off when the voltage of the gate electrode 3 is zero. 3 is a normally-on type transistor in which the depletion layer disappears in the lower channel layer 103 and is turned on.
　上記構成の電界効果トランジスタにおいて、基本トランジスタのゲート電極３とドレイン電極２との間の距離Ｌgdを１０μｍとしている。 In the field effect transistor having the above configuration, the distance Lgd between the gate electrode 3 and the drain electrode 2 of the basic transistor is 10 μm.
　さらに、並列に配置された複数の基本トランジスタのうち、一番外側に位置する基本トランジスタ(図１の点線６で囲われた部分)は、他の基本トランジスタよりもゲート電極３とドレイン電極２との間の距離Ｌgdを大きくしている(この実施の形態ではＬgd＝２０μｍ)。 Further, among the plurality of basic transistors arranged in parallel, the basic transistor located on the outermost side (the portion surrounded by the dotted line 6 in FIG. 1) has a gate electrode 3 and a drain electrode 2 which are more than the other basic transistors. The distance Lgd is increased (in this embodiment, Lgd = 20 μm).
　上記基本トランジスタ単体について、温度１５０℃、ソース電極を０Ｖ、基板電位を０V、ドレイン電極を６００V、ゲート電極を－１０Vの条件でバイアス試験を実施した。このバイアス試験の結果は、ゲート電極３とドレイン電極２との間の距離Ｌgd＝１０μｍでは、平均寿命が４５時間５分だったところ、Ｌgd＝２０μｍでは５７３時間であった。 The above basic transistor was subjected to a bias test at a temperature of 150 ° C., a source electrode of 0 V, a substrate potential of 0 V, a drain electrode of 600 V, and a gate electrode of −10 V. As a result of this bias test, when the distance between the gate electrode 3 and the drain electrode 2 was Lgd = 10 μm, the average life was 45 hours and 5 minutes, but when Lgd = 20 μm, it was 573 hours.
　このようにすることで、最外周の基本トランジスタの寿命を相対的に長くなるようにすることで、早々に破壊することを防ぐことができるようになるため、寿命の長い大電流素子を実現することができる。 By doing so, the life of the basic transistor at the outermost periphery is made relatively long, so that it can be prevented from being destroyed quickly, thereby realizing a long-lived high-current element. be able to.
　比較のため、従来の基本トランジスタが全て同一構造の電界効果トランジスタにおいて同様のバイアス試験を実施したところ、多くのサンプルにおいて最外周の基本トランジスタで破壊が生じた。 For comparison, all the conventional basic transistors were subjected to the same bias test on field effect transistors having the same structure, and in many samples, breakdown occurred in the outermost basic transistors.
　上記構成の電界効果トランジスタ１によれば、複数の基本トランジスタのうちの点線６で囲まれた最外周の基本トランジスタを、それ以外の基本トランジスタよりも耐絶縁性を高くした構成とすることによって、素子全体での寿命を長くできる。 According to the field effect transistor 1 having the above configuration, the outermost basic transistor surrounded by the dotted line 6 among the plurality of basic transistors is configured to have higher insulation resistance than other basic transistors. The lifetime of the entire device can be extended.
　また、上記最外周の基本トランジスタを、それ以外の基本トランジスタよりもゲート電極３とドレイン電極２との間の距離Ｌgdを長くすることにより絶縁距離を広げて、耐絶縁性を高めることができる。 In addition, by increasing the distance Lgd between the gate electrode 3 and the drain electrode 2 of the outermost basic transistor as compared with the other basic transistors, the insulation distance can be increased and the insulation resistance can be improved.
　また、Ｓiウェハ上にＧaＮをエピタキシャル成長させたＧaＮ-on-Ｓi基板を用いることでコストを抑えることができる。 Also, the cost can be suppressed by using a GaN-on-Si substrate in which GaN is epitaxially grown on a Si wafer.
　また、上記チャネル層１０３とキャリア供給層１０４とのヘテロ接合界面に形成された２次元電子ガス(２ＤＥＧ)が発生することによって、電子移動度が高く高速動作が可能な電界効果トランジスタ１を実現できる。 Further, the generation of the two-dimensional electron gas (2DEG) formed at the heterojunction interface between the channel layer 103 and the carrier supply layer 104 can realize the field effect transistor 1 having high electron mobility and capable of high speed operation. .
　〔第２実施形態〕
　図３はこの発明の第２実施形態の電界効果トランジスタ１００の平面図を示している。 [Second Embodiment]
FIG. 3 is a plan view of a field effect transistor 100 according to the second embodiment of the present invention.
　この第２実施形態の電界効果トランジスタ１００は、外側に位置する基本トランジスタを除いて第１実施形態の電界効果トランジスタ１と同一の構成をしている。 The field effect transistor 100 of the second embodiment has the same configuration as the field effect transistor 1 of the first embodiment except for the basic transistor located outside.
　この第２実施形態の電界効果トランジスタ１００は、点線５で囲われた部分で1つの基本トランジスタとなっており、大電流を扱えるように複数の基本トランジスタが並列に接続された構造となっている。 The field effect transistor 100 of the second embodiment is one basic transistor in a portion surrounded by a dotted line 5 and has a structure in which a plurality of basic transistors are connected in parallel so as to handle a large current. .
　さらに、複数の基本トランジスタのうちの一番外側に位置する基本トランジスタ(点線１０６で囲われた部分)は、ゲート電極３０が隣接する基本トランジスタのソース電極４に接続されたダイオード接続トランジスタとなっている。点線１０６で囲まれた基本トランジスタのゲート電極３０は、ＡlＧaＮ層１０４とショットキー接合するようになっており、ショットキーダイオードとなるように形成されている。なお、このゲート電極３０にはゲート電圧を印加するための配線は接続されていない。また、図３では、最外周の基本トランジスタのゲート電極３０と他の基本トランジスタのソース電極４との配線は図示していない。 Furthermore, the outermost basic transistor (portion surrounded by the dotted line 106) among the plurality of basic transistors is a diode-connected transistor in which the gate electrode 30 is connected to the source electrode 4 of the adjacent basic transistor. Yes. The gate electrode 30 of the basic transistor surrounded by the dotted line 106 is in Schottky junction with the AlGaN layer 104 and is formed to be a Schottky diode. The gate electrode 30 is not connected to a wiring for applying a gate voltage. In FIG. 3, the wiring between the gate electrode 30 of the outermost basic transistor and the source electrode 4 of another basic transistor is not shown.
　また、図４は上記電界効果トランジスタの最外周の基本トランジスタの要部の断面図を示している。図４において、ゲート電極３の左側に凹部４０を設けることによって、この最外周の基本トランジスタの２次元電子ガス(２ＤＥＧ)が他の基本トランジスタのソース電極と接続されないようにしている。 FIG. 4 is a cross-sectional view of the main part of the outermost basic transistor of the field effect transistor. In FIG. 4, the recess 40 is provided on the left side of the gate electrode 3 so that the two-dimensional electron gas (2DEG) of the outermost basic transistor is not connected to the source electrode of another basic transistor.
　このような構造をとることで、点線１０６で囲まれた最外周の基本トランジスタにおけるドレイン－ゲート間の距離Ｌgdを、点線５で囲まれた他の基本トランジスタの場合より広く取ることが可能になるため、耐圧を高くすることが可能となる。 By adopting such a structure, the drain-gate distance Lgd in the outermost basic transistor surrounded by the dotted line 106 can be made wider than in the case of other basic transistors surrounded by the dotted line 5. Therefore, the breakdown voltage can be increased.
　上記構成の電界効果トランジスタ１００によれば、最外周部分(点線１０６で囲まれた最外周の基本トランジスタ)でドレイン－ゲート間の距離を相対的に長くなるようにすることで、早々に破壊することを防ぐことができるようになるため、寿命の長い大電流素子を実現することができる。また、製造プロセスの変更も小さく、フォトエッチング用マスクの変更のみで実現することができる。 According to the field effect transistor 100 having the above configuration, the distance between the drain and the gate is relatively increased in the outermost peripheral portion (the outermost basic transistor surrounded by the dotted line 106), thereby quickly breaking down. Since this can be prevented, a long-life high-current element can be realized. Further, the change in the manufacturing process is small and can be realized only by changing the photoetching mask.
　さらに、ＧaＮＨＦＥＴでは、ソース電極４に高電圧が印加された場合、ドレイン電極２側に電流を流すことが可能となり、Ｓi－ＩＧＢＴ(絶縁ゲートバイポーラトランジスタ)で見られたボディダイオードと同様の機能を持たせることが可能となる。 Furthermore, in the GaN FET, when a high voltage is applied to the source electrode 4, it becomes possible to flow a current to the drain electrode 2 side, and the function similar to that of the body diode seen in Si-IGBT (insulated gate bipolar transistor) is achieved. It is possible to have it.
　上記第２実施形態の電界効果トランジスタ１００は、第１実施形態の電界効果トランジスタ１と同様の効果を有する。 The field effect transistor 100 of the second embodiment has the same effect as the field effect transistor 1 of the first embodiment.
　また、上記ダイオード接続トランジスタとなる最外周の基本トランジスタを、それ以外の基本トランジスタよりもゲート電極３とドレイン電極２との間の距離を長くすることにより絶縁距離を広げて、耐絶縁性を高くできる。 In addition, the outermost basic transistor to be the diode-connected transistor has a longer insulation distance by increasing the distance between the gate electrode 3 and the drain electrode 2 than the other basic transistors, thereby increasing the insulation resistance. it can.
　上記第１,第２実施形態では、Ｓi基板１０１上にバッファ層１０２,チャネル層１０３,キャリア供給層１０４が積層された電界効果トランジスタについて説明したが、この発明の電界効果トランジスタの基板は、Ｓi基板に限らず、サファイヤ基板やＳiＣ基板を用いてもよく、サファイヤ基板やＳiＣ基板上に窒化物半導体層を成長させてもよいし、ＧaＮ基板にＡlＧaＮ層を成長させる等のように、窒化物半導体からなる基板上に窒化物半導体層を成長させてもよい。また、基板と窒化物半導体層との間にバッファ層を形成してもよいし、窒化物半導体層の第１半導体層と第２半導体層との間にヘテロ改善層を形成してもよい。 In the first and second embodiments, the field effect transistor in which the buffer layer 102, the channel layer 103, and the carrier supply layer 104 are stacked on the Si substrate 101 has been described. However, the substrate of the field effect transistor according to the present invention includes Si. The substrate is not limited to a sapphire substrate or SiC substrate, a nitride semiconductor layer may be grown on the sapphire substrate or SiC substrate, or an AlGaN layer is grown on the GaN substrate. A nitride semiconductor layer may be grown on a semiconductor substrate. Further, a buffer layer may be formed between the substrate and the nitride semiconductor layer, or a hetero improvement layer may be formed between the first semiconductor layer and the second semiconductor layer of the nitride semiconductor layer.
　また、上記第１,第２実施の形態では、オーミック電極がＧaＮ層に達するリセス構造のＨＦＥＴについて説明したが、リセスを形成せずにアンドープＡlＧaＮ層上にソース電極およびドレイン電極となるオーミック電極を形成したＨＦＥＴにこの発明を適用してもよい。また、この発明の窒化物半導体装置は、２ＤＥＧを利用するＨＦＥＴに限らず、ＭＩＳ(Metal Insulator Semiconductor)ＦＥＴ、ＭＯＳ(Metal Oxide Semiconductor)ＦＥＴ、ＭＥＳ(Metal Semiconductor)ＦＥＴ等の他の構成の電界効果トランジスタであっても同様の効果が得られる。 In the first and second embodiments, the HFET having the recess structure in which the ohmic electrode reaches the GaN layer has been described. However, the ohmic electrode that becomes the source electrode and the drain electrode is formed on the undoped AlGaN layer without forming the recess. The present invention may be applied to the formed HFET. In addition, the nitride semiconductor device of the present invention is not limited to an HFET using 2DEG, but has a field effect of other configurations such as a MIS (Metal Insulator Semiconductor) FET, a MOS (Metal Oxide Semiconductor) FET, and a MES (Metal Semiconductor) FET. Even if it is a transistor, the same effect is acquired.
　また、上記第１実施形態では、ゲート電極と半導体の間に絶縁膜があるＭＩＳ－ＨＦＥＴ構造でもよい。 In the first embodiment, a MIS-HFET structure having an insulating film between the gate electrode and the semiconductor may be used.
　また、上記第１,第２実施形態では、ノーマリーオンタイプのＨＦＥＴについて説明したが、ノーマリーオフタイプの窒化物半導体装置にこの発明を適用してもよい。 In the first and second embodiments, the normally-on type HFET has been described. However, the present invention may be applied to a normally-off type nitride semiconductor device.
　また、上記第１,第２実施形態では、アンドープＧaＮからなるチャネル層１０３と、アンドープＡlＧaＮからなるキャリア供給層１０４を用いた電界効果トランジスタについて説明したが、他の半導体材料を用いたチャネル層,キャリア供給層でもよく、例えば、ＡlxＩnyＧa１－x－yＮ(ｘ≧０、ｙ≧０、０≦ｘ＋ｙ≦１)で表される窒化物半導体でもよい。 In the first and second embodiments, the field effect transistor using the channel layer 103 made of undoped GaN and the carrier supply layer 104 made of undoped AlGaN is described. However, the channel layer using other semiconductor materials, It may be a carrier supply layer, for example, a nitride semiconductor represented by Al x In y Ga 1-xy N (x ≧ 0, y ≧ 0, 0 ≦ x + y ≦ 1).
　この発明の具体的な実施の形態について説明したが、この発明は上記第１,第２実施形態に限定されるものではなく、この発明の範囲内で種々変更して実施することができる。 Although specific embodiments of the present invention have been described, the present invention is not limited to the first and second embodiments described above, and various modifications can be made within the scope of the present invention.
　すなわち、この発明および実施形態をまとめると、次のようになる。 That is, the present invention and the embodiment are summarized as follows.
　この発明の電界効果トランジスタは、
　基板１０１と、
　上記基板１０１上に形成され、キャリアが走行するチャネル層１０３と、
　上記チャネル層１０３上に形成され、上記チャネル層１０３に上記キャリアを供給するキャリア供給層１０４と、
　上記キャリア供給層１０４または上記チャネル層１０３のうちの少なくとも上記キャリア供給層１０４に接合されたソース電極４と、
　上記ソース電極４に対向して配置され、上記キャリア供給層１０４または上記チャネル層１０３のうちの少なくとも上記キャリア供給層１０４に接合されたドレイン電極２と、
　上記ソース電極４と上記ドレイン電極２との間に配置され、上記チャネル層１０３の上記キャリアの走行を制御するためのゲート電極３,３０と
を備え、
　上記チャネル層１０３、上記キャリア供給層１０４、上記ソース電極４、上記ドレイン電極２および上記ゲート電極３,３０で複数の基本トランジスタが形成されており、
　上記複数の基本トランジスタのうちの最外周の基本トランジスタは、それ以外の基本トランジスタよりも耐絶縁性を高くした構成をしていることを特徴とする。 The field effect transistor of this invention is
A substrate 101;
A channel layer 103 formed on the substrate 101 and carrying carriers,
A carrier supply layer 104 formed on the channel layer 103 and supplying the carriers to the channel layer 103;
A source electrode 4 bonded to at least the carrier supply layer 104 of the carrier supply layer 104 or the channel layer 103;
A drain electrode 2 disposed opposite to the source electrode 4 and joined to at least the carrier supply layer 104 of the carrier supply layer 104 or the channel layer 103;
A gate electrode 3, 30 disposed between the source electrode 4 and the drain electrode 2 for controlling the carrier travel of the channel layer 103;
A plurality of basic transistors are formed by the channel layer 103, the carrier supply layer 104, the source electrode 4, the drain electrode 2, and the gate electrodes 3, 30.
Among the plurality of basic transistors, the outermost basic transistor has a structure with higher insulation resistance than the other basic transistors.
　上記構成によれば、複数の基本トランジスタのうちの最外周の基本トランジスタを、それ以外の基本トランジスタよりも耐絶縁性を高くした構成とすることによって、素子全体での寿命を長くできる。 According to the above configuration, the lifetime of the entire element can be extended by configuring the outermost basic transistor of the plurality of basic transistors to have higher insulation resistance than the other basic transistors.
　また、一実施形態の電界効果トランジスタでは、
　上記複数の基本トランジスタのうちの最外周の基本トランジスタは、それ以外の基本トランジスタよりも上記ゲート電極３,３０と上記ドレイン電極２との間の距離を長くすることにより耐絶縁性を高くしている。 In the field effect transistor of one embodiment,
Among the plurality of basic transistors, the outermost basic transistor has a higher insulation resistance by increasing the distance between the gate electrodes 3 and 30 and the drain electrode 2 than the other basic transistors. Yes.
　上記実施形態によれば、複数の基本トランジスタのうちの最外周の基本トランジスタを、それ以外の基本トランジスタよりもゲート電極３,３０とドレイン電極２との間の距離を長くすることにより絶縁距離を広げて、耐絶縁性を高めることができる。 According to the embodiment, the outermost basic transistor of the plurality of basic transistors has a longer insulation distance than the other basic transistors by increasing the distance between the gate electrodes 3 and 30 and the drain electrode 2. It can be expanded to increase insulation resistance.
　また、一実施形態の電界効果トランジスタでは、
　上記複数の基本トランジスタのうちの最外周の基本トランジスタは、上記ゲート電極３０と他の基本トランジスタのソース電極４とが接続されたダイオード接続トランジスタとした。 In the field effect transistor of one embodiment,
The outermost basic transistor of the plurality of basic transistors is a diode-connected transistor in which the gate electrode 30 and the source electrode 4 of another basic transistor are connected.
　上記実施形態によれば、複数の基本トランジスタのうちの最外周の基本トランジスタを、ゲート電極３０と他の基本トランジスタのソース電極４とが接続されたダイオード接続トランジスタとすることによって、ソース電極４に高電圧が印加されたときに、ドレイン電極２側に電流を流すことができる。 According to the above-described embodiment, the outermost basic transistor of the plurality of basic transistors is a diode-connected transistor in which the gate electrode 30 and the source electrode 4 of another basic transistor are connected to each other. When a high voltage is applied, current can flow to the drain electrode 2 side.
　また、一実施形態の電界効果トランジスタでは、
　上記ダイオード接続トランジスタとなる上記最外周の基本トランジスタは、それ以外の基本トランジスタよりも上記ゲート電極３０と上記ドレイン電極２との間の距離を長くすることにより耐絶縁性を高くしている。 In the field effect transistor of one embodiment,
The outermost basic transistor serving as the diode-connected transistor has higher insulation resistance than the other basic transistors by increasing the distance between the gate electrode 30 and the drain electrode 2.
　上記実施形態によれば、ダイオード接続トランジスタとなる最外周の基本トランジスタを、それ以外の基本トランジスタよりもゲート電極３とドレイン電極２との間の距離を長くすることにより絶縁距離を広げて、耐絶縁性を高めることができる。 According to the above-described embodiment, the outermost basic transistor serving as a diode-connected transistor is made longer by increasing the distance between the gate electrode 3 and the drain electrode 2 than the other basic transistors, thereby increasing the resistance. Insulation can be enhanced.
　また、一実施形態の電界効果トランジスタでは、
　上記基板はＳi基板１０１である。 In the field effect transistor of one embodiment,
The substrate is the Si substrate 101.
　上記実施形態によれば、Ｓi基板１０１上にチャネル層１０３とキャリア供給層１０４を積層する電界効果トランジスタにおいて、例えばＳiウェハ上にＧaＮをエピタキシャル成長させたＧaＮ-on-Ｓi基板を用いることでコストを抑えることができる。 According to the embodiment, in the field effect transistor in which the channel layer 103 and the carrier supply layer 104 are stacked on the Si substrate 101, for example, the cost is reduced by using the GaN-on-Si substrate in which GaN is epitaxially grown on the Si wafer. Can be suppressed.
　また、一実施形態の電界効果トランジスタでは、
　上記基本トランジスタはヘテロ接合電界効果トランジスタである。 In the field effect transistor of one embodiment,
The basic transistor is a heterojunction field effect transistor.
　上記実施形態によれば、チャネル層１０３とキャリア供給層１０４とのヘテロ接合界面に形成された２次元電子ガス(２ＤＥＧ)が発生することによって、電子移動度が高く高速動作が可能な電界効果トランジスタを実現できる。 According to the above-described embodiment, a field effect transistor that has high electron mobility and can operate at high speed by generating a two-dimensional electron gas (2DEG) formed at the heterojunction interface between the channel layer 103 and the carrier supply layer 104. Can be realized.
　１,１００…電界効果トランジスタ
　２…ドレイン電極
　３,３０…ゲート電極
　４…ソース電極
　２１…ドレインパッド
　４０…凹部
　４１…ソースパッド
　１０１…Ｓi基板
　１０２…バッファ層
　１０３…チャネル層
　１０４…キャリア供給層
　１０５…絶縁膜 DESCRIPTION OF SYMBOLS 1,100 ... Field effect transistor 2 ... Drain electrode 3,30 ... Gate electrode 4 ... Source electrode 21 ... Drain pad 40 ... Recess 41 ... Source pad 101 ... Si substrate 102 ... Buffer layer 103 ... Channel layer 104 ... Carrier supply layer 105 ... Insulating film

Claims (5)

  1. 　基板(１０１)と、
    　上記基板(１０１)上に形成され、キャリアが走行するチャネル層(１０３)と、
    　上記チャネル層(１０３)上に形成され、上記チャネル層(１０３)に上記キャリアを供給するキャリア供給層(１０４)と、
    　上記キャリア供給層(１０４)または上記チャネル層(１０３)のうちの少なくとも上記キャリア供給層(１０４)に接合されたソース電極(４)と、
    　上記ソース電極(４)に対向して配置され、上記キャリア供給層(１０４)または上記チャネル層(１０３)のうちの少なくとも上記キャリア供給層(１０４)に接合されたドレイン電極(２)と、
    　上記ソース電極(４)と上記ドレイン電極(２)との間に配置され、上記チャネル層(１０３)の上記キャリアの走行を制御するためのゲート電極(３,３０)と
    を備え、
    　上記チャネル層(１０３)、上記キャリア供給層(１０４)、上記ソース電極(４)、上記ドレイン電極(２)および上記ゲート電極(３,３０)で複数の基本トランジスタが形成されており、
    　上記複数の基本トランジスタのうちの最外周の基本トランジスタは、それ以外の基本トランジスタよりも耐絶縁性を高くした構成をしていることを特徴とする電界効果トランジスタ。     A substrate (101);
    A channel layer (103) formed on the substrate (101) and carrying carriers,
    A carrier supply layer (104) formed on the channel layer (103) and supplying the carrier to the channel layer (103);
    A source electrode (4) joined to at least the carrier supply layer (104) of the carrier supply layer (104) or the channel layer (103);
    A drain electrode (2) disposed opposite to the source electrode (4) and joined to at least the carrier supply layer (104) of the carrier supply layer (104) or the channel layer (103);
    A gate electrode (3, 30) disposed between the source electrode (4) and the drain electrode (2) for controlling the traveling of the carriers in the channel layer (103);
    A plurality of basic transistors are formed by the channel layer (103), the carrier supply layer (104), the source electrode (4), the drain electrode (2) and the gate electrode (3, 30),
    3. A field effect transistor characterized in that an outermost basic transistor of the plurality of basic transistors has a higher insulation resistance than other basic transistors.
  2. 　請求項１に記載の電界効果トランジスタにおいて、
    　上記複数の基本トランジスタのうちの最外周の基本トランジスタは、それ以外の基本トランジスタよりも上記ゲート電極(３,３０)と上記ドレイン電極(２)との間の距離を長くすることにより耐絶縁性を高くしていることを特徴とする電界効果トランジスタ。     The field effect transistor of claim 1, wherein
    Among the plurality of basic transistors, the outermost basic transistor is more resistant to insulation by increasing the distance between the gate electrode (3, 30) and the drain electrode (2) than the other basic transistors. A field effect transistor characterized by having a high height.
  3. 　請求項１に記載の電界効果トランジスタにおいて、
    　上記複数の基本トランジスタのうちの最外周の基本トランジスタは、上記ゲート電極(３０)と他の基本トランジスタのソース電極(４)とが接続されたダイオード接続トランジスタとしたことを特徴とする電界効果トランジスタ。     The field effect transistor of claim 1, wherein
    The outermost basic transistor of the plurality of basic transistors is a diode-connected transistor in which the gate electrode (30) and the source electrode (4) of another basic transistor are connected to each other. .
  4. 　請求項３に記載の電界効果トランジスタにおいて、
    　上記ダイオード接続トランジスタとなる上記最外周の基本トランジスタは、それ以外の基本トランジスタよりも上記ゲート電極(３０)と上記ドレイン電極(２)との間の距離を長くすることにより耐絶縁性を高くしていることを特徴とする電界効果トランジスタ。     The field effect transistor of claim 3,
    The outermost basic transistor to be the diode-connected transistor has higher insulation resistance by making the distance between the gate electrode (30) and the drain electrode (2) longer than the other basic transistors. A field effect transistor characterized by comprising:
  5. 　請求項１から４までのいずれか１つに記載の電界効果トランジスタにおいて、
    　上記基板(１０１)はＳi基板であることを特徴とする電界効果トランジスタ。     The field effect transistor according to any one of claims 1 to 4,
    The field effect transistor according to claim 1, wherein the substrate (101) is a Si substrate.
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