WO2014162794A1 - 液晶表示装置およびその駆動方法 - Google Patents
液晶表示装置およびその駆動方法 Download PDFInfo
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- WO2014162794A1 WO2014162794A1 PCT/JP2014/054322 JP2014054322W WO2014162794A1 WO 2014162794 A1 WO2014162794 A1 WO 2014162794A1 JP 2014054322 W JP2014054322 W JP 2014054322W WO 2014162794 A1 WO2014162794 A1 WO 2014162794A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2203/00—Function characteristic
- G02F2203/30—Gray scale
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- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0434—Flat panel display in which a field is applied parallel to the display plane
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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- G09G2320/0252—Improving the response speed
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- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/041—Temperature compensation
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0435—Change or adaptation of the frame rate of the video stream
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- G09G2340/00—Aspects of display data processing
- G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame
Definitions
- the present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display device that performs AC driving and a driving method thereof.
- the liquid crystal display device applies a voltage between the pixel electrode and the common electrode to change the alignment direction (major axis direction) of the liquid crystal molecules, thereby controlling the amount of light transmitted through the liquid crystal layer to the liquid crystal panel. Display an image.
- one frame period when the refresh rate is 60 Hz may be referred to as “normal one frame period”. For this reason, the length of a normal one frame period is 16.7 msec.
- Japanese Unexamined Patent Application Publication No. 2004-4629 performs “overshoot driving” in which a voltage higher than the voltage corresponding to the image signal is applied to the liquid crystal layer.
- a liquid crystal display device is disclosed.
- a lookup table hereinafter referred to as “LUT” or “table” that stores correction values associated with each combination of the gradation value of the previous frame and the gradation value of the current frame is used. .
- the correction value associated with the combination of the gradation value of the previous frame and the gradation value of the current frame is read from the LUT, and overshoot driving is performed using the corrected image signal obtained by correcting the image signal with the correction value.
- the response speed of the liquid crystal display device can be improved.
- a voltage having the same polarity is continuously applied to the liquid crystal layer, image sticking occurs and the liquid crystal layer deteriorates.
- AC driving is performed to reverse the polarity every time a data voltage corresponding to an image signal is written.
- flicker based on flexopolarization occurs as will be described later, and the display quality of the image may be reduced.
- This flicker is more likely to occur in a horizontal electric field type liquid crystal display device such as an FFS mode than in a vertical electric field type liquid crystal display device such as a VA mode, and usually displays a moving image by updating an image at a refresh rate of 60 Hz.
- it is easier to visually recognize when performing a pause drive that alternately repeats a refresh period in which an image is updated and a pause period in which an image update is paused.
- an object of the present invention is to provide a liquid crystal display device and a driving method thereof that can prevent display quality from being deteriorated by suppressing flicker based on flexopolarization generated during AC driving.
- a first aspect of the present invention is a liquid crystal display device that performs AC driving, A plurality of scanning signal lines formed on an insulating substrate; A plurality of data signal lines respectively intersecting with the plurality of scanning signal lines; A plurality of pixel forming portions respectively formed at intersections of the plurality of scanning signal lines and the plurality of data signal lines; Either a corrected image signal that has been subjected to gradation correction processing that corrects a temporal change in the signal with respect to input image data, or an image signal that has not been subjected to the gradation correction processing with respect to the input image data is output.
- a gradation control unit A scanning signal line driving circuit that sequentially selects and scans the plurality of scanning signal lines; Either the data voltage corresponding to the target gradation value generated based on the image signal or the gradation correction voltage corrected based on the data voltage generated based on the corrected image signal is the plurality of data signals.
- a display control unit for controlling the scanning signal line driving circuit and the data signal line driving circuit, The display control unit writes the gradation correction voltage in the first frame period and writes the data voltage having the same polarity as the gradation correction voltage in the second frame period to the plurality of pixel formation units. Control to refresh, The length of the first frame period is 1 ⁇ 4 or more of one frame period when the refresh rate is 60 Hz, and is less than the one frame period.
- the length of the second frame period is the same as the length of the first frame period.
- the display control unit provides a pause period in which the writing of the data voltage to the plurality of pixel formation units is suspended after the writing of the data voltage to the plurality of pixel formation units is completed in the second frame period. It is characterized by that.
- the gradation control unit includes a frame memory for storing the input image data for each frame; A table for storing correction values associated with the gradation value of the previous frame and the gradation value of the current frame of the input image data; A comparison circuit that obtains a gradation value of a current frame of the input image data and a gradation value of a previous frame of the input image data stored in the frame memory and outputs the gradation value to the table; An addition circuit that outputs either the corrected image signal or the image signal to the data signal line driving circuit based on the input image data; The table stores correction values respectively associated with combinations of the gradation value of the current image and the gradation value of the previous frame of the input image data, and stores the correction level of the current image of the input image data from the comparison circuit.
- the display control unit When the display control unit is given update information indicating that the input image data is not updated from the comparison circuit, the display control unit sets the length of the first frame period based on the update information.
- a drive frequency control circuit for adjusting the length to be shorter than the length is included.
- a sixth aspect of the present invention is the fifth aspect of the present invention,
- the update information includes first update information indicating that the input image data is not updated, and second update information indicating that the input image data is updated,
- the display control unit when given the first update information from the comparison circuit, a driving period including a gradation correction period for writing the gradation correction voltage and a data voltage writing period for writing the data voltage;
- a drive / pause control circuit for generating a drive / pause control signal indicating that only the data voltage writing period is provided when the second update information is supplied alternately with the pause period; It is characterized by.
- a temperature sensor for measuring a temperature around the liquid crystal display device includes a plurality of sub-tables that store different correction values for each predetermined temperature range, The table selects one sub-table corresponding to the temperature information from the plurality of sub-tables based on temperature information given from the temperature sensor.
- the pixel forming unit has a control terminal connected to the scanning signal line, a first conduction terminal connected to the data signal line, and a second conduction to the pixel electrode to which the data voltage or the gradation correction voltage is to be applied. It includes a thin film transistor in which a terminal is connected and a channel layer is formed using an oxide semiconductor.
- a ninth aspect of the present invention is the eighth aspect of the present invention.
- the oxide semiconductor contains indium, gallium, zinc, and oxygen.
- the data signal line driving circuit applies a ground potential to the data signal line during the pause period.
- An eleventh aspect of the present invention is the third aspect of the present invention,
- the data signal line driver circuit is characterized in that the potential of the data signal line is floated during the pause period.
- a common electrode and a pixel electrode are formed on the insulating substrate, the other electrode is superimposed on the other electrode through an insulating film, and a plurality of openings are formed on the other electrode. It is characterized by.
- alternating current is applied by any of dot inversion driving, line inversion driving, column inversion driving, and frame inversion driving. It is driven.
- a fourteenth aspect of the present invention is a method of driving a liquid crystal display device that displays an image represented by input image data on a display unit, Gradation correction to a data voltage corresponding to the target gradation value of the input image data during a period of 1/4 or more of one frame period when the refresh rate is 60 Hz and less than the one frame period
- a fifteenth aspect of the present invention is the fourteenth aspect of the present invention,
- the period during which the data voltage is applied in the data voltage application step is the same length as the period during which the gradation correction voltage is applied in the gradation correction voltage application step.
- the gradation correction processing for adjusting the period so that the area of the “positive effective region” and the area of the “negative effective region” are substantially equal in the first frame period.
- the length of the first frame period is equal to or longer than 1 ⁇ 4 of one frame period when the refresh rate is 60 Hz, and any period included in less than the one frame period.
- the second frame period in which the data voltage is written in each driving period is set to the same length as the first frame period in which the gradation correction voltage is written.
- a rest period is provided after the writing of the gradation correction voltage and the data voltage is completed.
- the addition circuit provided in the gradation control unit corrects the gradation value of the input image data with the correction value given from the table when performing gradation correction processing. An image signal is output, and then an image signal without correcting the gradation value of the input image data is output.
- the gradation correction voltage can be written before the data voltage corresponding to the target gradation value generated based on the image signal is written to the pixel formation portion, flicker based on flexo polarization generated during AC driving is prevented. It is suppressed.
- the gradation correction voltage is applied to the pixel.
- the length of the first frame period for writing in the formation portion is shortened. Thereby, the writing of the gradation correction voltage is completed before the luminance of the pixel formation portion becomes too high, and thus flicker based on flexo polarization that occurs during AC driving is suppressed.
- the drive / pause control circuit included in the display control unit when the drive / pause control circuit included in the display control unit is given the first update information indicating that the input image data has not been updated, the gradation correction period.
- the second update information indicating that the input image data is updated is given by alternately switching between the driving period composed of the data voltage writing period and the pause period, only the data voltage writing period is provided. A drive / pause control signal for instructing this is generated.
- the display control unit writes the data voltage in a period having the same length as the normal frame period.
- the display control unit A drive / pause signal instructing to write the correction period and the data voltage writing period in a period shorter than the normal frame period is generated and output. Accordingly, the drive / pause control circuit can output a drive / pause control signal corresponding to normal drive or pause drive to the data signal line drive circuit based on the input image data.
- the temperature sensor and the plurality of sub-tables for storing different correction values depending on the temperature are provided, and the plurality of sub-tables are set according to the temperature of the environment in which the liquid crystal display device is used. Either one is selected and gradation correction processing is performed. As a result, in a liquid crystal display device used in a wide temperature range, the brightness when the gradation correction voltage is written can be adjusted to the optimum brightness regardless of the temperature. Flicker based is suppressed.
- a thin film transistor in which a channel layer is formed of an oxide semiconductor is used as a switching element of each pixel formation portion.
- the off-leakage current of the thin film transistor is greatly reduced, and the voltage written in the pixel capacitance of each pixel formation portion is held for a longer period.
- power consumption for image display can be significantly reduced.
- the operation of the data signal line driving circuit is stopped to make the potential of the data signal line floating. Thereby, the power consumption of the data signal line driving circuit can be reduced.
- the occurrence of flicker can be suppressed in the FFS mode liquid crystal display device in which flicker is likely to occur due to flexopolarization that occurs during AC driving.
- the liquid crystal display device is any one of dot inversion driving, line inversion driving, column inversion driving, and frame inversion driving. Flickering can be suppressed even when AC driving is performed.
- FIG. 6 is a diagram illustrating a change in luminance in one pixel formation portion when the polarity of an image signal changes from positive polarity to negative polarity in the first basic study. It is a timing chart which shows the drive method of the liquid crystal display device performed by the 2nd basic examination. In a 2nd basic examination, it is a figure which shows the change of the brightness
- FIG. 5 is a diagram for explaining the reason why flicker occurs when driven by the driving method shown in FIG. 4.
- 1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention. It is a block diagram which shows the structure of the display control part contained in the liquid crystal display device shown in FIG. It is a figure which shows an example of a structure of LUT used with the liquid crystal display device shown in FIG. It is a timing chart which shows the drive method of the liquid crystal display device shown in FIG.
- FIG. 8 is a diagram illustrating a change in luminance in one pixel formation portion when the polarity of an image signal changes from positive polarity to negative polarity in the driving method of the liquid crystal display device shown in FIG. 7.
- FIG. 8 is a diagram illustrating a change in luminance in one pixel formation portion when the polarity of an image signal changes from positive polarity to negative polarity in the driving method of the liquid crystal display device shown in FIG. 7.
- FIG. 8 is a diagram for explaining that generation of flicker is suppressed in the driving method of the liquid crystal display device shown in FIG. 7.
- 6 is a timing chart showing a method for driving a liquid crystal display device according to a first modification of the first embodiment. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the display control part contained in the liquid crystal display device shown in FIG. It is a figure which shows an example of LUT for normal temperature used with the liquid crystal display device shown in FIG. It is a figure which shows an example of LUT for high temperature used with the liquid crystal display device shown in FIG. It is a figure which shows an example of LUT for low temperature used with the liquid crystal display device shown in FIG.
- the driving method of the liquid crystal display device includes a vertical electric field method such as a VA mode in which a voltage is applied in a direction perpendicular to the insulating substrate, and an IPS mode and an FFS mode in which a voltage is applied in a direction substantially parallel to the insulating substrate.
- a horizontal electric field method In the horizontal electric field method, unlike the vertical electric field method, not only pixel electrodes but also common electrodes are formed on one insulating substrate (array substrate) in order to generate an electric field in a direction substantially parallel to the insulating substrate. ing.
- the liquid crystal molecules When a voltage is applied between the pixel electrode and the common electrode, the liquid crystal molecules rotate in a plane parallel to the insulating substrate and are aligned in the direction of the electric field.
- a liquid crystal display device that employs such a horizontal electric field method has better viewing angle characteristics than a liquid crystal display device that employs a vertical electric field method.
- the FFS mode liquid crystal panel is a panel developed to solve the problems of the low aperture ratio and low transmittance of the IPS mode liquid crystal panel, and is also called an oblique electric field method.
- FIG. 1 is a plan view of a pixel forming portion 10 formed on an array substrate constituting an FFS mode liquid crystal panel
- FIG. 2 is a cross-sectional view of the FFS mode liquid crystal panel shown in FIG.
- the FFS mode liquid crystal panel includes an array substrate and a color filter substrate.
- scanning signal lines GL and common wirings CS are formed in parallel to each other, and data signal lines SL are formed in a direction perpendicular to the scanning signal lines GL and the common wirings CS.
- On the insulating substrate a common electrode 13 that covers substantially the entire pixel forming portion 10 and is electrically connected to the common wiring CS is formed.
- a pixel electrode 12 provided with a plurality of openings (slits) 12s in a stripe shape is formed on the upper surface of the common electrode 13 with an insulating film 16 interposed therebetween.
- a thin film transistor (TFT) 11 that functions as a switching element is formed in the vicinity of the intersection of the scanning signal line GL and the data signal line SL.
- a semiconductor layer (channel layer) 11a is arranged on the surface of the scanning signal line GL, and a part of the data signal line SL is extended so as to cover a part of the surface of the semiconductor layer 11a to form the source electrode S.
- the scanning signal line GL below the layer 11a constitutes the gate electrode G, and a part of the pixel electrode 12 overlapping the semiconductor layer 11a constitutes the drain electrode D.
- An alignment film 18 oriented in a predetermined direction is formed on the pixel electrode 12.
- a color filter layer 17 and an alignment film 18 are sequentially formed on the surface of the color filter substrate.
- the array substrate and the color filter substrate are arranged so that the alignment films 18 face each other, and a liquid crystal layer is sandwiched between the substrates.
- the FFS mode liquid crystal panel has a wider viewing angle and higher contrast than the IPS mode liquid crystal panel, and is bright because it has a high transmittance.
- flicker is likely to occur.
- polarizing plates are attached to the array substrate and the color filter substrate, respectively, but illustration and description thereof are omitted.
- the liquid crystal molecules in the liquid crystal panel try to align in the direction of the electric field.
- a force for fixing the alignment direction of the liquid crystal molecules to the rubbing direction of the alignment film 18 works due to the alignment regulating force of the alignment film 18. If the orientation direction of the liquid crystal molecules changes suddenly due to these forces, the polarization (flexo polarization) generated thereby becomes obvious without being canceled.
- This flexo polarization itself causes alignment deformation of liquid crystal molecules in response to an electric field, and is superimposed on the alignment deformation caused by dielectric anisotropy.
- first region P1 in the vicinity of the slit 12s of the pixel electrode 12 and a region P2 (hereinafter referred to as “second”) away from the slit 12s.
- second region P2 in the same pixel forming unit 10.
- the light transmittance is different from that of “region P2”).
- the common electrode is the lower electrode and the pixel electrode is the upper electrode.
- the pixel electrode may be the lower electrode and the common electrode may be the upper electrode.
- the plurality of slits are formed in the common electrode serving as the upper electrode.
- a change in light transmittance due to flexopolarization occurs remarkably in the FFS mode liquid crystal panel, but is also seen in the IPS mode liquid crystal panel.
- FIG. 3 shows the formation of one pixel when the polarity of the data voltage corresponding to the target gradation value of the image signal (hereinafter abbreviated as “data voltage”) changes from positive polarity to negative polarity in the first basic study.
- FIG. 6 is a diagram showing a change in luminance within a unit 10. As described above, in one pixel forming unit 10, there are two regions having different luminances according to the distance from the slit 12s. By writing a positive image signal in such a pixel formation portion, the luminance of the first region P1 close to the slit 12s is higher than the luminance of the second region P2 far from the slit 12s.
- the brightness of the second region P2 continues to rise slowly.
- the brightness of the first region P1 rapidly decreases and then becomes a constant value.
- the viewer sees the change in the luminance of the first region P1 and the luminance of the second region P2 at the same time.
- the luminance visually recognized by the viewer rapidly decreases immediately after the polarity is switched from positive polarity to negative polarity. For this reason, the viewer visually recognizes the decrease in luminance as flicker.
- Such flicker is also a phenomenon that can be seen in normal driving for displaying a moving image at a refresh rate of 60 Hz in an FFS mode liquid crystal display device.
- the refresh rate is as high as 60 Hz, the viewer can flicker. There is little to worry about the occurrence of.
- the pause driving since the refresh rate is low, the occurrence of flicker becomes remarkable.
- the first basic study when the polarity of the data voltage is switched from the positive polarity to the negative polarity, the second region P2 has a low luminance to a high luminance compared to the speed at which the first region P1 changes from a high luminance to a low luminance. Because of the slow change speed, there is a problem that the luminance is greatly reduced immediately after the polarity of the data voltage is switched. For this reason, if it is possible to suppress a rapid decrease in luminance of the first region P1 immediately after the polarity of the data voltage is switched in AC driving, it is considered that the occurrence of flicker can be suppressed.
- FIG. 4 is a timing chart showing a driving method of the liquid crystal display device examined in the second basic study.
- an overshoot voltage (OS) having a voltage value larger than the data voltage is written in the first frame period (first F period) every driving period.
- the data voltage is written in the second frame period (second F period).
- a pause period is provided by inserting N pause frames.
- FIG. 5 is a diagram showing a change in luminance in one pixel forming unit 10 when the polarity of the data voltage changes from positive to negative in the second basic study. As shown in FIG. 5, before switching the polarity of the data voltage from the positive polarity to the negative polarity, the negative overshoot voltage is first written for one frame period, and the negative data voltage is written for the next one frame period.
- FIG. 5 shows only the case where the polarity of the data voltage is switched from positive polarity to negative polarity. However, when switching the polarity of the data voltage from the negative polarity to the positive polarity, the positive overshoot voltage is first written for one frame period and the data voltage is written for the next one frame period. Similarly, the overshoot voltage is written for one frame period and the data voltage is written for the next one frame period while switching the polarity.
- the luminance change in the first region P1 and the second region P2 when the polarity of the data voltage changes from positive polarity to negative polarity will be described.
- the frame period (first frame period) immediately before the data voltage is written is switched. Negative overshoot voltage is written.
- the brightness of the second region P2 rapidly increases from low brightness to high brightness.
- the luminance of the first region P1 rapidly decreases from high luminance to luminance determined by the overshoot voltage, and thereafter the luminance is maintained.
- the data voltage is written in the next frame period (second frame period).
- the luminance that has increased excessively due to the overshoot drive decreases from the luminance corresponding to the data voltage to a constant value thereafter.
- the first region P1 it further decreases from the luminance increased by the overshoot drive in the first frame period to the luminance determined by the data voltage, and then becomes a constant value.
- FIG. 6 is a diagram for explaining the reason why flicker occurs when driven by the driving method shown in FIG.
- FIG. 6 compared with FIG. 3 showing the first basic study, by performing overshoot driving in the first one frame period, a rapid decrease in luminance immediately after switching the polarity is suppressed.
- the area of the area where the luminance is higher than the average luminance (hereinafter referred to as “positive effective area”) by the overshoot drive is reduced to the area of the area where the luminance is lower (hereinafter referred to as “negative effective area”). It is larger than that.
- Such an imbalance between the area of the positive effective region and the area of the negative effective region is caused by the brightness of the second region P2 becoming too high.
- the area of the “positive effective region” is considered to be a cause of flicker.
- Embodiments of the present invention made to suppress the occurrence of flicker due to flexo polarization based on the first and second basic studies will be described below.
- pause driving refers to driving that alternately repeats a driving period for refreshing a screen and a pause period for pausing refreshing, and normal driving includes driving only and does not include a pause period.
- the driving period in the pause driving includes an overshoot driving period and a data voltage writing period for writing a data voltage corresponding to the image data, as described later, and the driving period in the normal driving includes only the data voltage writing period.
- the “one frame period” is a period necessary for refreshing for one screen. In each embodiment described later, 16.7 msec, which is the length of one frame period when the refresh rate is 60 Hz, is set to “one frame. Although it is the length of “period”, the present invention is not limited to this.
- FIG. 7 is a block diagram illustrating a configuration of the liquid crystal display device 100 according to the present embodiment.
- the liquid crystal display device 100 includes a display control unit 200, a drive unit 300, a gradation control unit 400, and a display unit 500.
- the driving unit 300 includes a data signal line driving circuit 310 and a scanning signal line driving circuit 320.
- the display unit 500 constitutes a liquid crystal panel. This liquid crystal panel may have a configuration in which the display unit 500 and either or both of the data signal line driving circuit 310 and the scanning signal line driving circuit 320 are integrally formed.
- a host (not shown) mainly composed of a CPU (Central Processing Unit) is provided outside the liquid crystal display device 100, and the host displays image data DV (“input image” representing an image to be displayed on the display unit 500. Data including data) is transmitted to the liquid crystal display device 100.
- CPU Central Processing Unit
- the display unit 500 includes a plurality of data signal lines SL, a plurality of scanning signal lines GL, a plurality of common wirings (not shown), the plurality of data signal lines SL, and a plurality of scanning signal lines.
- a plurality of pixel forming portions 10 arranged in a matrix corresponding to each intersection of GL are formed.
- FIG. 7 for convenience, one pixel formation unit 10, one data signal line SL and one scanning signal line GL connected to the pixel formation unit 10 are shown.
- a gate terminal (also referred to as “control terminal”) is connected to the corresponding scanning signal line GL, and a source terminal (also referred to as “first conduction terminal”) is connected to the corresponding data signal line SL.
- a thin film transistor (TFT) 11 functioning as a switching element, a pixel electrode 12 connected to a drain terminal (also referred to as “second conduction terminal”) of the TFT 11, and a plurality of pixel formation portions 10 are provided in common.
- the common electrode 13 and the liquid crystal layer provided in common to the plurality of pixel forming portions 10 sandwiched between the two array substrates and the color filter substrate (none of which is shown) constituting the liquid crystal panel. (Not shown).
- the pixel capacitor Cp is composed of the pixel electrode 12, the common electrode 13, and the insulating film 16 sandwiched between them.
- the common electrodes 13 of the pixel forming portions 10 are connected to each other by a common wiring (not shown).
- the arrangement of the TFT 11, the pixel electrode 12, the common electrode 13 and the like in each pixel forming portion 10 is the same as that of the FFS mode pixel panel shown in FIGS.
- the TFT 11 included in each pixel forming portion 10 for example, a TFT having an oxide semiconductor as a channel layer is used. More specifically, the channel layer of the TFT 11 is formed of In—Ga—Zn—O (indium gallium zinc) containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). Has been. In a TFT using In—Ga—Zn—O for the channel layer, off-leakage current is significantly reduced as compared with a silicon-based TFT using amorphous silicon or the like for the channel layer. Thereby, the voltage written in the pixel capacitance Cp of each pixel forming unit 10 is held for a longer period.
- In—Ga—Zn—O indium gallium zinc
- oxide semiconductor other than In—Ga—Zn—O for example, indium, gallium, zinc, copper (Cu), silicon (Si), tin (Sn), aluminum (Al), calcium (Ca), germanium ( A similar effect can be obtained even when an oxide semiconductor containing at least one of Ge) and lead (Pb) is used for the channel layer.
- the detailed configuration of the display control unit 200 will be described later, but is typically realized as an IC (Integrated Circuit).
- the display control unit 200 controls the data signal line drive circuit control signal Ssc, the scanning signal line based on these signals.
- a drive circuit control signal Sgc, a common voltage signal (not shown), and the like are generated.
- the data signal line drive circuit control signal Ssc is supplied to the data signal line drive circuit 310, the scan signal line drive circuit control signal Sgc is supplied to the scan signal line drive circuit 320, and the common voltage signal is provided in the display unit 500.
- the display control unit 200 also switches an amplifier enable signal (also referred to as “driving / pause control signal”) AE, data voltage for switching between normal driving and pause driving, or switching between a driving period and a pause period in pause driving.
- a polarity control signal PC for switching the polarity from positive polarity to negative polarity or switching from negative polarity to positive polarity and a dot clock output signal DCLK_OUT, which will be described later, are generated, and these signals are sent to the data signal line drive circuit 310. give.
- the gradation control unit 400 outputs the image data DV transmitted from the host as the image signal DS to the data signal line driving circuit 310, or corrects the gradation value represented by the image data DV to correct the large gradation value.
- An image signal DCS is generated and output to the data signal line driving circuit 310.
- the data signal line drive circuit control signal Ssc supplied to the data signal line drive circuit 310 includes, for example, a source start pulse signal, a source clock signal, a latch strobe signal, and the like.
- the data signal line driving circuit 310 operates an internal shift register and sampling latch circuit (not shown) in accordance with the data signal line driving circuit control signal Ssc, so that an image signal supplied from the gradation control unit 400 is obtained.
- the DS and the corrected image signal DCS are respectively converted into a data voltage and an overshoot voltage which are analog signals by a DA converter circuit (not shown), and applied to each data signal line SL.
- the scanning signal line driving circuit 320 repeats the application of the active scanning signal to each scanning signal line GL in a predetermined cycle in accordance with the scanning signal line driving circuit control signal Sgc.
- the scanning signal line drive circuit control signal Sgc includes, for example, a gate clock signal and a gate start pulse signal. In response to the gate clock signal and the gate start pulse signal, the scanning signal line driving circuit 320 generates a scanning signal by operating a shift register (not shown) therein and applies it to each scanning signal line GL.
- a backlight unit (not shown) is provided on the back side of the display unit 500, and the backlight unit irradiates backlight light from the back side of the display unit 500.
- the backlight unit may be controlled by the display control unit 200, or may be controlled by other methods.
- the liquid crystal panel is a reflection type, it is not necessary to provide a backlight unit.
- the scanning signal is applied to each scanning signal line GL, the overshoot voltage and the data voltage are sequentially applied to each data signal line SL, and the backlight unit is driven to transmit the scanning signal.
- An image represented by the image data DV is displayed on the display unit 500 of the liquid crystal panel.
- FIG. 8 is a block diagram illustrating a configuration of the display control unit 200 included in the liquid crystal display device 100 according to the present embodiment.
- the display control unit 200 includes a drive / pause control circuit 21, a polarity control circuit 22, a timing generator 23, and a drive frequency control circuit 24.
- the drive frequency control circuit 24 includes a PLL (Phase Locked Loop). ) Circuit 25 and selector 26.
- the display control unit 200 is provided with a first dot clock signal DCLK_A and signals such as a synchronization signal Hsync, Vsync, and the like, and a dot clock selection signal SEL_DCLK (sometimes referred to as “update information”) is a gradation control unit 400.
- the dot clock selection signal SEL_DCLK includes information indicating either the pause driving or the normal driving and information indicating the transmission speed (clock speed) of the image data DV necessary for each driving.
- the PLL circuit 25 is based on the first dot clock signal DCLK_A.
- a second dot clock signal DCLK_B indicating the transmission speed of the image data in the data voltage writing period (also referred to as “second frame period”) is generated and supplied to the selector 26.
- the clock speed indicated by the second dot clock signal DCLK_B is faster than the clock speed indicated by the first dot clock signal DCLK_A
- the length of one frame period when the second dot clock signal DCLK_B is given is This is shorter than the length of one frame period when the one dot clock signal DCLK_A is given.
- the length of one frame period can be changed depending on which of the first and second dot clock signals DCLK_A and DCLK_B is supplied to the data signal line driver circuit 310.
- the selector 26 selects either the first dot clock signal DCLK_A or the second dot clock signal DCLK_B according to the dot clock selection signal SEL_DCLK given from the gradation control unit 400 and outputs the selected signal to the timing generator 23. That is, the selector 26 selects and outputs the first dot clock signal DCLK_A when performing normal driving based on the dot clock selection signal SEL_DCLK, and selects the second dot clock signal DCLK_B when performing pause driving. Output.
- the first or second dot clock signal DCLK_A, DCLK_B selected and output by the selector 26 is referred to as a dot clock output signal DCLK_OUT.
- this invention since this invention has a big effect by applying to a rest drive, below, the case where it applies to a rest drive is demonstrated in detail, and the case where it applies to a normal drive is demonstrated supplementarily.
- the timing generator 23 uses the data signal line drive circuit for the synchronization signal Hsync and Vsync.
- the control signal Ssc and the scanning signal line drive circuit control signal Sgc are generated, and the data signal line drive circuit control signal Ssc is supplied to the data signal line drive circuit 310, the drive / pause control circuit 21 and the polarity control circuit 22,
- the scanning signal line driving circuit control signal Sgc is supplied to the scanning signal line driving circuit 320.
- the timing generator 23 uses the dot clock output signal DCLK_OUT given from the selector 26 as a data signal line drive circuit 310, a drive / pause control circuit 21, a polarity control circuit 22, and a frame memory 31 of a gradation control unit 400 described later. To give.
- the drive / pause control circuit 21 is based on the dot clock selection signal SEL_DCLK given from the gradation control unit 400, the dot clock output signal DCLK_OUT given from the timing generator 23, and the data signal line drive circuit control signal Ssc.
- An amplifier enable signal AE is generated and applied to the data signal line drive circuit 310.
- the drive / pause control circuit 21 generates an active amplifier enable signal AE and supplies the active amplifier enable signal AE to the data signal line drive circuit 310 during the overshoot drive period and the data voltage writing period of the pause drive.
- An analog amplifier (not shown) provided in is operated. Thereby, the data signal line driving circuit 310 applies the overshoot voltage and the data voltage to the data signal line SL in order.
- the analog amplifier is paused by generating an inactive amplifier enable signal AE and supplying it to the data signal line drive circuit 310. That is, when the dot clock selection signal SEL_DCLK indicating that the image data DV has not been updated is given, the drive / pause control circuit 21 performs overshoot drive period and data voltage writing in order to perform pause drive.
- An amplifier enable signal AE that instructs to refresh the screen by increasing the clock speed of the period is generated, and the amplifier enable signal AE is output to the data signal line driver circuit 310. In this way, the drive / pause control circuit 21 sets an overshoot drive period and a data voltage writing period that are shorter than the length of a normal one frame period.
- the drive / pause control circuit 21 provides only the data voltage writing period, In addition, an amplifier enable signal AE that instructs to refresh the screen at a normal clock speed is generated, and the amplifier enable signal AE is output to the data signal line driver circuit 310. As a result, the liquid crystal display device 100 is driven by normal driving. In this way, the drive / pause control circuit 21 can output the amplifier enable signal AE corresponding to the pause drive or the normal drive to the data signal line drive circuit 310 based on the input image data.
- the polarity control circuit 22 generates a polarity control signal PC that inverts the polarity of the image signal DS based on the dot clock output signal DCLK_OUT and the data signal line drive circuit control signal Ssc given from the timing generator 23, and drives the data signal line. This is applied to the circuit 310.
- the data signal line drive circuit 310 makes the polarity of the overshoot voltage and the data voltage applied to the data signal line SL positive or negative based on the polarity control signal PC.
- the scanning signal line driving circuit 320 sequentially selects and drives each scanning signal line GL based on the scanning signal line driving circuit control signal Sgc.
- the data signal line driving circuit 310 receives the image signal DS output from the gradation control unit 400 based on the data signal line driving circuit control signal Ssc, the dot clock output signal DCLK_OUT, the polarity control signal PC, and the amplifier enable signal AE.
- the data voltage that is an analog signal is converted, and the data voltage is applied to each data signal line SL.
- the corrected image signal DCS is converted into an overshoot voltage, and the overshoot voltage is applied to the data signal line SL.
- the overshoot voltage and the data voltage applied to the data signal line SL are sequentially written into the pixel formation unit 10 connected to the scanning signal line GL selected by applying an active scanning signal.
- the period in which the data signal line driving circuit 310 can apply the data voltage or the overshoot voltage to the data signal line SL is a period in which the active amplifier enable signal AE is received from the driving / pause control circuit 21.
- the polarity of the data voltage and the overshoot voltage applied to the data signal line SL is determined by the polarity control signal PC.
- the data signal line driving circuit 310 may apply a ground potential to each data signal line SL during the idle period. Thereby, since the potential of each data signal line is fixed, malfunction due to noise can be prevented. Alternatively, the data signal line driver circuit 310 may stop the operation, thereby floating the potential of the data signal line SL. Thereby, the power consumption of the data signal line driving circuit 310 can be reduced.
- the gradation control unit 400 outputs, to the data signal line driving circuit 310, a corrected image signal DCS that has been subjected to correction for emphasizing changes to the image data DV transmitted from the host, or an image signal DS that has not been corrected.
- the configuration of such a gradation control unit 400 will be described.
- the gradation control unit 400 includes a frame memory 31, a comparison circuit 32, an LUT 33, and an addition circuit 34.
- the frame memory 31 can store the image data DV transmitted from the host for only one frame.
- the comparison circuit 32 determines the tone value of the image data DV (the tone value of the current frame) and the tone value of the image signal DS stored in the frame memory 31 in the immediately preceding frame period (the tone value of the previous frame). ) And the gradation values are given to the LUT 33.
- the LUT 33 stores a plurality of correction values associated with each gradation value of the previous frame and each gradation value of the current frame. If the comparison circuit 32 gives the gradation value of the previous frame and the gradation value of the current frame to the LUT 33, the LUT 33 reads the correction values associated with them and supplies them to the addition circuit 34.
- the comparison circuit 32 obtains the gradation value of the current frame based on the image data DV of the current frame and the gradation value of the previous frame based on the image data DV of the previous frame stored in the frame memory 31. Compare them. When it is determined that the gradation values are equal, the comparison circuit 32 notifies the display control unit 200 to perform pause driving, assuming that the image has not been updated. For this purpose, the comparison circuit 32 generates a dot clock selection signal SEL_DCLK indicating that the second dot clock signal DCLK_B for increasing the clock speed in the driving period should be selected, and the driving / pause control circuit 21 of the display control unit 200. This is given to the selector 26.
- the comparison circuit 32 If it is determined that the gradation values are not equal, the comparison circuit 32 notifies the display control unit 200 to perform normal driving, assuming that the image has been updated. Therefore, the comparison circuit 32 generates a dot clock selection signal SEL_DCLK indicating that the first dot clock signal DCLK_A should be selected, and supplies the dot clock selection signal SEL_DCLK to the drive / pause control circuit 21 and the selector 26 of the display control unit 200.
- the addition circuit 34 is connected to the frame memory 31 and the LUT 33, and is given the image data DV stored in the frame memory 31.
- the adder circuit 34 adds the correction value given from the LUT 33 to the gradation value of the current frame given from the frame memory 31 to generate the corrected image signal DCS, and sends it to the data signal line drive circuit 310.
- the data signal line drive circuit 310 D / A converts the corrected image signal DCS into an overshoot voltage and applies it to the data signal line SL.
- the image data DV stored in the frame memory 31 is immediately supplied from the frame memory 31 to the adding circuit 34.
- the adder circuit 34 outputs the image data DV given from the frame memory 31 to the data signal line drive circuit 310 as an image signal DS.
- the dot clock output signal DCLK_OUT output from the timing generator 23 is supplied not only to the data signal line driving circuit 310 but also to the frame memory 31.
- the image data DV stored in the frame memory 31 is supplied to the comparison circuit 32 and the addition circuit 34 at a high clock speed, so that the length of the overshoot period and the data voltage writing period is increased. Can be shortened.
- FIG. 9 is a diagram illustrating an example of the configuration of the LUT 33 used in the liquid crystal display device 100 according to the present embodiment.
- the LUT 33 stores correction values for emphasizing temporal changes in the image data DV in association with the combination of the gradation value of the previous frame and the gradation value of the current frame. .
- the corresponding correction value is 6 gradations from the LUT 70. Therefore, the addition circuit 34 generates the corrected image signal DCS by adding the correction value to the image data DV.
- the correction value of the closest gradation value stored in the LUT 33 is used and the correction value is obtained by the interpolation method.
- FIG. 10 is a timing chart showing a driving method of the liquid crystal display device 100 according to the present embodiment.
- the liquid crystal display device 100 writes the positive overshoot voltage in the first frame period and the positive data voltage in the second frame period in the first drive period. Thereafter, in order to keep the positive data voltage written in the second frame period as it is, (N + 1) pause frame periods are inserted and set as a pause period.
- a negative overshoot voltage is written in the first frame period, and a negative data voltage is written in the second frame period.
- (N + 1) pause frame periods are inserted and set as a pause period.
- a positive overshoot voltage is written in the first frame period, and a positive data voltage is written in the second frame period.
- a pause period in which the positive data voltage written in the second frame period is maintained as it is.
- a negative overshoot voltage is written in the first frame period, and a negative data voltage is written in the second frame period. After that, a pause period in which the negative polarity data voltage written in the second frame period is maintained as it is.
- the lengths of the first and second frame periods in each drive period are shorter than the normal one frame period, for example, 1/2 the length of the normal one frame period.
- Period hereinafter referred to as “1/2 frame period”
- the length of the subsequent pause frame period is the same as the length of a normal one frame period.
- FIG. 11 is a diagram showing a change in luminance in one pixel forming unit 10 when the polarity of the data voltage changes from positive polarity to negative polarity in the driving method of the present embodiment.
- the overshoot period is set to 1/2 frame period. In this way, immediately before writing the data voltage corresponding to the image signal DS to the pixel forming unit 10, by writing the overshoot voltage corresponding to the gradation value larger than the gradation value of the image signal DS, It is possible to suppress a significant decrease in luminance immediately after reversing the polarity.
- by making the overshoot voltage writing time shorter than the normal one frame period it is possible to shift to the next second frame period in a state where the luminance does not increase significantly in the first frame period.
- FIG. 12 is a diagram for explaining that the occurrence of flicker is suppressed when driven by the driving method shown in FIG. As shown in FIG. 12, by performing overshoot driving in the first one frame period, a rapid decrease in luminance immediately after switching the polarity is suppressed.
- the area of the “positive effective region” is small and is substantially equal to the area of the “negative effective region”, so that the occurrence of flicker based on flexopolarization is suppressed.
- the length of the first frame period in which overshoot driving is performed in each driving period is a half period of 16.7 msec which is a normal one frame period, that is, a 1/2 frame period.
- the length of the pause frame period is 16.7 msec, which is a normal one frame period.
- the pause period shown in FIG. 10 is an (N + 1) frame period, which is longer by one frame than the N frame period, which is the pause period shown in FIG.
- the length of the second frame period in each driving period is preferably set to a 1 ⁇ 2 frame period that is the same as the length of the first frame period.
- the time from when the overshoot voltage is written to when the data voltage is written that is, the time from when the overshoot voltage is written to when it is written.
- the area of the “positive effective region” is the same in each pixel forming unit 10, and flicker unevenness can be suppressed.
- the length of the second frame period may be different from the length of the first frame period.
- the length of the first frame period If the length of the first frame period is longer than the normal one frame period, the overshoot voltage written in each pixel formation portion becomes too high. As a result, the area of the “positive effective region” becomes too larger than the area of the “negative effective region”, and flicker based on flexo polarization tends to occur. For this reason, the length of the overshoot drive period needs to be less than one frame period.
- the TFT 11 is turned off before a sufficient overshoot voltage is written in each pixel forming unit 10. For this reason, the absolute value of the overshoot voltage to be written in each pixel forming unit 10 becomes small. As a result, the area of the “positive effective region” is smaller than the area of the “negative effective region”, and flicker based on flexo polarization is likely to occur.
- the inventor has found that it is preferable to set the application time of the overshoot voltage to 1 ⁇ 4 frame period or more for the following reason. That is, in a display having a vertical resolution of 2048, in order to write 99% of the voltage value applied to the data signal line SL to the pixel forming unit 10, the charging time (the length of one horizontal period) is at least 2. It was found that it must be 0 ⁇ sec or more. For this reason, the time required to write the overshoot voltage to the pixel forming portion 10 for one screen is obtained by the following equation (1).
- the 4.2 msec obtained by the above equation (1) is about 1/4 of the normal 1frame period of 16.7 msec. From this, in this embodiment, in order to suppress the occurrence of flicker based on flexopolarization, it is understood that the length of the frame period to which the overshoot voltage is applied must be at least 1/4 frame period. It was.
- the lengths of the first and second frame periods in each driving period must be less than one frame period and not less than 1 ⁇ 4 frame period.
- overshoot driving is performed in the first frame period of each driving period.
- the length of the first frame period in which the overshoot voltage is applied is set to be a quarter or more of the normal one frame period and less than the normal one frame period.
- the length of the second frame period is set to the same period as the length of the first frame period. It is preferable. Accordingly, it is possible to uniformly suppress the occurrence of flicker based on flexopolarization in each pixel forming unit 10.
- FIG. 13 is a timing chart showing a driving method of the liquid crystal display device according to the first modification of the present embodiment.
- the gradation value of the previous frame is equal to the gradation value of the current frame. Therefore, the first and second frame periods are provided, the length of each frame period is 1 ⁇ 2 frame period, positive overshoot voltage is written in the first frame period, and positive polarity is written in the second frame period. Write data voltage. Thereafter, in order to keep the positive data voltage written in the second frame period as it is, (N + 1) pause frame periods are inserted and set as a pause period.
- the gradation value of the previous frame is different from the gradation value of the current frame. Therefore, in order to perform normal driving, a third frame period (third F period) having the same length as the normal one frame period is provided, and a negative data voltage is written in the third frame period.
- the gradation value of the previous frame is equal to the gradation value of the current frame, so the pause drive is performed again as in the case of the first drive period.
- pause driving is performed, and when the gradation value of the previous frame is different from the gradation value of the current frame, normal driving is performed. repeat.
- the area of the “positive effective region” and the area of the “negative effective region” are substantially equal, and the occurrence of flicker based on flexopolarization is suppressed.
- the overshoot drive for applying the overshoot voltage larger than the data voltage is performed before the screen is refreshed with the data voltage corresponding to the image data.
- the undershoot period is made shorter than the normal one frame period. Accordingly, it is possible to uniformly suppress the occurrence of flicker based on flexopolarization in each pixel forming unit 10.
- the addition circuit 34 subtracts the correction value supplied from the LUT 33 from the gradation value of the current frame supplied from the frame memory 31 to generate the corrected image signal DCS.
- the process of generating the corrected image signal DCS by adding or subtracting the correction value given from the LUT 33 to the gradation value of the current frame given from the frame memory 31 is called “gradation correction process”, and is an overshoot.
- the voltage and the undershoot voltage are sometimes referred to as “gradation correction voltage”.
- Second Embodiment> If the temperature around the liquid crystal display device 100 changes, not only the alignment deformation caused by the dielectric anisotropy, but also the alignment deformation caused by the flexopolarization changes. For example, even if overshoot driving is performed at a low temperature using an LUT that stores a correction value set at a normal temperature, the response speed of the liquid crystal at a low temperature is reduced and the speed is not sufficiently high. As a result, it is difficult to adjust the area of the “positive effective region” to be approximately the same as the area of the “negative effective region” within a period shorter than one frame period.
- the liquid crystal display device 100 used in a wide temperature range includes a plurality of different LUTs for each temperature range so that an optimum overshoot drive can be performed by adding an optimum correction value according to the temperature. It is preferable to have.
- FIG. 14 is a block diagram showing a configuration of the liquid crystal display device 100 according to the present embodiment
- FIG. 15 is a block diagram showing a configuration of the display control unit 200 included in the liquid crystal display device 100 shown in FIG.
- a temperature sensor 27 is provided in the display control unit 200 of the liquid crystal display device 100 as shown in FIGS.
- Three different LUTs 35a to 35c are provided for each.
- the same components as those shown in FIGS. 7 and 8 are denoted by the same reference numerals, and the description thereof is omitted. The description will focus on the different components. .
- FIG. 16 is a diagram showing an example of a normal temperature LUT 35a used in the liquid crystal display device 100
- FIG. 17 is a diagram showing an example of a high temperature LUT 35b
- FIG. 18 is a diagram showing an example of a low temperature LUT 35c.
- FIG. As can be seen from FIGS. 16 to 18, the correction values are set so as to decrease in the order of the low temperature LUT 35c, the normal temperature LUT 35a, and the high temperature LUT 35b.
- the overshoot voltage at a low temperature at which the response speed of the liquid crystal is lowered is set to be larger than that at normal temperature, and the overshoot voltage at high temperature is set to be smaller than that at normal temperature.
- LUTs 35a to 35c provided for each temperature range are also called sub-tables. Further, the number of LUTs provided for each temperature range is not limited to three, and may be more or less depending on the purpose of use of the liquid crystal display device.
- the temperature sensor 27 is provided in the display control unit 200, and one of the LUTs 35a to 35c is selected based on the temperature information Tp from the temperature sensor 27.
- the temperature sensor 27 is provided in the display control unit 200, it may be provided on the display unit 500 separately from the display control unit 200.
- the display control unit 200 acquires the temperature information Tp from the temperature sensor 27 by serial communication, and selects any one of the LUTs 35a to 35c corresponding to the temperature information Tp.
- the temperature sensor 27 can be provided at an arbitrary position on the insulating substrate.
- the circuit configuration of the display control unit 200 is not complicated. Thereby, the manufacturing cost of the liquid crystal display device 100 can be reduced.
- the overshoot drive is performed by selecting any of the LUTs 35a to 35c according to the temperature information Tp of the environment in which the liquid crystal display device 100 is used, which is measured by the temperature sensor 27.
- the “positive effective area” and the “negative effective area” can be made substantially equal regardless of the temperature of the environment in which they are performed. Thus, even in the liquid crystal display device 100 used in a wide temperature range, the occurrence of flicker due to flexopolarization can be suppressed.
- the liquid crystal display device 100 driven by the horizontal electric field method has been described.
- the present invention can be similarly applied to a liquid crystal display device driven by the vertical electric field method.
- inversion driving in each liquid crystal display device can be applied to AC driving by any of the dot inversion driving, line inversion driving, column inversion driving, and frame inversion driving. Even in this case, the same effects as those of the above embodiments can be obtained.
- the present invention is applied to a liquid crystal display device that performs AC driving, and in particular, is applied to a liquid crystal display device that performs lateral electric field driving or pause driving.
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Abstract
Description
絶縁基板上に形成された複数本の走査信号線と、
前記複数本の走査信号線とそれぞれ交差する複数本のデータ信号線と、
前記複数本の走査信号線および前記複数本のデータ信号線の各交差点にそれぞれ形成された複数個の画素形成部と、
入力画像データに対して信号の時間的変化を補正する階調補正処理を行った補正画像信号、および、前記入力画像データに対して前記階調補正処理を行わない画像信号のいずれかを出力する階調制御部と、
前記複数の走査信号線を順に選択して走査する走査信号線駆動回路と、
前記画像信号に基づいて生成された目標階調値に対応するデータ電圧と、前記補正画像信号に基づいて生成された、前記データ電圧を補正した階調補正電圧のいずれかを前記複数のデータ信号線に印加するデータ信号線駆動回路と、
前記走査信号線駆動回路および前記データ信号線駆動回路を制御する表示制御部とを備え、
前記表示制御部は、前記複数の画素形成部に、第1フレーム期間に前記階調補正電圧を書込み、第2フレーム期間に前記階調補正電圧と同じ極性の前記データ電圧を書き込むことによって画面のリフレッシュを行うように制御し、
前記第1フレーム期間の長さは、リフレッシュレートが60Hzの時の1フレーム期間の1/4以上の期間であって、かつ前記1フレーム期間未満の期間であることを特徴とする。
前記第2フレーム期間の長さは、前記第1フレーム期間の長さと同じであることを特徴とする。
前記表示制御部は、前記第2フレーム期間において前記複数の画素形成部への前記データ電圧の書込みが終了した後に、前記複数の画素形成部への前記データ電圧の書き込みを休止する休止期間を設けることを特徴とする。
前記階調制御部は
前記入力画像データをフレームごとに記憶するフレームメモリと、
前記入力画像データの前フレームの階調値および現フレームの階調値に対応づけられた補正値を記憶するテーブルと、
前記入力画像データの現フレームの階調値と前記フレームメモリに記憶されていた前記入力画像データの前フレームの階調値とを求めて前記テーブルに出力する比較回路と、
前記入力画像データに基づいて前記補正画像信号および前記画像信号のいずれかを前記データ信号線駆動回路に出力する加算回路とを含み、
前記テーブルは、前記入力画像データの現フレームの階調値と前フレームの階調値との組合せにそれぞれ対応づけられた補正値を記憶し、前記比較回路から前記入力画像データの現フレームの階調値と前フレームの階調値とを与えられれば、前記組合せの中から対応する補正値を前記加算回路に出力し、
前記加算回路は、前記補正画像信号を出力するときには、前記テーブルから与えられた補正値によって前記入力画像データの階調値を補正して出力し、前記画像信号を出力するときには、前記入力画像データの階調値を補正することなく出力することを特徴とする。
前記表示制御部は、前記比較回路から前記入力画像データが更新されていないことを示す更新情報を与えられたとき、前記更新情報に基づいて前記第1フレーム期間の長さを前記1フレーム期間の長さよりも短くなるように調整する駆動周波数制御回路を含むことを特徴とする。
前記更新情報は、前記入力画像データが更新されていないことを示す第1更新情報と、前記入力画像データが更新されていることを示す第2更新情報とを含み、
前記表示制御部は、前記比較回路から、前記第1更新情報を与えられたときには、前記階調補正電圧を書き込む階調補正期間および前記データ電圧を書き込むデータ電圧書込期間からなる駆動期間と、休止期間とを交互に切り替え、前記第2更新情報を与えられたときには、前記データ電圧書込期間のみを設けることを示す駆動/休止制御信号を生成するための駆動/休止制御回路をさらに含むことを特徴とする。
前記液晶表示装置の周囲の温度を測定する温度センサをさらに備え、
前記テーブルは、所定の温度範囲ごとに異なる補正値を記憶する複数の副テーブルを含み、
前記テーブルは、前記温度センサから与えられる温度情報に基づき、前記複数の副テーブルから前記温度情報に対応する1つの副テーブルを選択することを特徴とする。
前記画素形成部は、前記走査信号線に制御端子が接続され、前記データ信号線に第1導通端子が接続され、前記データ電圧または前記階調補正電圧が印加されるべき画素電極に第2導通端子が接続され、酸化物半導体によりチャネル層が形成された薄膜トランジスタを含むことを特徴とする。
前記酸化物半導体は、インジウム、ガリウム、亜鉛、および酸素を含むことを特徴とする。
前記データ信号線駆動回路は、前記休止期間中において前記データ信号線に接地電位を印加することを特徴とする。
前記データ信号線駆動回路は、前記休止期間中において前記データ信号線の電位をフローティングにすることを特徴とする。
前記絶縁基板上に、共通電極と画素電極とが、一方の電極上に他方の電極が絶縁膜を介して重畳的に形成され、前記他方の電極上に複数の開口部が形成されていることを特徴とする。
リフレッシュレートが60Hzの時の1フレーム期間の1/4以上の期間であって、かつ前記1フレーム期間未満である期間に、前記入力画像データの目標階調値に対応するデータ電圧に階調補正処理を施した階調補正電圧を画素形成部に書き込むことにより液晶層に前記階調補正電圧を印加する階調補正電圧印加ステップと、
前記データ電圧を、前記階調補正処理を施すことなく前記画素形成部に書き込むことにより前記液晶層に前記データ電圧を印加するデータ電圧印加ステップとを備えることを特徴とする。
前記データ電圧印加ステップにおいて前記データ電圧を印加する期間は、前記階調補正電圧印加ステップにおいて前記階調補正電圧を印加する期間と同じ長さの期間であることを特徴とする。
<1.1 フリッカの発生原因>
液晶表示装置の駆動方式には、絶縁基板に対して垂直な方向に電圧を印加するVAモード等の縦電界方式と、絶縁基板に対して概ね平行な方向に電圧を印加するIPSモードやFFSモード等の横電界方式がある。横電界方式では、縦電界方式の場合と異なり、絶縁基板に対して概ね平行な方向の電界を発生させるために、一方の絶縁基板(アレイ基板)上に画素電極だけでなく共通電極も形成されている。これらの画素電極と共通電極との間に電圧を印加すれば、液晶分子は絶縁基板に対して平行な面内で回転し、電界の方向に配向する。このような横電界方式を採用した液晶表示装置では、縦電界方式を採用した液晶表示装置に比べて視野角特性が優れている。特にFFSモードの液晶パネルは、IPSモードの液晶パネルが有する低開口率および低透過率という問題点を解決するために開発されたパネルであり、斜め電界方式とも呼ばれる。
同一の画素形成部10内におけるフレクソ分極に基づく輝度の変化について説明する。図3は、第1の基礎検討において、画像信号の目標階調値に対応するデータ電圧(以下「データ電圧」と略す)の極性が正極性から負極性に変化する際に、1つの画素形成部10内における輝度の変化を示す図である。上述のように、1つの画素形成部10内には、スリット12sからの距離に応じて輝度の異なる2つの領域がある。このような画素形成部に正極性の画像信号が書き込まれることによって、スリット12sに近い第1領域P1の輝度は、スリット12sから離れている第2領域P2の輝度に比べて高くなっている。
第1の基礎検討において、データ電圧の極性が正極性から負極性に切り替わるときに、第1領域P1が高輝度から低輝度に変化する速度に比べて、第2領域P2が低輝度から高輝度に変化する速度が遅いために、データ電圧の極性が切り替わった直後に輝度が大きく低下するという問題があった。このため、交流駆動においてデータ電圧の極性が切り替わった直後の第1領域P1の輝度の急激な低下を抑制することができれば、フリッカの発生を抑制できると考えられる。
以下の説明において、休止駆動とは、画面をリフレッシュする駆動期間と、リフレッシュを休止する休止期間とを交互に繰り返す駆動をいい、通常駆動とは、駆動期間のみからなり、休止期間を含まない駆動をいう。また、休止駆動における駆動期間は、後述するように、オーバーシュート駆動期間と、画像データに応じたデータ電圧を書き込むデータ電圧書込期間を含み、通常駆動における駆動期間はデータ電圧書込期間のみを含む。また、「1フレーム期間」とは1画面分のリフレッシュに必要な期間であり、後述の各実施形態では、リフレッシュレートが60Hzのときの1フレーム期間の長さである16.7msecを「1フレーム期間」の長さとするが、本発明はこれに限定されない。
図7は、本実施形態に係る液晶表示装置100の構成を示すブロック図である。この液晶表示装置100は、表示制御部200と、駆動部300と、階調制御部400と、表示部500とを備えている。駆動部300は、データ信号線駆動回路310と走査信号線駆動回路320とを含んでいる。表示部500は液晶パネルを構成する。この液晶パネルは、表示部500と、データ信号線駆動回路310および走査信号線駆動回路320の双方または一方とが一体的に形成された構成としてもよい。液晶表示装置100の外部には、主としてCPU(Central Processing Unit)により構成されるホスト(図示しない)が設けられており、ホストは表示部500に表示すべき画像を表す画像データDV(「入力画像データ」ともいう)を含むデータを液晶表示装置100に送信する。
図8は、本実施形態に係る液晶表示装置100に含まれる表示制御部200の構成を示すブロック図である。図8に示すように、表示制御部200は、駆動/休止制御回路21、極性制御回路22、タイミングジェネレータ23、および駆動周波数制御回路24を含み、駆動周波数制御回路24は、PLL(Phase Locked Loop)回路25およびセレクタ26を含む。表示制御部200には、第1ドットクロック信号DCLK_Aや、同期信号Hsync、Vsync等の信号がホストから与えられ、ドットクロック選択信号SEL_DCLK(「更新情報」という場合がある)が階調制御部400から与えられる。ドットクロック選択信号SEL_DCLKには、休止駆動と通常駆動のいずれかを示す情報と共に、それぞれの駆動に必要な画像データDVの送信速度(クロック速度)を示す情報が含まれている。
階調制御部400は、ホストから送信された画像データDVに対して変化を強調する補正を行った補正画像信号DCS、または補正を行わない画像信号DSをデータ信号線駆動回路310に出力する。このような階調制御部400の構成を説明する。図7に示すように、階調制御部400は、フレームメモリ31、比較回路32、LUT33および加算回路34を含む。フレームメモリ31は、ホストから送信された画像データDVを1フレーム分だけ記憶することができる。
上記第1および第2基礎検討の結果から、「正の実効領域」の面積と「負の実効領域」の面積が概ね等しくなるようにオーバーシュート駆動を行った後に、目標階調値に対応する画像信号DSを画素形成部10に書き込めば、フレクソ分極に起因するフリッカの発生を抑制できることがわかる。
2.0(μsec)×2048/100≒4.2(msec)…(1)
上記式(1)によって求めた4.2msecは通常の1フレーム期間の長さである16.7msecの約1/4になる。このことから、本実施形態において、フレクソ分極に基づくフリッカの発生を抑制するためには、オーバーシュート電圧を印加するフレーム期間の長さは、少なくとも1/4フレーム期間以上でなければならないことがわかった。
本実施形態によれば、各駆動期間の第1フレーム期間に、オーバーシュート駆動を行う。このオーバーシュート駆動において、オーバーシュート電圧を印加する第1フレーム期間の長さを、通常の1フレーム期間の1/4以上の期間であって、かつ通常の1フレーム期間未満とする。これにより、「正の実効領域」の面積と「負の実効領域」の面積とが概ね等しくなり、フレクソ分極に基づくフリッカの発生が抑制される。
上記実施形態では、前フレームの階調値と現フレームの階調値とが等しくない場合には、通常駆動が行われるとした。しかし、休止駆動を行っているときに、前フレームの階調値と現フレームの階調値とが等しくない場合も生じる。図13は、本実施形態の第1の変形例に係る液晶表示装置の駆動方法を示すタイミングチャートである。
上記実施形態では、画像データに応じたデータ電圧によって画面をリフレッシュする前に、データ電圧よりも大きなオーバーシュート電圧を印加するオーバーシュート駆動を行った。しかし、オーバーシュート駆動を行う代わりに、データ電圧よりも小さなアンダーシュート電圧を印加するアンダーシュート駆動を行うことが好ましい場合がある。このようなアンダーシュート駆動においても、「正の実効領域」の面積を「負の実効領域の面積」と概ね等しくするために、アンダーシュート期間を通常の1フレーム期間よりも短くする。これにより、各画素形成部10においてフレクソ分極に基づくフリッカの発生をむらなく抑制することが可能になる。この場合、アンダーシュート駆動を行う場合には、加算回路34は、フレームメモリ31から与えられる現フレームの階調値から、LUT33から与えられる補正値を減算して補正画像信号DCSを生成する。
液晶表示装置100の周囲の温度が変化すれば、誘電率異方性により引き起こされる配向変形だけでなく、フレクソ分極によって引き起こされる配向変形も変化する。例えば、常温で設定した補正値を記憶したLUTを用いて、低温時にオーバーシュート駆動を行っても、低温時の液晶の応答速度が低下していて、十分速くならない。その結果、1フレーム期間よりも短い期間内に「正の実効領域」の面積を「負の実効領域」の面積と同程度になるように調整することは難しい。一方、高温時に常温時と同じ条件でオーバーシュート駆動を行えば、高温時の液晶の応答速度が速いので、画像の輝度が高くなり過ぎ、「正の実効領域」の面積が大きくなり過ぎる。このように、周囲の温度が高くても低くても、「正の実効領域」の面積と、「負の実効領域」の面積がバランスしなくなるので、フレクソ分極に基づくフリッカが発生しやすくなる。そこで、広い温度範囲で使用される液晶表示装置100は、温度に応じた最適な補正値を加算して最適なオーバーシュート駆動を行うことができるように、温度範囲ごとに異なる複数個のLUTを有することが好ましい。
図14は、本実施形態に係る液晶表示装置100の構成を示すブロック図であり、図15は図14に示す液晶表示装置100に含まれる表示制御部200の構成を示すブロック図である。図7に示す液晶表示装置100の場合と異なり、図14および図15に示すように、液晶表示装置100の表示制御部200に温度センサ27が設けられ、また階調制御部400には温度範囲ごとに異なる3個のLUT35a~35cが設けられている。なお、図14および図15に示す構成要素のうち、図7および図8に示す構成要素と同じ構成要素には同じ参照符号を付してその説明を省略し、異なる構成要素を中心に説明する。
本実施形態によれば、温度センサ27によって測定された、液晶表示装置100が使用される環境の温度情報Tpに応じて、LUT35a~35cのいずれかを選択してオーバーシュート駆動を行うので、使用される環境の温度によらず「正の実効面積」と「負の実効面積」とを概ね等しくすることができる。このように、広い温度範囲で使用される液晶表示装置100においても、フレクソ分極によるフリッカの発生を抑制することができる。
上記各実施形態では、横電界方式によって駆動される液晶表示装置100について説明したが、縦電界方式によって駆動される液晶表示装置にも本発明を同様に適用することができる。
11…薄膜トランジスタ(TFT)
11a…チャネル層(半導体層)
12…画素電極
12s…開口部(スリット)
13…共通電極
16…絶縁膜
18…配向膜
21…駆動/休止制御回路
22…極性制御回路
23…タイミングジェネレータ
24…駆動周波数制御回路
25…PLL回路
26…セレクタ
27…温度センサ
31…フレームメモリ
32…比較回路
33、35…ルックアップテーブル(LUT)
35a…常温用ルックアップテーブル(副テーブル)
35b…高温用ルックアップテーブル(副テーブル)
35c…低温用ルックアップテーブル(副テーブル)
34…加算回路
40…階調制御部
50…加算回路
100…液晶表示装置
200…表示制御部
310…データ信号線駆動回路
320…ソース信号線駆動回路
400…階調制御部400
500…表示部
Cp…画素容量
GL…走査信号線
SL…データ信号線
CS…コモン配線
DV…画像データ(入力画像データ)
DS…画像信号
DCS…補正画像信号
P1…第1領域
P2…第2領域
Tp…温度情報
Claims (15)
- 交流駆動を行う液晶表示装置であって、
絶縁基板上に形成された複数本の走査信号線と、
前記複数本の走査信号線とそれぞれ交差する複数本のデータ信号線と、
前記複数本の走査信号線および前記複数本のデータ信号線の各交差点にそれぞれ形成された複数個の画素形成部と、
入力画像データに対して信号の時間的変化を補正する階調補正処理を行った補正画像信号、および、前記入力画像データに対して前記階調補正処理を行わない画像信号のいずれかを出力する階調制御部と、
前記複数の走査信号線を順に選択して走査する走査信号線駆動回路と、
前記画像信号に基づいて生成された目標階調値に対応するデータ電圧と、前記補正画像信号に基づいて生成された、前記データ電圧を補正した階調補正電圧のいずれかを前記複数のデータ信号線に印加するデータ信号線駆動回路と、
前記走査信号線駆動回路および前記データ信号線駆動回路を制御する表示制御部とを備え、
前記表示制御部は、前記複数の画素形成部に、第1フレーム期間に前記階調補正電圧を書込み、第2フレーム期間に前記階調補正電圧と同じ極性の前記データ電圧を書き込むことによって画面のリフレッシュを行うように制御し、
前記第1フレーム期間の長さは、リフレッシュレートが60Hzの時の1フレーム期間の1/4以上の期間であって、かつ前記1フレーム期間未満の期間であることを特徴とする、液晶表示装置。 - 前記第2フレーム期間の長さは、前記第1フレーム期間の長さと同じであることを特徴とする、請求項1に記載の液晶表示装置。
- 前記表示制御部は、前記第2フレーム期間において前記複数の画素形成部への前記データ電圧の書込みが終了した後に、前記複数の画素形成部への前記データ電圧の書き込みを休止する休止期間を設けることを特徴とする、請求項1に記載の液晶表示装置。
- 前記階調制御部は
前記入力画像データをフレームごとに記憶するフレームメモリと、
前記入力画像データの前フレームの階調値および現フレームの階調値に対応づけられた補正値を記憶するテーブルと、
前記入力画像データの現フレームの階調値と前記フレームメモリに記憶されていた前記入力画像データの前フレームの階調値とを求めて前記テーブルに出力する比較回路と、
前記入力画像データに基づいて前記補正画像信号および前記画像信号のいずれかを前記データ信号線駆動回路に出力する加算回路とを含み、
前記テーブルは、前記入力画像データの現フレームの階調値と前フレームの階調値との組合せにそれぞれ対応づけられた補正値を記憶し、前記比較回路から前記入力画像データの現フレームの階調値と前フレームの階調値とを与えられれば、前記組合せの中から対応する補正値を前記加算回路に出力し、
前記加算回路は、前記補正画像信号を出力するときには、前記テーブルから与えられた補正値によって前記入力画像データの階調値を補正して出力し、前記画像信号を出力するときには、前記入力画像データの階調値を補正することなく出力することを特徴とする、請求項1に記載の液晶表示装置。 - 前記表示制御部は、前記比較回路から前記入力画像データが更新されていないことを示す更新情報を与えられたとき、前記更新情報に基づいて前記第1フレーム期間の長さを前記1フレーム期間の長さよりも短くなるように調整する駆動周波数制御回路を含むことを特徴とする、請求項4に記載の液晶表示装置。
- 前記更新情報は、前記入力画像データが更新されていないことを示す第1更新情報と、前記入力画像データが更新されていることを示す第2更新情報とを含み、
前記表示制御部は、前記比較回路から、前記第1更新情報を与えられたときには、前記階調補正電圧を書き込む階調補正期間および前記データ電圧を書き込むデータ電圧書込期間からなる駆動期間と、休止期間とを交互に切り替え、前記第2更新情報を与えられたときには、前記データ電圧書込期間のみを設けることを示す駆動/休止制御信号を生成するための駆動/休止制御回路をさらに含むことを特徴とする、請求項5に記載の液晶表示装置。 - 前記液晶表示装置の周囲の温度を測定する温度センサをさらに備え、
前記テーブルは、所定の温度範囲ごとに異なる補正値を記憶する複数の副テーブルを含み、
前記テーブルは、前記温度センサから与えられる温度情報に基づき、前記複数の副テーブルから前記温度情報に対応する1つの副テーブルを選択することを特徴とする、請求項4に記載の液晶表示装置。 - 前記画素形成部は、前記走査信号線に制御端子が接続され、前記データ信号線に第1導通端子が接続され、前記データ電圧または前記階調補正電圧が印加されるべき画素電極に第2導通端子が接続され、酸化物半導体によりチャネル層が形成された薄膜トランジスタを含むことを特徴とする、請求項1に記載の液晶表示装置。
- 前記酸化物半導体は、インジウム、ガリウム、亜鉛、および酸素を含むことを特徴とする、請求項8に記載の液晶表示装置。
- 前記データ信号線駆動回路は、前記休止期間中において前記データ信号線に接地電位を印加することを特徴とする、請求項3に記載の液晶表示装置。
- 前記データ信号線駆動回路は、前記休止期間中において前記データ信号線の電位をフローティングにすることを特徴とする、請求項3に記載の液晶表示装置。
- 前記絶縁基板上に、共通電極と画素電極とが、一方の電極上に他方の電極が絶縁膜を介して重畳的に形成され、前記他方の電極上に複数の開口部が形成されていることを特徴とする、請求項1に記載の液晶表示装置。
- 請求項1~12のいずれかに記載の液晶表示装置は、ドット反転駆動、ライン反転駆動、カラム反転駆動、およびフレーム反転駆動のいずれかにより交流駆動されることを特徴とする、請求項1に記載の液晶表示装置。
- 入力画像データにより表わされる画像を表示部に表示する液晶表示装置の駆動方法であって、
リフレッシュレートが60Hzの時の1フレーム期間の1/4以上の期間であって、かつ前記1フレーム期間未満である期間に、前記入力画像データの目標階調値に対応するデータ電圧に階調補正処理を施した階調補正電圧を画素形成部に書き込むことにより液晶層に前記階調補正電圧を印加する階調補正電圧印加ステップと、
前記データ電圧を、前記階調補正処理を施すことなく前記画素形成部に書き込むことにより前記液晶層に前記データ電圧を印加するデータ電圧印加ステップとを備えることを特徴とする、液晶表示装置の駆動方法。 - 前記データ電圧印加ステップにおいて前記データ電圧を印加する期間は、前記階調補正電圧印加ステップにおいて前記階調補正電圧を印加する期間と同じ長さの期間であることを特徴とする、請求項14に記載の液晶表示装置の駆動方法。
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