WO2014150587A1 - Heterogeneous graphene-based devices - Google Patents

Heterogeneous graphene-based devices Download PDF

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Publication number
WO2014150587A1
WO2014150587A1 PCT/US2014/023700 US2014023700W WO2014150587A1 WO 2014150587 A1 WO2014150587 A1 WO 2014150587A1 US 2014023700 W US2014023700 W US 2014023700W WO 2014150587 A1 WO2014150587 A1 WO 2014150587A1
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Prior art keywords
foundation
graphene
substrate
state
graphene stack
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PCT/US2014/023700
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French (fr)
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Mark Alan Davis
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Solan, LLC
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Publication of WO2014150587A1 publication Critical patent/WO2014150587A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/04—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of carbon-silicon compounds, carbon or silicon
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/15—Nano-sized carbon materials
    • C01B32/182—Graphene
    • C01B32/184—Preparation
    • C01B32/186—Preparation by chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02516—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02527—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1606—Graphene

Definitions

  • the disclosed implementations generally relate to graphene-based devices that include two or more types of graphene with different electrical properties.
  • a thin layer of a material can exhibit properties for various promising applications that are substantially diminished in the bulk three-dimensional counterparts of the material.
  • a graphene sheet and/or a graphene including a plurality of graphene sheets are good examples.
  • graphene sheets and ultra-thin graphite layers have demonstrated a number of distinguishing chemical, mechanical, electronic and optical properties, including high carrier mobility, high Young's elastic modulus, and excellent thermoconductivity.
  • Such materials are well suited for applications in electronic devices, super-strong composite materials, and energy generation and storage.
  • graphene-based structures e.g., graphene quantum dots, graphene nanoribbons, graphene nanonetworks, graphene plasmonics, and graphene super-lattices
  • graphene can be used in electronics, composite materials, and for energy generation and storage.
  • One aspect of the disclosure is a device including a first graphene stack and a second graphene stack.
  • the first graphene stack is characterized by a first lattice orientation and a band gap energy above a threshold.
  • the second graphene stack is characterized by a second lattice orientation.
  • the second graphene stack does not have a band gap energy.
  • the second graphene stack has a de minimus band gap energy substantially below a first band gap threshold.
  • the second lattice orientation is different from the first lattice orientation.
  • the device further comprises an electrically conductive contact between the first graphene stack and the second graphene stack. The mismatch between the first lattice orientation and the second lattice orientation creates an electrical property limiting boundary between the first graphene stack and the second graphene stack.
  • the device also includes a first foundation supporting the first graphene stack and a second foundation supporting the second graphene stack.
  • the first foundation is characterized by a first state that is one of (i) a first crystallographic state and (ii) a first amorphic state.
  • the first foundation influences the first lattice orientation of the first graphene stack.
  • the second foundation is characterized by a second state, other than the first state, that is one of (i) a second crystallographic state and (ii) the second amorphic state. The second foundation influences the second lattice orientation of the second graphene stack.
  • At least one of the first foundation and the second foundation comprises a substrate material.
  • the substrate material is suitable for growing a graphene stack.
  • at least one of the first foundation and the second foundation comprises a foundation material that is suitable for a graphene stack.
  • At least one of the first foundation and the second foundation comprises at least one of silicon carbide (SiC), ruthenium, iridium, platinum, copper, cobalt, nickel, palladium and stainless steel.
  • the device also includes a common substrate supporting the first foundation and the second foundation.
  • the device also includes a common substrate supporting at least one of the first foundation and the second foundation, and the common substrate supports at least one of the first graphene stack and the second graphene stack.
  • the substrate comprises a material selected from the group consisting of: neoceram, barosilicate glass, germanium arsenide, a IV-V semiconductor material, a substantially metallic material, a high temperature glass, and any combination thereof.
  • the substrate comprises silicon, monocrystalline silicon, Si0 2 glass, soda lime glass, lead glass, doped Si0 2 , aluminosilicate glass, borosilicate glass, dichroic glass, germanium/semiconductor glass, glass ceramic, silicate/fused silica, quartz or chalcogenide/sulphide glass.
  • the substrate is a [100]-oriented silicon wafer, a [110]- oriented silicon wafer, or a [111] -oriented silicon wafer.
  • the foundation material includes a carbon implanted portion of the substrate.
  • the substrate is characterized by the first crystallographic state
  • the first graphene stack is characterized by epitaxial growth from the substrate by consuming or using the foundation material, and the first graphene stack has a lattice mismatch of 1% or less with respect to the first crystallographic state of the substrate.
  • one of the first foundation and the second foundation is nickel and the first crystallographic state is Ni(l l l). In some implementations, one of the first foundation and the second foundation is platinum and the first crystallographic state is Pt(l l l). In some implementations, one of the first foundation and the second foundation is palladium and the first crystallographic state is Pd(l l l). In some implementations, one of the first foundation and the second foundation is rutinium and the first crystallographic state is Ru(l l l). In some implementations, one of the first foundation and the second foundation is iridium and the first crystallographic state is Ir(l l l).
  • one of the first foundation and the second foundation is nickel and the first crystallographic state poly-crystalline nickel. In some implementations, one of the first foundation and the second foundation is copper and the first crystallographic state poly-crystalline copper. In some implementations, one of the first foundation and the second foundation is silicon carbide and the first crystallographic state is SiC(OOOl).
  • the device also includes at least one of a junction- defined device, a field effect defined device and a doped channel defined device integrated with the first and second graphene stacks.
  • the junction-defined device includes one of a transistor and a diode.
  • the field effect defined includes one of a transistor and a diode.
  • the first and second graphene stacks are integrated with circuitry comprising one of field-effect defined devices and junction- defined devices.
  • Figure 1A is a plan view of a single-substrate heterogeneous graphene -based device in accordance with some implementations.
  • Figure IB is a cross-sectional of the single-substrate heterogeneous graphene- based device illustrated in Figure 1 A, in accordance with some implementations.
  • Figure 2 is a flowchart of an implementation of a method of manufacturing a heterogeneous graphene-based device including two or more types of graphene with varying electrical properties on a single-substrate device in accordance with some implementations.
  • Figure 3 is a flowchart of an implementation of a method of manufacturing a heterogeneous graphene-based device including two or more types of graphene with varying electrical properties on a single-substrate device in accordance with some implementations.
  • homogeneous single-substrate graphene - that can be produced by conventional methods - generally limits the types of graphene-based components that can be integrated onto a single-substrate graphene-based device which, in turn, limits a broader integration of functions on a single-substrate graphene-based device.
  • various implementations described herein include single-substrate heterogeneous graphene-based devices having two or more types of graphene with varying electrical properties and methods for producing the same.
  • implementations of single-substrate heterogeneous graphene-based devices include at least two graphene stacks characterized by respective lattice orientations and/or respective band gap energies (or absence of a significant band gap energy).
  • an electrical connection between the first and second graphene stacks is characterized by an electrical property limiting boundary resulting from lattice mismatch.
  • graphite-based structures e.g. graphene quantum dots, graphene nanoribbons (GNRs), graphene nanonetworks, graphene plasmonics and graphene super-lattices, exhibit many exceptional chemical, mechanical, electronic and optical properties, and are very desirable for use in electronic devices, composite materials, and energy generation and storage.
  • Such graphite-based structures in general comprise a graphene layer, typically nanometers thick and having a characteristic dimension also in the nanometers range.
  • GNRs are required to have a width within a few nanometers due to the inverse relationship between the band gap and the width of the GNRs.
  • various methods are provided for fabricating graphite- based structures while achieving desired size, specified geometries, and characterized electronic properties of the graphite -based structures. These methods include, but are not limited to, (1) the combination of e-beam lithography and oxygen plasma etching, (2) stripping of graphite that is sonochemically processed, and (3) bottom-up chemical synthesis, e.g., by cyclodehydrogenation of l,4-diiodo-2,3,5,6-tetraphenylbenzene6, or 10,10'-dibromo-9,9'-bianthryl, polyanthrylene oligomers self-assembled on Au(l 11), Ag(l 11) or silica substrates, to name a few examples.
  • graphene sheets are stacked, with different pitch and critical dimensions, such that devices have multiple pass functionality.
  • structures comprising multiple levels of graphene layers allow for more versatile and efficient band gap devices.
  • layered materials refer to a material comprising a plurality of sheets, with each sheet having a substantially planar structure.
  • the term “stacks” refers to one or more sheets of a material (e.g., one or more layers of graphene).
  • a graphene stack can also refer to one, a few, several, several tens, several hundreds or several thousands sheets of graphene, where each such sheet is a one-atom thick sheet composed of sp -hybridized carbon.
  • graphene structures is used interchangeably with “graphene.”
  • the term “stacks” is interchangeable with the terms “graphene stacks” and “stacks of graphene.”
  • the term “substrate” refers to one layer or multiple layers.
  • a substrate is glass, Si, Si0 2 , SiC, or another material.
  • the term “substrate” is equivalent to and interchangeable with the term “substrate stack.”
  • substrate hereinafter refers to any combination of layers upon which additional processing operations are performed. For instance, when one or more layers of a respective material (e.g., Si0 2 , S1 3 N 4 ) is grown on a silicon wafer, the term substrate alternatively refers (e.g., depending on context) to the silicon alone or to the silicon wafer inclusive of the one or more layers.
  • foundation material refers to any material that is suitable for growing graphene.
  • foundation materials are catalytic metals, e.g., Pt, Au, Fe, Rh, Ti, Ir, Ru, Ni, or Cu.
  • foundation materials are non-metal materials, such as Si, SiC, non-stoichiometric SiC (e.g., boron doped or otherwise), and other carbon enhanced materials.
  • carbon enhanced refers to any materials into which carbon has been added.
  • Figure 1A is a plan view of a single-substrate heterogeneous graphene-based device 100 in accordance with some implementations.
  • Figure IB is a cross-sectional of the heterogeneous graphene-based device 100 taken along line 1-1 ' in Figure 1A.
  • implementations of single-substrate heterogeneous graphene-based devices include at least two graphene stacks characterized by respective lattice orientations and/or respective band gap energies (or absence of a significant band gap energy).
  • an electrical connection between two graphene stacks is characterized by an electrical property limiting boundary resulting from lattice mismatch.
  • the device 100 includes a planar substrate 102. While a planar substrate is illustrated, those skilled in the art will appreciate that in some implementations, a substrate is patterned so as to define different regions of graphene growth.
  • the device 100 also includes first patterned foundation material (Fl) 110-1, second patterned foundation material (F2) 110-2, and third patterned foundation material (F3) 110-3, each of which is used to grow a respective graphene stack.
  • first patterned foundation material (Fl) 110-1 is used to grow a first graphene stack (Gl) 120-1
  • the second patterned foundation material (F2) 110-2 is used to grow a second graphene stack (G2) 120-2
  • the third patterned foundation material (F3) 110-1 is used to grow a third graphene stack (G3) 120-3.
  • the device 100 includes the first graphene stack (Gl) 120-1, the second graphene stack (G2) 120-2, and the third graphene stack (G3) 120-3.
  • the first graphene stack (Gl) is in electrical contact with the second graphene stack (G2), and the second graphene stack (G2) is also in electrical contact with the third graphene stack (G3).
  • a substrate 102 is a solid substance in the form of a planar slice.
  • the substrate 102 can be rigid or flexible.
  • the substrate 102 is made of a dielectric material, a semiconducting material, a metallic material, or a combination of such materials.
  • Exemplary dielectric materials include glass, silicon dioxide, neoceram, and sapphire.
  • Exemplary semiconducting materials include silicon (Si), silicon carbide (SiC), germanium (Ge), boron nitride (BN), and molybdenum sulfide (MoS).
  • Exemplary metallic materials comprise copper (Cu), nickel (Ni), platinum (Pt), gold (Au), cobalt (Co), ruthenium (Ru), palladium (Pd), titanium (Ti), silver (Ag), aluminum (Al), cadmium (Cd), iridium (Ir), combinations thereof, and alloys thereof.
  • the substrate 102 comprises Si, Si0 2 , SiC, Cu, Ni, or other materials.
  • the substrate 102 substantially comprises neoceram, borosilicate glass, germanium arsenide, a IV -V semiconductor material, a substantially metallic material, a high temperature glass, or a combination thereof.
  • the substrate 102 substantially comprises silicon, monocrystalline silicon, Si0 2 glass, soda lime glass, lead glass, doped Si0 2 , aluminosilicate glass, borosilicate glass, dichroic glass, germanium/semiconductor glass, glass ceramic, silicate/fused silica, quartz or chalcogenide/sulphide glass.
  • the substrate is made of polymethacrylate (PMMA), polyethylene terephthalate (PET), polyvinyl alcohol (PVA), or cellulose acetate (CA).
  • the substrate 102 includes one layer. In some implementations, the substrate 102 includes a plurality of layers. In some implementations, a substrate comprises a plurality of overlying layers, in which one or more layers are different from one or more other layers. In some implementations, a layer of another material is applied onto the substrate. In some implementations, the substrate has crystallographic symmetry. In some implementations, the substrate is an amorphous solid.
  • Each of the three patterned foundation materials (F1-F3) 1 10-1 , 1 10-2, 1 10-3 is characterized by one of a respective crystallographic state and respective amorphic state, which in turn, influences the respective lattice orientations of the first graphene stack (Gl) 120-1 , the second graphene stack (G2) 120-2, and the third graphene stack (G3) 120-3. Additionally, each of the graphene stacks (G1-G3) 1 10-1 , 1 10-2, 1 10-3 is characterized by a respective lattice orientation.
  • a first (e.g., Gl) of the graphene stacks is characterized by a respective band gap energy while a second (e.g., G2) of the graphene stacks is characterized by either (i) not having a band gap energy or (ii) having a de minimus band gap energy.
  • the electrically conductive contact between electrically connected graphene stacks is characterized by a mismatch between the respective lattice orientations of the graphene stacks that creates an electrical property limiting boundary between the graphene stacks.
  • graphene stacks Gl and G2 have the same crystallographic state, but owing to the differences in lattice orientation in their originating respective foundations, Gl and G2 have a lattice orientation mismatch that creates an electrical property limiting boundary between Gl and G2 as a result of this lattice mismatch.
  • Gl and G2 have the same lattice constants, other than lattice orientation, and their orientation mismatches by greater than 0.5 degrees.
  • Gl and G2 have the same lattice constants, other than lattice orientation, and their orientation mismatches by greater than 1 degree.
  • Gl and G2 have corresponding lattice constants that are within 1 percent of each other, other than lattice orientation, and their orientation mismatches.
  • the band gap energy of a graphene stack is at least in part a function of the width of the graphene stack forming a graphene nanoribbon.
  • the band gap energy of a graphene nanoribbon varies as an inverse function of the width of the graphene nanoribbon causing different graphene stacks (e.g., Gl , G2, and G3) with different respective widths (Wl , W2, and W3) to have different band gap energies.
  • a device 100 is integrated with circuitry comprising one of field- effect defined devices and junction-defined devices using any of a number of semiconductor manufacturing processes including, but not limited to, a complementary metal oxide field effect transistor (CMOS) process.
  • CMOS complementary metal oxide field effect transistor
  • devices made from one or more graphene stacks can be integrated with various combinations of digital, analog and radio frequency (RF) and microwave circuitry.
  • FIG. 2 is a flowchart of an implementation of a portion of a method 200 of manufacturing a heterogeneous graphene-based device including two or more types of graphene with varying electrical properties on a single-substrate device in accordance with some implementations.
  • a heterogeneous graphene-based device is manufactured by combining a first graphene stack having a first lattice orientation with a second graphene stack characterized by a second lattice orientation and one of not having a band gap energy and a de minimus band gap energy substantially below the first threshold.
  • the second lattice orientation is different from the first lattice orientation.
  • the portion of the method depicted in Figure 2 includes growing at least one respective first graphene stack on a patterned first foundation characterized by a first lattice orientation and a band gap energy above a threshold.
  • the method 200 includes creating a foundation material on a substrate.
  • the substrate is characterized by first state that is (i) a first crystallographic state or (ii) a first amorphic state.
  • the creating results in the patterning of the foundation material into a plurality regions on the substrate, each region in the plurality of regions isolated from other regions in the plurality of regions.
  • creating a foundation material on a substrate includes depositing the first foundation material on the substrate, and patterning the first foundation material.
  • creating a foundation material on a substrate includes patterning a substrate, and depositing foundation material on at least select portions of the patterned substrate.
  • the deposited foundation material is further patterned.
  • creating a foundation material on a substrate includes implanting first exposed portions of a substrate with carbon.
  • the method 200 includes causing the foundation material to adopt a favored crystallographic or a favored amorphic state.
  • causing the foundation material to adopt a favored crystallographic or a favored amorphic state includes exposing the foundation material to a heat source under one or more crystallographic inducement conditions.
  • causing the foundation material to adopt a favored crystallographic or a favored amorphic state includes selecting the first foundation material based at least on its possible crystallographic state and/or amorphic states, and inducing a particular one of the possible crystallographic state and/or amorphic states.
  • the method 200 includes forming at least a first graphene stack in a first region in the plurality of regions from the foundation material, wherein the graphene device comprises the graphene stack.
  • FIG. 3 is a flowchart of an implementation of a method of manufacturing a heterogeneous graphene -based device including two or more type of graphene with varying electrical properties on a single-substrate device in accordance with some implementations.
  • a heterogeneous graphene-based device is manufactured by combining a first graphene stack, having a first lattice orientation and first band gap energy, with a second graphene stack characterized by a second lattice orientation and one of (i) not having a band gap energy and (ii) a de minimus band gap energy substantially below the first threshold, where the second lattice orientation is different from the first lattice orientation.
  • the method 300 includes forming a first patterned foundation material characterized by a first state that is (i) a first crystallographic state or first amorphic state.
  • forming a first patterned foundation material includes depositing the first foundation material on the substrate, and patterning the first foundation material.
  • forming a first patterned foundation material includes patterning a substrate, and depositing the first foundation material on at least select portions of the patterned substrate.
  • the deposited first foundation material is further patterned.
  • forming a first patterned foundation material includes implanting first exposed portions of a substrate with carbon.
  • the method 300 includes forming a second patterned foundation material characterized by a second state, that is other than the first state, and that is (i) a second crystallographic state or a second amorphic state.
  • forming a second patterned foundation material includes depositing the second foundation material on the substrate, and patterning the second foundation material.
  • forming a second patterned foundation material includes patterning a substrate, and depositing the second foundation material on at least select portions of the patterned substrate.
  • the deposited second foundation material is further patterned.
  • forming a second patterned foundation material includes implanting second exposed portions of a substrate with carbon.
  • the method 300 includes growing respective first and second graphene stacks on the first and second foundation materials such that at least one of the first graphene stacks and at least one of the second graphene stacks form an electrically conductive contact defined by an electrical property limiting boundary resulting from lattice mismatch.
  • one of the first graphene stacks abuts one of the second graphene stacks on the substrate.
  • a device produced by the method 300 includes at least a first graphene stack characterized by a first lattice orientation and a band gap energy above a threshold and a second graphene stack characterized by a second lattice orientation and one of (i) not having a band gap energy and (ii) a de minimus band gap energy substantially below the first threshold.
  • the second lattice orientation is different from the first lattice orientation.
  • the device also includes an electrically conductive contact between the first graphene stack and the second graphene stack, where the mismatch between first lattice orientation and the second lattice orientation create an electrical property limiting boundary between the first graphene stack and the second graphene stack.
  • first means "first,” “second,” etc.
  • these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, which changing the meaning of the description, so long as all occurrences of the "first contact” are renamed consistently and all occurrences of the second contact are renamed consistently.
  • the first contact and the second contact are both contacts, but they are not the same contact.
  • the phrase “if it is determined [that a stated condition precedent is true]” or “if [a stated condition precedent is true]” or “when [a stated condition precedent is true]” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.

Abstract

A device comprising first and second graphene stacks is provided. The first graphene stack has a first lattice orientation and a band gap energy above a threshold. The second graphene stack has a second lattice orientation and either (i) no or (ii) a de minimus band gap energy. The first and second lattice orientations differ. An electrically conductive contact between the graphene stacks provides an electrical property limiting boundary. In some instances, first and second foundations respectively support the first and second graphene stacks. The first foundation is characterized by a first state that is one of (i) a first crystallographic state and (ii) a first amorphic state. The second foundation is characterized by a second state, other than the first state, that is one of (i) a second crystallographic state and (ii) a second amorphic state. The first and second foundations respectively influence the first and second lattice orientations.

Description

Heterogeneous Graphene-Based Devices
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application claims priority to United States Patent Application No
61/800,187, filed March 15, 2013, entitled "Heterogeneous Graphene-Based Devices," which is hereby incorporated by reference herein in its entirety.
TECHNICAL FIELD
[0002] The disclosed implementations generally relate to graphene-based devices that include two or more types of graphene with different electrical properties.
BACKGROUND
[0003] A thin layer of a material, typically nanometers thick, can exhibit properties for various promising applications that are substantially diminished in the bulk three-dimensional counterparts of the material. A graphene sheet and/or a graphene including a plurality of graphene sheets are good examples. Compared to its bulk three-dimensional counterparts, graphene sheets and ultra-thin graphite layers have demonstrated a number of distinguishing chemical, mechanical, electronic and optical properties, including high carrier mobility, high Young's elastic modulus, and excellent thermoconductivity. Such materials are well suited for applications in electronic devices, super-strong composite materials, and energy generation and storage. As such, graphene-based structures (e.g., graphene quantum dots, graphene nanoribbons, graphene nanonetworks, graphene plasmonics, and graphene super-lattices) have wide ranging applications because of some of the distinguishing chemical, mechanical, electronic, and optical properties. For example, graphene can be used in electronics, composite materials, and for energy generation and storage.
[0004] However, conventional methods of manufacturing graphene-based structures do not enable the growth two or more graphene stacks with varying electrical properties on a single- substrate device. In other words, only one type of graphene can be produced on one substrate and/or foundation material using conventional methods. The currently available homogeneity of single-substrate graphene generally limits the types of graphene-based components that can be integrated onto a single-substrate graphene-based device, which in turn, limits a broader integration of functions on a single-substrate graphene-based device.
SUMMARY
[0005] Various implementations of methods and devices that are within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the attributes described herein. Without limiting the scope of the claims, some prominent features are described herein. After considering the discussion herein, and particularly the section entitled "Detailed Description," one will understand how aspects of various implementations are used to configure single-substrate heterogeneous graphene-based devices having two or more types of graphene with varying electrical properties, and enable methods of manufacturing the same. In turn, in some implementations, include single-substrate graphene-based with a broad integration of functions.
[0006] One aspect of the disclosure is a device including a first graphene stack and a second graphene stack. The first graphene stack is characterized by a first lattice orientation and a band gap energy above a threshold. The second graphene stack is characterized by a second lattice orientation. In some embodiments the second graphene stack does not have a band gap energy. In some embodiments the second graphene stack has a de minimus band gap energy substantially below a first band gap threshold. The second lattice orientation is different from the first lattice orientation. The device further comprises an electrically conductive contact between the first graphene stack and the second graphene stack. The mismatch between the first lattice orientation and the second lattice orientation creates an electrical property limiting boundary between the first graphene stack and the second graphene stack.
[0007] In some implementations, the device also includes a first foundation supporting the first graphene stack and a second foundation supporting the second graphene stack. The first foundation is characterized by a first state that is one of (i) a first crystallographic state and (ii) a first amorphic state. In such embodiments, the first foundation influences the first lattice orientation of the first graphene stack. In some embodiments the second foundation is characterized by a second state, other than the first state, that is one of (i) a second crystallographic state and (ii) the second amorphic state. The second foundation influences the second lattice orientation of the second graphene stack. [0008] In some implementations, at least one of the first foundation and the second foundation comprises a substrate material. In some implementations, the substrate material is suitable for growing a graphene stack. In some implementations, at least one of the first foundation and the second foundation comprises a foundation material that is suitable for a graphene stack.
[0009] In some implementations, at least one of the first foundation and the second foundation comprises at least one of silicon carbide (SiC), ruthenium, iridium, platinum, copper, cobalt, nickel, palladium and stainless steel. In some implementations, the device also includes a common substrate supporting the first foundation and the second foundation. In some implementations, the device also includes a common substrate supporting at least one of the first foundation and the second foundation, and the common substrate supports at least one of the first graphene stack and the second graphene stack.
[0010] In some implementations, the substrate comprises a material selected from the group consisting of: neoceram, barosilicate glass, germanium arsenide, a IV-V semiconductor material, a substantially metallic material, a high temperature glass, and any combination thereof. In some implementations, the substrate comprises silicon, monocrystalline silicon, Si02 glass, soda lime glass, lead glass, doped Si02, aluminosilicate glass, borosilicate glass, dichroic glass, germanium/semiconductor glass, glass ceramic, silicate/fused silica, quartz or chalcogenide/sulphide glass.
[0011] In some implementations, the substrate is a [100]-oriented silicon wafer, a [110]- oriented silicon wafer, or a [111] -oriented silicon wafer.
[0012] In some implementations, the foundation material includes a carbon implanted portion of the substrate. In some implementations, the substrate is characterized by the first crystallographic state, and the first graphene stack is characterized by epitaxial growth from the substrate by consuming or using the foundation material, and the first graphene stack has a lattice mismatch of 1% or less with respect to the first crystallographic state of the substrate.
[0013] In some implementations, one of the first foundation and the second foundation is nickel and the first crystallographic state is Ni(l l l). In some implementations, one of the first foundation and the second foundation is platinum and the first crystallographic state is Pt(l l l). In some implementations, one of the first foundation and the second foundation is palladium and the first crystallographic state is Pd(l l l). In some implementations, one of the first foundation and the second foundation is rutinium and the first crystallographic state is Ru(l l l). In some implementations, one of the first foundation and the second foundation is iridium and the first crystallographic state is Ir(l l l). In some implementations, one of the first foundation and the second foundation is nickel and the first crystallographic state poly-crystalline nickel. In some implementations, one of the first foundation and the second foundation is copper and the first crystallographic state poly-crystalline copper. In some implementations, one of the first foundation and the second foundation is silicon carbide and the first crystallographic state is SiC(OOOl).
[0014] In some implementations, the device also includes at least one of a junction- defined device, a field effect defined device and a doped channel defined device integrated with the first and second graphene stacks. In some implementations, the junction-defined device includes one of a transistor and a diode. In some implementations, the field effect defined includes one of a transistor and a diode. In some implementations, the first and second graphene stacks are integrated with circuitry comprising one of field-effect defined devices and junction- defined devices.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] So that the manner in which features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other effective aspects.
[0016] Figure 1A is a plan view of a single-substrate heterogeneous graphene -based device in accordance with some implementations.
[0017] Figure IB is a cross-sectional of the single-substrate heterogeneous graphene- based device illustrated in Figure 1 A, in accordance with some implementations. [0018] Figure 2 is a flowchart of an implementation of a method of manufacturing a heterogeneous graphene-based device including two or more types of graphene with varying electrical properties on a single-substrate device in accordance with some implementations.
[0019] Figure 3 is a flowchart of an implementation of a method of manufacturing a heterogeneous graphene-based device including two or more types of graphene with varying electrical properties on a single-substrate device in accordance with some implementations.
[0020] In accordance with common practice the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.
DETAILED DESCRIPTION
[0021] As noted above, homogeneous single-substrate graphene - that can be produced by conventional methods - generally limits the types of graphene-based components that can be integrated onto a single-substrate graphene-based device which, in turn, limits a broader integration of functions on a single-substrate graphene-based device. By contrast, various implementations described herein include single-substrate heterogeneous graphene-based devices having two or more types of graphene with varying electrical properties and methods for producing the same. More specifically, implementations of single-substrate heterogeneous graphene-based devices include at least two graphene stacks characterized by respective lattice orientations and/or respective band gap energies (or absence of a significant band gap energy). In some implementations, an electrical connection between the first and second graphene stacks is characterized by an electrical property limiting boundary resulting from lattice mismatch.
[0022] Numerous details are described herein in order to provide a thorough understanding of example implementations illustrated in the accompanying drawings. However, the invention may be practiced without many of the specific details and is only limited by the language of the claims. Well-known methods, structure and components have not been described in exhaustive detail so as not to unnecessarily obscure more pertinent aspects of the implementations described herein. [0023] In some implementations, graphite-based structures, e.g. graphene quantum dots, graphene nanoribbons (GNRs), graphene nanonetworks, graphene plasmonics and graphene super-lattices, exhibit many exceptional chemical, mechanical, electronic and optical properties, and are very desirable for use in electronic devices, composite materials, and energy generation and storage. Such graphite-based structures in general comprise a graphene layer, typically nanometers thick and having a characteristic dimension also in the nanometers range. For example, in order to obtain adequate band gaps for operation at room temperature, GNRs are required to have a width within a few nanometers due to the inverse relationship between the band gap and the width of the GNRs.
[0024] In some implementations, various methods are provided for fabricating graphite- based structures while achieving desired size, specified geometries, and characterized electronic properties of the graphite -based structures. These methods include, but are not limited to, (1) the combination of e-beam lithography and oxygen plasma etching, (2) stripping of graphite that is sonochemically processed, and (3) bottom-up chemical synthesis, e.g., by cyclodehydrogenation of l,4-diiodo-2,3,5,6-tetraphenylbenzene6, or 10,10'-dibromo-9,9'-bianthryl, polyanthrylene oligomers self-assembled on Au(l 11), Ag(l 11) or silica substrates, to name a few examples.
[0025] In some implementations, different pitch and duty cycle combinations in graphene devices are utilized to improve efficiency. In particular, in some implementations, graphene sheets are stacked, with different pitch and critical dimensions, such that devices have multiple pass functionality. Similarly, in some implementations, structures comprising multiple levels of graphene layers allow for more versatile and efficient band gap devices.
[0026] The disclosed implementations are described in the context of methods for fabricating thin films from layered materials and in the context of thin films made therefrom. In this specification and claims, layered materials refer to a material comprising a plurality of sheets, with each sheet having a substantially planar structure.
[0027] As used herein, the term "stacks" refers to one or more sheets of a material (e.g., one or more layers of graphene). For instance, a graphene stack can also refer to one, a few, several, several tens, several hundreds or several thousands sheets of graphene, where each such sheet is a one-atom thick sheet composed of sp -hybridized carbon. As used herein, the term "graphene structures" is used interchangeably with "graphene." As used herein, the term "stacks" is interchangeable with the terms "graphene stacks" and "stacks of graphene."
[0028] As used herein, the term "substrate" refers to one layer or multiple layers. In some implementations, a substrate is glass, Si, Si02, SiC, or another material. When referring to multiple layers, the term "substrate" is equivalent to and interchangeable with the term "substrate stack." Moreover, it should be understood that the term "substrate" hereinafter refers to any combination of layers upon which additional processing operations are performed. For instance, when one or more layers of a respective material (e.g., Si02, S13N4) is grown on a silicon wafer, the term substrate alternatively refers (e.g., depending on context) to the silicon alone or to the silicon wafer inclusive of the one or more layers.
[0029] As used herein, the term "foundation material" refers to any material that is suitable for growing graphene. In some implementations, foundation materials are catalytic metals, e.g., Pt, Au, Fe, Rh, Ti, Ir, Ru, Ni, or Cu. In some other implementations, foundation materials are non-metal materials, such as Si, SiC, non-stoichiometric SiC (e.g., boron doped or otherwise), and other carbon enhanced materials. As used herein, the phrase "carbon enhanced" materials refers to any materials into which carbon has been added.
[0030] Those of ordinary skill in the art will realize that the following detailed description of the present application is illustrative only and is not intended to be in any way limiting. Other implementations of the present application will readily suggest themselves to such skilled persons having benefit of this disclosure. Reference will now be made in detail to implementations of the present application as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.
[0031] In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.
[0032] Figure 1A is a plan view of a single-substrate heterogeneous graphene-based device 100 in accordance with some implementations. And Figure IB is a cross-sectional of the heterogeneous graphene-based device 100 taken along line 1-1 ' in Figure 1A. As described herein, implementations of single-substrate heterogeneous graphene-based devices include at least two graphene stacks characterized by respective lattice orientations and/or respective band gap energies (or absence of a significant band gap energy). In some implementations, an electrical connection between two graphene stacks is characterized by an electrical property limiting boundary resulting from lattice mismatch. Moreover, while certain specific features are illustrated, those skilled in the art will appreciate from the present disclosure that various other features (e.g. metal connecting lines, layers of other materials, etc.) have not been illustrated for the sake of brevity and so as not to obscure more pertinent aspects of the implementations disclosed herein.
[0033] To that end, with reference to both Figures 1A and IB, the device 100 includes a planar substrate 102. While a planar substrate is illustrated, those skilled in the art will appreciate that in some implementations, a substrate is patterned so as to define different regions of graphene growth.
[0034] The device 100 also includes first patterned foundation material (Fl) 110-1, second patterned foundation material (F2) 110-2, and third patterned foundation material (F3) 110-3, each of which is used to grow a respective graphene stack. Specifically, the first patterned foundation material (Fl) 110-1 is used to grow a first graphene stack (Gl) 120-1, the second patterned foundation material (F2) 110-2 is used to grow a second graphene stack (G2) 120-2, and the third patterned foundation material (F3) 110-1 is used to grow a third graphene stack (G3) 120-3. As such, the device 100 includes the first graphene stack (Gl) 120-1, the second graphene stack (G2) 120-2, and the third graphene stack (G3) 120-3. The first graphene stack (Gl) is in electrical contact with the second graphene stack (G2), and the second graphene stack (G2) is also in electrical contact with the third graphene stack (G3).
[0035] In some implementations, a substrate 102 is a solid substance in the form of a planar slice. The substrate 102 can be rigid or flexible. In some implementations, the substrate 102 is made of a dielectric material, a semiconducting material, a metallic material, or a combination of such materials. Exemplary dielectric materials include glass, silicon dioxide, neoceram, and sapphire. Exemplary semiconducting materials include silicon (Si), silicon carbide (SiC), germanium (Ge), boron nitride (BN), and molybdenum sulfide (MoS). Exemplary metallic materials comprise copper (Cu), nickel (Ni), platinum (Pt), gold (Au), cobalt (Co), ruthenium (Ru), palladium (Pd), titanium (Ti), silver (Ag), aluminum (Al), cadmium (Cd), iridium (Ir), combinations thereof, and alloys thereof. In some implementations, the substrate 102 comprises Si, Si02, SiC, Cu, Ni, or other materials. In some implementations, the substrate 102 substantially comprises neoceram, borosilicate glass, germanium arsenide, a IV -V semiconductor material, a substantially metallic material, a high temperature glass, or a combination thereof.
[0036] In some implementations, the substrate 102 substantially comprises silicon, monocrystalline silicon, Si02 glass, soda lime glass, lead glass, doped Si02, aluminosilicate glass, borosilicate glass, dichroic glass, germanium/semiconductor glass, glass ceramic, silicate/fused silica, quartz or chalcogenide/sulphide glass. In some implementations, the substrate is made of polymethacrylate (PMMA), polyethylene terephthalate (PET), polyvinyl alcohol (PVA), or cellulose acetate (CA).
[0037] In some implementations, the substrate 102 includes one layer. In some implementations, the substrate 102 includes a plurality of layers. In some implementations, a substrate comprises a plurality of overlying layers, in which one or more layers are different from one or more other layers. In some implementations, a layer of another material is applied onto the substrate. In some implementations, the substrate has crystallographic symmetry. In some implementations, the substrate is an amorphous solid.
[0038] Each of the three patterned foundation materials (F1-F3) 1 10-1 , 1 10-2, 1 10-3 is characterized by one of a respective crystallographic state and respective amorphic state, which in turn, influences the respective lattice orientations of the first graphene stack (Gl) 120-1 , the second graphene stack (G2) 120-2, and the third graphene stack (G3) 120-3. Additionally, each of the graphene stacks (G1-G3) 1 10-1 , 1 10-2, 1 10-3 is characterized by a respective lattice orientation. Additionally, in some implementations, a first (e.g., Gl) of the graphene stacks is characterized by a respective band gap energy while a second (e.g., G2) of the graphene stacks is characterized by either (i) not having a band gap energy or (ii) having a de minimus band gap energy. In turn, in some implementations, the electrically conductive contact between electrically connected graphene stacks (e.g., Gl and G2) is characterized by a mismatch between the respective lattice orientations of the graphene stacks that creates an electrical property limiting boundary between the graphene stacks. In other words, in this example, graphene stacks Gl and G2 have the same crystallographic state, but owing to the differences in lattice orientation in their originating respective foundations, Gl and G2 have a lattice orientation mismatch that creates an electrical property limiting boundary between Gl and G2 as a result of this lattice mismatch. In some embodiments, Gl and G2 have the same lattice constants, other than lattice orientation, and their orientation mismatches by greater than 0.5 degrees. In some embodiments, Gl and G2 have the same lattice constants, other than lattice orientation, and their orientation mismatches by greater than 1 degree. In some embodiments, Gl and G2 have corresponding lattice constants that are within 1 percent of each other, other than lattice orientation, and their orientation mismatches.
[0039] In some implementations, the band gap energy of a graphene stack is at least in part a function of the width of the graphene stack forming a graphene nanoribbon. For example, the band gap energy of a graphene nanoribbon varies as an inverse function of the width of the graphene nanoribbon causing different graphene stacks (e.g., Gl , G2, and G3) with different respective widths (Wl , W2, and W3) to have different band gap energies.
[0040] Moreover, while the three graphene stacks (G1 -G3) are shown in Figures 1A and
IB, in some implementations, a device 100 is integrated with circuitry comprising one of field- effect defined devices and junction-defined devices using any of a number of semiconductor manufacturing processes including, but not limited to, a complementary metal oxide field effect transistor (CMOS) process. As such, devices made from one or more graphene stacks can be integrated with various combinations of digital, analog and radio frequency (RF) and microwave circuitry.
[0041] Figure 2 is a flowchart of an implementation of a portion of a method 200 of manufacturing a heterogeneous graphene-based device including two or more types of graphene with varying electrical properties on a single-substrate device in accordance with some implementations. In some implementations, as described below in greater detail with reference to Figure 3, a heterogeneous graphene-based device is manufactured by combining a first graphene stack having a first lattice orientation with a second graphene stack characterized by a second lattice orientation and one of not having a band gap energy and a de minimus band gap energy substantially below the first threshold. The second lattice orientation is different from the first lattice orientation. As such, briefly, the portion of the method depicted in Figure 2 includes growing at least one respective first graphene stack on a patterned first foundation characterized by a first lattice orientation and a band gap energy above a threshold.
[0042] To that end, as represented by block 2-1, the method 200 includes creating a foundation material on a substrate. The substrate is characterized by first state that is (i) a first crystallographic state or (ii) a first amorphic state. The creating results in the patterning of the foundation material into a plurality regions on the substrate, each region in the plurality of regions isolated from other regions in the plurality of regions. In some implementations, as represented by block 2- la, creating a foundation material on a substrate includes depositing the first foundation material on the substrate, and patterning the first foundation material. In some implementations, as represented by block 2- lb, creating a foundation material on a substrate includes patterning a substrate, and depositing foundation material on at least select portions of the patterned substrate. In some implementations, the deposited foundation material is further patterned. In some implementations, as represented by block 2-lc, creating a foundation material on a substrate includes implanting first exposed portions of a substrate with carbon.
[0043] As represented by block 2-2, the method 200 includes causing the foundation material to adopt a favored crystallographic or a favored amorphic state. In some implementations, as represented by block 2-2a, causing the foundation material to adopt a favored crystallographic or a favored amorphic state includes exposing the foundation material to a heat source under one or more crystallographic inducement conditions. In some implementations, as represented by block 2-2b, causing the foundation material to adopt a favored crystallographic or a favored amorphic state includes selecting the first foundation material based at least on its possible crystallographic state and/or amorphic states, and inducing a particular one of the possible crystallographic state and/or amorphic states. [0044] As represented by block 2-3, the method 200 includes forming at least a first graphene stack in a first region in the plurality of regions from the foundation material, wherein the graphene device comprises the graphene stack.
[0045] Figure 3 is a flowchart of an implementation of a method of manufacturing a heterogeneous graphene -based device including two or more type of graphene with varying electrical properties on a single-substrate device in accordance with some implementations. Briefly, a heterogeneous graphene-based device is manufactured by combining a first graphene stack, having a first lattice orientation and first band gap energy, with a second graphene stack characterized by a second lattice orientation and one of (i) not having a band gap energy and (ii) a de minimus band gap energy substantially below the first threshold, where the second lattice orientation is different from the first lattice orientation.
[0046] To that end, as represented by block 3-1, the method 300 includes forming a first patterned foundation material characterized by a first state that is (i) a first crystallographic state or first amorphic state. In some implementations, as represented by block 3- la, forming a first patterned foundation material includes depositing the first foundation material on the substrate, and patterning the first foundation material. In some implementations, as represented by block 3- lb, forming a first patterned foundation material includes patterning a substrate, and depositing the first foundation material on at least select portions of the patterned substrate. In some implementations, the deposited first foundation material is further patterned. In some implementations, as represented by block 3-lc, forming a first patterned foundation material includes implanting first exposed portions of a substrate with carbon.
[0047] As represented by block 3-2, the method 300 includes forming a second patterned foundation material characterized by a second state, that is other than the first state, and that is (i) a second crystallographic state or a second amorphic state. In some implementations, as represented by block 3 -2a, forming a second patterned foundation material includes depositing the second foundation material on the substrate, and patterning the second foundation material. In some implementations, as represented by block 3-2b, forming a second patterned foundation material includes patterning a substrate, and depositing the second foundation material on at least select portions of the patterned substrate. In some implementations, the deposited second foundation material is further patterned. In some implementations, as represented by block 3-2c, forming a second patterned foundation material includes implanting second exposed portions of a substrate with carbon.
[0048] As represented by block 3-3, the method 300 includes growing respective first and second graphene stacks on the first and second foundation materials such that at least one of the first graphene stacks and at least one of the second graphene stacks form an electrically conductive contact defined by an electrical property limiting boundary resulting from lattice mismatch. In some embodiments one of the first graphene stacks abuts one of the second graphene stacks on the substrate.
[0049] A device produced by the method 300 includes at least a first graphene stack characterized by a first lattice orientation and a band gap energy above a threshold and a second graphene stack characterized by a second lattice orientation and one of (i) not having a band gap energy and (ii) a de minimus band gap energy substantially below the first threshold. The second lattice orientation is different from the first lattice orientation. The device also includes an electrically conductive contact between the first graphene stack and the second graphene stack, where the mismatch between first lattice orientation and the second lattice orientation create an electrical property limiting boundary between the first graphene stack and the second graphene stack.
[0050] It will also be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, which changing the meaning of the description, so long as all occurrences of the "first contact" are renamed consistently and all occurrences of the second contact are renamed consistently. The first contact and the second contact are both contacts, but they are not the same contact.
[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0052] As used herein, the term "if may be construed to mean "when" or "upon" or "in response to determining" or "in accordance with a determination" or "in response to detecting," that a stated condition precedent is true, depending on the context. Similarly, the phrase "if it is determined [that a stated condition precedent is true]" or "if [a stated condition precedent is true]" or "when [a stated condition precedent is true]" may be construed to mean "upon determining" or "in response to determining" or "in accordance with a determination" or "upon detecting" or "in response to detecting" that the stated condition precedent is true, depending on the context.

Claims

What is claimed is:
1. A device comprising:
a first graphene stack characterized by a first lattice orientation and a band gap energy above a threshold;
a second graphene stack characterized by a second lattice orientation and one of (i) not having a band gap energy and (ii) having a de minimus band gap energy substantially below the first threshold, wherein the second lattice orientation is different from the first lattice orientation; and
an electrically conductive contact between the first graphene stack and the second graphene stack, wherein the mismatch between the first lattice orientation and the second lattice orientation creates an electrical property limiting boundary between the first graphene stack and the second graphene stack.
2. The device of claim 1 further comprising:
a first foundation supporting the first graphene stack, wherein the first foundation is characterized by a first state that is one of a first crystallographic state and a first amorphic state, and wherein the first foundation influences the first lattice orientation of the first graphene stack; and
a second foundation supporting the second graphene stack, wherein the second foundation is characterized by a second state, other than the first state, that is one of a second crystallographic state and a second amorphic state, wherein the second foundation influences the second lattice orientation of the second graphene stack.
3. The device of claim 2, wherein at least one of the first foundation and the second foundation comprises a substrate material.
4. The device of claim 3, wherein the substrate material is suitable for growing a graphene stack.
5. The device of claim 2, wherein at least one of the first foundation and the second foundation comprises a foundation material that is suitable for a graphene stack.
6. The device of claim 5, wherein at least one of the first foundation and the second foundation comprises at least one of silicon carbide (SiC), ruthenium, iridium, platinum, copper, cobalt, nickel, palladium and stainless steel.
7. The device of claim 5, further comprising a common substrate supporting the first foundation and the second foundation.
8. The device of claim 5, further comprising a common substrate supporting at least one of the first foundation and the second foundation, and wherein the common substrate supports at least one of the first graphene stack and the second graphene stack.
9. The device of claim 7 or 8, wherein the substrate comprises a material selected from the group consisting of: neoceram, barosilicate glass, germanium arsenide, a IV-V semiconductor material, a substantially metallic material, a high temperature glass, and a combination thereof.
10. The device of claim 7 or 8, wherein the substrate comprises silicon, monocrystalline silicon, Si02 glass, soda lime glass, lead glass, doped Si02, aluminosilicate glass, borosilicate glass, dichroic glass, germanium/semiconductor glass, glass ceramic, silicate/fused silica, quartz or chalcogenide/sulphide glass.
11. The device of claim 7 or 8, wherein the substrate is a [100]-oriented silicon wafer, a [110]-oriented silicon wafer, or a [11 l]-oriented silicon wafer.
12. The device of claim 7 or 8, wherein the foundation material includes a carbon implanted portion of the substrate.
13. The device of claim 7 or 8, wherein the substrate is characterized by the first
crystallographic state, wherein the first graphene stack is characterized by epitaxial growth from the substrate by consuming or using the foundation material, and wherein the first graphene stack has a lattice mismatch of 1% or less with respect to the first crystallographic state of the substrate.
14. The device of claim 2, wherein one of the first foundation and the second foundation is nickel and the first crystallographic state is Ni(l 11).
15. The device of claim 2, wherein one of the first foundation and the second foundation is platinum and the first crystallographic state is Pt(l 11).
16. The device of claim 2, wherein one of the first foundation and the second foundation is palladium and the first crystallographic state is Pd(l 11).
17. The device of claim 2, wherein one of the first foundation and the second foundation is rutinium and the first crystallographic state is Ru(l 11).
18. The device of claim 2, wherein one of the first foundation and the second foundation is iridium and the first crystallographic state is Ir(l 1 1).
19. The device of claim 2, wherein one of the first foundation and the second foundation is nickel and the first crystallographic state is poly-crystalline nickel.
20. The device of claim 2, wherein one of the first foundation and the second foundation is copper and the first crystallographic state is poly-crystalline copper.
21. The device of claim 2, wherein one of the first foundation and the second foundation is silicon carbide and the first crystallographic state is SiC(OOOl).
22. The device of any one of claims 1-21, further comprising at least one of a junction- defined device, a field effect defined device and a doped channel defined device integrated with the first and second graphene stacks.
23. The device of any one of claims 1-21, further comprising a junction-defined device integrated with the first and second graphene stacks, wherein the junction-defined device includes one of a transistor and a diode.
24. The device of any one of claims 1-21, further comprising field effect defined device integrated with the first and second graphene stacks, wherein the field effect defined device includes one of a transistor and a diode.
25. The device of any one of claims 1-21, wherein the first and second graphene stacks are integrated with circuitry comprising one of field-effect defined devices and junction-defined devices.
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