WO2014086058A1 - FinFET及其制造方法 - Google Patents

FinFET及其制造方法 Download PDF

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Publication number
WO2014086058A1
WO2014086058A1 PCT/CN2012/086523 CN2012086523W WO2014086058A1 WO 2014086058 A1 WO2014086058 A1 WO 2014086058A1 CN 2012086523 W CN2012086523 W CN 2012086523W WO 2014086058 A1 WO2014086058 A1 WO 2014086058A1
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gate
layer
masking layer
sacrificial
semiconductor
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PCT/CN2012/086523
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English (en)
French (fr)
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朱慧珑
梁擎擎
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中国科学院微电子研究所
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Publication of WO2014086058A1 publication Critical patent/WO2014086058A1/zh
Priority to US14/723,226 priority Critical patent/US9583593B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • This invention relates to semiconductor technology and, more particularly, to FinFETs and methods of fabricating the same. Background technique
  • the FinFET includes a semiconductor fin for forming a channel region and a gate stack covering at least one sidewall of the semiconductor fin.
  • the gate stack intersects the semiconductor fins and includes a gate conductor and a gate dielectric.
  • the gate dielectric separates the gate conductor from the semiconductor fins.
  • the FinFET can have a double gate, triple gate or ring gate configuration, and the width (i.e., thickness) of the semiconductor fins is small, so that the FinFET can improve the control of the gate conductors on the channel region and suppress the short channel effect.
  • a conventional fabrication process for gate stacking involves depositing a dielectric layer and a conductor layer and then photolithographically forming a pattern of gate stacks.
  • a dielectric layer and a conductor layer depositing a dielectric layer and a conductor layer and then photolithographically forming a pattern of gate stacks.
  • a method of fabricating a FinFET comprising: forming a semiconductor fin; forming one of a source region and a drain region; forming a sacrificial sidewall; forming a source region and a drain with a sacrificial sidewall as a mask Another of the regions; removing the sacrificial sidewalls; and replacing the sacrificial sidewalls with a gate stack comprising a gate conductor and a gate dielectric, the gate dielectric separating the gate conductor from the semiconductor fins.
  • a FinFET comprising: a semiconductor fin; a source region and a drain region in the semiconductor fin; a masking layer over one of the source region and the drain region, the masking layer having a sidewall facing the other of the source region and the drain region; and the source region and A gate stack between the drain regions, the gate stacks the gate dielectric and the gate conductor, wherein the gate dielectric separates the gate conductor from the semiconductor fins.
  • the present invention utilizes a sacrificial sidewall to form a gate stack that can be much smaller than the gate length of a conventional FinFET. Also, the sacrificial sidewall is used as a mask to form the other of the source and drain regions, and the gate stack can be substantially aligned with the source and drain regions accordingly.
  • the present invention can reduce the use of masks and the need for complicated photolithography processes, thereby reducing manufacturing costs.
  • FIG. 1 through 10 illustrate a flow chart of a method of fabricating a FinFET in accordance with an embodiment of the present invention
  • Figure 11 shows a perspective view of a FinFET in accordance with an embodiment of the present invention. detailed description
  • semiconductor structure refers to various steps in the fabrication of a semiconductor device.
  • the general term for the entire semiconductor structure formed in the middle includes all layers or regions that have been formed.
  • Many specific details of the invention are described below, such as the structure, materials, dimensions, processing, and techniques of the invention, in order to provide a clear understanding of the invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.
  • the semiconductor material includes, for example, a group III-V semiconductor such as GaAs, InP, GaN, SiC, and a group IV semiconductor such as Si, Ge.
  • the gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni 3 Si, Pt, Ru, Ir, Mo, HfRu, RuOx
  • conductive materials such as TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni
  • the gate dielectric may be composed of SiO 2 or a material having a dielectric constant greater than SiO 2 , and includes, for example, an oxide, a nitride, an oxynitride, a silicate, an aluminate, a titanate, wherein the oxide includes, for example, Si0 2 .
  • the nitride includes, for example, Si 3 N 4
  • the silicate includes, for example, HfSiOx
  • the aluminate includes, for example, LaA10 3
  • the titanate includes, for example, SrTi0 3
  • oxynitrides include, for example, SiON.
  • the gate dielectric may be formed not only by materials well known to those skilled in the art, but also materials developed for the gate dielectric in the future.
  • a replacement gate process In a conventional back gate process (ie, a replacement gate process), after the source and drain regions are fabricated in the substrate using the "dummy" gate stack and the sidewalls on either side of the dummy gate stack, the sidewalls on both sides are retained Holes are defined between the side walls to fill the pores to form a true grid stack.
  • an "alternative side wall” process is proposed. After forming the source and drain regions, a layer of material on one side of the source and drain regions is retained, and a gate stack (particularly, a gate conductor) is formed as a sidewall on the sidewalls of the remaining material layer .
  • the gate stack can be formed in a larger space (specifically, a region substantially the gate region + the other of the source region and the drain region), and the gate stack is formed only in the small gate opening between the sidewall spacers
  • the conventional process can make the process easier.
  • the present invention can be embodied in various forms, some of which are described below.
  • the steps shown in Figures 1 to 10 are performed, wherein the top view and the cut-out position of the cross-sectional view are shown in Figures 4c to 10c, in Figures 1 to 3 and 4a to 10a
  • a cross-sectional view taken along line AA in the width direction of the semiconductor fin is shown, and a cross-sectional view along line BB in the length direction of the semiconductor fin is shown in FIGS. 4b to 10b.
  • a semiconductor substrate as an initial structure is a conventional SOI wafer including a semiconductor substrate 101, an insulating buried layer 102, and a semiconductor layer 103 in order from bottom to top.
  • the thickness of the semiconductor layer 103 is, for example, about 5 nm - 20 nm, such as 10 nm, 15 nm
  • the thickness of the insulating buried layer 102 is, for example, about 5 nm - 30 nm, such as 10 nm, 15 nm, 20 nm or 25 nm.
  • the material of the semiconductor substrate 101 may be bulk silicon, or a Group IV semiconductor material such as SiGe or Ge, or a Group III-V compound semiconductor (e.g., gallium arsenide) material.
  • a Group IV semiconductor material such as SiGe or Ge
  • a Group III-V compound semiconductor e.g., gallium arsenide
  • the insulating buried layer 102 may be an oxide buried layer, an oxynitride buried layer or other insulating buried layer.
  • the semiconductor layer 103 will be used to form semiconductor fins and provide source and drain regions and channel regions for the FinFET.
  • the semiconductor layer 103 is composed of, for example, a semiconductor material selected from a group IV semiconductor (eg, silicon, germanium or silicon germanium) or a group III-V compound semiconductor (eg, gallium arsenide).
  • the semiconductor layer 103 may be Single crystal Si or SiGe.
  • SmartCutTM (referred to as "smart stripping” or “smart cutting") methods may be used, including bonding two wafers respectively comprising an oxide surface layer formed by thermal oxidation or deposition to each other, wherein two wafers are Hydrogen implantation has been performed to form a hydrogen implantation region in a certain depth of the silicon body below the oxide surface layer, and then the hydrogen implantation region is transformed into a microcavity layer under pressure, temperature rise, etc., thereby facilitating micro The portions on both sides of the cavity layer are separated, and the portion containing the bonded oxide surface layer after peeling is used as the SOI wafer.
  • the thickness of the insulating buried layer of the SOI wafer can be varied by controlling the process parameters of thermal oxidation or deposition.
  • the thickness of the semiconductor layer contained in the SOI wafer can be changed by controlling the energy of hydrogen injection.
  • the patterning may include the steps of: forming a patterned photoresist mask PR1 on the semiconductor layer 103 by a photolithography process including exposure and development; by dry etching, such as ion milling, plasma etching, reaction
  • the exposed portion of the semiconductor layer 103 is removed by ion etching, laser ablation, or by wet etching in which an etchant solution is used, and the etching stops at the top of the insulating buried layer 102.
  • the photoresist mask PR1 is removed by dissolving or ashing in a solvent. Then, through known deposition processes such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), Atomic layer deposition, sputtering, etc., forms a conformal oxide layer 104 and a covered first masking layer 105 (e.g., silicon nitride) on the surface of the semiconductor structure, as shown in FIG.
  • the surface of the semiconductor structure is planarized, for example, by chemical mechanical polishing (CMP). By controlling the time, the CMP removes only a portion of the first masking layer 105 without reaching the oxide layer 104.
  • CMP chemical mechanical polishing
  • first masking layer 105 In order to facilitate the formation of sacrificial sidewalls on the semiconductor fins 103', it is desirable to retain a first masking layer 105 of sufficient thickness to provide sidewalls for forming sacrificial sidewalls. Moreover, the first masking layer 105 also provides mechanical support for the semiconductor fins 103'. The thickness of the first masking layer 105 is more than twice the height of the semiconductor fins 103'.
  • the first masking layer 105 is patterned by the above-described patterning process to expose the semiconductor fins 103' to be used to form a portion of the source and drain regions, as shown in FIG. 4a. 4b and 4c are shown.
  • the exposed portion of the first masking layer 105 is removed relative to the oxide layer 104.
  • the patterned first masking layer 105 has sidewalls extending along a length direction perpendicular to the semiconductor fins 103'.
  • the semiconductor fins 103' are subjected to a first ion implantation to form one of a source region and a drain region (not shown), as shown in FIGS. 5a, 5b, and 5c.
  • a first ion implantation for a P-type device, a p-type impurity such as In, BF 2 or B can be implanted; for an n-type device, an n-type impurity such as As or ? can be implanted. .
  • Additional ion implantation can also be performed to form the extension and halo regions as desired by the design.
  • the above-described P-type impurity may be implanted for the p-type device, and the above-described n-type impurity may be implanted for the n-type device.
  • the additional ion implantation for forming the halo region the above-described n-type impurity may be implanted for the P-type device, and the p-type impurity described above may be implanted for the n-type device.
  • an annealing treatment such as spike annealing, laser annealing, rapid annealing, or the like may be performed to activate the implanted impurities.
  • a second masking layer 106 (e.g., silicon oxide) is deposited over the semiconductor structure, for example, by the known deposition process described above.
  • a planarization process such as CMP, is then used to obtain the surface of the planar semiconductor structure, as shown in Figures 6a, 6b and 6c.
  • the CMP uses the first masking layer 105 as a stop layer.
  • the second masking layer 106 and the first masking layer 105 are adjacent to each other, and respectively cover a portion of the semiconductor fin 103' where one of the source and drain regions has been formed and a portion where the other of the source and drain regions are to be formed. .
  • the first masking layer 105 is selectively removed by selective dry etching or wet etching, such as RIE, with respect to the adjacent second masking layer 106 and the underlying oxide layer 104, as shown in FIG. 7a. 7b and 7c are shown.
  • the etch exposes one sidewall of the second masking layer 106 and does not require the use of an additional photoresist mask.
  • a nitride layer of, for example, 10 to 50 nm is deposited on the surface of the semiconductor structure by the above-described known deposition process, and then the sacrificial spacer 107 is formed on the sidewall of the second masking layer 106 by anisotropic etching. , as shown in Figures 8a, 8b and 8c.
  • the sacrificial sidewalls 107 are formed and material the same as conventional gate spacers and extend along a length perpendicular to the semiconductor fins 103'. As will be described below, the sacrificial sidewalls 107 are eventually removed and replaced by gate stacks.
  • the semiconductor fins 103' are subjected to a second ion implantation to form another one of the source and drain regions (not shown), as shown in the figure. 9a, 9b and 9c are shown.
  • the p-type impurity described above may be implanted into the p-type device, and the n-type impurity may be implanted into the n-type device.
  • Additional ion implantation can also be performed to form the extension and halo regions as desired by the design.
  • the above-described P-type impurity may be implanted for the p-type device, and the above-described n-type impurity may be implanted for the n-type device.
  • the additional ion implantation for forming the halo region the above-described n-type impurity may be implanted for the P-type device, and the p-type impurity described above may be implanted for the n-type device.
  • an annealing treatment such as spike annealing, laser annealing, rapid annealing, or the like may be performed to activate the implanted impurities.
  • the sacrificial spacer 107 is selectively removed by a dry etch or wet etch, such as RIE, with respect to the adjacent second masking layer 106 and the underlying oxide layer 104 using a suitable etchant.
  • a dry etch or wet etch such as RIE
  • Adjacent second masking layer 106 may also be etched while removing underlying oxide layer 104. Since the thickness of the second masking layer 106 can be much larger than the oxide layer 104, the second masking layer 106 remains after etching, except that the thickness is slightly reduced. This can be achieved by controlling the etching time.
  • a dielectric layer such as Hf0 2
  • a gate conductor layer such as polysilicon
  • the conductor layer is anisotropically etched to remove a portion of the conductor layer extending in parallel with the main surface of the semiconductor substrate 101.
  • the vertically extending portions of the gate conductor layer on the sidewalls of the second masking layer 106 remain, forming gate conductors 109 in the form of sidewall spacers.
  • the exposed portion of the dielectric layer is selectively removed relative to the gate conductor 109 and the second masking layer 106 using the gate conductor 109 as a hard mask and a suitable etchant to form the gate dielectric 108.
  • the gate stack includes a gate dielectric 108 and a gate conductor 109, wherein the gate dielectric 108 separates the gate conductor 109 from the semiconductor fins 103' as shown in Figures 10a, 10b and 10c.
  • the dielectric layer has a thickness of about 2 to 5 nanometers.
  • the thickness of the gate conductor layer is about 10-45 nm.
  • a success function adjustment layer (not shown) may be formed between the gate conductor 109 and the gate dielectric 108.
  • the work function adjusting layer may include, for example, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa, NiTa, MoN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi, Ni 3 Si, Pt, Ru, Ir Mo, HfRu, RuO x and combinations thereof may have a thickness of about 2-10 nm.
  • a work function adjusting layer is a preferred layer, and a gate stack including a work function adjusting layer (e.g., Hf0 2 /TiN/poly Si) can advantageously achieve reduced gate leakage current. .
  • a work function adjusting layer e.g., Hf0 2 /TiN/poly Si
  • a conformal nitride layer (eg, nitrided) may be formed on the surface of the semiconductor structure in accordance with conventional steps (such as those described in connection with Figures 8a, 8b, and 8c for forming the sacrificial spacers 107). Silicon) and the nitride layer is formed into a spacer (not shown) by anisotropic etching.
  • the nitride layer covers the exposed sidewalls of the gate conductor 109 such that the gate conductor 109 is electrically isolated from adjacent source or drain regions and conductive paths.
  • an interlayer insulating layer, a conductive via in the interlayer insulating layer, a wiring or an electrode on the upper surface of the interlayer insulating layer are formed on the obtained semiconductor structure, thereby completing the other FinFET section.
  • FIG 11 shows a perspective view of a FinFET 100 in accordance with an embodiment of the present invention.
  • the FinFET 101 is formed, for example, of a SOI wafer.
  • the SOI wafer includes a semiconductor substrate 101 and an insulating buried layer 102 And the semiconductor layer 103, wherein the insulating buried layer 102 is located between the semiconductor substrate 101 and the semiconductor layer 103.
  • the semiconductor fin 103 ' is formed of a semiconductor layer 103 .
  • Source and drain regions (not shown) of FinFET 100 are formed in two different portions of semiconductor fin 103'.
  • the oxide layer 104 and the second masking layer 106 are located above one of the source and drain regions.
  • the oxide layer 104 and oxide 106 are part of an interlayer dielectric layer.
  • the oxide layer 104 and oxide 106 have sidewalls adjacent to the other of the source and drain regions to provide mechanical support for the gate stack.
  • the gate stack includes a gate dielectric 108 and a gate conductor 109.
  • Gate dielectric 108 separates gate conductor 109 from semiconductor fin 103' and includes a first portion on the sidewall of second masking layer 106 and a second portion on semiconductor fin 103'. That is, in the cross section parallel to the longitudinal direction of the semiconductor fin 103' and passing through the semiconductor fin 103', the cross-sectional shape of the gate dielectric 108 is L-shaped.
  • the gate stack is substantially aligned with the source and drain regions. Also, the gate stack intersects the semiconductor fins 103', for example, along a length direction perpendicular to the semiconductor fins 103'.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

提供一种FinFET（100）及其制造方法，其中制造FinFET（100）的方法包括：形成半导体鳍片（103）；形成源区和漏区中的一个；形成牺牲侧墙（107）；以牺牲侧墙（107）作为掩模，形成源区和漏区中的另一个；去除牺牲侧墙（107）；以及采用栅堆叠替代牺牲侧墙（107），栅堆叠包括栅极导体（109）和栅极电介质（108），栅极电介质（108）将栅极导体（109）与半导体鳍片（103）隔开。

Description

FinFET及其制造方法 本申请要求了 2012年 12月 6日提交的、申请号为 201210520949. 5、 发明名称为 "FinFET及其制造方法"的中国专利申请的优先权，其全部内 容通过引用结合在本申请中。 技术领域
本发明涉及半导体技术， 更具体地， 涉及 FinFET及其制造方法。 背景技术
随着平面型半导体器件的尺寸越来越小， 短沟道效应愈加明显。 为 此， 提出了立体型半导体器件如 FinFET (鳍片场效应晶体管）。 FinFET 包括用于形成沟道区的半导体鳍片和至少覆盖半导体鳍片的一个侧壁的 栅堆叠。 栅堆叠与半导体鳍片相交， 并包括栅极导体和栅极电介质。 栅 极电介质将栅极导体和半导体鳍片之间隔开。 FinFET可以具有双栅、 三 栅或环栅配置， 而且半导体鳍片的宽度（即厚度）小， 因此 FinFET可以 改善栅极导体对沟道区的载流子的控制以及抑制短沟道效应。 传统的制 造栅堆叠的工艺包括沉积电介质层和导体层， 然后光刻形成栅堆叠的图 案。 然而， 随着器件尺寸的缩小， 在半导体鳍片的长度方向上形成小尺 寸 （即栅长） 的栅极越来越困难。
因此， 仍然期望提供制造小栅极尺寸的半导体器件的方法。 发明内容
本发明的目的是提供具有减小的栅极尺寸的 FinFET及其制造方法。 根据本发明的一方面， 提供一种制造 FinFET的方法， 包括： 形成半 导体鳍片； 形成源区和漏区中的一个； 形成牺牲侧墙； 以牺牲侧墙作为 掩模， 形成源区和漏区中的另一个； 去除牺牲侧墙； 以及采用栅堆叠替 代牺牲侧墙， 该栅堆叠包括栅极导体和栅极电介质， 栅极电介质将栅极 导体与半导体鳍片隔开。
根据本发明的另一方面， 提供一种 FinFET, 包括： 半导体鳍片； 位 于半导体鳍片中的源区和漏区；位于源区和漏区中的一个之上的掩蔽层， 掩蔽层具有面对源区和漏区中的另一个的侧壁； 以及位于源区和漏区之 间的栅堆叠， 栅堆叠栅极电介质和栅极导体， 其中栅极电介质将栅极导 体与半导体鳍片隔开。
本发明利用牺牲侧墙形成栅堆叠，从而可以比常规的 FinFET的栅长 小很多。 并且， 以牺牲侧墙作为掩模， 形成源区和漏区中的另一个， 相 应地可以实现栅堆叠与源区和漏区的大致对准。 本发明可以减少掩模的 使用以及对复杂的光刻工艺的需求， 从而降低制造成本。 附图说明
通过以下参照附图对本发明实施例的描述， 本发明的上述以及其他 目的、 特征和优点将更为清楚， 在附图中：
图 1至 10说明根据本发明的实施例制造 FinFET的方法的流程图； 以及
图 11示出根据本发明的实施例的 FinFET的透视图。 具体实施方式
以下将参照附图更详细地描述本发明。 在各个附图中， 相同的元件 采用类似的附图标记来表示。 为了清楚起见， 附图中的各个部分没有按 比例绘制。
为了简明起见， 可以在一幅图中描述经过数个歩骤后获得的半导体 结构。
应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另 一层、 另一个区域 "上面"或 "上方" 时， 可以指直接位于另一层、 另 一个区域上面， 或者在其与另一层、 另一个区域之间还包含其它的层或 区域。 并且， 如果将器件翻转， 该一层、 一个区域将位于另一层、 另一 个区域 "下面"或 "下方" 。 如果为了描述直接位于另一层、 另一个区 域上面的情形， 本文将采用 "直接在……上面"或 "在……上面并与之 邻接" 的表述方式。
在本申请中， 术语 "半导体结构"指在制造半导体器件的各个歩骤 中形成的整个半导体结构的统称， 包括已经形成的所有层或区域。 在下 文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处理工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员 能够理解的那样， 可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出， FinFET的各个部分可以由本领域的技术人 员公知的材料构成。半导体材料例如包括 III-V族半导体，如 GaAs、 InP、 GaN、 SiC， 以及 IV族半导体， 如 Si、 Ge。 栅极导体可以由能够导电的 各种材料形成， 例如金属层、 掺杂多晶硅层、 或包括金属层和掺杂多晶 硅层的叠层栅导体或者是其他导电材料，例如为 TaC、TiN、TaTbN、TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax, MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx |和所述各种 导电材料的组合。栅极电介质可以由 Si02或介电常数大于 Si02的材料构 成， 例如包括氧化物、 氮化物、 氧氮化物、 硅酸盐、 铝酸盐、 钛酸盐， 其中， 氧化物例如包括 Si02、 Hf02、Zr02、 A1203、 Ti02、 La203， 氮化物例 如包括 Si3N4， 硅酸盐例如包括 HfSiOx, 铝酸盐例如包括 LaA103， 钛酸盐 例如包括 SrTi03， 氧氮化物例如包括 SiON。 并且， 栅极电介质不仅可以 由本领域的技术人员公知的材料形成， 也可以采用将来开发的用于栅极 电介质的材料。
在常规的后栅工艺 （即替代栅工艺） 中， 在利用 "假"栅堆叠以及 该假栅堆叠两侧的侧墙在衬底中制造出源区和漏区之后， 保留两侧的侧 墙而在侧墙之间限定出孔隙， 通过填充孔隙来形成真正的栅堆叠。 与此 不同， 在本发明中， 提出了一种 "替代侧墙"工艺。 在形成源区和漏区 之后， 保留位于源区和漏区之一一侧的材料层， 并在该保留的材料层的 侧壁上以侧墙的形式形成栅堆叠（特别是， 栅导体）。从而可以在较大的 空间（具体地， 大致为栅区 +源区和漏区中另一个的区域）上来形成栅堆 叠， 相比于仅在侧墙之间的小栅极开口中形成栅堆叠的常规工艺， 可以 使得工艺更加容易进行。
本发明可以各种形式呈现， 以下将描述其中一些示例。
按照本发明的方法的实施例，执行图 1至 10所示的歩骤，其中在图 4c至 10c中示出俯视图以及截面图的截取位置，在图 1至 3和 4a至 10a 中示出在半导体鳍片的宽度方向上沿线 A-A截取的截面图， 在图 4b至 10b中示出在半导体鳍片的长度方向上沿线 B-B的截面图
参见图 1， 作为初始结构的半导体衬底是常规的 S0I晶片， 从下至 上依次包括半导体衬底 101、 绝缘埋层 102和半导体层 103。 半导体层 103的厚度例如约为 5nm - 20nm， 如 10nm、 15nm, 并且， 绝缘埋层 102 的厚度例如约为 5nm — 30nm， 如 10nm、 15nm、 20nm或 25nm。
半导体衬底 101材料可为体硅、 或 SiGe、 Ge等 IV族半导体材料、 或 III族 -V族化合物半导体 （如， 砷化镓） 材料。
绝缘埋层 102可以是氧化物埋层、氮氧化物埋层或其他的绝缘埋层。 半导体层 103将用于形成半导体鳍片，并提供 FinFET的源区和漏区 以及沟道区。半导体层 103例如由选自 IV族半导体（如，硅、锗或硅锗） 或 III族 -V族化合物半导体（如， 砷化镓） 的半导体材料组成， 本实施 例中， 半导体层 103可为单晶 Si或 SiGe。
用于形成上述 S0I晶片的工艺是已知的。例如，可以使用 SmartCut™ (称为 "智能剥离"或 "智能切割"）方法， 包括将分别包含通过热氧化 或沉积形成的氧化物表面层的两个晶片彼此键合， 其中， 两个晶片之一 已经进行氢注入， 从而在氧化物表面层以下的一定深度的硅本体内形成 氢注入区域， 然后， 在压力、 温度升高等情况下氢注入区域转变成微空 腔层， 从而有利于使微空腔层两边的部分分离， 剥离后包含键合的氧化 物表面层的部分作为 S0I晶片来使用。 通过控制热氧化或沉积的工艺参 数， 可以改变 S0I晶片的绝缘埋层的厚度。 通过控制氢注入的能量， 可 以改变 S0I晶片中包含的半导体层的厚度。
接下来，将半导体层 103图案化为半导体鳍片 103' ，如图 2所示。 该图案化可以包括以下歩骤： 通过包含曝光和显影的光刻工艺， 在半导 体层 103上形成含有图案的光抗蚀剂掩模 PR1; 通过干法蚀刻， 如离子 铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 或者通过其中使用蚀 刻剂溶液的湿法蚀刻， 去除半导体层 103的暴露部分， 该蚀刻停止在绝 缘埋层 102的顶部。
接下来， 通过在溶剂中溶解或灰化去除光抗蚀剂掩模 PR1。 然后， 通过已知的沉积工艺， 如 CVD (化学气相沉积）、 PVD (物理气相沉积）、 原子层沉积、 溅射等， 在半导体结构的表面上形成共形的氧化物层 104 和覆盖的第一掩蔽层 105 (例如， 氮化硅）， 如图 3所示。 例如通过化学 机械抛光（CMP )平整半导体结构的表面。通过控制时间， 使得 CMP仅去 除第一掩蔽层 105的一部分， 而没有到达氧化物层 104。 为了有利于在 半导体鳍片 103 ' 上形成牺牲侧墙， 希望保留厚度足够大的第一掩蔽层 105以提供用于形成牺牲侧墙的侧壁。 而且， 第一掩蔽层 105还提供对 半导体鳍片 103 ' 的机械支撑。 第一掩蔽层 105的厚度约为半导体鳍片 103 ' 的高度的两倍以上。
接下来， 采用光致抗蚀剂掩模， 通过上述的图案化工艺将第一掩蔽 层 105图案化， 以暴露半导体鳍片 103 ' 将用于形成源区和漏区之一部 分， 如图 4a、 4b和 4c所示。 在该图案化工艺的蚀刻歩骤中， 相对于氧 化物层 104去除第一掩蔽层 105的暴露部分。 图案化之后的第一掩蔽层 105具有沿着垂直于半导体鳍片 103 ' 的长度方向延伸的侧壁。
接下来， 以第一掩蔽层 105作为硬掩模， 对半导体鳍片 103 ' 进行 第一次离子注入以形成源区和漏区之一 （未示出）， 如图 5a、 5b 和 5c 所示。第一次离子注入中，对于 P型器件，可以通过注入 p型杂质如 In、 BF2或 B; 对于 n型器件， 可以通过注入 n型杂质如 As或？。
按照设计需要，还可以进行附加的离子注入以形成延伸区和暈圈区。 在用于形成延伸区的附加的离子注入中， 对于 p型器件， 可以注入上述 的 P型杂质， 对于 n型器件， 可以注入上述的 n型杂质。 在用于形成暈 圈区的附加的离子注入中， 对于 P型器件， 可以注入上述的 n型杂质， 对于 n型器件， 可以注入上述的 p型杂质。
可选地，在第一次离子注入之后，可以进行退火处理例如尖峰退火、 激光退火、 快速退火等， 以激活注入的杂质。
接下来， 通过上述已知的沉积工艺， 在半导体结构上例如沉积第二 掩蔽层 106 (例如， 氧化硅）。 然后进行平面化处理， 例如采用 CMP , 获 得平整的半导体结构的表面， 如图 6a、 6b和 6c所示。 该 CMP以第一掩 蔽层 105作为停止层。 结果， 第二掩蔽层 106和第一掩蔽层 105相互邻 接， 并且分别覆盖半导体鳍片 103 ' 上已经形成源区和漏区之一的部分 和将要形成源区和漏区中的另一个的部分。 接下来， 通过选择性的干法蚀刻或湿法蚀刻， 例如 RIE, 相对于邻 接的第二掩蔽层 106和位于下方的氧化物层 104， 选择性地去除第一掩 蔽层 105， 如图 7a、 7b和 7c所示。 该蚀刻暴露第二掩蔽层 106的一个 侧壁， 并且不需要使用附加的光致抗蚀剂掩模。
接下来， 通过上述的已知的沉积工艺， 在半导体结构的表面上沉积 例如 10-50纳米的氮化物层， 然后通过各向异性蚀刻在第二掩蔽层 106 的侧壁上形成牺牲侧墙 107， 如图 8a、 8b和 8c所示。 该牺牲侧墙 107 的形成和材料与常规的栅极侧墙相同， 并且沿着垂直于半导体鳍片 103 ' 的长度方向延伸。如下文将要描述的那样，该牺牲侧墙 107最终去 除并由栅堆叠代替。
接下来， 以第二掩蔽层 106和牺牲侧墙 107作为硬掩模， 对半导体 鳍片 103 ' 进行第二次离子注入以形成源区和漏区中的另一个 （未示 出）， 如图 9a、 9b和 9c所示。 第二次离子注入中， 对于 p型器件， 可以 注入上述的 P型杂质， 对于 n型器件， 可以注入上述的 n型杂质。
按照设计需要，还可以进行附加的离子注入以形成延伸区和暈圈区。 在用于形成延伸区的附加的离子注入中， 对于 p型器件， 可以注入上述 的 P型杂质， 对于 n型器件， 可以注入上述的 n型杂质。 在用于形成暈 圈区的附加的离子注入中， 对于 P型器件， 可以注入上述的 n型杂质， 对于 n型器件， 可以注入上述的 p型杂质。
可选地，在第二次离子注入之后，可以进行退火处理例如尖峰退火、 激光退火、 快速退火等， 以激活注入的杂质。
接下来， 采用合适的蚀刻剂， 通过上述的干法蚀刻或湿法蚀刻， 例 如 RIE,相对于邻接的第二掩蔽层 106和位于下方的氧化物层 104，选择 性地去除牺牲侧墙 107。在完全去除牺牲侧墙之后， 采用合适的蚀刻剂， 进一歩去除之前位于下方的氧化物层 104的未被邻接的第二掩蔽层 106 遮挡的部分。 在去除下方的氧化物层 104时， 邻接的第二掩蔽层 106也 可能受到蚀刻。 由于第二掩蔽层 106的厚度可以远大于氧化物层 104， 因此第二掩蔽层 106在蚀刻之后仍然保留， 只是厚度稍有减小。 这可以 通过控制蚀刻时间来实现。
然后， 通过已知的沉积工艺， 在半导体结构的表面上依次形成共形 的电介质层（例如 Hf02) 以及栅极导体层（例如多晶硅）。对导体层进行 各向异性蚀刻， 以去除导体层与半导体衬底 101的主表面平行延伸的部 分。 栅极导体层位于第二掩蔽层 106的侧壁上的垂直延伸的部分保留， 形成侧墙形式的栅极导体 109。 进一歩地， 采用栅极导体 109作为硬掩 模并采用合适的蚀刻剂， 相对于栅极导体 109和第二掩蔽层 106选择性 地去除电介质层的暴露部分， 以形成栅极电介质 108。 栅堆叠包括栅极 电介质 108和栅极导体 109， 其中栅极电介质 108将栅极导体 109与半 导体鳍片 103 ' 隔开， 如图 10a、 10b和 10c所示。
电介质层的厚度约为 2-5纳米。栅极导体层的厚度约为 10-45纳米。 结果， 通过控制栅极导体层的厚度， 所形成的栅极导体 109与图 8a、 8b 和 8c所示的牺牲侧墙 107大致对准， 进而使得所形成的栅极导体 109 与延伸区 111a和源区和漏区中的另一个 111b大致对准。
可选地， 在栅极导体 109和栅极电介质 108之间还可以形成功函数 调节层（未示出）。功函数调节层例如可以包括 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTa、 NiTa、 MoN、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSi、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx及其组合， 厚 度可以约为 2-10nm。 正如本领域的技术人员已知的那样， 功函数调节层 是优选的层， 包含功函数调节层的栅堆叠 （如 Hf02/TiN/多晶 Si ) 可以 有利地获得减小的栅极漏电流。
在形成包括栅极电介质 108和栅极导体 109的栅堆叠之后， 栅极导 体 109的一个侧壁与第二掩蔽层 106的侧壁邻接， 另一个侧壁则是暴露 的。 可以进一歩按照常规的歩骤 （例如结合图 8a、 8b和 8c描述的用于 形成牺牲侧墙 107的那些歩骤），在半导体结构的表面上形成共形的氮化 物层（例如，氮化硅），并通过各向异性蚀刻将该氮化物层形成为侧墙（未 示出）。 该氮化物层覆盖栅极导体 109 的暴露侧壁， 使得栅极导体 109 与相邻的源区或漏区和导电通道电隔离。在图 10所示的歩骤之后，在所 得到的半导体结构上形成层间绝缘层、 位于层间绝缘层中的导电通道、 位于层间绝缘层上表面的布线或电极， 从而完成 FinFET的其他部分。
图 11示出根据本发明的实施例的 FinFET 100的透视图。 该 FinFET 101例如由 S0I晶片形成。 S0I晶片包括半导体衬底 101、 绝缘埋层 102 和半导体层 103，其中绝缘埋层 102位于半导体衬底 101和半导体层 103 之间。 半导体鳍片 103 ' 由半导体层 103形成。 FinFET 100的源区和漏 区（未示出）形成在半导体鳍片 103 ' 的两个不同部分中。氧化物层 104 和第二掩蔽层 106位于源区和漏区中的一个上方。 该氧化物层 104和氧 化物 106作为层间介质层的一部分。 该氧化物层 104和氧化物 106具有 与源区和漏区中的另一个相邻的侧壁， 从而为栅堆叠提供机械支撑。 栅 堆叠包括栅极电介质 108和栅极导体 109。 栅极电介质 108将栅极导体 109与半导体鳍片 103 ' 隔开，并且包括位于第二掩蔽层 106的侧壁上的 第一部分和位于半导体鳍片 103 ' 上的第二部分。 也即， 在与半导体鳍 片 103 ' 的长度方向平行且经过半导体鳍片 103 ' 的截面中，栅极电介质 108的截面形状为 L形。 栅堆叠与源区和漏区大致对准。 并且， 栅堆叠 与半导体鳍片 103 ' 相交，例如沿着垂直于半导体鳍片 103 ' 的长度方向 延伸。
在以上的描述中， 对于各层的构图、 蚀刻等技术细节并没有做出详 细的说明。 但是本领域技术人员应当理解， 可以通过各种技术手段， 来 形成所需形状的层、 区域等。 另外， 为了形成同一结构， 本领域技术人 员还可以设计出与以上描述的方法并不完全相同的方法。 另外， 尽管在 以上分别描述了各实施例， 但是这并不意味着各个实施例中的措施不能 有利地结合使用。
以上对本发明的实施例进行了描述。 但是， 这些实施例仅仅是为了 说明的目的， 而并非为了限制本发明的范围。 本发明的范围由所附权利 要求及其等价物限定。 不脱离本发明的范围， 本领域技术人员可以做出 多种替代和修改， 这些替代和修改都应落在本发明的范围之内。

Claims

权 利 要 求
1、 一种制造 FinFET的方法， 包括：
形成半导体鳍片；
形成源区和漏区中的一个；
形成牺牲侧墙；
以牺牲侧墙作为掩模， 形成源区和漏区中的另一个；
去除牺牲侧墙； 以及
采用栅堆叠替代牺牲侧墙， 该栅堆叠包括栅极导体和栅极电介质， 极电介质将栅极导体与半导体鳍片隔开。
2、根据权利要求 1所述的方法，其中在形成源区和漏区中的一个的 骤中以第一掩蔽层作为硬掩模。
3、 根据权利要求 2所述的方法， 其中形成牺牲侧墙的歩骤包括： 形成与第一掩蔽层邻接的第二掩蔽层；
去除第一掩蔽层以暴露第二掩蔽层的一个侧壁； 以及
在第二掩蔽层的暴露的侧壁上形成牺牲侧墙。
4、根据权利要求 3所述的方法，其中在形成源区和漏区中的另一个 歩骤中， 第二掩蔽层遮挡所述源区和漏区中的一个。
5、根据权利要求 3所述的方法，其中采用栅堆叠替代牺牲侧墙包括: 去除牺牲侧墙；
形成共形的电介质层；
在电介质层上形成共形的导体层；
将导体层图案化为栅极导体； 以及
以栅极导体作为掩模， 将电介质层图案化为栅极电介质， 使得栅极 介质包括位于第二掩蔽层的侧壁上的第一部分和位于半导体鳍片上的 二部分。
6、根据权利要求 1所述的方法，其中栅极导体的厚度与牺牲侧墙的 度大致相等。
7、 一种 FinFET, 包括：
半导体鳍片； 位于半导体鳍片中的源区和漏区；
位于源区和漏区中的一个之上的掩蔽层， 掩蔽层具有面对源区和漏 区中的另一个的侧壁； 以及
位于源区和漏区之间的栅堆叠， 栅堆叠栅极电介质和栅极导体， 其 中栅极电介质将栅极导体与半导体鳍片隔开。
8、 根据权利要求 7所述的 FinFET, 其中， 栅极电介质包括位于掩 蔽层的侧壁上的第一部分和位于半导体鳍片上的第二部分。
9、 根据权利要求 7所述的 FinFET, 其中， 掩蔽层是层间绝缘层的 一部分。
PCT/CN2012/086523 2012-12-06 2012-12-13 FinFET及其制造方法 WO2014086058A1 (zh)

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