WO2014084126A1 - Display element and method for manufacturing same - Google Patents

Display element and method for manufacturing same Download PDF

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Publication number
WO2014084126A1
WO2014084126A1 PCT/JP2013/081449 JP2013081449W WO2014084126A1 WO 2014084126 A1 WO2014084126 A1 WO 2014084126A1 JP 2013081449 W JP2013081449 W JP 2013081449W WO 2014084126 A1 WO2014084126 A1 WO 2014084126A1
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WO
WIPO (PCT)
Prior art keywords
substrate
film
pixel electrode
protective film
counter substrate
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PCT/JP2013/081449
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French (fr)
Japanese (ja)
Inventor
久我　雷二郎
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株式会社Ｊｖｃケンウッド
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Publication of WO2014084126A1 publication Critical patent/WO2014084126A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133354—Arrangements for aligning or assembling substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G02F1/136281—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon having a transmissive semiconductor substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G02F2201/503—Arrangements improving the resistance to shock

Definitions

  • the present invention relates to a display element and a manufacturing method thereof, and more particularly to a display element having a structure in which two substrates are bonded together and a manufacturing method thereof.
  • the liquid crystal display element has a structure in which liquid crystal is sandwiched between a first substrate and a second substrate.
  • the first substrate and the second substrate are bonded together with a sealing material. Then, liquid crystal is sealed in a space formed by the first substrate, the second substrate, and the sealing material.
  • the first substrate is a drive substrate and the second substrate is a counter substrate.
  • Patent Document 1 discloses a liquid crystal display device having a spacer in contact with a protective layer formed in a non-demagnetization region and controlling the thickness of the liquid crystal layer to be constant (paragraph 0040).
  • the spacer is formed of the same material as that for forming the protective layer.
  • Patent Document 2 discloses a liquid crystal display device including an impact protection pattern for preventing damage to a thin film transistor, a driver circuit portion, and a terminal portion from an impact at the time of scribe / break when dividing into unit cells.
  • JP 2009-276743 A Japanese Patent Laid-Open No. 2001-305569
  • an object of the present invention is to provide a display device with high productivity and a manufacturing method thereof.
  • a method for manufacturing a display element includes a drive substrate having a transistor, a counter substrate disposed to face the drive substrate, a display region, and the drive substrate and the counter substrate.
  • a display element comprising: a sealing material for bonding together a step of forming a first film using a pixel electrode material on the drive substrate; and a protective film on the first film Forming a protective film harder than the counter substrate using a material; and patterning the first film and the protective film to form a pixel electrode connected to the transistor in the display region; Forming a dummy pixel electrode in a peripheral region outside the region, and in the display region so that the protective film on the dummy pixel electrode remains in the peripheral region.
  • a display element includes a drive substrate having a transistor, a counter substrate disposed to face the drive substrate, and a display region, and the drive substrate and the counter substrate are bonded to each other.
  • the display element according to the present embodiment is described as a reflective liquid crystal display element, but is not particularly limited. Any display element may be used as long as the driving substrate and the counter substrate are bonded to each other with a sealant.
  • FIG. 1 is a plan view showing a configuration of a liquid crystal display element
  • FIG. 2 is a sectional view thereof.
  • the thickness direction of the liquid crystal display element is defined as the Z direction
  • the direction along the edge of the rectangular liquid crystal display element is defined as the X direction and the Y direction.
  • the liquid crystal display element 100 includes a driving substrate 1 that is a first substrate, a counter substrate 2 that is a second substrate, and a sealing material 6.
  • the drive substrate 1 and the counter substrate 2 that are arranged to face each other are bonded together by a sealing material 6.
  • the sealing material 6 is formed in a rectangular frame shape on the surface of one substrate facing the other substrate, and the inside thereof becomes the display region 3.
  • a plurality of pixels 3a are arranged in an array. That is, the area where the pixels 3 a are arranged becomes the display area 3.
  • Each pixel 3a is provided with a transistor described later. Therefore, the drive substrate 1 is a transistor array substrate arranged in an array.
  • the outside of the rectangular display area 3 is a frame-shaped peripheral area 4.
  • peripheral circuits such as a shift register and a video switch are formed as will be described later.
  • one end of the driving substrate 1 protrudes from the counter substrate 2, and a terminal 47 connected to an external control circuit is formed at the protruding portion.
  • a plurality of terminals 47 are arranged along the Y direction.
  • the terminal 47 is connected to a printed board or a flexible board.
  • a liquid crystal 7 is sealed in a space formed by the drive substrate 1, the counter substrate 2, and the sealing material 6.
  • the driving substrate 1 and the counter substrate 2 are provided with alignment films 91 and 92 for aligning the liquid crystal 7 in a predetermined direction.
  • the alignment films 91 and 92 are disposed so as to face each other.
  • the alignment films 91 and 92 can be formed by obliquely depositing SiO or the like.
  • the sealing material 6 contains an in-seal spacer 8.
  • the drive substrate 1 is a silicon substrate cut out from a silicon wafer. Each pixel 3a is provided with a reflective pixel electrode (not shown) connected to a transistor which is a switching element.
  • the counter substrate 2 is a glass substrate cut out from a transparent mother glass substrate.
  • a counter electrode 105 is formed on the entire surface of the counter substrate 2.
  • the counter electrode 105 is formed on a transparent conductive film such as indium tin oxide (hereinafter referred to as ITO (Indium Tin Oxide)).
  • ITO Indium Tin Oxide
  • the liquid crystal 7 is driven by the voltage between the reflective pixel electrode and the counter electrode 105. When light enters from the counter substrate 2 side, the polarization state of the light reflected by the reflective pixel electrode is controlled according to the state of the liquid crystal 7. Therefore, a desired image can be displayed in the display area 3 by controlling the display signal supplied to each reflective pixel electrode. Further, an antireflection film or the like may be formed on the display side surface of the counter substrate 2 as necessary.
  • FIG. 3 is a cross-sectional view showing the configuration of the drive substrate 1 in the pixel 3a.
  • FIG. 3 shows a configuration before the drive substrate 1 is completed, specifically, a configuration after the reflective pixel electrode 14 is formed and before the uppermost insulating film is formed.
  • the drive substrate 1 which is a silicon substrate has a transistor 12.
  • the transistor 12 is a MOS (Metal Oxide Semiconductor) transistor, and has a source 40, a drain 41, and a gate 42.
  • the source 40 and the drain 41 are, for example, N + regions formed by impurity doping.
  • the gate 42 is disposed to face the channel between the source 40 and the drain 41 via the gate insulating film 45a.
  • An element isolation region 43 is provided between adjacent transistors 12.
  • the adjacent transistor 12 is isolated by the element isolation region 43.
  • an insulating film 45 including a gate insulating film 45a is provided on the drive substrate 1. Further, the first wiring layer 10 is provided on the transistor 12. A second wiring layer 11 is provided on the first wiring layer 10. An insulating film 45 is interposed between the first wiring layer 10 and the second wiring layer 11. Note that the first wiring layer 10 and the second wiring layer 11 serve as wiring patterns for supplying signals and voltages from the outside to the transistor 12 and the like.
  • An interlayer insulating film 13 is provided on the second wiring layer 11.
  • a reflective pixel electrode 14 is provided on the interlayer insulating film 13. That is, the interlayer insulating film 13 is interposed between the second wiring layer 11 and the reflective pixel electrode 14.
  • the reflective pixel electrode 14 has a laminated structure of a barrier film 51 and a reflective film 52.
  • the barrier film 51 for example, a TiN (titanium nitride) film having a thickness of 50 nm can be used.
  • the reflective film 52 for example, an Al—Cu alloy film having a thickness of 200 nm can be used.
  • the surface of the reflective pixel electrode 14 is a reflective surface that reflects light.
  • the partial pattern 10 a of the first wiring layer 10 is connected to the partial pattern 11 a of the second wiring layer 11 through the contact hole 46.
  • the pattern 11a of the second wiring layer 11 is connected to the reflective pixel electrode 14 via the contact plug 17a.
  • the contact plug 17a is embedded in the interlayer insulating film 13.
  • the contact plug 17a is formed of a metal such as tungsten.
  • the reflective pixel electrode 14 is connected to the source 40 through the contact plug 17a, the pattern 11a of the second wiring layer 11, the contact hole 46, the pattern 10a of the first wiring layer 10, and the contact hole 46. Further, the drive substrate 1 has a storage capacitor 44 for holding the charge of the reflective pixel electrode 14 in each pixel 3a.
  • the source 40 is connected to the storage capacitor electrode 44 a of the storage capacitor 44 through the contact hole 46, the pattern 10 a of the first wiring layer 10, and the contact hole 46.
  • FIG. 4 is a cross-sectional view showing the configuration of the drive substrate 1 in the peripheral region 4 where the peripheral circuit is provided.
  • FIG. 4 shows a configuration before the drive substrate 1 is completed, specifically, a configuration after the protective film 15 is formed and before the uppermost insulating film is formed.
  • the drive substrate 1 has a transistor 12.
  • the transistor 12 is a MOS transistor similar to the transistor 12 in the pixel 3 a and has a source 40, a drain 41, and a gate 42. Similar to the pixel 3 a, a first wiring layer 10 and a second wiring layer 11 are provided on the transistor 12.
  • An interlayer insulating film 13 is provided on the second wiring layer 11.
  • a dummy pixel electrode 14 a is provided on the interlayer insulating film 13.
  • a protective film 15 is provided on the dummy pixel electrode 14a.
  • the dummy pixel electrode 14a is made of the same material as that of the reflective pixel electrode 14. That is, the dummy pixel electrode 14 a has a laminated structure of the barrier film 51 and the reflective film 52.
  • the reflective pixel electrode 14 and the dummy pixel electrode 14a have a two-layer structure of a TiN (titanium nitride) film having a thickness of 50 nm and an Al—Cu alloy film having a thickness of 200 nm, but the material is particularly limited. It is not something.
  • the protective film 15 is formed of a TiN film having a thickness of 300 nm, for example.
  • the protective film 15 is thicker than the reflective pixel electrode 14 and the dummy pixel electrode 14a.
  • the protective film 15 is formed of the same material as the barrier film 51, but may be formed of a different material.
  • the protective film 15 may be a tungsten film or a laminated film containing other materials.
  • a protective film 15 is formed directly on the dummy pixel electrode 14a.
  • the dummy pixel electrode 14a has a predetermined size.
  • the protective film 15 is formed on the dummy pixel electrode 14a so as not to protrude from the dummy pixel electrode 14a. As will be described later, the protective film 15 is disposed along the cutting line of the counter substrate 2.
  • FIGS. 5A to 12B are process cross-sectional views showing the configuration in each process.
  • 5A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, and FIG. 12A show cross-sectional configurations in the peripheral region 4, which is a characteristic portion of this embodiment.
  • FIGS. 5B, 6, 7 B, 8 B, 9 B, 10 B, 11 B, and 12 B show cross-sectional configurations in the display region 3.
  • FIGS. 5B, 6, 7 B, 8 B, 9 B, 10 B, 11 B, and 12 B the configuration below the first wiring layer 10 is omitted.
  • the interlayer insulating film 13 is formed on the second wiring layer 11.
  • the insulating film is formed on the second wiring layer 11 by using a known film forming method such as a plasma chemical vapor deposition method (hereinafter, referred to as a plasma CVD method (Chemical Vapor Deposition)).
  • a plasma CVD method Chemical Vapor Deposition
  • the second wiring layer 11 is covered with the interlayer insulating film 13 as shown in FIGS. 5A and 5B.
  • a SiO 2 film having a thickness of 0.8 ⁇ m can be used.
  • a via hole 16 is formed in the interlayer insulating film 13.
  • a resist pattern (not shown) is formed on the interlayer insulating film 13 by photolithography.
  • a via hole 16 reaching the second wiring layer 11 is formed.
  • the via hole 16 can be formed by anisotropic dry etching using a mixed gas such as CHF 3 , CF 4 , and Ar.
  • the via hole 16 is not formed in the interlayer insulating film 13, so that the configuration shown in FIG. That is, the etching process is performed in the display region 3 in a state where the interlayer insulating film 13 in the peripheral region 4 is covered with the resist pattern.
  • contact plugs 17a embedded in the via holes 16 are formed.
  • a TiN film (not shown) is formed as a barrier film on the interlayer insulating film 13 provided with the via hole 16 by using a known film forming method such as a sputtering method (for example, about 50 nm).
  • a tungsten film is formed using a known film formation method such as a plasma CVD method.
  • CMP Chemical Mechanical Polishing
  • the tungsten film is the outermost surface in the portion that was the via hole 16
  • the interlayer insulating film 13 is the outermost surface in the other portions.
  • the thickness of the interlayer insulating film 13 that has undergone the CMP process is, for example, about 0.5 ⁇ m.
  • a barrier film and a tungsten film 17 are formed on the interlayer insulating film 13, and the structure shown in FIG. 7A is obtained. Thereafter, in the peripheral region 4, the barrier film and the tungsten film 17 formed on the interlayer insulating film 13 are all removed by CMP, and the interlayer insulating film 13 is exposed. Therefore, after the CMP process, the configuration is the same as that shown in FIG. 5A.
  • a barrier film 51, a reflective film 52, and a TiN film 23 are formed on the interlayer insulating film 13 on which the contact plugs 17a are formed. That is, the barrier film 51 is directly formed on the contact plug 17 a and the interlayer insulating film 13. Then, the reflective film 52 is directly formed on the barrier film 51. Further, the TiN film 23 is directly formed on the reflective film 52. As described above, the three conductive films of the barrier film 51, the reflective film 52, and the TiN film 23 are continuously formed on the second wiring layer 11. As will be described later, the reflective pixel electrode 14 and the dummy pixel electrode 14a are formed by patterning the barrier film 51 and the reflective film 52. Further, as will be described later, the protective film 15 is formed by patterning the TiN film 23.
  • the barrier film 51, the reflective film 52, and the TiN film 23 can be formed by a sputtering apparatus or a vapor deposition apparatus.
  • a TiN film having a thickness of 50 nm can be used.
  • an Al—Cu alloy film having a thickness of 200 nm can be used.
  • the thickness of the TiN film 23 can be 300 nm.
  • the barrier film 51, the reflective film 52, and the TiN film 23 are patterned. Therefore, a resist is applied on the TiN film 23, and the first resist pattern 19 is formed using a known photolithography process. As a result, the configuration shown in FIGS. 9A and 9B is obtained. Here, the resist is exposed by a photomask having a pixel separation pattern and a terminal separation pattern. As shown in FIG. 9B, in the display area 3, the first resist pattern 19 has an opening 19b. The opening 19b is disposed at a location other than the contact plug 17a, that is, a location corresponding to the interlayer insulating film 13. The opening 19b is provided to separate the reflective pixel electrode 14 of the adjacent pixel 3a. In FIG.
  • the opening 19b is not shown, but the opening 19b is also formed in the peripheral region 4 where the barrier film 51, the reflective film 52, and the TiN film 23 are removed, as in the display region 3.
  • the terminal 47 is separated as shown in FIGS.
  • etching is performed by a reactive ion etching (hereinafter referred to as RIE (Reactive Ion Etching)) apparatus using a mixed gas such as BCl 3 and Cl 2 .
  • RIE reactive Ion Etching
  • the barrier film 51, the reflective film 52, and the TiN film 23 are removed between the pixels 3a.
  • a pattern of the reflective pixel electrode 14 having a two-layer structure of the barrier film 51 and the reflective film 52 is formed in a portion that remains without being etched.
  • the barrier film 51, the reflective film 52, and the TiN film 23 are continuously etched to form a predetermined pattern.
  • the remaining barrier film 51 and the reflective film 52 form a pattern of the dummy pixel electrode 14a.
  • the TiN film 23 and the first resist pattern 19 are formed on the dummy pixel electrode 14 a and the reflective pixel electrode 14.
  • the barrier film 51, the reflective film 52, and the TiN film 23 are patterned using the first resist pattern 19 as a mask.
  • the first resist pattern 19 on the TiN film 23 is removed and cleaned with an oxygen ashing apparatus.
  • a resist is applied, and a second resist pattern 54 is formed using a known photolithography process. Thereby, it becomes the structure shown to FIG. 11A and FIG. 11B.
  • a resist pattern 54 is disposed on the TiN film 23.
  • the second resist pattern 54 has an opening 54a.
  • the opening 54a is formed at a position corresponding to the surface dividing groove 30 for cutting the counter substrate 2 in a later step.
  • the display area 3 shown in FIG. 11B has a configuration in which the resist is removed by development and the second resist pattern 54 is not formed. That is, in the display area 3, the second resist pattern 54 does not cover the TiN film 23, and all the TiN film 23 is exposed. In other words, the entire display area 3 becomes the opening 54b.
  • the TiN film 23 is etched using the second resist pattern 54 as a mask. Thereby, the TiN film 23 is patterned, and the protective film 15 is formed by the remaining TiN film 23. Then, when the second resist pattern 54 is removed, the configuration shown in FIGS. 12A and 12B is obtained. For example, the TiN film 23 is etched using a microwave etching apparatus using fluorine radicals as an etching species.
  • the TiN film 23 on the reflective film 52 is completely etched. That is, the reflective film 52 is exposed on the surface. Thereby, the reflective pixel electrode 14 is formed on the outermost surface. Therefore, the surface of the reflective pixel electrode 14 becomes a reflective surface on which light for display is reflected.
  • a protective film 15 is formed on the reflective pixel electrode. That is, in the opening 54a, the TiN film 23 on the dummy pixel electrode 14a is etched, so that a part of the reflective film 52 is exposed. And in the location covered with the resist pattern 54, the protective film 15 (TiN film 23) remains without being etched. Thereby, in the peripheral region 4, the pattern of the protective film 15 is formed on the dummy pixel electrode 14a.
  • an uppermost insulating film (not shown) is formed on the reflective pixel electrode 14, the dummy pixel electrode 14a, the protective film 15, and the like.
  • the uppermost insulating film is formed so that the terminal 47 shown in FIGS. 1 and 2 is exposed. Thereby, the drive substrate 1 is completed.
  • an alignment film 91 is formed on the drive substrate 1 (see FIG. 2).
  • the alignment film 91 is formed at least directly below the sealing material 6 and in the display region 3 so that the terminals 47 are exposed.
  • a counter electrode 105 and an alignment film 92 are formed on the counter substrate 2.
  • an ITO film having a thickness of 0.08 ⁇ m is used as the counter electrode 105.
  • the ITO film is formed using a sputtering method.
  • the alignment films 91 and 92 can be, for example, SiO 2 films having a thickness of 0.1 ⁇ m.
  • the alignment films 91 and 92 may be formed by forming a SiO 2 film having a thickness of 0.1 ⁇ m by oblique deposition.
  • the alignment films 91 and 92 align the liquid crystal 7 in a predetermined direction.
  • an antireflection film may be formed on the surface of the counter substrate 2 opposite to the surface on which the alignment film 92 is formed.
  • a laminated film of Nb 2 O 2 and SiO 2 having a thickness of 0.3 ⁇ m can be used as an antireflection film.
  • the antireflection film can be provided by forming a laminated film on the other surface side of the glass substrate using a vacuum deposition method.
  • the bonding a single bonding method in which the driving substrate 1 and the counter substrate 2 are bonded one by one, a mother substrate in which a wafer state or a plurality of cells are connected, and a corresponding mother glass substrate are bonded to each other.
  • a batch bonding in which a single cell is formed by dividing.
  • the present invention is applicable to both.
  • a silicon wafer and a mother glass substrate are bonded together to form a bonded structure.
  • the method of manufacturing each liquid crystal display element is used by cut
  • a silicon wafer having a plurality of drive substrates 1 is formed.
  • a counter electrode 105 and an alignment film 92 are formed on a mother glass substrate having a size equivalent to that of a silicon wafer. Thereby, a mother glass substrate having a plurality of counter substrates 2 is formed.
  • the sealing material 6 is applied to at least one of a silicon wafer provided with a plurality of drive substrates 1 and a mother glass substrate provided with a plurality of counter substrates 2.
  • the sealing material 6 containing the in-seal spacer 8 is applied on the silicon wafer.
  • the sealing material 6 is formed in a frame shape so as to surround the display area 3 of each cell.
  • the sealing material 6 is formed so as not to be applied on the protective film 15.
  • the sealing material 6 an epoxy resin adhesive that is cured by UV light and heat can be used.
  • a spacer ball made of SiO 2 having a diameter of 2 to 3 ⁇ m can be used.
  • the spacer 8 in the seal is mixed in a ratio of about 0.1% by weight with respect to the sealing material 6 serving as an adhesive material.
  • the width (seal width) of the expanded sealing material 6 after bonding can be set to 700 ⁇ m to 1 mm.
  • liquid crystal material is dropped on the silicon wafer by ODF (One Drop Filling) method.
  • ODF One Drop Filling
  • the liquid crystal material is dropped on the regions surrounded by the sealing material 6.
  • alignment is performed so that the drive substrate 1 and the counter substrate 2 face each other, and the silicon wafer and the mother glass substrate are disposed to face each other.
  • the sealing material 6 is cured using heat, UV light, or both.
  • the sealing material 6 is temporarily cured by irradiating UV light from the mother glass substrate side.
  • the bonded structure is taken out from the bonding apparatus and thermally cured at 120 ° C. for 2 hours. Thereby, the sealing material 6 is cured, and a bonded structure in which the silicon wafer and the mother glass substrate are bonded to each other is completed.
  • the silicon wafer is pressed against the mother glass substrate so that the cell gap is 2 to 3 ⁇ m.
  • the sealing material 6 is crushed and the in-seal spacer 8 comes into contact with the silicon wafer and the mother glass substrate.
  • the thickness of the sealing material 6 of the bonded structure is defined by the in-seal spacer 8.
  • the bonded structure is cut along the X direction and the Y direction. Specifically, after the silicon wafer is cut, the mother glass substrate is cut. Thereby, the bonded structure is separated into cells. Each of the separated cells becomes a liquid crystal display element 100.
  • An external control device or the like is connected to the liquid crystal display element 100 manufactured as described above by wire bonding or an anisotropic conductive film. That is, the control device is connected to the terminal 47. Thereby, the liquid crystal 7 is driven according to the voltage supplied to the pixel electrode. Light that has passed through the counter substrate 2 and the liquid crystal 7 from the outside is reflected by the reflective pixel electrode 14. Depending on the state of the liquid crystal 7, the amount of light reflected by the reflective pixel electrode 14 and emitted to the outside changes. A desired image can be displayed in response to a control signal from the external control device.
  • Such a reflective liquid crystal display element is suitable for a projector that projects an image, and can also be used for a head-up display mounted on a vehicle such as an automobile.
  • FIG. 13 is a plan view showing a cutting line in the bonded structure.
  • FIG. 14 is an XZ sectional view showing the configuration of the bonded structure, and
  • FIG. 15 is a YZ sectional view. 16 to 21 are process cross-sectional views for cutting the bonded structure and separating it into cells.
  • the bonded structure 103 has a structure in which the silicon wafer 101 and the mother glass substrate 102 are bonded together by the sealing material 6.
  • the silicon wafer 101 has a plurality of rectangular drive substrates 1, and the mother glass substrate 102 has a plurality of rectangular counter substrates 2.
  • the drive substrates 1 are arranged in an array.
  • the opposing substrates 2 are arranged in an array.
  • the silicon wafer 101 and the mother glass substrate 102 are arranged to face each other in a state where the driving substrate 1 and the counter substrate 2 are aligned.
  • FIG. 13 shows an example in which six drive substrates 1 and counter substrates 2 are provided, the number of cells cut out from the bonded structure is not particularly limited.
  • the bonded structure 103 can be separated into cells by cutting along the cutting lines L1 to L3. Therefore, a plurality of liquid crystal display elements 100 can be formed.
  • cutting lines L1 and L3 in the Y direction and cutting lines L2 in the X direction are provided.
  • the cutting line L2 is a line for cutting the silicon wafer 101 and the mother glass substrate 102.
  • the silicon wafer 101 and the mother glass substrate 102 are cut in the X direction along the cutting line L2.
  • the silicon wafer 101 and the mother glass substrate 102 have the same cutting line L2 in the X direction.
  • the cutting line L1 is a line for cutting the mother glass substrate 102.
  • the cutting line L3 is a line for cutting the silicon wafer 101.
  • the silicon wafer 101 and the mother glass substrate 102 have different Y-direction cutting lines L1 and L3. Therefore, a part of the drive substrate 1 is configured to protrude from the counter substrate 2. This is because the terminal 47 provided on the driving substrate 1 is exposed. That is, the terminal 47 is formed in a portion corresponding to one side end of the counter substrate 2 of the drive substrate 1 and protruding from the counter substrate 2.
  • a plurality of terminals 47 are arranged along the edge of the drive substrate 1. That is, the plurality of terminals 47 are arranged along the Y direction parallel to the cutting line L3.
  • the driving substrate 1 and the counter substrate 2 are aligned so that the terminal 47 is disposed between the cutting line L1 and the cutting line L3 in a plan view of the bonded structure 103 viewed from the mother glass substrate 102 side.
  • a glass dividing groove 28 is formed in the mother glass substrate 102 of the bonded structure 103.
  • the glass dividing groove 28 is formed along the cutting line L1, the cutting line L2, and the cutting line L3. Further, along the cutting lines L2 and L3, a front surface dividing groove 30 is formed on the surface of the silicon wafer 101, and a rear surface dividing groove 29 is formed on the back surface.
  • the front surface dividing groove 30 is formed before bonding, and the back surface dividing groove 29 is formed after bonding.
  • the rear surface dividing groove 29 and the front surface dividing groove 30 can be formed by half-cutting the silicon wafer 101 with a dicing blade of a dicing apparatus.
  • the glass dividing groove 28 is formed after bonding.
  • the glass dividing groove 28 is formed by marking the mother glass substrate 102 with a scriber.
  • the bonding structure 103 which has the glass parting groove
  • the adhesive sheet 32 is provided on the stage of the breaker device.
  • the adhesive sheet 32 is bonded to the mother glass substrate 102 of the bonded structure 103, and the bonded structure 103 is fixed.
  • the breaker squeegee 31 for scribe break is arranged on the cutting line L1 or the cutting line L3. Then, the bonded structure 103 fixed on the adhesive sheet 32 with the breaker squeegee 31 is hit from above. That is, the breaker squeegee 31 is pushed from above the silicon wafer 101. By doing so, the mother glass substrate 102 is cut based on the glass dividing grooves 28.
  • a local force may be applied to the bonded structure 103.
  • FIG. 19 when the foreign material 61 is sandwiched between the adhesive sheet 32 and the bonded structure 103, local damage may be applied to the bonded structure 103.
  • FIG. 20 there is a possibility that small fragments 36 of the substrate generated when one side is divided remain on the other parting line. Then, as shown in FIG. 21, when the other side is divided, the fragment 36 damages the drive circuit, leading to malfunction of the element.
  • the interlayer insulating film 13 is destroyed, causing a short circuit or disconnection of the first wiring layer 10 and the second wiring layer 11 located below the interlayer insulating film 13, leading to a malfunction of the liquid crystal display element 100. Therefore, there is a possibility that the yield is deteriorated and the productivity is lowered.
  • FIG. 22 is a diagram for explaining a region where the protective film 15 is provided, and is a plan view of the liquid crystal display element 100. As shown in FIG. 22, the side end surface of the counter substrate 2 corresponds to the cutting line L1 shown in FIGS.
  • a circuit such as a shift register is formed in a part of the peripheral area 4.
  • a region where a circuit is formed is defined as a peripheral circuit region.
  • a protective film 15 for protecting the circuit in the peripheral circuit region is formed in a region immediately below one side end surface of the counter substrate 2 (end surface cut along the above-described cutting line L1). That is, the protective film 15 is formed between the sealing material 6 and the terminal 47 in the driving substrate 1.
  • the protective film 15 is formed in a strip shape at a position corresponding to one end face of the counter substrate 2 in the drive substrate 1.
  • the protective film 15 is formed along the Y direction.
  • the protective film 15 is formed using TiN that is harder than the reflective pixel electrode 14, the second wiring layer 11, and the first wiring layer 10. Therefore, the peripheral circuit region having the transistor 12 provided in the lower layer can be protected.
  • the protective film 15 is not limited to the TiN film 23, and a tungsten film, a tungsten alloy film, or the like can be used.
  • FIG. 23 is a side sectional view showing a configuration around the protective film 15.
  • a protective film is formed in a region corresponding to one end surface of the counter substrate 2 formed along the cutting line L1 of the driving substrate 1 (hereinafter, also referred to as immediately below the cutting line L1). 15 is provided. That is, the peripheral circuit region 58 between the sealing material 6 and the terminal 47 is covered with the protective film 15.
  • the protective film 15 is provided on the drive substrate 1 in the region corresponding to the region immediately below the cutting line L1.
  • the mother glass substrate 102 is cut along a cutting line L1 corresponding to the region where the protective film 15 is formed.
  • the protective film 15 protects the peripheral circuit in the peripheral circuit region 58 even when a local force or damage occurs in the vicinity of the cutting line L1. That is, breakage of the transistor 12, disconnection of the first wiring layer 10 and the second wiring layer 11, a short circuit, and the like can be prevented, and yield can be improved. Since the protective film material is formed after the step of forming the reflective film 52, the lower layer than the reflective film 52 can be prevented from being affected.
  • FIG. 24 is a side cross-sectional view of a portion of the drive substrate 1 where the protective film 15 is formed.
  • the protective film 15 protects the peripheral circuit even when the counter substrate 2 is damaged and the fragments 36 are scattered.
  • the protective film 15 is preferably made of a material harder than the counter substrate 2. That is, the protective film 15 is formed of a material having a hardness higher than that of the glass material used as the counter substrate 2.
  • the protective film 15 is harder than the scattered pieces 36 of the counter substrate 2, so that the broken pieces 36 can be further prevented from penetrating the protective film 15. Thereby, a yield can be improved and productivity can be improved.
  • the protective film 15 may also be formed in regions corresponding to the other cutting lines L2 and L3.
  • FIG. 25 shows an enlarged cross-sectional view of the periphery of the protective film 15.
  • the width of the protective film 15 on the sealing material 6 side from the cutting line L1 is set to 100 ⁇ m, and the width of the protective film 15 on the terminal 47 side from the cutting line L1 is set to 400 ⁇ m. That is, the entire width of the protective film 15 is set to 500 ⁇ m, and the protective film 15 is disposed asymmetrically with respect to the cutting line L1. By doing in this way, damage to the circuit right below the cutting line L1 can be prevented more.
  • the width of the protective film 15 immediately below the cutting line L1 may be changed according to the dimensions of the region for forming the circuit and the conditions in the cutting process.
  • the protective film 15 By providing the protective film 15 with a width, not only in the region where the normal glass hits directly at the time of cutting, but also in the case where the location of the direct hit is shifted in the lateral direction instead of the vertical when the scribe is done, The formed transistor 12 and the like can be protected.
  • the protective film 15 immediately below the cutting line L1 may not be formed so as to correspond to the entire cutting line L1. That is, the transistor 12 and the wiring may be formed in the lower layer, and the protective film 15 may be formed only in a region that needs to be protected. In the region where the transistor 12 and the wiring are not formed, the protective film 15 may not be formed.
  • the protective film 15 may not be continuously formed in a belt shape. That is, the protective film 15 may be formed in a plurality of regions. In this case, the pattern of the adjacent protective film 15 is made sufficiently smaller than the scattered pieces 36. By doing so, it is possible to prevent the fragments 36 of the counter substrate 2 from damaging the peripheral circuits below the cutting line L1 in the cutting process. Further, by dividing the protective film 15 immediately below the cutting line L1, it is possible to prevent a short circuit through the protective film 15 immediately below the cutting line L1.

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Abstract

A display element having high productivity and a method for manufacturing the display element can be provided. A display element according to one embodiment of the present invention is provided with: a drive substrate (1) which comprises a transistor (12); a counter substrate (2) which is arranged so as to face the drive substrate (1); a seal material (6) which is arranged so as to surround a display region (3) and bonds the drive substrate (1) and the counter substrate (2) with each other; a protective film (15) which is formed of a material that is harder than the counter substrate (2) in a peripheral region that is right below at least one end face of the counter substrate (2) and is outside the display region (3) of the drive substrate (1); a reflective pixel electrode (14) which is arranged within the display region (3) and has a surface that serves as a light reflection surface; and a dummy pixel electrode (14a) which is arranged below the protective film (15) and is formed of the same material as the reflective pixel electrode (14).

Description

表示素子、及びその製造方法Display element and manufacturing method thereof
　本発明は、表示素子、及びその製造方法に関し、特に詳しくは、２枚の基板が貼り合わされた構造を有する表示素子、及びその製造方法に関する。 The present invention relates to a display element and a manufacturing method thereof, and more particularly to a display element having a structure in which two substrates are bonded together and a manufacturing method thereof.
　液晶表示素子は、第１の基板と第２の基板との間に液晶が挟持された構造を有している。第１の基板と第２の基板とはシール材によって貼り合わされる。そして、第１の基板と第２の基板とシール材とで形成された空間に液晶が封入されている。アクティブマトリクス型液晶表示素子では、第１の基板が駆動基板となり、第２の基板が対向基板となる。 The liquid crystal display element has a structure in which liquid crystal is sandwiched between a first substrate and a second substrate. The first substrate and the second substrate are bonded together with a sealing material. Then, liquid crystal is sealed in a space formed by the first substrate, the second substrate, and the sealing material. In the active matrix liquid crystal display element, the first substrate is a drive substrate and the second substrate is a counter substrate.
　特許文献１には、非消磁領域に形成された保護層に接して、液晶層の厚みを一定に制御するスペーサを有する液晶表示装置が開示されている（段落００４０）。スペーサは、保護層の形成材料と同様の材料で形成されている。 Patent Document 1 discloses a liquid crystal display device having a spacer in contact with a protective layer formed in a non-demagnetization region and controlling the thickness of the liquid crystal layer to be constant (paragraph 0040). The spacer is formed of the same material as that for forming the protective layer.
　特許文献２には、単位セルに分断する際のスクライブ／ブレーク時の衝撃から薄膜トランジスタ、ドライバ回路部、端子部の損傷を防止するための衝撃保護パターンを備えた液晶表示装置が開示されている。 Patent Document 2 discloses a liquid crystal display device including an impact protection pattern for preventing damage to a thin film transistor, a driver circuit portion, and a terminal portion from an impact at the time of scribe / break when dividing into unit cells.
特開２００９－２７６７４３号公報JP 2009-276743 A 特開２００１－３０５５６９号公報Japanese Patent Laid-Open No. 2001-305569
　液晶表示素子などの表示素子では、製造工程の簡略化や歩留まりの改善などによって、さらなる生産性の向上を図ることが望まれている。 In display elements such as liquid crystal display elements, it is desired to further improve productivity by simplifying the manufacturing process and improving yield.
　本発明は、上記問題に鑑み、生産性の高い表示素子とその製造方法を提供することを目的とする。 In view of the above problems, an object of the present invention is to provide a display device with high productivity and a manufacturing method thereof.
　本発明の一態様にかかる表示素子の製造方法は、トランジスタを有する駆動基板と、前記駆動基板と対向配置された対向基板と、表示領域を囲むように配置され、前記駆動基板と前記対向基板とを貼り合わせるシール材と、を備えた表示素子の製造方法であって、前記駆動基板の上に画素電極材料を用いて第１の膜を形成するステップと、前記第１の膜上に保護膜材料を用いて前記対向基板より硬い保護膜を形成するステップと、前記第１の膜及び前記保護膜をパターニングすることで、前記表示領域において前記トランジスタと接続される画素電極を形成し、前記表示領域の外側の周辺領域においてダミー画素電極を形成するステップと、前記周辺領域において前記ダミー画素電極の上の前記保護膜が残存するよう、前記表示領域において前記画素電極の上の前記保護膜を除去するステップと、前記駆動基板と前記対向基板との間に前記シール材を配置した状態で、前記駆動基板と前記対向基板を貼り合わせるステップと、前記保護膜が形成された領域に対応する切断線に沿って前記対向基板を切断するステップと、を有するものである。
　本発明の一態様にかかる表示素子は、トランジスタを有する駆動基板と、前記駆動基板と対向配置された対向基板と、表示領域を囲むように配置され、前記駆動基板と前記対向基板とを貼り合わせるシール材と、前記対向基板の少なくとも一側端面の直下に対応する、前記駆動基板の前記表示領域より外側の周辺領域に形成された、前記対向基板よりも硬い保護膜と、前記表示領域内に形成され、前記トランジスタと接続される画素電極と、前記保護膜の下に形成され、前記画素電極と同じ材料で形成されたダミー画素電極と、を備えたものである。 A method for manufacturing a display element according to one embodiment of the present invention includes a drive substrate having a transistor, a counter substrate disposed to face the drive substrate, a display region, and the drive substrate and the counter substrate. A display element comprising: a sealing material for bonding together a step of forming a first film using a pixel electrode material on the drive substrate; and a protective film on the first film Forming a protective film harder than the counter substrate using a material; and patterning the first film and the protective film to form a pixel electrode connected to the transistor in the display region; Forming a dummy pixel electrode in a peripheral region outside the region, and in the display region so that the protective film on the dummy pixel electrode remains in the peripheral region. Removing the protective film on the pixel electrode; bonding the drive substrate and the counter substrate in a state where the sealant is disposed between the drive substrate and the counter substrate; and the protection Cutting the counter substrate along a cutting line corresponding to the region where the film is formed.
A display element according to one embodiment of the present invention includes a drive substrate having a transistor, a counter substrate disposed to face the drive substrate, and a display region, and the drive substrate and the counter substrate are bonded to each other. A sealing material, a protective film harder than the counter substrate, formed in a peripheral region outside the display region of the drive substrate, corresponding to a position directly below at least one side end surface of the counter substrate; and in the display region A pixel electrode formed and connected to the transistor; and a dummy pixel electrode formed under the protective film and made of the same material as the pixel electrode.
　本発明によれば、生産性の高い表示素子とその製造方法を提供することができる。 According to the present invention, it is possible to provide a display element with high productivity and a manufacturing method thereof.
本実施の形態にかかる液晶表示素子の構成を模式的に示す平面図である。It is a top view which shows typically the structure of the liquid crystal display element concerning this Embodiment. 本実施の形態にかかる液晶表示素子の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the liquid crystal display element concerning this Embodiment. 駆動基板の画素部分の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the pixel part of a drive substrate. 駆動基板の周辺領域の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the peripheral region of a drive board | substrate. 駆動基板の周辺部分を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the peripheral part of a drive board | substrate. 駆動基板の画素領域の構成を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the structure of the pixel area | region of a drive substrate. 駆動基板の画素領域の構成を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the structure of the pixel area | region of a drive substrate. 駆動基板の周辺部分を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the peripheral part of a drive board | substrate. 駆動基板の画素領域の構成を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the structure of the pixel area | region of a drive substrate. 駆動基板の周辺部分を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the peripheral part of a drive board | substrate. 駆動基板の画素領域の構成を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the structure of the pixel area | region of a drive substrate. 駆動基板の周辺部分を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the peripheral part of a drive board | substrate. 駆動基板の画素領域の構成を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the structure of the pixel area | region of a drive substrate. 駆動基板の周辺部分を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the peripheral part of a drive board | substrate. 駆動基板の画素領域の構成を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the structure of the pixel area | region of a drive substrate. 駆動基板の周辺部分を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the peripheral part of a drive board | substrate. 駆動基板の画素領域の構成を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the structure of the pixel area | region of a drive substrate. 駆動基板の周辺部分を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the peripheral part of a drive board | substrate. 駆動基板の画素領域の構成を模式的に示す製造工程断面図である。It is manufacturing process sectional drawing which shows typically the structure of the pixel area | region of a drive substrate. 貼り合わせ構造体の切断線を示す平面図である。It is a top view which shows the cutting line of a bonding structure. 貼り合わせ構造体の構成を示すＸＺ断面図である。It is XZ sectional drawing which shows the structure of a bonding structure. 貼り合わせ構造体の構成を示すＹＺ断面図である。It is YZ sectional drawing which shows the structure of a bonding structure. 貼り合わせ構造体のＸ方向に沿った構成を示す工程断面図である。It is process sectional drawing which shows the structure along the X direction of the bonding structure. 貼り合わせ構造体のＹ方向の構成を示す工程断面図である。It is process sectional drawing which shows the structure of the Y direction of a bonding structure. 切断時において、切断線直下の周辺回路領域において発生する問題点を示す断面図である。It is sectional drawing which shows the problem which generate | occur | produces in the peripheral circuit area | region immediately under a cutting line at the time of a cutting | disconnection. 切断時において、切断線直下の周辺回路領域において発生する問題点を示す断面図である。It is sectional drawing which shows the problem which generate | occur | produces in the peripheral circuit area | region immediately under a cutting line at the time of a cutting | disconnection. 切断時において、切断線直下の周辺回路領域において発生する問題点を示す断面図である。It is sectional drawing which shows the problem which generate | occur | produces in the peripheral circuit area | region immediately under a cutting line at the time of a cutting | disconnection. 切断時において、切断線直下の周辺回路領域において発生する問題点を示す断面図である。It is sectional drawing which shows the problem which generate | occur | produces in the peripheral circuit area | region immediately under a cutting line at the time of a cutting | disconnection. 保護膜が形成された領域を模式的に示す平面図である。It is a top view which shows typically the area | region in which the protective film was formed. 保護膜の周辺の構成を模式的に示す側面断面図である。It is side surface sectional drawing which shows typically the periphery structure of a protective film. 保護膜が回路を保護する様子を示す側面断面図である。It is side surface sectional drawing which shows a mode that a protective film protects a circuit. 切断線直下における保護膜を示す断面図である。It is sectional drawing which shows the protective film just under a cutting line. 切断線直下における保護膜の寸法例を示す断面図である。It is sectional drawing which shows the example of a dimension of the protective film just under a cutting line.
　以下、図面を参照して、本発明の実施の形態について説明する。なお、以下の説明では、本実施の形態にかかる表示素子が、反射型の液晶表示素子であるとして説明するが、特に限定されるものではない。駆動基板と対向基板とがシール材によって貼り合わされた構成を有する表示素子であればよい。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the display element according to the present embodiment is described as a reflective liquid crystal display element, but is not particularly limited. Any display element may be used as long as the driving substrate and the counter substrate are bonded to each other with a sealant.
　（全体構成）
　まず、液晶表示素子の全体構成について、説明する。図１は、液晶表示素子の構成を示す平面図であり、図２はその断面図である。なお、図１、及び図２では、液晶表示素子の厚さ方向をＺ方向とし、矩形の液晶表示素子の端辺に沿った方向をＸ方向及びＹ方向としている。 (overall structure)
First, the overall configuration of the liquid crystal display element will be described. FIG. 1 is a plan view showing a configuration of a liquid crystal display element, and FIG. 2 is a sectional view thereof. In FIGS. 1 and 2, the thickness direction of the liquid crystal display element is defined as the Z direction, and the direction along the edge of the rectangular liquid crystal display element is defined as the X direction and the Y direction.
　液晶表示素子１００は、第１の基板である駆動基板１と、第２の基板である対向基板２と、シール材６と、を備えている。対向配置された駆動基板１と対向基板２とはシール材６によって貼り合わされている。シール材６は一方の基板の他方の基板と対向する面上に矩形枠状に形成されており、その内側が表示領域３となる。表示領域３には、複数の画素３ａがアレイ状に配置されている。すなわち、画素３ａが配置された領域が表示領域３となる。それぞれの画素３ａには、後述するトランジスタが配置されている。したがって、駆動基板１は、アレイ状に配置されたトランジスタアレイ基板となる。 The liquid crystal display element 100 includes a driving substrate 1 that is a first substrate, a counter substrate 2 that is a second substrate, and a sealing material 6. The drive substrate 1 and the counter substrate 2 that are arranged to face each other are bonded together by a sealing material 6. The sealing material 6 is formed in a rectangular frame shape on the surface of one substrate facing the other substrate, and the inside thereof becomes the display region 3. In the display area 3, a plurality of pixels 3a are arranged in an array. That is, the area where the pixels 3 a are arranged becomes the display area 3. Each pixel 3a is provided with a transistor described later. Therefore, the drive substrate 1 is a transistor array substrate arranged in an array.
　矩形状の表示領域３の外側が、額縁状の周辺領域４となる。周辺領域４には、後述するようにシフトレジスタ、ビデオスイッチ等の周辺回路が形成されている。周辺領域４において、駆動基板１の一端は対向基板２からはみ出しており、そのはみ出した部分に、外部の制御回路と接続される端子４７が形成される。ここでは、複数の端子４７がＹ方向に沿って配列されている。端子４７はプリント基板やフレキシブル基板等と接続される。 The outside of the rectangular display area 3 is a frame-shaped peripheral area 4. In the peripheral region 4, peripheral circuits such as a shift register and a video switch are formed as will be described later. In the peripheral region 4, one end of the driving substrate 1 protrudes from the counter substrate 2, and a terminal 47 connected to an external control circuit is formed at the protruding portion. Here, a plurality of terminals 47 are arranged along the Y direction. The terminal 47 is connected to a printed board or a flexible board.
　図２に示すように、駆動基板１と対向基板２とシール材６とで形成された空間には、液晶７が封入されている。駆動基板１と対向基板２には、液晶７を所定の方向に配向するための配向膜９１、９２が設けられている。配向膜９１、９２は、互いに向かうように配置されている。配向膜９１、９２は、ＳｉＯなどを斜め蒸着することによって形成することができる。また、シール材６は、シール内スペーサ８を含有している。 As shown in FIG. 2, a liquid crystal 7 is sealed in a space formed by the drive substrate 1, the counter substrate 2, and the sealing material 6. The driving substrate 1 and the counter substrate 2 are provided with alignment films 91 and 92 for aligning the liquid crystal 7 in a predetermined direction. The alignment films 91 and 92 are disposed so as to face each other. The alignment films 91 and 92 can be formed by obliquely depositing SiO or the like. Further, the sealing material 6 contains an in-seal spacer 8.
　駆動基板１は、シリコンウェハから切り出されたシリコン基板である。そして、それぞれの画素３ａには、スイッチング素子であるトランジスタと接続された反射画素電極（不図示）が設けられている。対向基板２は透明なマザーガラス基板から切り出されたガラス基板である。対向基板２の全面には、対向電極１０５が形成されている。対向電極１０５は、酸化インジウムスズ（以下、ＩＴＯ（Indium　Tin　Oxide））などの透明導電膜に形成されている。反射画素電極と対向電極１０５との間の電圧によって液晶７が駆動する。対向基板２側から光が入射すると、液晶７の状態に応じて、反射画素電極で反射される光の偏光状態が制御される。したがって、各反射画素電極に供給する表示信号を制御することで、表示領域３内に所望の画像を表示することができる。また、対向基板２の表示側の面には、必要に応じて反射防止膜等を形成してもよい。 The drive substrate 1 is a silicon substrate cut out from a silicon wafer. Each pixel 3a is provided with a reflective pixel electrode (not shown) connected to a transistor which is a switching element. The counter substrate 2 is a glass substrate cut out from a transparent mother glass substrate. A counter electrode 105 is formed on the entire surface of the counter substrate 2. The counter electrode 105 is formed on a transparent conductive film such as indium tin oxide (hereinafter referred to as ITO (Indium Tin Oxide)). The liquid crystal 7 is driven by the voltage between the reflective pixel electrode and the counter electrode 105. When light enters from the counter substrate 2 side, the polarization state of the light reflected by the reflective pixel electrode is controlled according to the state of the liquid crystal 7. Therefore, a desired image can be displayed in the display area 3 by controlling the display signal supplied to each reflective pixel electrode. Further, an antireflection film or the like may be formed on the display side surface of the counter substrate 2 as necessary.
　（画素３ａの構成）
　次に、画素３ａの断面構成について図３を用いて説明する。図３は、画素３ａにおける駆動基板１の構成を示す断面図である。なお、図３は、駆動基板１の完成前の構成、具体的には、反射画素電極１４を形成した後、最上層絶縁膜の形成前の構成を示している。シリコン基板である駆動基板１は、トランジスタ１２を有している。トランジスタ１２は、ＭＯＳ(Metal　Oxide　Semiconductor)トランジスタであり、ソース４０、ドレイン４１、及びゲート４２を有している。ソース４０、及びドレイン４１は、例えば、不純物ドープによって形成されたＮ＋領域となっている。ゲート４２は、ソース４０とドレイン４１との間のチャネルと、ゲート絶縁膜４５ａを介して対向配置されている。隣接するトランジスタ１２の間には、素子分離領域４３が設けられている。素子分離領域４３によって、隣接するトランジスタ１２が分離される。 (Configuration of Pixel 3a)
Next, a cross-sectional configuration of the pixel 3a will be described with reference to FIG. FIG. 3 is a cross-sectional view showing the configuration of the drive substrate 1 in the pixel 3a. FIG. 3 shows a configuration before the drive substrate 1 is completed, specifically, a configuration after the reflective pixel electrode 14 is formed and before the uppermost insulating film is formed. The drive substrate 1 which is a silicon substrate has a transistor 12. The transistor 12 is a MOS (Metal Oxide Semiconductor) transistor, and has a source 40, a drain 41, and a gate 42. The source 40 and the drain 41 are, for example, N + regions formed by impurity doping. The gate 42 is disposed to face the channel between the source 40 and the drain 41 via the gate insulating film 45a. An element isolation region 43 is provided between adjacent transistors 12. The adjacent transistor 12 is isolated by the element isolation region 43.
　駆動基板１上には、ゲート絶縁膜４５ａを含む絶縁膜４５が設けられている。さらに、トランジスタ１２の上には、第１配線層１０が設けられている。第１配線層１０の上には、第２配線層１１が設けられている。第１配線層１０と第２配線層１１の間には、絶縁膜４５が介在している。なお、第１配線層１０、及び第２配線層１１は、外部からの信号や電圧をトランジスタ１２等に供給するための配線パターンとなる。 On the drive substrate 1, an insulating film 45 including a gate insulating film 45a is provided. Further, the first wiring layer 10 is provided on the transistor 12. A second wiring layer 11 is provided on the first wiring layer 10. An insulating film 45 is interposed between the first wiring layer 10 and the second wiring layer 11. Note that the first wiring layer 10 and the second wiring layer 11 serve as wiring patterns for supplying signals and voltages from the outside to the transistor 12 and the like.
　第２配線層１１の上には、層間絶縁膜１３が設けられている。層間絶縁膜１３の上には、反射画素電極１４が設けられている。すなわち、第２配線層１１と反射画素電極１４との間には、層間絶縁膜１３が介在している。反射画素電極１４は、バリア膜５１と反射膜５２の積層構造となっている。バリア膜５１としては、例えば、厚さ５０ｎｍのＴｉＮ（窒化チタン）膜を用いることができる。反射膜５２としては、例えば、厚さ２００ｎｍのＡｌ－Ｃｕ合金膜を用いることができる。反射画素電極１４の表面は光を反射する反射面となる。 An interlayer insulating film 13 is provided on the second wiring layer 11. A reflective pixel electrode 14 is provided on the interlayer insulating film 13. That is, the interlayer insulating film 13 is interposed between the second wiring layer 11 and the reflective pixel electrode 14. The reflective pixel electrode 14 has a laminated structure of a barrier film 51 and a reflective film 52. As the barrier film 51, for example, a TiN (titanium nitride) film having a thickness of 50 nm can be used. As the reflective film 52, for example, an Al—Cu alloy film having a thickness of 200 nm can be used. The surface of the reflective pixel electrode 14 is a reflective surface that reflects light.
　第１配線層１０の一部のパターン１０ａは、コンタクトホール４６を介して、第２配線層１１の一部のパターン１１ａと接続されている。第２配線層１１のパターン１１ａは、コンタクトプラグ１７ａを介して反射画素電極１４と接続されている。コンタクトプラグ１７ａは、層間絶縁膜１３に埋め込まれている。コンタクトプラグ１７ａは、タングステンなどの金属によって形成されている。 The partial pattern 10 a of the first wiring layer 10 is connected to the partial pattern 11 a of the second wiring layer 11 through the contact hole 46. The pattern 11a of the second wiring layer 11 is connected to the reflective pixel electrode 14 via the contact plug 17a. The contact plug 17a is embedded in the interlayer insulating film 13. The contact plug 17a is formed of a metal such as tungsten.
　反射画素電極１４は、コンタクトプラグ１７ａ、第２配線層１１のパターン１１ａ、コンタクトホール４６、第１配線層１０のパターン１０ａ、コンタクトホール４６を介して、ソース４０と接続されている。さらに、駆動基板１は、各画素３ａに、反射画素電極１４の電荷を保持するための保持容量４４を有している。ソース４０は、コンタクトホール４６、第１配線層１０のパターン１０ａ、コンタクトホール４６を介して、保持容量４４の保持容量電極４４ａと接続されている。 The reflective pixel electrode 14 is connected to the source 40 through the contact plug 17a, the pattern 11a of the second wiring layer 11, the contact hole 46, the pattern 10a of the first wiring layer 10, and the contact hole 46. Further, the drive substrate 1 has a storage capacitor 44 for holding the charge of the reflective pixel electrode 14 in each pixel 3a. The source 40 is connected to the storage capacitor electrode 44 a of the storage capacitor 44 through the contact hole 46, the pattern 10 a of the first wiring layer 10, and the contact hole 46.
　（周辺領域４の構成）
　次に、周辺領域４の構成について、図４を用いて説明する。図４は、周辺回路が設けられた周辺領域４における駆動基板１の構成を示す断面図である。なお、図４は、駆動基板１の完成前の構成、具体的には、保護膜１５の形成後、最上層絶縁膜の形成前の構成を示している。周辺領域４において、駆動基板１は、トランジスタ１２を有している。トランジスタ１２は、画素３ａにおけるトランジスタ１２と同様のＭＯＳトランジスタであり、ソース４０、ドレイン４１、及びゲート４２を有している。画素３ａと同様に、トランジスタ１２の上には、第１配線層１０、及び第２配線層１１が設けられている。第２配線層１１の上には、層間絶縁膜１３が設けられている。層間絶縁膜１３の上には、ダミー画素電極１４ａが設けられている。ダミー画素電極１４ａの上には、保護膜１５が設けられている。 (Configuration of peripheral area 4)
Next, the configuration of the peripheral region 4 will be described with reference to FIG. FIG. 4 is a cross-sectional view showing the configuration of the drive substrate 1 in the peripheral region 4 where the peripheral circuit is provided. FIG. 4 shows a configuration before the drive substrate 1 is completed, specifically, a configuration after the protective film 15 is formed and before the uppermost insulating film is formed. In the peripheral region 4, the drive substrate 1 has a transistor 12. The transistor 12 is a MOS transistor similar to the transistor 12 in the pixel 3 a and has a source 40, a drain 41, and a gate 42. Similar to the pixel 3 a, a first wiring layer 10 and a second wiring layer 11 are provided on the transistor 12. An interlayer insulating film 13 is provided on the second wiring layer 11. A dummy pixel electrode 14 a is provided on the interlayer insulating film 13. A protective film 15 is provided on the dummy pixel electrode 14a.
　ダミー画素電極１４ａは反射画素電極１４と同じ材料によって形成されている。すなわち、ダミー画素電極１４ａは、バリア膜５１と反射膜５２の積層構造を有している。なお、反射画素電極１４、及びダミー画素電極１４ａとして、厚さ５０ｎｍのＴｉＮ（窒化チタン）膜、及び厚さ２００ｎｍのＡｌ－Ｃｕ合金膜の２層構造を用いているが、特に材料は限定されるものではない。 The dummy pixel electrode 14a is made of the same material as that of the reflective pixel electrode 14. That is, the dummy pixel electrode 14 a has a laminated structure of the barrier film 51 and the reflective film 52. The reflective pixel electrode 14 and the dummy pixel electrode 14a have a two-layer structure of a TiN (titanium nitride) film having a thickness of 50 nm and an Al—Cu alloy film having a thickness of 200 nm, but the material is particularly limited. It is not something.
　保護膜１５は、例えば、厚さ３００ｎｍのＴｉＮ膜によって形成されている。保護膜１５は、反射画素電極１４、及びダミー画素電極１４ａよりも厚くなっている。なお、保護膜１５を、バリア膜５１と同じ材料で形成しているが、異なる材料で形成してもよい。例えば、保護膜１５をタングステン膜としてもよく、その他の材料を含む積層膜としてもよい。ダミー画素電極１４ａの上には、直接、保護膜１５が形成されている。ダミー画素電極１４ａは、所定の大きさになっている。そして、保護膜１５は、ダミー画素電極１４ａからはみ出さないように、ダミー画素電極１４ａ上に形成される。後述するように、保護膜１５は、対向基板２の切断線に沿って配置されている。 The protective film 15 is formed of a TiN film having a thickness of 300 nm, for example. The protective film 15 is thicker than the reflective pixel electrode 14 and the dummy pixel electrode 14a. The protective film 15 is formed of the same material as the barrier film 51, but may be formed of a different material. For example, the protective film 15 may be a tungsten film or a laminated film containing other materials. A protective film 15 is formed directly on the dummy pixel electrode 14a. The dummy pixel electrode 14a has a predetermined size. The protective film 15 is formed on the dummy pixel electrode 14a so as not to protrude from the dummy pixel electrode 14a. As will be described later, the protective film 15 is disposed along the cutting line of the counter substrate 2.
　（製造工程）
　以下、本実施の形態にかかる液晶表示素子１００の製造方法について、図５Ａ～図１２Ｂを用いて説明する。図５Ａ～図１２Ｂは、各工程における構成を示す工程断面図である。図５Ａ、図７Ａ、図８Ａ、図９Ａ、図１０Ａ、図１１Ａ、及び図１２Ａは本実施の特徴部分である周辺領域４での断面構成を示している。図５Ｂ、図６、図７Ｂ、図８Ｂ、図９Ｂ、図１０Ｂ、図１１Ｂ、及び図１２Ｂは表示領域３での断面構成を示している。 (Manufacturing process)
Hereinafter, a method for manufacturing the liquid crystal display element 100 according to the present embodiment will be described with reference to FIGS. 5A to 12B. 5A to 12B are process cross-sectional views showing the configuration in each process. 5A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, and FIG. 12A show cross-sectional configurations in the peripheral region 4, which is a characteristic portion of this embodiment. FIGS. 5B, 6, 7 B, 8 B, 9 B, 10 B, 11 B, and 12 B show cross-sectional configurations in the display region 3.
　以下の説明では、第２配線層１１を形成した後の製造工程を説明する。図５Ｂ、図６、図７Ｂ、図８Ｂ、図９Ｂ、図１０Ｂ、図１１Ｂ、及び図１２Ｂでは、第１配線層１０よりも下の構成を省略して図示している。 In the following description, a manufacturing process after forming the second wiring layer 11 will be described. In FIGS. 5B, 6, 7 B, 8 B, 9 B, 10 B, 11 B, and 12 B, the configuration below the first wiring layer 10 is omitted.
　まず、第２配線層１１の上に、層間絶縁膜１３を形成する。例えば、第２配線層１１の上から絶縁膜をプラズマ化学蒸着法（以下、プラズマＣＶＤ法（Chemical　Vapor　Deposition））などの公知の成膜方法を用いて成膜する。こうすることで、図５Ａ、及び図５Ｂに示すように、第２配線層１１が層間絶縁膜１３によって覆われる。層間絶縁膜１３としては、厚さ０．８μｍのＳｉＯ２膜を用いることができる。 First, the interlayer insulating film 13 is formed on the second wiring layer 11. For example, the insulating film is formed on the second wiring layer 11 by using a known film forming method such as a plasma chemical vapor deposition method (hereinafter, referred to as a plasma CVD method (Chemical Vapor Deposition)). By so doing, the second wiring layer 11 is covered with the interlayer insulating film 13 as shown in FIGS. 5A and 5B. As the interlayer insulating film 13, a SiO 2 film having a thickness of 0.8 μm can be used.
　次に、図６に示すように、層間絶縁膜１３にＶｉａホール１６を形成する。例えば、フォトリソグラフィ法によって、層間絶縁膜１３の上にレジストパターン（不図示）を形成する。レジストパターンが形成された状態で層間絶縁膜１３をエッチングすることで、第２配線層１１に到達するＶｉａホール１６が形成される。例えば、ＣＨＦ３、ＣＦ４，Ａｒなどの混合ガスを用いた異方性ドライエッチングでＶｉａホール１６を形成することができる。なお、周辺領域４では、層間絶縁膜１３にＶｉａホール１６を形成しないため、図５Ａに示す構成のままとなっている。すなわち、周辺領域４の層間絶縁膜１３がレジストパターンによって覆われた状態で表示領域３ではエッチング工程が実行される。 Next, as shown in FIG. 6, a via hole 16 is formed in the interlayer insulating film 13. For example, a resist pattern (not shown) is formed on the interlayer insulating film 13 by photolithography. By etching the interlayer insulating film 13 with the resist pattern formed, a via hole 16 reaching the second wiring layer 11 is formed. For example, the via hole 16 can be formed by anisotropic dry etching using a mixed gas such as CHF 3 , CF 4 , and Ar. In the peripheral region 4, the via hole 16 is not formed in the interlayer insulating film 13, so that the configuration shown in FIG. That is, the etching process is performed in the display region 3 in a state where the interlayer insulating film 13 in the peripheral region 4 is covered with the resist pattern.
　続いて、図７Ｂに示すようにＶｉａホール１６に埋め込まれるコンタクトプラグ１７ａを形成する。例えば、Ｖｉａホール１６が設けられた層間絶縁膜１３の上から、バリア膜としてＴｉＮ膜（図示省略）をスパッタ法等の公知の成膜方法を用いて非常に薄く（たとえば、５０ｎｍ程度）成膜し、次にプラズマＣＶＤ法などの公知の成膜方法を用いて、タングステン膜を成膜する。そして、層間絶縁膜１３に到達するまで化学機械研磨（以下、ＣＭＰ（Chemical　Mechanical　Polishing））によりタングステン膜、及びバリア膜を除去していくことで、タングステン膜、及びバリア膜がＶｉａホールを埋めてコンタクトプラグ１７ａが形成される。換言すると、Ｖｉａホール１６であった箇所はタングステン膜が最表面となり、その他は、層間絶縁膜１３が最表面となる。ＣＭＰ工程を経た層間絶縁膜１３の厚さは、例えば、約０．５μｍとなっている。 Subsequently, as shown in FIG. 7B, contact plugs 17a embedded in the via holes 16 are formed. For example, a TiN film (not shown) is formed as a barrier film on the interlayer insulating film 13 provided with the via hole 16 by using a known film forming method such as a sputtering method (for example, about 50 nm). Then, a tungsten film is formed using a known film formation method such as a plasma CVD method. Then, by removing the tungsten film and the barrier film by chemical mechanical polishing (hereinafter, CMP (Chemical Mechanical Polishing)) until the interlayer insulating film 13 is reached, the tungsten film and the barrier film fill the via hole. Contact plug 17a is formed. In other words, the tungsten film is the outermost surface in the portion that was the via hole 16, and the interlayer insulating film 13 is the outermost surface in the other portions. The thickness of the interlayer insulating film 13 that has undergone the CMP process is, for example, about 0.5 μm.
　また、周辺領域４では、層間絶縁膜１３の上にバリア膜とタングステン膜１７が成膜されて、図７Ａに示す構成となる。その後、周辺領域４では、ＣＭＰによって、層間絶縁膜１３の上に形成されたバリア膜とタングステン膜１７が全て除去され、層間絶縁膜１３が露出する。したがって、ＣＭＰ工程を経た後は、図５Ａに示す構成と同じ構成になる。 Further, in the peripheral region 4, a barrier film and a tungsten film 17 are formed on the interlayer insulating film 13, and the structure shown in FIG. 7A is obtained. Thereafter, in the peripheral region 4, the barrier film and the tungsten film 17 formed on the interlayer insulating film 13 are all removed by CMP, and the interlayer insulating film 13 is exposed. Therefore, after the CMP process, the configuration is the same as that shown in FIG. 5A.
　次に、図８Ａ、及び図８Ｂに示すように、コンタクトプラグ１７ａが形成された層間絶縁膜１３の上に、バリア膜５１、反射膜５２、及びＴｉＮ膜２３を形成する。すなわち、コンタクトプラグ１７ａと層間絶縁膜１３の上にバリア膜５１を直接成膜する。そして、バリア膜５１の上に反射膜５２を直接成膜する。さらに、反射膜５２の上にＴｉＮ膜２３を直接成膜する。このように第２配線層１１の上に、バリア膜５１、反射膜５２、及びＴｉＮ膜２３の３層の導電膜が連続して成膜される。後述するように、バリア膜５１、反射膜５２がパターニングされることで、反射画素電極１４、及びダミー画素電極１４ａが形成される。また、後述するように、ＴｉＮ膜２３がパターニングされることで、保護膜１５が形成される。 Next, as shown in FIGS. 8A and 8B, a barrier film 51, a reflective film 52, and a TiN film 23 are formed on the interlayer insulating film 13 on which the contact plugs 17a are formed. That is, the barrier film 51 is directly formed on the contact plug 17 a and the interlayer insulating film 13. Then, the reflective film 52 is directly formed on the barrier film 51. Further, the TiN film 23 is directly formed on the reflective film 52. As described above, the three conductive films of the barrier film 51, the reflective film 52, and the TiN film 23 are continuously formed on the second wiring layer 11. As will be described later, the reflective pixel electrode 14 and the dummy pixel electrode 14a are formed by patterning the barrier film 51 and the reflective film 52. Further, as will be described later, the protective film 15 is formed by patterning the TiN film 23.
　例えば、バリア膜５１、反射膜５２、及びＴｉＮ膜２３は、スパッタ装置、又は蒸着装置により成膜することができる。バリア膜５１としては、厚さ５０ｎｍのＴｉＮ膜を用いることができる。反射膜５２としては、厚さ２００ｎｍのＡｌ－Ｃｕ合金膜を用いることできる。ＴｉＮ膜２３の厚さは３００ｎｍとすることができる。 For example, the barrier film 51, the reflective film 52, and the TiN film 23 can be formed by a sputtering apparatus or a vapor deposition apparatus. As the barrier film 51, a TiN film having a thickness of 50 nm can be used. As the reflective film 52, an Al—Cu alloy film having a thickness of 200 nm can be used. The thickness of the TiN film 23 can be 300 nm.
　次に、バリア膜５１、反射膜５２、及びＴｉＮ膜２３をパターニングする。そのため、ＴｉＮ膜２３の上に、レジストを塗布し、公知のフォトリソグラフィ工程を用いて、第１のレジストパターン１９を形成する。これにより、図９Ａ、及び図９Ｂに示す構成となる。ここでは、画素分離パターンと端子分離パターンを有するフォトマスクによって、レジストを露光する。図９Ｂに示すように、表示領域３では、第１のレジストパターン１９が開口部１９ｂを有している。開口部１９ｂは、コンタクトプラグ１７ａ以外の箇所、すなわち層間絶縁膜１３に対応する箇所に配置される。開口部１９ｂは、隣接する画素３ａの反射画素電極１４を分離するために設けられる。図９Ａでは、開口部１９ｂが図示されていないが、周辺領域４においても表示領域３と同様に、開口部１９ｂが、バリア膜５１、反射膜５２、及びＴｉＮ膜２３を除去する箇所に形成される。これにより、例えば、図１、２に示したように端子４７が分離される。 Next, the barrier film 51, the reflective film 52, and the TiN film 23 are patterned. Therefore, a resist is applied on the TiN film 23, and the first resist pattern 19 is formed using a known photolithography process. As a result, the configuration shown in FIGS. 9A and 9B is obtained. Here, the resist is exposed by a photomask having a pixel separation pattern and a terminal separation pattern. As shown in FIG. 9B, in the display area 3, the first resist pattern 19 has an opening 19b. The opening 19b is disposed at a location other than the contact plug 17a, that is, a location corresponding to the interlayer insulating film 13. The opening 19b is provided to separate the reflective pixel electrode 14 of the adjacent pixel 3a. In FIG. 9A, the opening 19b is not shown, but the opening 19b is also formed in the peripheral region 4 where the barrier film 51, the reflective film 52, and the TiN film 23 are removed, as in the display region 3. The Thereby, for example, the terminal 47 is separated as shown in FIGS.
　そして、第１のレジストパターン１９が形成された状態で、バリア膜５１、反射膜５２、及びＴｉＮ膜２３を一括してエッチングすると、図１０Ａ、及び図１０Ｂに示す構成となる。ここでは、例えば、ＢＣｌ３、Ｃｌ２等の混合ガスを用いた反応性イオンエッチング（以下、ＲＩＥ(Reactive　Ion　Etching)）装置などでエッチングを行う。画素３ａでは、図１０Ｂに示すように、画素３ａ間の部分で、バリア膜５１、反射膜５２、及びＴｉＮ膜２３が除去される。これにより、エッチングされずに残った箇所には、バリア膜５１、反射膜５２の２層構造を有する反射画素電極１４のパターンが形成される。 Then, when the barrier film 51, the reflective film 52, and the TiN film 23 are collectively etched with the first resist pattern 19 formed, the configuration shown in FIGS. 10A and 10B is obtained. Here, for example, etching is performed by a reactive ion etching (hereinafter referred to as RIE (Reactive Ion Etching)) apparatus using a mixed gas such as BCl 3 and Cl 2 . In the pixel 3a, as shown in FIG. 10B, the barrier film 51, the reflective film 52, and the TiN film 23 are removed between the pixels 3a. As a result, a pattern of the reflective pixel electrode 14 having a two-layer structure of the barrier film 51 and the reflective film 52 is formed in a portion that remains without being etched.
　周辺領域４においても、バリア膜５１、反射膜５２、及びＴｉＮ膜２３が連続してエッチングされて、所定のパターンが形成される。残存したバリア膜５１、及び反射膜５２によりダミー画素電極１４ａのパターンが形成される。なお、この段階では、ダミー画素電極１４ａ、及び反射画素電極１４の上に、ＴｉＮ膜２３、及び第１のレジストパターン１９が形成されている。このように、第１のレジストパターン１９をマスクとして用いて、バリア膜５１、反射膜５２、及びＴｉＮ膜２３をパターニングする。そして、酸素アッシング装置で、ＴｉＮ膜２３上の第１のレジストパターン１９を除去して、洗浄する。 Also in the peripheral region 4, the barrier film 51, the reflective film 52, and the TiN film 23 are continuously etched to form a predetermined pattern. The remaining barrier film 51 and the reflective film 52 form a pattern of the dummy pixel electrode 14a. At this stage, the TiN film 23 and the first resist pattern 19 are formed on the dummy pixel electrode 14 a and the reflective pixel electrode 14. In this way, the barrier film 51, the reflective film 52, and the TiN film 23 are patterned using the first resist pattern 19 as a mask. Then, the first resist pattern 19 on the TiN film 23 is removed and cleaned with an oxygen ashing apparatus.
　次に、レジストを塗布し、公知のフォトリソグラフィ工程を用いて、第２のレジストパターン５４を形成する。これにより、図１１Ａ、及び図１１Ｂに示す構成となる。周辺領域４では、図１１Ａに示すように、ＴｉＮ膜２３の上にレジストパターン５４が配置される。また、周辺領域４では、第２のレジストパターン５４は開口部５４ａを有している。例えば、開口部５４ａは、後の工程で対向基板２を切断するための表面分断溝３０に対応する位置に形成される。 Next, a resist is applied, and a second resist pattern 54 is formed using a known photolithography process. Thereby, it becomes the structure shown to FIG. 11A and FIG. 11B. In the peripheral region 4, as shown in FIG. 11A, a resist pattern 54 is disposed on the TiN film 23. In the peripheral region 4, the second resist pattern 54 has an opening 54a. For example, the opening 54a is formed at a position corresponding to the surface dividing groove 30 for cutting the counter substrate 2 in a later step.
　一方、図１１Ｂに示す表示領域３では、現像によりレジストが除去されて、第２のレジストパターン５４が形成されていない構成となる。すなわち、表示領域３では、第２のレジストパターン５４が、ＴｉＮ膜２３を覆っておらず、全てのＴｉＮ膜２３が露出した構成となる。換言すると、表示領域３全体が開口部５４ｂとなる。 On the other hand, the display area 3 shown in FIG. 11B has a configuration in which the resist is removed by development and the second resist pattern 54 is not formed. That is, in the display area 3, the second resist pattern 54 does not cover the TiN film 23, and all the TiN film 23 is exposed. In other words, the entire display area 3 becomes the opening 54b.
　そして、第２のレジストパターン５４をマスクとして用いて、ＴｉＮ膜２３をエッチングする。これにより、ＴｉＮ膜２３がパターニングされて、残ったＴｉＮ膜２３によって保護膜１５が形成される。そして、第２のレジストパターン５４を除去すると、図１２Ａ、及び図１２Ｂに示す構成となる。例えば、フッ素ラジカルをエッチング種としたマイクロ波エッチング装置を用いてＴｉＮ膜２３がエッチングされる。 Then, the TiN film 23 is etched using the second resist pattern 54 as a mask. Thereby, the TiN film 23 is patterned, and the protective film 15 is formed by the remaining TiN film 23. Then, when the second resist pattern 54 is removed, the configuration shown in FIGS. 12A and 12B is obtained. For example, the TiN film 23 is etched using a microwave etching apparatus using fluorine radicals as an etching species.
　表示領域３では、図１２Ｂに示すように、反射膜５２の上のＴｉＮ膜２３が完全にエッチングされる。すなわち、反射膜５２が表面に露出した構成となる。これにより、反射画素電極１４が最表面に形成される。したがって、反射画素電極１４の表面が表示するための光が反射される反射面となる。 In the display area 3, as shown in FIG. 12B, the TiN film 23 on the reflective film 52 is completely etched. That is, the reflective film 52 is exposed on the surface. Thereby, the reflective pixel electrode 14 is formed on the outermost surface. Therefore, the surface of the reflective pixel electrode 14 becomes a reflective surface on which light for display is reflected.
　一方、周辺領域４では、図１２Ａに示すように、反射画素電極１４の上に保護膜１５が形成される。すなわち、開口部５４ａにおいて、ダミー画素電極１４ａ上のＴｉＮ膜２３がエッチングされることで、反射膜５２の一部が露出する。そして、レジストパターン５４で覆われていた箇所では、保護膜１５（ＴｉＮ膜２３）がエッチングされずに残存する。これにより、周辺領域４では、保護膜１５のパターンがダミー画素電極１４ａ上に形成される。 On the other hand, in the peripheral region 4, as shown in FIG. 12A, a protective film 15 is formed on the reflective pixel electrode. That is, in the opening 54a, the TiN film 23 on the dummy pixel electrode 14a is etched, so that a part of the reflective film 52 is exposed. And in the location covered with the resist pattern 54, the protective film 15 (TiN film 23) remains without being etched. Thereby, in the peripheral region 4, the pattern of the protective film 15 is formed on the dummy pixel electrode 14a.
　この後、反射画素電極１４、ダミー画素電極１４ａ、及び保護膜１５等の上から、最上層の絶縁膜（不図示）を形成する。最上層の絶縁膜は図１、図２に示す端子４７が露出するように形成される。これにより、駆動基板１が完成する。 Thereafter, an uppermost insulating film (not shown) is formed on the reflective pixel electrode 14, the dummy pixel electrode 14a, the protective film 15, and the like. The uppermost insulating film is formed so that the terminal 47 shown in FIGS. 1 and 2 is exposed. Thereby, the drive substrate 1 is completed.
　そして、上記の駆動基板１に配向膜９１を形成する（図２参照）。配向膜９１は、端子４７が露出するように、少なくともシール材６直下と、表示領域３に形成される。対向基板２に、対向電極１０５及び配向膜９２を形成する。ここでは、厚さ０．０８μｍのＩＴＯ膜を対向電極１０５として用いている。ＩＴＯ膜は、スパッタリング法を用いて、形成される。配向膜９１、９２は、例えば、厚さ０．１μｍのＳｉＯ２膜とすることができる。例えば、斜方蒸着法により、厚さ０．１μｍのＳｉＯ２膜を形成することで、配向膜９１、９２を形成してもよい。この配向膜９１、９２によって、液晶７が所定の方向に配向する。また、対向基板２の配向膜９２が形成された面と反対側の面には、反射防止膜を形成してもよい。例えば、厚さ０．３μｍのＮｂ２Ｏ２とＳｉＯ２の積層膜を反射防止膜とすることができる。例えば、真空蒸着法を用いて、ガラス基板の他面側に積層膜を形成することで、反射防止膜を設けることができる。 Then, an alignment film 91 is formed on the drive substrate 1 (see FIG. 2). The alignment film 91 is formed at least directly below the sealing material 6 and in the display region 3 so that the terminals 47 are exposed. A counter electrode 105 and an alignment film 92 are formed on the counter substrate 2. Here, an ITO film having a thickness of 0.08 μm is used as the counter electrode 105. The ITO film is formed using a sputtering method. The alignment films 91 and 92 can be, for example, SiO 2 films having a thickness of 0.1 μm. For example, the alignment films 91 and 92 may be formed by forming a SiO 2 film having a thickness of 0.1 μm by oblique deposition. The alignment films 91 and 92 align the liquid crystal 7 in a predetermined direction. Further, an antireflection film may be formed on the surface of the counter substrate 2 opposite to the surface on which the alignment film 92 is formed. For example, a laminated film of Nb 2 O 2 and SiO 2 having a thickness of 0.3 μm can be used as an antireflection film. For example, the antireflection film can be provided by forming a laminated film on the other surface side of the glass substrate using a vacuum deposition method.
　次に、駆動基板１と対向基板２とを貼り合わせる工程について説明する。貼り合わせに関しては、駆動基板１と対向基板２を１枚ずつ貼り合わせる単個貼り合わせの場合と、ウェハ状態若しくは複数枚のセルが連なったマザー基板とそれに見合ったマザーガラス基板を貼り合わせてその後分断を行って単個のセルを形成する一括貼り合わせがある。本発明はどちらにも適用可能である。ここでは、シリコンウェハとマザーガラス基板とを貼り合わせて、貼り合わせ構造体を形成する。そして、貼り合わせ構造体を切断線に沿って切断することで、それぞれの液晶表示素子を製造する方法を用いている。 Next, the process of bonding the drive substrate 1 and the counter substrate 2 will be described. As for the bonding, a single bonding method in which the driving substrate 1 and the counter substrate 2 are bonded one by one, a mother substrate in which a wafer state or a plurality of cells are connected, and a corresponding mother glass substrate are bonded to each other. There is a batch bonding in which a single cell is formed by dividing. The present invention is applicable to both. Here, a silicon wafer and a mother glass substrate are bonded together to form a bonded structure. And the method of manufacturing each liquid crystal display element is used by cut | disconnecting a bonding structure along a cutting line.
　例えば、８インチのシリコンウェハを用意して、上記の処理を行うことで、駆動基板１を複数備えるシリコンウェハが形成される。シリコンウェハと同等の大きさを有するマザーガラス基板に、対向電極１０５と配向膜９２を形成する。これにより、複数の対向基板２を有するマザーガラス基板が形成される。 For example, by preparing an 8-inch silicon wafer and performing the above processing, a silicon wafer having a plurality of drive substrates 1 is formed. A counter electrode 105 and an alignment film 92 are formed on a mother glass substrate having a size equivalent to that of a silicon wafer. Thereby, a mother glass substrate having a plurality of counter substrates 2 is formed.
　駆動基板１を複数備えたシリコンウェハと、対向基板２を複数備えたマザーガラス基板との少なくとも一方にシール材６を塗布する。ここでは、シール内スペーサ８を含有するシール材６をシリコンウェハ上に塗布する。シール材６は、各セルの表示領域３を囲むように枠状に形成される。シール材６は、保護膜１５の上に塗布されないように形成する。 The sealing material 6 is applied to at least one of a silicon wafer provided with a plurality of drive substrates 1 and a mother glass substrate provided with a plurality of counter substrates 2. Here, the sealing material 6 containing the in-seal spacer 8 is applied on the silicon wafer. The sealing material 6 is formed in a frame shape so as to surround the display area 3 of each cell. The sealing material 6 is formed so as not to be applied on the protective film 15.
　シール材６としては、ＵＶ光と熱によって硬化するエポキシ樹脂系接着剤を使用することができる。シール内スペーサ８は、直径が２～３μｍのＳｉＯ２からなるスペーサボールを用いることができる。また、シール内スペーサ８は接着材料となるシール材６に対する重量比で０．１％程度の割合で混入されている。例えば、貼り合わせ後、延伸したシール材６の幅（シール幅）は７００μｍ～１ｍｍとすることができる。 As the sealing material 6, an epoxy resin adhesive that is cured by UV light and heat can be used. As the spacer 8 in the seal, a spacer ball made of SiO 2 having a diameter of 2 to 3 μm can be used. The spacer 8 in the seal is mixed in a ratio of about 0.1% by weight with respect to the sealing material 6 serving as an adhesive material. For example, the width (seal width) of the expanded sealing material 6 after bonding can be set to 700 μm to 1 mm.
　次にＯＤＦ（One　Drop　Filling）法によって、適量の液晶材料をシリコンウェハ上に滴下する。液晶材料は、シール材６で囲まれた領域にそれぞれ滴下される。そして、駆動基板１と対向基板２とが対向するように位置合わせを行って、シリコンウェハとマザーガラス基板を対向配置する。 Next, an appropriate amount of liquid crystal material is dropped on the silicon wafer by ODF (One Drop Filling) method. The liquid crystal material is dropped on the regions surrounded by the sealing material 6. Then, alignment is performed so that the drive substrate 1 and the counter substrate 2 face each other, and the silicon wafer and the mother glass substrate are disposed to face each other.
　シリコンウェハとマザーガラス基板とが対向配置された状態で、シリコンウェハとマザーガラス基板とが近づくように押圧する。これにより、セルギャップがシール内スペーサ８によって規定される。そして、シリコンウェハを押圧しながら、熱又はＵＶ光、あるいはその両方を用いて、シール材６を硬化する。例えば、マザーガラス基板側から、ＵＶ光を照射して、シール材６を仮硬化する。シール材６の仮硬化後に貼り合わせ装置より、貼り合わせ構造体を取り出して、１２０℃で２時間の熱硬化を行う。これにより、シール材６が硬化して、シリコンウェハとマザーガラス基板とが貼り合わされた貼り合わせ構造体が完成する。ここでは、セルギャップを２～３μｍとするように、シリコンウェハをマザーガラス基板に押し付ける。これにより、シール材６が押し潰されて、シール内スペーサ８がシリコンウェハとマザーガラス基板に当接する。貼り合わせ構造体のシール材６の厚みは、シール内スペーサ８によって規定される。 In a state where the silicon wafer and the mother glass substrate are arranged to face each other, the silicon wafer and the mother glass substrate are pressed so as to approach each other. Thereby, the cell gap is defined by the in-seal spacer 8. Then, while pressing the silicon wafer, the sealing material 6 is cured using heat, UV light, or both. For example, the sealing material 6 is temporarily cured by irradiating UV light from the mother glass substrate side. After the sealing material 6 is temporarily cured, the bonded structure is taken out from the bonding apparatus and thermally cured at 120 ° C. for 2 hours. Thereby, the sealing material 6 is cured, and a bonded structure in which the silicon wafer and the mother glass substrate are bonded to each other is completed. Here, the silicon wafer is pressed against the mother glass substrate so that the cell gap is 2 to 3 μm. As a result, the sealing material 6 is crushed and the in-seal spacer 8 comes into contact with the silicon wafer and the mother glass substrate. The thickness of the sealing material 6 of the bonded structure is defined by the in-seal spacer 8.
　そして、貼り合わせ構造体をＸ方向、及びＹ方向に沿って切断する。具体的には、シリコンウェハを切断した後に、マザーガラス基板を切断する。これにより、貼り合わせ構造体がセルに分離される。分離されたセルの各々が液晶表示素子１００となる。 Then, the bonded structure is cut along the X direction and the Y direction. Specifically, after the silicon wafer is cut, the mother glass substrate is cut. Thereby, the bonded structure is separated into cells. Each of the separated cells becomes a liquid crystal display element 100.
　上記のように製造された液晶表示素子１００に対して、外部の制御装置などをワイヤボンディングや異方性導電膜などによって接続する。すなわち、端子４７に、制御装置を接続する。これにより、画素電極に供給された電圧に応じて、液晶７が駆動する。外部から対向基板２及び液晶７を通過した光は、反射画素電極１４で反射される。液晶７の状態に応じて、反射画素電極１４で反射されて外部に出射する光の光量が変化する。外部制御装置からの制御信号に応じて所望の画像を表示することができる。このような反射型の液晶表示素子は、画像を投影するプロジェクタに好適であり、さらには、自動車などの乗り物に搭載されるヘッドアップディスプレイに利用することが可能である。 An external control device or the like is connected to the liquid crystal display element 100 manufactured as described above by wire bonding or an anisotropic conductive film. That is, the control device is connected to the terminal 47. Thereby, the liquid crystal 7 is driven according to the voltage supplied to the pixel electrode. Light that has passed through the counter substrate 2 and the liquid crystal 7 from the outside is reflected by the reflective pixel electrode 14. Depending on the state of the liquid crystal 7, the amount of light reflected by the reflective pixel electrode 14 and emitted to the outside changes. A desired image can be displayed in response to a control signal from the external control device. Such a reflective liquid crystal display element is suitable for a projector that projects an image, and can also be used for a head-up display mounted on a vehicle such as an automobile.
　（切断線Ｌ１直下での問題点）
　次に、切断工程で生じる問題点について、図１３～図２１を用いて説明する。図１３は、貼り合わせ構造体における切断線を示す平面図である。図１４は、貼り合わせ構造体の構成を示すＸＺ断面図であり、図１５は、ＹＺ断面図である。図１６～図２１は、貼り合わせ構造体を切断して、各セルに分離するための工程断面図である。 (Problem just below the cutting line L1)
Next, problems that occur in the cutting process will be described with reference to FIGS. FIG. 13 is a plan view showing a cutting line in the bonded structure. FIG. 14 is an XZ sectional view showing the configuration of the bonded structure, and FIG. 15 is a YZ sectional view. 16 to 21 are process cross-sectional views for cutting the bonded structure and separating it into cells.
　図１３～図１５に示すように、貼り合わせ構造体１０３は、シリコンウェハ１０１とマザーガラス基板１０２がシール材６によって貼り合わされた構造を有している。シリコンウェハ１０１は、矩形の駆動基板１を複数有しており、マザーガラス基板１０２は矩形の対向基板２を複数有している。シリコンウェハ１０１において、駆動基板１はアレイ状に配列されている。マザーガラス基板１０２において、対向基板２はアレイ状に配列されている。そして、駆動基板１と対向基板２とが位置合わせされた状態で、シリコンウェハ１０１とマザーガラス基板１０２とが対向配置している。図１３では、駆動基板１と対向基板２とが、６個設けられている例を示しているが、貼り合わせ構造体から切り出されるセルの数は特に限定されるものではない。 As shown in FIGS. 13 to 15, the bonded structure 103 has a structure in which the silicon wafer 101 and the mother glass substrate 102 are bonded together by the sealing material 6. The silicon wafer 101 has a plurality of rectangular drive substrates 1, and the mother glass substrate 102 has a plurality of rectangular counter substrates 2. In the silicon wafer 101, the drive substrates 1 are arranged in an array. In the mother glass substrate 102, the opposing substrates 2 are arranged in an array. The silicon wafer 101 and the mother glass substrate 102 are arranged to face each other in a state where the driving substrate 1 and the counter substrate 2 are aligned. Although FIG. 13 shows an example in which six drive substrates 1 and counter substrates 2 are provided, the number of cells cut out from the bonded structure is not particularly limited.
　そして、貼り合わせ構造体１０３を切断線Ｌ１～Ｌ３に沿って切断することで、各セルに分離することができる。よって、複数の液晶表示素子１００を形成することができる。図１３では、Ｙ方向の切断線Ｌ１、Ｌ３と、Ｘ方向の切断線Ｌ２が設けられている。切断線Ｌ２は、シリコンウェハ１０１とマザーガラス基板１０２を切断するラインとなる。換言すると、シリコンウェハ１０１とマザーガラス基板１０２とを切断線Ｌ２に沿ってＸ方向に切断する。シリコンウェハ１０１とマザーガラス基板１０２とで、Ｘ方向の切断線Ｌ２が同じ位置となっている。 Then, the bonded structure 103 can be separated into cells by cutting along the cutting lines L1 to L3. Therefore, a plurality of liquid crystal display elements 100 can be formed. In FIG. 13, cutting lines L1 and L3 in the Y direction and cutting lines L2 in the X direction are provided. The cutting line L2 is a line for cutting the silicon wafer 101 and the mother glass substrate 102. In other words, the silicon wafer 101 and the mother glass substrate 102 are cut in the X direction along the cutting line L2. The silicon wafer 101 and the mother glass substrate 102 have the same cutting line L2 in the X direction.
　切断線Ｌ１は、マザーガラス基板１０２を切断するラインとなる。切断線Ｌ３は、シリコンウェハ１０１を切断するラインとなる。シリコンウェハ１０１とマザーガラス基板１０２とで、Ｙ方向の切断線Ｌ１、Ｌ３が異なる位置となっている。したがって、駆動基板１の一部は、対向基板２からはみ出した構成となる。これは、駆動基板１上に設けられた端子４７を露出するためである。すなわち、駆動基板１の対向基板２の一側端に対応し、対向基板２からはみ出した部分に、端子４７が形成されている。ここでは、複数の端子４７が駆動基板１の端辺に沿って配列されている。すなわち、複数の端子４７は、切断線Ｌ３と平行なＹ方向に沿って配列されている。貼り合わせ構造体１０３をマザーガラス基板１０２側から見た平面視において、切断線Ｌ１と切断線Ｌ３との間に、端子４７が配置されるよう、駆動基板１と対向基板２の位置合わせがなされる。 The cutting line L1 is a line for cutting the mother glass substrate 102. The cutting line L3 is a line for cutting the silicon wafer 101. The silicon wafer 101 and the mother glass substrate 102 have different Y-direction cutting lines L1 and L3. Therefore, a part of the drive substrate 1 is configured to protrude from the counter substrate 2. This is because the terminal 47 provided on the driving substrate 1 is exposed. That is, the terminal 47 is formed in a portion corresponding to one side end of the counter substrate 2 of the drive substrate 1 and protruding from the counter substrate 2. Here, a plurality of terminals 47 are arranged along the edge of the drive substrate 1. That is, the plurality of terminals 47 are arranged along the Y direction parallel to the cutting line L3. The driving substrate 1 and the counter substrate 2 are aligned so that the terminal 47 is disposed between the cutting line L1 and the cutting line L3 in a plan view of the bonded structure 103 viewed from the mother glass substrate 102 side. The
　ここで、シール材６でシリコンウェハ１０１とマザーガラス基板１０２とを貼り合わせた後の、切断工程について説明する。シリコンウェハ１０１は、ダイシングブレードによって切断される。一方、マザーガラス基板１０２は、スクライブブレークによって切断される。そのため、図１６、図１７に示すように、貼り合わせ構造体１０３のマザーガラス基板１０２は、ガラス分断溝２８が形成される。なお、ガラス分断溝２８は、切断線Ｌ１と切断線Ｌ２と切断線Ｌ３に沿って形成される。また、切断線Ｌ２、Ｌ３に沿ってシリコンウェハ１０１の表面には表面分断溝３０、裏面には裏面分断溝２９が形成されている。 Here, the cutting process after bonding the silicon wafer 101 and the mother glass substrate 102 with the sealing material 6 will be described. The silicon wafer 101 is cut by a dicing blade. On the other hand, the mother glass substrate 102 is cut by a scribe break. Therefore, as shown in FIGS. 16 and 17, a glass dividing groove 28 is formed in the mother glass substrate 102 of the bonded structure 103. The glass dividing groove 28 is formed along the cutting line L1, the cutting line L2, and the cutting line L3. Further, along the cutting lines L2 and L3, a front surface dividing groove 30 is formed on the surface of the silicon wafer 101, and a rear surface dividing groove 29 is formed on the back surface.
　表面分断溝３０は、貼り合わせ前に形成し、裏面分断溝２９は、貼り合わせ後に形成する。ダイシング装置のダイシングブレードによって、シリコンウェハ１０１をハーフカットすることで、裏面分断溝２９、及び表面分断溝３０を形成することができる。ガラス分断溝２８は、貼り合わせ後に形成する。例えば、スクライバで、マザーガラス基板１０２を罫書くことで、ガラス分断溝２８を形成する。 The front surface dividing groove 30 is formed before bonding, and the back surface dividing groove 29 is formed after bonding. The rear surface dividing groove 29 and the front surface dividing groove 30 can be formed by half-cutting the silicon wafer 101 with a dicing blade of a dicing apparatus. The glass dividing groove 28 is formed after bonding. For example, the glass dividing groove 28 is formed by marking the mother glass substrate 102 with a scriber.
　そして、ガラス分断溝２８、裏面分断溝２９、及び表面分断溝３０を有する貼り合わせ構造体１０３を粘着シート３２上に載置する（図１８参照）。なお、粘着シート３２は、ブレーカ装置のステージ上に設けられている。貼り合わせ構造体１０３のマザーガラス基板１０２に粘着シート３２が貼り合わされ、貼り合わせ構造体１０３が固定される。 And the bonding structure 103 which has the glass parting groove | channel 28, the back surface parting groove | channel 29, and the surface parting groove | channel 30 is mounted on the adhesive sheet 32 (refer FIG. 18). The adhesive sheet 32 is provided on the stage of the breaker device. The adhesive sheet 32 is bonded to the mother glass substrate 102 of the bonded structure 103, and the bonded structure 103 is fixed.
　スクライブブレークするためのブレーカスキージ３１を、切断線Ｌ１、又は切断線Ｌ３上に配置する。そして、ブレーカスキージ３１で粘着シート３２上に固定された貼り合わせ構造体１０３を上から叩く。すなわち、シリコンウェハ１０１の上からブレーカスキージ３１を押し込んでいく。こうすることで、ガラス分断溝２８に基づいてマザーガラス基板１０２が切断される。 The breaker squeegee 31 for scribe break is arranged on the cutting line L1 or the cutting line L3. Then, the bonded structure 103 fixed on the adhesive sheet 32 with the breaker squeegee 31 is hit from above. That is, the breaker squeegee 31 is pushed from above the silicon wafer 101. By doing so, the mother glass substrate 102 is cut based on the glass dividing grooves 28.
　図１８に示すように、ブレーカスキージ３１が貼り合わせ構造体１０３に対して傾いていると、貼り合わせ構造体１０３に対して局所的な力が加わる可能性がある。あるいは、図１９に示すように、粘着シート３２と貼り合わせ構造体１０３との間に、異物６１を挟み込んだ場合、貼り合わせ構造体１０３に対して局所的なダメージが加わる可能性がある。図２０に示すように、一方の辺を分断した際に発生する基板の小さな破片３６が他方の分断線上に残存してしまうおそれがある。すると、図２１に示すように他方の辺を分断する際に破片３６が駆動回路に損傷を与え素子の動作不良につながる。 As shown in FIG. 18, if the breaker squeegee 31 is inclined with respect to the bonded structure 103, a local force may be applied to the bonded structure 103. Alternatively, as shown in FIG. 19, when the foreign material 61 is sandwiched between the adhesive sheet 32 and the bonded structure 103, local damage may be applied to the bonded structure 103. As shown in FIG. 20, there is a possibility that small fragments 36 of the substrate generated when one side is divided remain on the other parting line. Then, as shown in FIG. 21, when the other side is divided, the fragment 36 damages the drive circuit, leading to malfunction of the element.
　このような場合、層間絶縁膜１３が破壊され、その下層に位置する第１配線層１０、第２配線層１１の短絡や断線を引き起こしてしまい、液晶表示素子１００の動作不良につながる。したがって、歩留まりが劣化して、生産性が低下してしまう恐れがある。 In such a case, the interlayer insulating film 13 is destroyed, causing a short circuit or disconnection of the first wiring layer 10 and the second wiring layer 11 located below the interlayer insulating film 13, leading to a malfunction of the liquid crystal display element 100. Therefore, there is a possibility that the yield is deteriorated and the productivity is lowered.
　（切断線直下の保護膜１５）
　そこで、本実施の形態では、切断線直下に保護膜１５を設けている。切断線直下に保護膜１５を配置した構成について説明する。図２２は、保護膜１５が設けられた領域を説明するための図であり、液晶表示素子１００の平面図である。図２２に示すように、対向基板２の側端面が図１３、図１４で示した切断線Ｌ１に対応している。 (Protective film 15 just below the cutting line)
Therefore, in the present embodiment, the protective film 15 is provided immediately below the cutting line. A configuration in which the protective film 15 is disposed immediately below the cutting line will be described. FIG. 22 is a diagram for explaining a region where the protective film 15 is provided, and is a plan view of the liquid crystal display element 100. As shown in FIG. 22, the side end surface of the counter substrate 2 corresponds to the cutting line L1 shown in FIGS.
　周辺領域４の一部には、シフトレジスタなどの回路が形成されている。ここで、周辺領域４において、回路が形成された領域を周辺回路領域とする。また、対向基板２の一側端面（前述した切断線Ｌ１に沿って切断された端面）の直下の領域には、周辺回路領域の回路を保護するための保護膜１５が形成されている。すなわち、駆動基板１におけるシール材６と端子４７との間には、保護膜１５が形成されている。保護膜１５は、駆動基板１において対向基板２の一側端面に対応する位置に帯状に形成されている。保護膜１５は、Ｙ方向に沿って形成されている。保護膜１５は、反射画素電極１４、第２配線層１１、第１配線層１０よりも硬いＴｉＮを用いて形成されている。したがって、下層に設けられたトランジスタ１２を有する周辺回路領域を保護することができる。なお、保護膜１５としては、ＴｉＮ膜２３に限らず、タングステン膜やタングステン合金膜などを用いることができる。 A circuit such as a shift register is formed in a part of the peripheral area 4. Here, in the peripheral region 4, a region where a circuit is formed is defined as a peripheral circuit region. In addition, a protective film 15 for protecting the circuit in the peripheral circuit region is formed in a region immediately below one side end surface of the counter substrate 2 (end surface cut along the above-described cutting line L1). That is, the protective film 15 is formed between the sealing material 6 and the terminal 47 in the driving substrate 1. The protective film 15 is formed in a strip shape at a position corresponding to one end face of the counter substrate 2 in the drive substrate 1. The protective film 15 is formed along the Y direction. The protective film 15 is formed using TiN that is harder than the reflective pixel electrode 14, the second wiring layer 11, and the first wiring layer 10. Therefore, the peripheral circuit region having the transistor 12 provided in the lower layer can be protected. The protective film 15 is not limited to the TiN film 23, and a tungsten film, a tungsten alloy film, or the like can be used.
　図２３は、保護膜１５の周辺の構成を示す側面断面図である。図２３に示すように、駆動基板１の切断線Ｌ１に沿って形成された対向基板２の一側端面に対応する領域（以下、切断線Ｌ１の直下と呼ぶこともある）には、保護膜１５が設けられている。すなわち、シール材６と端子４７の間の周辺回路領域５８が保護膜１５によって覆われている。 FIG. 23 is a side sectional view showing a configuration around the protective film 15. As shown in FIG. 23, a protective film is formed in a region corresponding to one end surface of the counter substrate 2 formed along the cutting line L1 of the driving substrate 1 (hereinafter, also referred to as immediately below the cutting line L1). 15 is provided. That is, the peripheral circuit region 58 between the sealing material 6 and the terminal 47 is covered with the protective film 15.
　このように切断線Ｌ１の直下に対応する領域には、駆動基板１上に保護膜１５が設けられている。保護膜１５が形成された領域に対応する切断線Ｌ１に沿って、マザーガラス基板１０２を切断する。こうすることで、切断線Ｌ１の近傍に局所的な力やダメージが発生した場合でも、保護膜１５が周辺回路領域５８の周辺回路を保護する。すなわち、トランジスタ１２の破損、第１配線層１０、第２配線層１１の断線、短絡などを防ぐことができ、歩留まりを向上することができる。反射膜５２の成膜工程の後に保護膜材料を形成するため反射膜５２より下層に影響が及ぶのを防ぐことができる。 Thus, the protective film 15 is provided on the drive substrate 1 in the region corresponding to the region immediately below the cutting line L1. The mother glass substrate 102 is cut along a cutting line L1 corresponding to the region where the protective film 15 is formed. By doing so, the protective film 15 protects the peripheral circuit in the peripheral circuit region 58 even when a local force or damage occurs in the vicinity of the cutting line L1. That is, breakage of the transistor 12, disconnection of the first wiring layer 10 and the second wiring layer 11, a short circuit, and the like can be prevented, and yield can be improved. Since the protective film material is formed after the step of forming the reflective film 52, the lower layer than the reflective film 52 can be prevented from being affected.
　図２４は、駆動基板１の保護膜１５が形成された箇所の側面断面図である。切断工程において、対向基板２が破損して、破片３６が飛散した場合でも、保護膜１５が周辺回路を保護する。この場合、保護膜１５を対向基板２よりも硬い材質とすることが好ましい。すなわち、保護膜１５は、対向基板２となるガラス材料よりも硬度の大きい材料によって形成する。切断工程において、飛散した対向基板２の破片３６よりも保護膜１５が硬いため、破片３６が保護膜１５を貫通するのをより防ぐことができる。これにより、歩留まりを改善することができ、生産性を向上することができる。なお、他の切断線Ｌ２、Ｌ３に対応する領域にも、保護膜１５を形成するようにしてもよい。 FIG. 24 is a side cross-sectional view of a portion of the drive substrate 1 where the protective film 15 is formed. In the cutting process, the protective film 15 protects the peripheral circuit even when the counter substrate 2 is damaged and the fragments 36 are scattered. In this case, the protective film 15 is preferably made of a material harder than the counter substrate 2. That is, the protective film 15 is formed of a material having a hardness higher than that of the glass material used as the counter substrate 2. In the cutting step, the protective film 15 is harder than the scattered pieces 36 of the counter substrate 2, so that the broken pieces 36 can be further prevented from penetrating the protective film 15. Thereby, a yield can be improved and productivity can be improved. Note that the protective film 15 may also be formed in regions corresponding to the other cutting lines L2 and L3.
　次に、切断線Ｌ１直下の保護膜１５の寸法例について説明する。図２５に示すように、切断線Ｌ１の直下の領域に保護膜１５が形成されている。ここで、保護膜１５の周辺を拡大した断面図を図２６に示す。 Next, a dimension example of the protective film 15 immediately below the cutting line L1 will be described. As shown in FIG. 25, a protective film 15 is formed in a region immediately below the cutting line L1. Here, FIG. 26 shows an enlarged cross-sectional view of the periphery of the protective film 15.
　図２６に示すように、切断線Ｌ１よりもシール材６側の保護膜１５の幅を１００μｍとし、切断線Ｌ１よりも端子４７側の保護膜１５の幅を４００μｍとする。すなわち、保護膜１５の全体の幅を５００μｍとして、切断線Ｌ１に対して非対称に配置する。このようにすることで、切断線Ｌ１直下の回路の破損をより防ぐことができる。もちろん、回路を形成する領域の寸法や、切断工程における条件に応じて、切断線Ｌ１直下の保護膜１５の幅を変更してもよい。保護膜１５に幅を持たせることにより、分断時に通常ガラスが直撃する領域だけでなく、スクライブのときにクラックが垂直ではなく横方向にずれて直撃する場所がずれた場合でも、駆動基板１に形成されたトランジスタ１２等を保護することができる。 26, the width of the protective film 15 on the sealing material 6 side from the cutting line L1 is set to 100 μm, and the width of the protective film 15 on the terminal 47 side from the cutting line L1 is set to 400 μm. That is, the entire width of the protective film 15 is set to 500 μm, and the protective film 15 is disposed asymmetrically with respect to the cutting line L1. By doing in this way, damage to the circuit right below the cutting line L1 can be prevented more. Of course, the width of the protective film 15 immediately below the cutting line L1 may be changed according to the dimensions of the region for forming the circuit and the conditions in the cutting process. By providing the protective film 15 with a width, not only in the region where the normal glass hits directly at the time of cutting, but also in the case where the location of the direct hit is shifted in the lateral direction instead of the vertical when the scribe is done, The formed transistor 12 and the like can be protected.
　また、切断線Ｌ１直下の保護膜１５は、切断線Ｌ１の全体に対応するように形成されていなくてもよい。すなわち、下層にトランジスタ１２や配線などが形成されていて、保護が必要な領域のみに保護膜１５を形成するようにしてもよい。トランジスタ１２や配線が形成されていない領域では、保護膜１５を形成しなくてもよい。 Further, the protective film 15 immediately below the cutting line L1 may not be formed so as to correspond to the entire cutting line L1. That is, the transistor 12 and the wiring may be formed in the lower layer, and the protective film 15 may be formed only in a region that needs to be protected. In the region where the transistor 12 and the wiring are not formed, the protective film 15 may not be formed.
　なお、保護膜１５は、帯状に連続して形成されていなくてもよい。すなわち、複数の領域に分けて保護膜１５を形成してもよい。この場合、隣接する保護膜１５のパターンは、飛散する破片３６よりも十分小さくする。こうすることで、切断工程で対向基板２の破片３６が切断線Ｌ１の下層の周辺回路を破損するのを防ぐことができる。また、切断線Ｌ１直下の保護膜１５を分断することで、切断線Ｌ１直下の保護膜１５を通じた短絡を防ぐことができる。 Note that the protective film 15 may not be continuously formed in a belt shape. That is, the protective film 15 may be formed in a plurality of regions. In this case, the pattern of the adjacent protective film 15 is made sufficiently smaller than the scattered pieces 36. By doing so, it is possible to prevent the fragments 36 of the counter substrate 2 from damaging the peripheral circuits below the cutting line L1 in the cutting process. Further, by dividing the protective film 15 immediately below the cutting line L1, it is possible to prevent a short circuit through the protective film 15 immediately below the cutting line L1.
　以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は上記実施の形態に限られたものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
　１　駆動基板
　２　対向基板
　３　表示領域
　３ａ　画素
　４　周辺領域
　６　シール材
　７　液晶
　１２　トランジスタ
　１３　層間絶縁膜
　１４　反射画素電極
　１４ａ　ダミー画素電極
　１５　保護膜
　４７　端子 DESCRIPTION OF SYMBOLS 1 Drive substrate 2 Opposite substrate 3 Display area 3a Pixel 4 Peripheral area 6 Sealing material 7 Liquid crystal 12 Transistor 13 Interlayer insulating film 14 Reflective pixel electrode 14a Dummy pixel electrode 15 Protective film 47 Terminal

Claims (2)

  1. 　トランジスタを有する駆動基板と、
    　前記駆動基板と対向配置された対向基板と、
    　表示領域を囲むように配置され、前記駆動基板と前記対向基板とを貼り合わせるシール材と、を備えた表示素子の製造方法であって、
    　前記駆動基板の上に画素電極材料を用いて第１の膜を形成するステップと、
    　前記第１の膜上に保護膜材料を用いて前記対向基板より硬い保護膜を形成するステップと、
    　前記第１の膜及び前記保護膜をパターニングすることで、前記表示領域において前記トランジスタと接続される画素電極を形成し、前記表示領域の外側の周辺領域においてダミー画素電極を形成するステップと、
    　前記周辺領域において前記ダミー画素電極の上の前記保護膜が残存するよう、前記表示領域において前記画素電極の上の前記保護膜を除去するステップと、
    　前記駆動基板と前記対向基板との間に前記シール材を配置した状態で、前記駆動基板と前記対向基板を貼り合わせるステップと、
    　前記保護膜が形成された領域に対応する切断線に沿って前記対向基板を切断するステップと、を有する表示素子の製造方法。     A drive substrate having transistors;
    A counter substrate disposed opposite to the drive substrate;
    A sealing element that is disposed so as to surround a display region, and includes a sealing material that bonds the driving substrate and the counter substrate;
    Forming a first film on the driving substrate using a pixel electrode material;
    Forming a protective film harder than the counter substrate using a protective film material on the first film;
    Patterning the first film and the protective film to form a pixel electrode connected to the transistor in the display region, and forming a dummy pixel electrode in a peripheral region outside the display region;
    Removing the protective film on the pixel electrode in the display area so that the protective film on the dummy pixel electrode remains in the peripheral area;
    Bonding the drive substrate and the counter substrate in a state where the sealant is disposed between the drive substrate and the counter substrate;
    Cutting the counter substrate along a cutting line corresponding to a region where the protective film is formed.
  2. 　トランジスタを有する駆動基板と、
    　前記駆動基板と対向配置された対向基板と、
    　表示領域を囲むように配置され、前記駆動基板と前記対向基板とを貼り合わせるシール材と、
    　前記対向基板の少なくとも一側端面の直下に対応する、前記駆動基板の前記表示領域より外側の周辺領域に形成された、前記対向基板よりも硬い保護膜と、
    　前記表示領域内に形成され、前記トランジスタと接続される画素電極と、
    　前記保護膜の下に形成され、前記画素電極と同じ材料で形成されたダミー画素電極と、
    　を備えた表示素子。     A drive substrate having transistors;
    A counter substrate disposed opposite to the drive substrate;
    A sealing material disposed so as to surround a display region, and bonding the drive substrate and the counter substrate;
    A protective film harder than the counter substrate, which is formed in a peripheral region outside the display region of the drive substrate, corresponding to a position directly below at least one side end surface of the counter substrate;
    A pixel electrode formed in the display region and connected to the transistor;
    A dummy pixel electrode formed under the protective film and made of the same material as the pixel electrode;
    A display device comprising:
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