WO2014077355A1 - Dispositif de conversion de puissance - Google Patents

Dispositif de conversion de puissance Download PDF

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Publication number
WO2014077355A1
WO2014077355A1 PCT/JP2013/080879 JP2013080879W WO2014077355A1 WO 2014077355 A1 WO2014077355 A1 WO 2014077355A1 JP 2013080879 W JP2013080879 W JP 2013080879W WO 2014077355 A1 WO2014077355 A1 WO 2014077355A1
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WIPO (PCT)
Prior art keywords
conversion ratio
value
power
storage means
voltage
Prior art date
Application number
PCT/JP2013/080879
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English (en)
Japanese (ja)
Inventor
明史 小杉
肇 池田
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太陽誘電株式会社
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Application filed by 太陽誘電株式会社 filed Critical 太陽誘電株式会社
Priority to JP2014547051A priority Critical patent/JP6215224B2/ja
Publication of WO2014077355A1 publication Critical patent/WO2014077355A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/66—Regulating electric power
    • G05F1/67—Regulating electric power to the maximum power available from a generator, e.g. from solar cell
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H02J3/381—Dispersed generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2300/00—Systems for supplying or distributing electric power characterised by decentralized, dispersed, or local generation
    • H02J2300/20—The dispersed energy generation being of renewable origin
    • H02J2300/22—The renewable source being solar energy
    • H02J2300/24—The renewable source being solar energy of photovoltaic origin
    • H02J2300/26—The renewable source being solar energy of photovoltaic origin involving maximum power point tracking control for photovoltaic sources
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Definitions

  • the present invention relates to a power conversion device that is connected to a power source having a maximum value in output voltage power characteristics, such as a solar cell or a solar power generation panel, a wind power generator, or a fuel cell, and tracks to operate at the maximum output power point.
  • a power source having a maximum value in output voltage power characteristics, such as a solar cell or a solar power generation panel, a wind power generator, or a fuel cell, and tracks to operate at the maximum output power point.
  • Patent Document 1 a maximum power switching converter that switches a switching operation to a step-up operation, a step-down operation, or a direct connection circuit according to conditions of an input voltage and an output voltage is disclosed.
  • the step-up / step-down circuit When the step-up / step-down circuit is used in the power conversion device in this way, it operates as a booster circuit when the amount of solar radiation is large and the amount of generated power is large, and operates as a step-down circuit when the amount of solar radiation is small and the amount of power generation is small.
  • Patent Document 2 an automatic voltage regulator that increases or decreases the voltage value of the output side voltage in accordance with the voltage value of the input side voltage (output voltage of the solar cell) of the power converter.
  • the deviation between the output voltage (operating voltage) of the solar cell and the target voltage (maximum output power point voltage) of the solar cell is input to the input side of the automatic voltage regulator, and the output of the automatic voltage regulator corresponding to this is input.
  • a system for controlling the output of the inverter is configured.
  • the gain of the automatic voltage regulator is changed according to the amount of solar radiation (solar radiation conditions) to increase the follow-up speed to the maximum output power point.
  • the tracking speed is increased by using an approximate function related to the maximum output power point.
  • Patent Document 3 requires a separate data memory for storing the approximate function, which does not lead to an inexpensive product design.
  • any one photovoltaic power generation panel in the same string is connected to the cloud. Shadows and leaves of leaves appear on the panel, reducing the amount of solar radiation. If it does so, the electric current value of the solar power generation panel in which the other solar radiation amount is not falling will also fall by the electric current value of the solar power generation panel in which the solar radiation amount fell. For this reason, the electric power generation amount of the solar power generation panel in which these other solar radiation amounts have not decreased will also decrease. In the example of FIG. 22, when the amount of solar radiation of any one of the solar panels connected in series decreases and the power generation decreases to 50%, the power generation of other solar panels connected in series with this The amount is also reduced to 50%. *
  • an object of the present invention is to provide a power conversion device that includes a control unit that operates according to a low-capacity program and can handle both step-up and step-down.
  • a further object of the present invention is to provide a power converter that can follow the maximum power point more quickly than in the past.
  • the present invention inputs, as an input voltage, a voltage output from a power generation source having a maximum power point in a characteristic curve representing the relationship between output voltage and output power, and sets a voltage equal to the input voltage.
  • a step-up / step-down type that switches between an output pass-through mode, a step-down mode that outputs a voltage lower than the input voltage, and a step-up mode that outputs a voltage higher than the input voltage based on a control signal and that drives the switching element on and off
  • a DC / DC converter circuit ; a voltage detection circuit for detecting a voltage input from the power source to the step-up / step-down DC / DC converter circuit; and a current input from the power source to the step-up / step-down DC / DC converter circuit.
  • a current detection circuit to detect, a voltage value detected by the voltage detection circuit, and a current detected by the current detection circuit
  • the power value calculating means for calculating the power value at predetermined time intervals based on the power value, the conversion ratio is set based on the power value calculated by the power value calculating means, and the previously set conversion ratio and the current conversion ratio are set.
  • Conversion ratio setting means for setting, as a mode selection conversion ratio, a value obtained by increasing or decreasing the value of the conversion ratio set this time, based on the comparison result between the power value and the change in power value, and the mode selection conversion ratio
  • the conversion ratio for mode selection is a value within a high frequency range adjacent to the mid frequency range and larger than the mid frequency range
  • the DC / DC converter circuit is operated in the boost mode.
  • a power conversion device including a control means for outputting a control signal is proposed. *
  • the conversion ratio setting unit stores a first power value storage unit that stores a previously calculated power value and a power value calculated this time.
  • Second power value storage means for storing, first conversion ratio storage means for storing the value of the conversion ratio calculated last time, second conversion ratio storage means for storing the value of the conversion ratio calculated this time, 1 power value storage means, the second power value storage means, the first conversion ratio storage means, an initialization means for setting an initial value in the second conversion ratio storage means, and the first and second conversions Based on the value of the conversion ratio stored in the ratio storage means and the power value stored in the first and second power value storage means, the power value stored in the second power value storage means is Less than the power value stored in the first power value storage means And when the conversion ratio value stored in the second conversion ratio storage means is equal to or greater than the conversion ratio value stored in the first conversion ratio storage means, or stored in the second power value storage means.
  • the power value is greater than or equal to the power value stored in the first power value storage means, and the conversion ratio value stored in the second conversion ratio storage means is stored in the first conversion ratio storage means.
  • a value obtained by subtracting a predetermined adjustment value from the value of the conversion ratio stored in the second conversion ratio storage means is calculated this time and a new mode selection conversion ratio. Based on the first conversion ratio calculating means, the value of the conversion ratio stored in the first and second conversion ratio storage means, and the power value stored in the first and second power value storage means.
  • the power value stored in the second power value storage means is The conversion ratio value smaller than the power value stored in the first power value storage means and stored in the second conversion ratio storage means is equal to the conversion ratio stored in the first conversion ratio storage means. Or when the power value stored in the second power value storage means is greater than or equal to the power value stored in the first power value storage means and stored in the second conversion ratio storage means. When the conversion ratio value is equal to or greater than the conversion ratio value stored in the first conversion ratio storage means, a predetermined adjustment value is added to the conversion ratio value stored in the second conversion ratio storage means. And a second conversion ratio calculation means that uses the added value as a conversion ratio calculated this time and a new mode selection conversion ratio, and the control means includes the first conversion ratio calculation means or the second conversion ratio calculation.
  • the conversion ratio for mode selection calculated by the means Based on this, when the conversion ratio for mode selection is a value within a predetermined mid-range including the initial value stored in the first change ratio storage means, the DC / DC converter circuit is operated in the pass-through mode and The control signal for turning on and off the switching element based on the switching element on-time calculated using the mode selection conversion ratio is output, and the calculated mode selection conversion ratio is adjacent to the mid-range and the mid-range
  • the DC / DC converter circuit is operated in the step-up mode when the value is in a high frequency range larger than the range, and the switching element is turned on / off based on the switching element on-time calculated using the mode selection conversion ratio.
  • the control signal to be output, the calculated mode selection conversion ratio is adjacent to the mid-range and more than the mid-range.
  • a power converter having means for outputting a signal is proposed.
  • the present invention in the power converter, divides the input voltage range into a plurality of regions, with the voltage range including the maximum power point in the characteristic curve as a reference voltage region, and The adjustment value is set for each region, and the adjustment value in each region is separated from the reference voltage region with the adjustment value when the voltage detected by the voltage detection circuit is in the reference voltage region as a reference value. Therefore, a power conversion device set to a large value is proposed.
  • the DC / DC converter circuit is connected to an inductor for storing energy, an input terminal of the inductor, and an output of the power source.
  • a first switching element connected between the positive input terminal, a second switching element connected between the input terminal of the inductor and a negative input terminal connected to the output of the power source, and And a third switching element connected between the output terminal and the positive output terminal and a fourth switching element connected between the output terminal and the negative output terminal of the inductor.
  • the initial value of the mode selection conversion ratio (ConvRatio) is set to 100, the period is T1, and the first switching element is represented by the time represented by the equation (1).
  • the first switching element is turned on for 1 and a predetermined interval td1 is opened before and after the first switching element is turned off, and the second switching element is turned on for a time t1a expressed by equation (2).
  • T1 T1 ⁇ ConvRatio / 100
  • t1a T1 ⁇ t1 ⁇ td1 ⁇ 2
  • the initial value of the mode selection conversion ratio (ConvRatio) is set to 100 and the period is set to T1.
  • the third switching element is turned on for a time t2a expressed by equation (3), and a predetermined interval td2 is opened before and after the third switching element is turned off, and the fourth switching element is represented by equation (4).
  • T2a T1 ⁇ t2 ⁇ td2 ⁇ 2
  • t2 T1 ⁇ (ConvRatio ⁇ 100) / ConvRatio (4)
  • a power converter is proposed.
  • the present invention inputs, as an input voltage, a voltage output from a power generation source having a maximum power point in a characteristic curve representing the relationship between output voltage and output power, and sets a voltage equal to the input voltage.
  • a step-up DC / DC converter circuit that switches between a pass-through mode for outputting and a step-up mode for outputting a voltage higher than the input voltage based on a control signal and that drives a switching element on and off, and the step-up DC from the power source
  • a voltage detection circuit for detecting a voltage input to the DC / DC converter circuit, and a current detection circuit for detecting a current input from the power generation source to the step-up DC / DC converter circuit.
  • a power value calculation means for calculating a power value at a predetermined time interval based on the voltage value detected by the voltage detection circuit and the current value detected by the current detection circuit, and the power value calculated by the power value calculation means A value obtained by setting the conversion ratio based on the above and a value obtained by increasing or decreasing the value of the conversion ratio set this time based on the comparison result between the conversion ratio set last time and the conversion ratio set this time and the change in the power value.
  • Conversion ratio setting means for setting the mode selection conversion ratio, and the mode selection conversion ratio is used to determine the on / off time of the switching element, and the mode selection conversion ratio is within a predetermined mid-range.
  • a control signal for operating the DC / DC converter circuit in the pass-through mode is output, and the mode selection conversion ratio is adjacent to the mid-range and the mid-range
  • a DC / AC inverter circuit for converting the input voltage into an AC voltage, a voltage detection circuit for detecting a voltage output from the DC / AC inverter circuit, and a current output from the DC / AC inverter circuit A power conversion device including a current detection circuit is proposed. *
  • the conversion ratio setting unit stores a first power value storage unit that stores a previously calculated power value and a power value calculated this time.
  • Second power value storage means for storing, first conversion ratio storage means for storing the value of the conversion ratio calculated last time, second conversion ratio storage means for storing the value of the conversion ratio calculated this time, 1 power value storage means, second power value storage means, first conversion ratio storage means, and initialization means for setting an initial value in the second conversion ratio storage means.
  • the second power value storage is based on the conversion ratio value stored in the first and second conversion ratio storage means and the power value stored in the first and second power value storage means.
  • the power value stored in the means is smaller than the power value stored in the first power value storage means, and the value of the conversion ratio stored in the second conversion ratio storage means is the first conversion ratio storage.
  • the power value stored in the second power value storage means is greater than or equal to the power value stored in the first power value storage means and the second
  • the conversion ratio stored in the second conversion ratio storage means The value calculated by subtracting the predetermined adjustment value from the value of A first conversion ratio calculation means for setting a ratio and a new conversion ratio; values of conversion ratios stored in the first and second conversion ratio storage means; and stored in the first and second power value storage means.
  • the power value stored in the second power value storage means is smaller than the power value stored in the first power value storage means and stored in the second conversion ratio storage means.
  • the value of the conversion ratio being used is smaller than the value of the conversion ratio stored in the first conversion ratio storage means, or the power value stored in the second power value storage means is the first power value storage.
  • the conversion ratio value stored in the second conversion ratio storage means is greater than or equal to the conversion ratio value stored in the first conversion ratio storage means.
  • the value of the conversion ratio stored in the second conversion ratio storage means And a second conversion ratio calculation means that uses a value obtained by adding a predetermined adjustment value as a conversion ratio calculated this time and a new conversion ratio, and the control means includes the first conversion ratio calculation means or the second conversion ratio.
  • the DC Based on the conversion ratio for mode selection calculated by the ratio calculation means, the DC when the conversion ratio for mode selection is a value within a predetermined mid-range including the initial value stored in the first change ratio storage means.
  • the DC / DC converter circuit is operated in the boost mode when the conversion ratio is adjacent to the mid-range and is in a high-range range that is larger than the mid-range.
  • the present invention in the power converter, divides the input voltage range into a plurality of regions, with the voltage range including the maximum power point in the characteristic curve as a reference voltage region, and The adjustment value is set for each region, and the adjustment value in each region is separated from the reference voltage region with the adjustment value when the voltage detected by the voltage detection circuit is in the reference voltage region as a reference value. Therefore, a power conversion device set to a large value is proposed.
  • the operation mode of the DC / DC converter circuit can be switched to step-up or step-down based on the mode selection conversion ratio, and the on-time of the switching element can be calculated by the mode selection conversion ratio. Since the control means that operates according to the low-capacity program can be configured, the apparatus configuration can be simplified. Thereby, manufacturing cost can be reduced compared with the past. *
  • the adjustment value when the voltage detected by the voltage detection circuit is in the reference voltage region is set as a reference value, and the adjustment value in each region is set to a value that increases as the distance from the reference voltage region increases. Since the ON time of the switching element is calculated using the mode selection conversion ratio adjusted by the adjustment value, it is possible to follow the maximum power point more quickly than in the past.
  • the figure which shows the output voltage power characteristic of the power source which connects the power converter device of 1st Embodiment of this invention. Control flowchart for explaining the operation in the first embodiment of the present invention. Control flowchart for explaining the operation in the first embodiment of the present invention. Control flowchart for explaining the operation in the first embodiment of the present invention. Control flowchart for explaining the operation in the first embodiment of the present invention. Control flowchart for explaining the operation in the first embodiment of the present invention.
  • FIG. 4 is a waveform diagram for explaining an on / off control digital signal of a switching element during a step-down mode operation according to the first embodiment of the present invention.
  • FIG. 4 is a waveform diagram for explaining an on / off control digital signal of a switching element during a step-down mode operation according to the first embodiment of the present invention. The figure explaining the PWM width calculation at the time of the pressure
  • FIG. 4 is a waveform diagram for explaining an on / off control digital signal of the switching element during the boost mode operation according to the first embodiment of the present invention.
  • FIG. 4 is a waveform diagram for explaining an on / off control digital signal of a switching element during a boost mode operation in the first embodiment of the present invention.
  • Control flowchart for explaining the operation of the second embodiment of the present invention Control flowchart for explaining the operation of the second embodiment of the present invention. Control flowchart for explaining the operation of the second embodiment of the present invention. Control flowchart for explaining the operation of the second embodiment of the present invention. Control flowchart for explaining the operation of the second embodiment of the present invention.
  • the figure explaining the electric power generation amount of the solar power generation device when the photovoltaic power generation panel of a prior art example is connected in series The circuit diagram which shows the power converter device in 3rd Embodiment of this invention.
  • FIG. 25 is an enlarged view of the DC / DC converter unit 20 of FIG. FIG.
  • Control flowchart for explaining the operation of the third embodiment of the present invention Control flowchart for explaining the operation of the third embodiment of the present invention. Control flowchart for explaining the operation of the third embodiment of the present invention. Control flowchart for explaining the operation of the third embodiment of the present invention. Control flowchart for explaining the operation of the third embodiment of the present invention. Control flowchart for explaining the operation of the third embodiment of the present invention.
  • Waveform diagram illustrating an on / off control digital signal of the switching element during the boost mode operation in the third embodiment of the present invention The figure explaining the PWM width calculation at the time of the pressure
  • the circuit diagram which shows the power converter device in 5th Embodiment of this invention. 45 is an enlarged view of the DC / DC converter unit 20 of FIG. 45 is an enlarged view of the DC / AC inverter unit 30 of FIG.
  • FIG. 1 is a circuit diagram showing a power conversion device according to the first embodiment of the present invention.
  • reference numeral 10 denotes a power converter, which comprises a DC / DC converter circuit 11, a drive circuit 12, a control circuit 13, an input current detection circuit 14, an input voltage detection circuit 15, an output current detection circuit 16, and an output voltage detection circuit 17.
  • a power converter which comprises a DC / DC converter circuit 11, a drive circuit 12, a control circuit 13, an input current detection circuit 14, an input voltage detection circuit 15, an output current detection circuit 16, and an output voltage detection circuit 17.
  • the DC / DC converter circuit 11 includes four N-channel FETs (switching elements) (Q1, Q2, Q3, Q4), an energy storage inductor L1, and two capacitors Cin, Cout.
  • the source of the FET (Q1) is connected to the input terminal of the inductor L1 and the drain of the FET (Q2), the drain of the FET (Q1) is connected to one end of the capacitor Cin, and the other end of the capacitor Cin is connected to the ground terminals IN2 and OUT2. It is connected.
  • the source of FET (Q2) is the ground terminal IN2. , Connected to OUT2.
  • the source of the FET (Q3) is connected to the output terminal of the inductor L1 and the drain of the FET (Q4), the drain of the FET (Q3) is connected to one end of the capacitor Cout, and the other end of the capacitor Cout is connected to the ground terminal IN2, Connected to OUT2.
  • the source of the FET (Q4) is connected to the ground terminals IN2 and OUT2.
  • the drive circuit 12 includes an FET drive IC (FETdr), two bootstrap capacitors CB1 and CB2, and two bootstrap diodes DB1 and DB2.
  • FETdr FET drive IC
  • a 14-pin IC is used as the FET driving IC (FETdr).
  • Other specifications include: PWM input: 4, PWM high side output: 2, PWM low side output: 2, high side midpoint potential (HS terminal) withstand voltage: 200V, drive current (Sink / Source): 1A / A satisfying 1A was used. *
  • the first pin of the FET driving IC (FETdr) is connected to the cathode of the diode DB1 and one end of the capacitor CB1, and the voltage Vcc is applied to the anode of the diode DB1.
  • a voltage Vcc is applied to the second pin of the FET driving IC (FETdr).
  • the 3rd to 6th pins of the FET driving IC (FETdr) are connected to the control circuit 13.
  • the 7th pin of the FET driving IC (FETdr) is connected to the ground terminals IN2 and OUT2.
  • the 8th pin of the FET driving IC (FETdr) is connected to the gate of the FET (Q3).
  • the ninth pin of the FET driving IC is connected to one end of the capacitor CB2 and the other end of the inductor L1.
  • the 10th pin of the FET driving IC is connected to the gate of the FET (Q4).
  • the 11th pin of the FET driving IC is connected to the other end of the capacitor CB2 and the cathode of the diode DB2.
  • the 12th pin of the FET driving IC is connected to the gate of the FET (Q2).
  • the 13th pin of the FET driving IC is connected to the other end of the capacitor CB1 and one end of the inductor L1.
  • the 14th pin of the FET driving IC is connected to the gate of the FET (Q1). *
  • the control circuit 13 is composed of a CPU (MCU) composed of a 10-pin IC with a built-in RAM and ROM.
  • the specifications of this CPU (MCU) are: Architecture: 16 bits, ROM: 16 KB, RAM: 2 KB, ADC (AD converter): 10 bits, PWM output: 4 This is enough for a CPU of this level. is there.
  • the drive control program of this apparatus is written in this ROM. *
  • the voltage Vcc is applied to the first pin of the CPU (MCU), and the second pin is connected to the output of the input current detection circuit 14.
  • the third pin of the CPU (MCU) is connected to the output of the input voltage detection circuit 15, and the fourth pin is connected to the ground terminals IN2 and OUT2.
  • the fifth pin of the CPU (MCU) is connected to the output of the output voltage detection circuit 17, and the sixth pin is connected to the output of the output current detection circuit 16.
  • the 7th pin of the CPU (MCU) is connected to the 6th pin of the FET drive IC (FETdr), and the on / off drive signal (PWM2H) of the FET (Q3) is output to the 6th pin.
  • the 8th pin of the CPU (MCU) is connected to the 5th pin of the FET drive IC (FETdr), and the on / off drive signal (PWM2L) of the FET (Q4) is output to the 5th pin.
  • the 9th pin of the CPU (MCU) is connected to the 4th pin of the FET drive IC (FETdr), and the on / off drive signal (PWM1L) of the FET (Q2) is output to the 4th pin.
  • the 10th pin of the CPU (MCU) is connected to the 3rd pin of the FET drive IC (FETdr), and the on / off drive signal (PWM1H) of the FET (Q1) is output to the 3rd pin.
  • the input current detection circuit 14 includes a resistor R1 and an operational amplifier CA1, and one end of the resistor R1 is connected to the input terminal IN1 and the non-inverting input terminal of the operational amplifier CA1, and the other end of the resistor R1 is an FET (Q1 ) And the inverting input terminal of the operational amplifier CA1, and the output terminal of the operational amplifier CA1 is connected to the second pin of the CPU (MCU).
  • a resistor R1 and an operational amplifier CA1 and one end of the resistor R1 is connected to the input terminal IN1 and the non-inverting input terminal of the operational amplifier CA1, and the other end of the resistor R1 is an FET (Q1 )
  • Q1 FET
  • the input voltage detection circuit 15 includes two resistors R2 and R3. One end of the resistor R2 is connected to the input terminal IN1, and the other end of the resistor R2 is one end of the resistor R3 and the third of the CPU (MCU). The other end of the resistor R3 is connected to the ground terminals IN2 and OUT2. *
  • the output current detection circuit 16 includes a resistor R4 and an operational amplifier CA2. One end of the resistor R4 is connected to the output terminal OUT1 and a non-inverting input terminal of the operational amplifier CA2, and the other end of the resistor R4 is an FET (Q3 ) And the inverting input terminal of the operational amplifier CA2, and the output terminal of the operational amplifier CA2 is connected to the 6th pin of the CPU (MCU). *
  • the output voltage detection circuit 17 is composed of two resistors R5 and R6. One end of the resistor R5 is connected to the output terminal OUT1, and the other end of the resistor R5 is one end of the resistor R6 and the fifth CPU (MCU). The other end of the resistor R6 is connected to the ground terminals IN2 and OUT2. *
  • a photovoltaic power generation panel is connected as a power source PV between the input terminal IN1 and the ground terminal IN2, and a load is connected between the output terminal OUT1 and the ground terminal OUT2.
  • a photovoltaic power generation panel of the power source PV having an output voltage power characteristic as shown in FIG. 2 is used. That is, the characteristic of the curve A1 is shown when the solar radiation amount to the photovoltaic power generation panel is 100%, the characteristic of the curve A2 is shown when the solar radiation quantity is 80%, and the characteristic of the curve A3 when the solar radiation quantity is 60%. Indicates. When the solar radiation amount is 50%, the characteristic of the curve A4 is shown. When the solar radiation amount is 40%, the characteristic of the curve A5 is shown. When the solar radiation amount is 20%, the characteristic of the curve A6 is shown. The characteristic of the curve A7 is shown at 10%.
  • the maximum power point is about 82V when the amount of solar radiation is 100%, about 79V when the amount of solar radiation is 80%, about 75V when the amount of solar radiation is 60%, and the amount of solar radiation is 50%. Is about 73V, when the solar radiation amount is 40%, about 71V, when the solar radiation amount is 20%, about 67V, and when the solar radiation amount is 10%, it is about 64V. *
  • the output characteristics of the photovoltaic power generation panel are characteristics in which the output power has a maximum value. Further, when the amount of solar radiation increases, both output power and output voltage increase. Here, it can be seen that the maximum output power varies greatly depending on the amount of solar radiation, while the maximum output power point voltage has a smaller change width compared to the change amount of the maximum output power.
  • the CPU (MCU) of the power converter 10 switches the switching elements (Q1, Q2, Q3 of the DC / DC converter circuit 11). , Q4) are turned on and off to operate the DC / DC converter circuit 11 in either the pass-through mode, the step-down mode or the step-up mode.
  • the CPU sets 100 as the value of the mode selection conversion ratio ConvRatio and the previous conversion ratio ConvRatioMp, stores these values, and sets the maximum power value Pmpp. 0 is set and stored, and 1 is stored as the initial value of the adjustment amount E (SA1). *
  • the pass-through mode operation is an operation in which the input voltage is output from the input terminal IN1 to the output terminal OUT1 without being stepped down or boosted.
  • the CPU (MCU) outputs control signals (PWM1H, PWM1L, PWM2H, PWM2L) for turning on / off the four FETs (Q1, Q2, Q3, Q4) at the timings shown in FIGS.
  • These control signals are output with a period T.
  • the control signal (PWM1H) is a negative pulse signal having a period T and a pulse width (t1 + td1 ⁇ 2).
  • the control signal (PWM1L) is a positive pulse signal having a pulse width t1 output while the control signal (PWM1H) is at a low level.
  • the control signal (PWM2H) is the same as the control signal (PWM1H), and the control signal (PWM2L) is the same as the control signal (PWM1L).
  • the pass-through mode operation is performed by turning on / off the FETs (Q1, Q2, Q3, Q4) by these control signals (PWM1H, PWM1L, PWM2H, PWM2L).
  • the period T is set to 53.9 ⁇ s (18.552 kHz)
  • the pulse width t1 is set to 200 ns
  • td1 is set to 100 ns.
  • the CPU inputs the output of the input current detection circuit 14 and the output of the input voltage detection circuit 15 and acquires the input voltage value Vin and the input current value Iin (SA3).
  • the measurement is performed several times, for example, about four times, and the average value is used as the input voltage value Vin and the input current value Iin.
  • the CPU (MCU) performs INSTART determination (SA4).
  • the INSTART determination it is determined whether or not the detected input current Iin is larger than the INSTART value.
  • the INSTART value is different for each photovoltaic power generation panel, for example, 250 mA is set.
  • SA4 when the input current Iin is less than or equal to the INSTART value, the process proceeds to SA3, and when the input current Iin is greater than the INSTART value, it is determined whether or not the control time has come (SA5).
  • the CPU (MCU) measures the time and determines that the control time has been reached every certain minute time. *
  • the CPU inputs the output of the input current detection circuit 14 and the output of the input voltage detection circuit 15 and inputs the input voltage value Vin and the input current value Iin.
  • measurement is performed about four times, and the average value is used as the input voltage value Vin and the input current value Iin.
  • the CPU uses the acquired input voltage value Vin and input current value Iin and multiplies them to calculate the input power value Pin (SA7), and determines the magnitude of the input power value Pin (S7). SA8).
  • SA7 the input power value Pin
  • SA8 the input power value Pin
  • SA9 the maximum power value Pmpp
  • SA10 the input power value Pin
  • the CPU compares the value of the conversion ratio ConvRatio for mode selection with the value of the previous conversion ratio ConvRatioMp (SA9), and the value of the conversion ratio ConvRatio for mode selection is one previous.
  • SA9 the value of the conversion ratio ConvRatioMp
  • the CPU compares the value of the mode selection conversion ratio ConvRatio with the previous conversion ratio ConvRatioMp (SA10).
  • SA10 the value of the conversion ratio ConvRatio for mode selection is smaller than the value of the previous conversion ratio ConvRatioMp
  • the process proceeds to SA11 described later, and the value of the conversion ratio ConvRatioMp for which the mode selection conversion ratio ConvRatio is the previous value. In the above case, the process proceeds to SA16 described later.
  • the CPU (MCU) checks the lower limit of the value of the mode selection conversion ratio ConvRatio (SA14). That is, the CPU (MCU) compares the value of the mode selection conversion ratio ConvRatio with 20, and when the value of the mode selection conversion ratio ConvRatio is larger than 20, the CPU (MCU) proceeds to the processing of SA21 described later.
  • SA21 the value of the conversion ratio ConvRatio for mode selection is 20 or less
  • the value of the conversion ratio ConvRatio for mode selection is set to 20 and stored (SA15). Thereafter, the process proceeds to SA21 described later.
  • the CPU (MCU) stores the value of the mode selection conversion ratio ConvRatio as the previous conversion ratio ConvRatioMp (SA16). Further, the CPU (MCU) stores the input power value Pin as the maximum power value Pmpp (SA17), and increases the value of the mode selection conversion ratio ConvRatio (SA18). In this calculation process, a value obtained by adding the adjustment value Esa to the value of the mode selection conversion ratio ConvRatio is stored as a new value of the mode selection conversion ratio ConvRatio.
  • the CPU (MCU) checks the upper limit of the value of the mode selection conversion ratio ConvRatio (SA19). That is, the CPU (MCU) compares the value of the mode selection conversion ratio ConvRatio with 400, and when the value of the mode selection conversion ratio ConvRatio is smaller than 400, the CPU (MCU) proceeds to the processing of SA21 described later.
  • SA21 the value of the conversion ratio ConvRatio for mode selection is 400 or more
  • the value of the conversion ratio ConvRatio for mode selection is set to 400 and stored (SA20). Thereafter, the process proceeds to SA21 described later.
  • SA21 it is determined in which range the value of the mode selection conversion ratio ConvRatio is (SA21). That is, when the value of the mode selection conversion ratio ConvRatio is 92 or less, the process proceeds to the process of SA22 described later. When the value of the mode selection conversion ratio ConvRatio is 97 or more and 105 or less, the process proceeds to SA24, which will be described later, and when the value of the mode selection conversion ratio ConvRatio is 110 or more, the process proceeds to SA26, which will be described later. .
  • ConvRatio is larger than 92 and smaller than 97, or if the value of ConvRatio is larger than 105 and smaller than 110, the current operation mode is continued.
  • the operation mode is switched smoothly by providing hysteresis to the conversion ratio ConvRatio for selecting the operation mode.
  • the step-down mode is selected as the operation mode of the DC / DC converter circuit 11 (SA22), and then the PWM pulse width in the step-down mode operation is calculated and set (SA23).
  • the step-down mode operation of the DC / DC converter circuit 11 pulses of control signals (PWM1H, PWM1L, PWM2H, PWM2L) for driving the FETs (Q1, Q2, Q3, Q4) on and off as shown in FIGS. Set. *
  • control signal (PWM1H) is a positive pulse signal having a period T1 and a pulse width t1.
  • the control signal (PWM1L) is a positive pulse signal with a pulse width t1a output with an interval td1 before and after when the control signal (PWM1H) is at a low level.
  • the control signal (PWM2H) is a negative pulse signal with a period T and a pulse width (t2 + td2 ⁇ 2).
  • the falling edge of the control signal (PWM2H) is delayed by time td3 from the rising edge of the control signal (PWM1L). To do.
  • the control signal (PWM2L) is a positive pulse signal having a pulse width t2 output while the control signal (PWM2H) is at a low level.
  • the step-down mode operation is performed by turning on / off the FETs (Q1, Q2, Q3, Q4) by these control signals (PWM1H, PWM1L, PWM2H, PWM2L).
  • the period T is set to 53.9 ⁇ s (18.552 kHz), the period T1 is 7.7 ⁇ s (129.87 kHz)), and the pulse width t1 is 1.54 to 7.3 ⁇ s ( Step-down ratio: 0.200 to 0.948), t2 is set to 200 ns, td1 and td2 are set to 100 ns, and td3 is set to 0 ns.
  • the pulse width t1 is calculated by the following equation (1), and the pulse width t1a is calculated by the equation (2). *
  • t1 T1 x ConvRatio / 100mm
  • t1a T1-t1-td1 x 2
  • the control signals (PWM2H, PWM2L) for driving the FETs (Q3, Q4) on / off are DC / Only the DC converter circuit 11 is refreshed.
  • the aforementioned pass-through mode is selected as the operation mode of the DC / DC converter circuit 11 (SA24), and then the PWM pulse width in the pass-through mode operation is set (SA25).
  • the boost mode is selected as the operation mode of the DC / DC converter circuit 11 (SA26), and then the PWM pulse width in the boost mode operation is calculated and set (SA27).
  • the step-up mode operation of the DC / DC converter circuit 11 as shown in FIGS. 13 to 15, pulses of control signals (PWM1H, PWM1L, PWM2H, PWM2L) for driving each FET (Q1, Q2, Q3, Q4) on and off are generated.
  • control signal (PWM2H) is a positive pulse signal having a period T1 and a pulse width t2a.
  • the control signal (PWM2L) is a positive pulse signal having a pulse width t2 output with an interval td2 before and after when the control signal (PWM2H) is at a low level.
  • the control signal (PWM1H) is a negative pulse signal with a period T and a pulse width (t1 + td1 ⁇ 2).
  • the falling edge of the control signal (PWM1H) is delayed by time td3 from the rising edge of the control signal (PWM2L). To do.
  • the control signal (PWM1L) is a positive pulse signal having a pulse width t1 output while the control signal (PWM1H) is at a low level.
  • the boost mode operation is performed by turning on / off the FETs (Q1, Q2, Q3, Q4) by these control signals (PWM1H, PWM1L, PWM2H, PWM2L).
  • the period T is set to 53.9 ⁇ s (18.552 kHz)
  • the period T1 is 7.7 ⁇ s (129.87 kHz)
  • the pulse width t1 is 200 ns
  • t2 is 200 ns to 5.ns.
  • td1 and td2 are set to 100 ns
  • td3 is set to 0 to 100 ns.
  • the pulse width t2a is calculated by the following equation (3)
  • the pulse width t2 is calculated by the equation (4). *
  • the CPU performs a PWM pulse width change process for changing to the selected operation mode and the set pulse width (SA28), and proceeds to the process of SA5.
  • the power conversion apparatus 10 of the present embodiment can select the operation mode of the DC / DC converter circuit 11 by the mode selection conversion ratio ConvRatio, and can control the pulse width of the control signals (PWM1H, PWM1L, PWM2H, PWM2L). Since it can also be calculated, the program control can be simplified and the capacity of the program can be reduced as compared with the conventional case. As a result, the apparatus configuration can be simplified and sufficient control can be performed even with a 16 KB memory CPU (MCU), so that the manufacturing cost can be reduced as compared with the prior art.
  • MCU 16 KB memory CPU
  • the photovoltaic power generation apparatus which connected the said power converter device 10 for every photovoltaic power generation panel is shown in FIG.
  • the solar panels are connected in series, even if leaves of trees are placed on one of the solar panels and the solar radiation on the panel is reduced, Since the current value is set to be the same as the current value of the other solar power generation panel in which the solar radiation amount has not decreased by the power converter, the power generation amount of the other solar power generation panel in which the other solar radiation amount has not decreased is 100. % Is maintained. In the example of FIG. 16, even if the solar radiation amount of any one of the photovoltaic power generation panels connected in series decreases and the power generation amount decreases to 50%, another photovoltaic power generation panel connected in series to this The power generation amount is maintained at 100%. *
  • a DC / DC converter circuit 11 having an H-bridge type switching circuit is used.
  • a chopper type circuit step-down circuit, step-up circuit, H-bridge circuit
  • flyback circuit forward circuit
  • bridge type is used.
  • the same effect can be obtained by using either a circuit (half-bridge circuit or full-bridge circuit.
  • operational amplifiers CA1 and CA2 used in the input current detection circuit 14 and the output current detection circuit 16 It is preferable to use a high-side current detection amplifier that is resistant to noise.
  • the circuit diagram of the power conversion device in the second embodiment is the same as that of the first embodiment described above, and the solar power generation panel used as the power source PV is also the same as that of the first embodiment described above. *
  • FIGS. 17 to 22 The control flowcharts in the second embodiment are shown in FIGS. 17 to 22, and the power conversion apparatus 10 is driven by this control.
  • the processing of SB1 to SB6 is the same as the processing of SA1 to SA6 in the first embodiment described above
  • the processing of SB13 to SB34 is the same as the processing of SA7 to SA28 in the first embodiment described above.
  • the difference between the first embodiment and the second embodiment is that the processing of SB7 to SB12 is added in the second embodiment. *
  • the maximum power point voltage of a photovoltaic power generation panel tends to be high if the amount of solar radiation is large and conversely low if the amount of solar radiation is small, but compared with the change width of the output short circuit voltage from the output open voltage of the photovoltaic power generation panel, The width is small. Therefore, in the second embodiment, these problems are solved by varying the adjustment value Esa of the conversion ratio ConvRatio for mode selection according to the output voltage of the photovoltaic power generation panel, that is, the input voltage Vin to the power converter 10. I tried to do it. *
  • the input voltage Vin to the power converter 10 is divided into five regions as shown in FIG. 18, and the input voltage Vin is in the reference voltage region with the voltage range including the maximum power point as the reference voltage region.
  • the adjustment value Esa at the time is made equal to the reference value E, and the adjustment value in each region is set to a value that increases as the distance from the reference voltage region increases. That is, since the maximum power point needs to be reached quickly when the operating point is away from the reference voltage region, the adjustment value Esa of the mode selection conversion ratio ConvRatio is increased. On the other hand, when the operating point is close to the reference voltage region, it is necessary to continue to operate near the maximum power point, so the adjustment value Esa of the mode selection conversion ratio ConvRatio is reduced. *
  • the CPU (MCU) makes an INSTART determination (SB4), and when the input current Iin is larger than the INSTART value, it is determined whether or not the control time has come. Determine (SB5).
  • the CPU (MCU) measures the time and determines that the control time has been reached every certain minute time.
  • the CPU determines the value of the input voltage Vin (SB7).
  • the value of the adjustment value Esa is set to 5 times the value of the reference value E (SB8).
  • the value of the adjustment value Esa is set to three times the value of the reference value E (SB9).
  • the adjustment value Esa is set equal to the reference value E (SB10).
  • the value of the adjustment value Esa is set to three times the value of the reference value E (SB11).
  • the value of the adjustment value Esa is set to 5 times the value of the reference value E (SB12).
  • the process proceeds to SB13. *
  • the adjustment value Esa when the input voltage Vin is in the reference voltage region is set as the reference value E, and the adjustment value Esa in each region is set to a value that increases as the distance from the reference voltage region increases.
  • the on / off time of the FET Q1, Q2, Q3, Q4 is calculated using the conversion ratio ConvRatio for mode selection adjusted by the adjustment value Esa, the maximum power point can be followed more quickly than before. .
  • the time required to reach the maximum power point is about five times faster than that in the first embodiment. *
  • FIG. 25 is a circuit diagram showing the power conversion device 10 according to the third embodiment of the present invention.
  • the power conversion device 10 of this embodiment includes a DC / DC converter unit 20 and a DC / AC inverter unit 30.
  • FIG. 26 is an enlarged view of the DC / DC converter unit 20
  • FIG. 27 is an enlarged view of the DC / AC inverter unit 30.
  • the DC / DC converter unit 20 includes a DC / DC converter circuit 21, a DC / DC converter drive circuit 22, a control circuit (MCU) 23, an input current detection circuit 24, an input voltage detection circuit 25, a bridge unit current detection circuit 26,
  • the link voltage detection circuit 27 is configured.
  • the DC / AC inverter unit 30 includes a DC / AC inverter circuit 31, a DC / AC inverter drive circuit 32, an output voltage detection circuit 33, an output current detection circuit 34, and a filter circuit 35.
  • the DC / DC converter circuit 21 includes an N-channel FET (switching element) (Q), an inductor L, a diode D, and two capacitors Cin and C-LINK.
  • the source of the FET (Q) is connected to the ground terminal IN2, and the drain of the FET (Q) is connected to one end of the inductor L and the anode of the diode D.
  • the other end of the inductor L is connected to one end of the capacitor Cin, and the other end of the capacitor Cin is connected to the ground terminal IN2.
  • the cathode of the diode D is connected to one end of the capacitor C-LINK, and the other end of the capacitor C-LINK is connected to the ground terminal IN2. *
  • the DC / DC converter drive circuit 22 includes an NPN transistor Tr1 and a PNP transistor Tr2.
  • a voltage Vcc1 is applied to the collector of the NPN transistor Tr1. In the present embodiment, a voltage of 12V is applied.
  • the emitter of the NPN transistor Tr1 is connected to the emitter of the PNP transistor Tr2.
  • the collector of the PNP transistor Tr2 is connected to the ground terminals IN2 and OUT2.
  • a connection point Vo between the NPN transistor Tr1 and the PNP transistor Tr2 is connected to the gate of the FET (Q).
  • the bases of the NPN transistor Tr1 and the PNP transistor Tr2 are connected to a control circuit (MCU) 23. *
  • the control circuit 23 is composed of a CPU (MCU) composed of a 13-pin IC incorporating a RAM and a ROM.
  • the specifications of this CPU (MCU) are: Architecture: 16 bits, ROM: 16 KB, RAM: 2 KB, ADC (AD converter): 10 bits, PWM output: 5, This level of CPU can be used sufficiently. is there.
  • the drive control program of this apparatus is written in this ROM. *
  • the first pin of the CPU is connected to the output of the link voltage detection circuit 27, the second pin is connected to the bases of the NPN transistor Tr1 and the PNP transistor Tr2, and the voltage Vcc1 is applied to the third pin.
  • the 4th pin is connected to the output of the input current detection circuit 24, the 5th pin is connected to the output of the input voltage detection circuit 25, the 6th pin is connected to the ground terminals IN2 and OUT2, and the 7th pin is the output voltage.
  • the 8th pin is connected to the output of the output current detection circuit 33.
  • the 9th pin of the CPU is connected to the 6th pin of the FET drive IC (FETdr) of the DC / AC inverter drive circuit 32, and the N-channel FET of the DC / AC inverter circuit 31 is connected to the 6th pin.
  • the on / off drive signal (PWM2H) of (Q3) is output.
  • the 10th pin is connected to the 5th pin of the FET driving IC (FETdr), and the on / off driving signal (PWM2L) of the N-channel FET (Q4) of the DC / AC inverter circuit 31 is output to the 5th pin. .
  • the 11th pin is connected to the 4th pin of the FET drive IC (FETdr), and outputs the on / off drive signal (PWM1L) of the N-channel FET (Q2) of the DC / AC inverter circuit 31 to the 4th pin.
  • the 12th pin is connected to the 3rd pin of the FET drive IC (FETdr), and outputs the on / off drive signal (PWM1H) of the N-channel FET (Q1) of the DC / AC inverter circuit 31 to the 3rd pin.
  • the 13th pin is connected to the output of the bridge portion current detection circuit 26. *
  • the input current detection circuit 24 includes a resistor R1 and an operational amplifier CA1, and one end of the resistor R1 is connected to the input terminal IN1 and a non-inverting input terminal of the operational amplifier CA1, and the other end of the resistor R1.
  • the other end of the reactance L of the DC / DC converter circuit 21 is connected to the inverting input terminal of the operational amplifier CA1, and the output terminal of the operational amplifier CA1 is connected to the fourth pin of the CPU (MCU).
  • the input voltage detection circuit 25 includes two resistors R2 and R3. One end of the resistor R2 is connected to the input terminal IN1, and the other end of the resistor R2 is one end of the resistor R3 and 5 of the CPU (MCU). The other end of the resistor R3 is connected to the ground terminal IN2. *
  • the bridge portion current detection circuit 26 includes a resistor R4 and an operational amplifier CA2.
  • One end of the resistor R4 is connected to a DC-AC inverter circuit 31 of the DC / AC inverter portion 30 and a non-inverting input terminal of the operational amplifier CA2.
  • the other end of the resistor R4 is connected to the diode D and capacitor Cin of the DC / DC converter circuit 21, the resistor R5 of the link voltage detection circuit 27, and the inverting input terminal of the operational amplifier CA2.
  • the output terminal of the operational amplifier CA2 is connected to the 13th pin of the CPU (MCU). *
  • the link voltage detection circuit 27 includes two resistors R5 and R6. One end of the resistor R5 is connected to the other end of the resistor R4, the diode D and the capacitor Cin of the DC / DC converter circuit 21, and the resistor R5. The other end of the resistor R6 is connected to one end of the resistor R6 and the first pin of the CPU (MCU), and the other end of the resistor R6 is connected to the ground terminal IN2. *
  • the DC / AC inverter circuit 31 includes four N-channel FETs (switching elements) (Q1, Q2, Q3, Q4).
  • the source of the FET (Q1) is connected to the input terminal of the inductor L1 of the filter circuit 35 and the drain of the FET (Q2), and the drain of the FET (Q1) is connected to one end of the resistor R4 of the bridge current detection circuit 26. ing.
  • the source of the FET (Q2) is connected to the ground terminal IN2.
  • the source of the FET (Q3) is connected to the input terminal of the inductor L2 of the filter circuit 35 and the drain of the FET (Q4), and the drain of the FET (Q3) is connected to one end of the resistor R4 of the bridge current detection circuit 26. It is connected.
  • the source of the FET (Q4) is connected to the ground terminal IN2. *
  • the DC / AC inverter drive circuit 32 includes an FET drive IC (FETdr), two bootstrap capacitors CB1 and CB2, and two bootstrap diodes D1 and D2.
  • FETdr FET drive IC
  • a 14-pin IC is used as the FET driving IC (FETdr).
  • Other specifications include: PWM input: 4, PWM high side output: 2, PWM low side output: 2, high side midpoint potential (HS terminal) withstand voltage: 600V, drive current (Sink / Source): 1A / A satisfying 1A was used. *
  • the first pin of the FET driving IC (FETdr) is connected to the cathode of the diode D1 and one end of the capacitor CB1, and the voltage Vcc is applied to the anode of the diode D1.
  • a voltage Vcc is applied to the second pin of the FET driving IC (FETdr).
  • the 3rd pin of the FET driving IC (FETdr) is the 12th pin of the control circuit 23, the 4th pin is the 11th pin of the control circuit, the 5th pin is the 10th pin of the control circuit, and the 6th pin is the 9th of the control circuit. It is connected to each pin.
  • the 7th pin of the FET driving IC (FETdr) is connected to the ground terminal IN2.
  • the 8th pin of the FET driving IC (FETdr) is connected to the gate of the FET (Q3).
  • the 9th pin of the FET driving IC (FETdr) is connected to the gate of the FET (Q4).
  • the 10th pin of the FET driving IC (FETdr) is connected to one end of the capacitor CB2 and the input end of the inductor L2 of the filter circuit 35.
  • the 11th pin of the FET driving IC (FETdr) is connected to the other end of the capacitor CB2 and the cathode of the diode DB2.
  • the 12th pin of the FET driving IC (FETdr) is connected to the gate of the FET (Q2).
  • the 13th pin of the FET driving IC (FETdr) is connected to the other end of the capacitor CB1 and the input end of the inductor L1 of the filter circuit 35.
  • the 14th pin of the FET driving IC (FETdr) is connected to the gate of the FET (Q1). *
  • the output current detection circuit 33 includes a resistor R7 and an operational amplifier CA.
  • One end of the resistor R7 is connected to the output terminal OUT1, the non-inverting input terminal of the operational amplifier CA, and the diode bridge DB.
  • the other end of the resistor R7 is connected to one end of the capacitor Cout of the filter circuit 35, the other end of the inductor L2, and the inverting input terminal of the operational amplifier CA.
  • the output terminal of the operational amplifier CA is connected to the eighth pin of the CPU (MCU). It is connected. *
  • the output voltage detection circuit 34 includes a diode bridge DB including two resistors R8 and R9 and four diodes D, and one end of the resistor R8 is connected to one output terminal DBout1 of the diode bridge DB.
  • the other end of R8 is connected to one end of resistor R9 and the seventh pin of CPU (MCU), and the other end of resistor R9 and the other output terminal DBout2 of diode bridge DB are connected to ground terminal IN2 .
  • One input terminal DBin1 of the diode bridge DB is connected to the other end of the capacitor Cout of the filter circuit 35 and the output end of the inductor L1.
  • the other input terminal DBin2 of the diode bridge DB is connected to one end of the capacitor Cout of the filter circuit 35 and one end of the inductor L2.
  • the filter circuit 35 removes harmonic noise exceeding 20 kHz, and includes two inductors L1 and L2 and a capacitor Cout.
  • the inductors L1 and L2 are configured by a common mode choke coil made of amorphous or ferrite.
  • the output end of the inductor L1 is connected to the other end of the capacitor Cout, one input terminal DBin1 of the diode bridge DB, and one output terminal OUT1.
  • the output terminal of the inductor L2 is connected to one end of the capacitor Cout and one end of the resistor R7.
  • the photovoltaic power generation panel is connected as the power source PV between the input terminal IN1 and the output terminal IN2, and a load is connected between the output terminal OUT1 and the ground terminal OUT2. Connect LOAD.
  • a photovoltaic power generation panel of the power source PV having an output voltage power characteristic as shown in FIG. 26 is used. That is, the characteristic of the curve A1 is shown when the solar radiation amount to the photovoltaic power generation panel is 100%, the characteristic of the curve A2 is shown when the solar radiation quantity is 80%, and the characteristic of the curve A3 when the solar radiation quantity is 60%. Indicates. When the solar radiation amount is 50%, the characteristic of the curve A4 is shown. When the solar radiation amount is 40%, the characteristic of the curve A5 is shown. When the solar radiation amount is 20%, the characteristic of the curve A6 is shown. The characteristic of the curve A7 is shown at 10%.
  • the maximum power point is about 82V when the amount of solar radiation is 100%, about 79V when the amount of solar radiation is 80%, about 75V when the amount of solar radiation is 60%, and the amount of solar radiation is 50%. Is about 73V, when the solar radiation amount is 40%, about 71V, when the solar radiation amount is 20%, about 67V, and when the solar radiation amount is 10%, it is about 64V. *
  • the output characteristics of the photovoltaic power generation panel are characteristics in which the output power has a maximum value. Further, when the amount of solar radiation increases, both output power and output voltage increase. Here, it can be seen that the maximum output power varies greatly depending on the amount of solar radiation, while the maximum output power point voltage has a smaller change width compared to the change amount of the maximum output power.
  • the CPU (MCU) of the power converter 10 turns on and off the switching element (Q) of the DC / DC converter circuit 21.
  • the DC / DC converter circuit 21 is operated in either the pass-through mode or the boost mode.
  • the CPU sets 100 as the value of the mode selection conversion ratio ConvRatio and the previous conversion ratio ConvRatioMp, stores these values, and sets the maximum power value Pmpp. 0 is set and stored, and 1 is stored as the initial value of the adjustment amount E (SC1). *
  • the pass-through mode operation is an operation in which the input voltage is output from the input terminal IN1 to the cathode side of the diode D without being stepped down or boosted.
  • the C-LINK is charged with a voltage equivalent to the input voltage.
  • the period T is set to 53.9 ⁇ s (18.552 kHz)
  • the pulse width t1 is set to 200 ns
  • td1 is set to 100 ns.
  • the CPU inputs the output of the input current detection circuit 24 and the output of the input voltage detection circuit 25, and acquires the input voltage value Vin and the input current value Iin (SC3).
  • the measurement is performed several times, for example, about four times, and the average value is used as the input voltage value Vin and the input current value Iin.
  • control time it is determined whether or not the control time has come (SC4).
  • the CPU MCU
  • the CPU measures the time and determines that the control time has been reached every certain minute time.
  • the CPU inputs the output of the input current detection circuit 24 and the output of the input voltage detection circuit 25 and inputs the input voltage value Vin and the input current value Iin.
  • measurement is performed about four times, and the average value is used as the input voltage value Vin and the input current value Iin.
  • the CPU uses the acquired input voltage value Vin and input current value Iin and multiplies them to calculate the input power value Pin (SC6), and determines the magnitude of the input power value Pin (S6). SC7).
  • SC6 input power value
  • SC7 determines the magnitude of the input power value Pin
  • the CPU compares the value of the conversion ratio ConvRatio for mode selection with the value of the previous conversion ratio ConvRatioMp (SC8), and the value of the conversion ratio ConvRatio for mode selection is one previous.
  • SC8 the value of the conversion ratio ConvRatioMp
  • the CPU compares the value of the mode selection conversion ratio ConvRatio with the previous conversion ratio ConvRatioMp (SC9).
  • SC9 previous conversion ratio
  • the process proceeds to SC10 described later, and the value of the conversion ratio ConvRatioMp for the mode selection conversion ratio ConvRatio is the value of the previous conversion ratio.
  • the process proceeds to SC15 described later.
  • the CPU (MCU) checks the lower limit of the value of the mode selection conversion ratio ConvRatio (SC13). That is, the CPU (MCU) compares the value of the mode selection conversion ratio ConvRatio with 100, and when the value of the mode selection conversion ratio ConvRatio is larger than 100, the CPU (MCU) proceeds to the process of SC20 described later.
  • the value of the conversion ratio ConvRatio for mode selection is 100 or less, the value of the conversion ratio ConvRatio for mode selection is set to 100 and stored (SC14), and thereafter, the process proceeds to SC20 described later.
  • the CPU (MCU) checks the upper limit of the value of the mode selection conversion ratio ConvRatio (SC18). That is, the CPU (MCU) compares the value of the mode selection conversion ratio ConvRatio with 400, and when the value of the mode selection conversion ratio ConvRatio is smaller than 400, the CPU (MCU) proceeds to the process of SC20 described later.
  • the mode selection conversion ratio ConvRatio is set to 400 and stored (SC19), and thereafter, the process proceeds to SC20 described later.
  • the above-described pass-through mode is selected as the operation mode of the DC / DC converter circuit 21 (SC21), and then the PWM pulse width in the pass-through mode operation is set (SC22).
  • the boost mode is selected as the operation mode of the DC / DC converter circuit 21 (SC23), and then the PWM pulse width in the boost mode operation is calculated and set (SC24).
  • SC23 the operation mode of the DC / DC converter circuit 21
  • PWM_Boost a pulse of a control signal for driving the FET (Q) on and off is set as shown in FIGS. *
  • the CPU performs a PWM pulse width change process for changing to the selected operation mode and the set pulse width (SC25), and proceeds to the process of SC4.
  • the CPU performs a triangular wave modulation for comparing the signal wave detected by the output voltage detection circuit 33 with the triangular wave carrier, and the DC / AC inverter circuit 31 by the generated control signals (PWM1H, PWM1L, PWM2H, PWM2L).
  • FETs Q1, Q2, Q3, Q4 are turned on and off to operate the inverter.
  • FIG. 36 shows the relationship of PWM signals in triangular wave modulation.
  • PWM1H and the negative phase control signal PWM2L on and off of the switching signals of the positive phase control signal PWM1H and the negative phase control signal PWM2L, and the positive phase control signal PWM1L and the negative phase control signal PWM2H based on the frequency at which the detected signal wave intersects the triangular carrier. The timing of off is determined.
  • this modulation when the signal wave becomes large, the pulse widths of the PWM1H and PWM2L control signals are narrowed, and the pulse widths of the PWM1L and PWM2H control signals are widened.
  • FIG. 34 in this embodiment, two triangular wave carriers W1 and W2 having the same amplitude to be synchronized are used.
  • the frequencies of the triangular wave carriers W1 and W2 are both 20 kHz.
  • the triangular wave carrier W1 is used to determine the on and off timings of the positive phase control signal PWM1H and the negative phase control signal PWM2H.
  • the triangular wave carrier W2 is obtained by setting a predetermined amount offset to the triangular wave carrier W1, and is used for determining the on and off timings of the normal phase control signal PWM1L and the negative phase control signal PWM2L.
  • an offset value is set so that the triangular wave carrier W1 is shifted by a predetermined amount in the positive output voltage value direction.
  • the voltage value when the triangular wave carrier W1 and the signal from the output voltage detection circuit 33 first intersect in each carrier period is set as the threshold value in each carrier period.
  • FIG. 37 is a diagram illustrating the relationship between the two triangular wave carriers W1 and W2 and the threshold value and the dead time.
  • the threshold values of two continuous triangular wave carriers are set to the same value for easy illustration and understanding. As shown in FIG.
  • PWM1H and PWM2L are turned on when the signal from the output voltage detection circuit is higher than the threshold, and turned off when the signal from the output voltage detection circuit is lower than the threshold. It is configured.
  • the PWM1L and the PWM2H are configured to be turned on when the signal from the output voltage detection circuit is lower than the threshold value, and to be turned off when the signal from the output voltage detection circuit is higher than the threshold value.
  • PWM1H and PWM2L are turned on with a predetermined time interval (dead time) from both ends of the OFF period of PWM1L and PWM2H.
  • the length of the dead time in this embodiment is proportional to the amount of offset to be set.
  • the dead time is adjusted to be 100 nsec to 200 nsec. By providing such a dead time, it is possible to prevent an abnormal heat generation and damage of the switching element due to a short circuit caused by a simultaneous switching on of the conductor switch ignition elements and a through current flowing therethrough.
  • PWM1H and PWM2L output synchronized waveforms.
  • PWM1L and PWM2H output synchronized waveforms.
  • the output of the DC / AC inverter circuit 31 is 50 Hz or 60 Hz, and can be taken out as a commercial power source. *
  • the DC / AC inverter since the DC / AC inverter inputs a DC voltage and outputs an AC current, a DC voltage that is equal to or higher than the peak voltage of the commercial power supply voltage is required. Therefore, the DC / DC converter only needs to switch between the boost mode and the pass-through mode, so that the program control can be further simplified and the capacity of the program can be reduced. Further, commercial AC power can be taken out by the DC / AC inverter.
  • the circuit diagram of the power conversion device 10 in the fourth embodiment is the same as that of the third embodiment described above, and the solar power generation panel used as the power source PV is also the same as that of the third embodiment described above. *
  • FIGS. 38 to 43 the control flowchart in the fourth embodiment is shown in FIGS. 38 to 43, and the power conversion apparatus 10 is driven by this control.
  • the processing from SD1 to SD5 is the same as the processing from SC1 to SC5 in the third embodiment
  • the processing from SD12 to SD31 is the same as the processing from SC6 to SC25 in the third embodiment.
  • the difference between the third embodiment and the fourth embodiment is that the processing of SD6 to SD11 is added in the fourth embodiment. *
  • the maximum power point voltage of the photovoltaic power generation panel tends to be high if the amount of solar radiation is large and conversely low if the amount of solar radiation is small, but when compared with the change width of the output short circuit voltage from the output open voltage of the solar power generation panel, The width is small. Therefore, in the fourth embodiment, these problems are solved by varying the adjustment value Esa of the conversion ratio ConvRatio for mode selection according to the output voltage of the photovoltaic power generation panel, that is, the input voltage Vin to the power conversion device 10. I tried to do it.
  • the input voltage Vin to the power converter 10 is divided into five regions as shown in FIG. 44, and the input voltage Vin is in the reference voltage region with the voltage range including the maximum power point as the reference voltage region.
  • the adjustment value Esa at the time is made equal to the reference value E, and the adjustment value in each region is set to a value that increases as the distance from the reference voltage region increases. That is, since the maximum power point needs to be reached quickly when the operating point is away from the reference voltage region, the adjustment value Esa of the mode selection conversion ratio ConvRatio is increased. On the other hand, when the operating point is close to the reference voltage region, it is necessary to continue to operate near the maximum power point, so the adjustment value Esa of the mode selection conversion ratio ConvRatio is reduced. *
  • the CPU inputs the output of the input current detection circuit 24 and the output of the input voltage detection circuit 25, and inputs the input voltage value Vin and the input current value Iin.
  • measurement is performed about four times, and the average value is used as the input voltage value Vin and the input current value Iin.
  • the CPU determines the value of the input voltage Vin (SD6).
  • the value of the adjustment value Esa is set to 5 times the value of the reference value D (SD7).
  • the value of the adjustment value Esa is set to three times the value of the reference value D (SD8).
  • the adjustment value Esa is set equal to the reference value E (SD9).
  • the value of the adjustment value Esa is set to three times the value of the reference value E (SD10).
  • the value of the adjustment value Esa is set to 5 times the value of the reference value E (SD11).
  • the process proceeds to SD12. *
  • the adjustment value Esa when the input voltage Vin is in the reference voltage region is set as the reference value E, and the adjustment value Esa in each region is set to a value that increases as the distance from the reference voltage region increases.
  • the on / off time of the FET (Q) is calculated using the mode selection conversion ratio ConvRatio adjusted by the adjustment value Esa, the maximum power point can be followed more quickly than in the prior art.
  • the time required to reach the maximum power point is about five times faster than in the third embodiment. *
  • FIG. 45 is a circuit diagram showing the power converter 10 in the fifth embodiment of the present invention. Similar to the power conversion device in the third embodiment, the power conversion device 10 in the fifth embodiment includes a DC / DC converter circuit 21, a DC / DC converter drive circuit 22, a control circuit (MCU) 23, and an input current detection circuit. 24, a DC / DC converter section 20 comprising an input voltage detection circuit 25, a bridge section current detection circuit 26 and a link voltage detection circuit 27, a DC / AC inverter circuit 31, a DC / AC inverter drive circuit 32, an output current A DC / AC inverter unit 30 including a detection circuit 33, an output voltage detection circuit 34, and a filter circuit 35 is provided.
  • FIG. 46 is an enlarged view of the DC / DC converter unit 20, and FIG. 47 is an enlarged view of the DC / AC inverter unit 30. *
  • a DC / DC converter drive circuit 22 In the fifth embodiment, a DC / DC converter drive circuit 22, a control circuit (MCU) 23, an input current detection circuit 24 and an input voltage detection circuit 25, a bridge portion current detection circuit 26, a link voltage detection circuit 27, a DC / DC
  • the third embodiment is different from the third embodiment in that the AC inverter circuit 31, the DC / AC inverter drive circuit 32, the output current detection circuit 33, the output voltage detection circuit 34, and the filter circuit 35 are insulated.
  • the DC / DC converter circuit 21 of the present embodiment includes an N-channel FET (switching element) (Q), a transformer T1, a diode D, and two capacitors Cin and C-LINK.
  • the N-channel FET (switching element) (Q) and the capacitor Cin, and the diode D and the capacitor C-LINK are insulated by the transformer T1.
  • the voltage input to the DC / DC converter circuit 21 is input to the diode D and the capacitor C-LINK via the transformer T1.
  • the detection results of the bridge portion current detection circuit 26, the link voltage detection circuit 27, the output voltage detection circuit 33, and the output current detection circuit 34 are sent to the control circuit (MCU) via the photocoupler (F1-F4). ) 23. Further, control signals (PWM1H, PWM1L, PWM2H, PWM2L) for controlling the driving of the DC / AC inverter circuit 31 output from the control circuit (MCU) are for the DC / AC inverter through the photocoupler (F5-F8). Input to the drive circuit 32.
  • an insulating circuit is configured by photocouplers (F1-F8). *
  • the solar power generation panel is used as the power source PV.
  • the present invention is not limited to this, and the power source having the maximum value in the output voltage power characteristics, such as a wind power generator and a fuel cell, is described above.
  • the power converter 10 By connecting the power converter 10, the same effect as described above can be obtained.
  • a power source having a maximum value in output voltage power characteristics, such as a solar cell or a solar power generation panel, a wind power generator, a fuel cell, etc.
  • the operation mode of the DC / DC converter circuit can be switched at least to the pass-through mode and the boost mode based on the mode selection conversion ratio, and the on / off time of the switching element can be calculated based on the mode selection conversion ratio.
  • SYMBOLS 10 Power converter 11 ... DC / DC converter circuit 12 ... Drive circuit 13 ... Control circuit, 14 ... Input current detection circuit, 15 ... Input voltage detection circuit, 16 ... Output current detection circuit, 17 ... Output voltage detection circuit, Q1 , Q2, Q3, Q4 ... FET, Cin, Cout, CB1, CB2 ... Capacitor, DB1, DB2 ... Diode, R1-R6 ... Resistor, CA1, CA2 ... Operational amplifier.

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  • Sustainable Energy (AREA)
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  • Electromagnetism (AREA)
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Abstract

Selon la présente invention, un rapport de conversion est réglé sur la base d'une valeur de puissance électrique calculée à un intervalle de temps prescrit sur la base d'une valeur de tension et d'une valeur de courant qui sont introduites dans un circuit de convertisseur continu-continu élévateur/abaisseur provenant d'une source de génération de puissance. Une valeur à laquelle une valeur de rapport de conversion actuellement réglé est faite pour fluctuer est réglée en tant que rapport de conversion de sélection de mode sur la base de la variation de fluctuation de la valeur de puissance électrique, et d'un résultat de comparaison entre un rapport de conversion précédemment réglé et le rapport de conversion actuellement réglé. Un mode de fonctionnement d'un circuit de convertisseur continu-continu (11) est commuté vers un mode passant, un mode abaisseur, ou un mode élévateur, sur la base du rapport de conversion de sélection de mode, et le rapport de conversion de sélection de mode est utilisé pour calculer les temps d'allumage-extinction de FET (Q1, Q2, Q3, Q4). Par conséquent, un moyen de commande qui fonctionne en utilisant un programme de faible capacité peut être configuré, et ainsi une configuration de dispositif peut être simplifiée, et les coûts de fabrication peuvent être réduits plus que possible traditionnellement.
PCT/JP2013/080879 2012-11-15 2013-11-15 Dispositif de conversion de puissance WO2014077355A1 (fr)

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JP2018501767A (ja) * 2015-01-07 2018-01-18 フィリップス ライティング ホールディング ビー ヴィ 電力変換装置
JP2019050723A (ja) * 2017-09-11 2019-03-28 リニアー テクノロジー ホールティング エルエルシー 昇降圧レギュレータのパススルー安定化
JP2020077130A (ja) * 2018-11-06 2020-05-21 太陽誘電株式会社 電力変換装置、発電システムおよび発電制御方法
JP2020077132A (ja) * 2018-11-06 2020-05-21 太陽誘電株式会社 電力変換装置、発電システムおよび発電制御方法
JP2020077131A (ja) * 2018-11-06 2020-05-21 太陽誘電株式会社 電力変換装置、発電システムおよび発電制御方法
CN111707858A (zh) * 2020-06-29 2020-09-25 上海南芯半导体科技有限公司 一种高精度的升降压转换器输入电流采样方法
US11081961B2 (en) 2018-11-06 2021-08-03 Taiyo Yudenco., Ltd. Power convertor, power generation system, and power generation control method

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CN107947578B (zh) * 2017-12-04 2020-09-15 成都芯源***有限公司 一种应用于升降压电路的电流采样电路及其控制方法

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Cited By (9)

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Publication number Priority date Publication date Assignee Title
JP2018501767A (ja) * 2015-01-07 2018-01-18 フィリップス ライティング ホールディング ビー ヴィ 電力変換装置
JP2019050723A (ja) * 2017-09-11 2019-03-28 リニアー テクノロジー ホールティング エルエルシー 昇降圧レギュレータのパススルー安定化
JP2020077130A (ja) * 2018-11-06 2020-05-21 太陽誘電株式会社 電力変換装置、発電システムおよび発電制御方法
JP2020077132A (ja) * 2018-11-06 2020-05-21 太陽誘電株式会社 電力変換装置、発電システムおよび発電制御方法
JP2020077131A (ja) * 2018-11-06 2020-05-21 太陽誘電株式会社 電力変換装置、発電システムおよび発電制御方法
US11031786B2 (en) 2018-11-06 2021-06-08 Taiyo Yuden Co., Ltd. Power convertor, power generation system, and power generation control method
US11081961B2 (en) 2018-11-06 2021-08-03 Taiyo Yudenco., Ltd. Power convertor, power generation system, and power generation control method
CN111707858A (zh) * 2020-06-29 2020-09-25 上海南芯半导体科技有限公司 一种高精度的升降压转换器输入电流采样方法
CN111707858B (zh) * 2020-06-29 2023-09-01 上海南芯半导体科技股份有限公司 一种升降压转换器输入电流采样方法

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