WO2014024310A1 - Semiconductor element, hemt element, and method for manufacturing semiconductor element - Google Patents

Semiconductor element, hemt element, and method for manufacturing semiconductor element Download PDF

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WO2014024310A1
WO2014024310A1 PCT/JP2012/070521 JP2012070521W WO2014024310A1 WO 2014024310 A1 WO2014024310 A1 WO 2014024310A1 JP 2012070521 W JP2012070521 W JP 2012070521W WO 2014024310 A1 WO2014024310 A1 WO 2014024310A1
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layer
semiconductor device
iii nitride
group iii
manufacturing
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PCT/JP2012/070521
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French (fr)
Japanese (ja)
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智彦 杉山
宗太 前原
角谷　茂明
田中　光浩
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日本碍子株式会社
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Priority to EP12842688.9A priority Critical patent/EP2720257A4/en
Priority to PCT/JP2012/070521 priority patent/WO2014024310A1/en
Priority to KR1020137010864A priority patent/KR101933230B1/en
Priority to CN201280003274.5A priority patent/CN103828030B/en
Priority to US13/855,148 priority patent/US9478650B2/en
Publication of WO2014024310A1 publication Critical patent/WO2014024310A1/en

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Definitions

  • the present invention relates to a semiconductor element, and more particularly to a semiconductor element having a Schottky diode junction between a multilayer structure epitaxial substrate made of a group III nitride semiconductor and a metal electrode.
  • Nitride semiconductors are attracting attention as semiconductor materials for next-generation high-frequency / high-power devices because they have a high breakdown electric field and a high saturation electron velocity.
  • a HEMT (High Electron Mobility Transistor) element formed by laminating a barrier layer made of AlGaN and a channel layer made of GaN has a laminated interface due to a large polarization effect (spontaneous polarization effect and piezoelectric polarization effect) peculiar to nitride materials.
  • This utilizes the feature that a high-concentration two-dimensional electron gas (2DEG) is generated at the (heterointerface) (see, for example, Non-Patent Document 1).
  • 2DEG high-concentration two-dimensional electron gas
  • a single crystal (heterogeneous single crystal) having a composition different from that of a group III nitride such as silicon or SiC may be used.
  • a buffer layer such as a strained superlattice layer or a low temperature growth buffer layer is generally formed on the base substrate as an initial growth layer. Therefore, epitaxially forming the barrier layer, the channel layer, and the buffer layer on the base substrate is the most basic configuration of the HEMT element substrate using the base substrate made of different single crystals.
  • a spacer layer having a thickness of about 1 nm may be provided between the barrier layer and the channel layer for the purpose of promoting spatial confinement of the two-dimensional electron gas.
  • the spacer layer is made of, for example, AlN. Furthermore, a cap layer made of, for example, an n-type GaN layer or a superlattice layer is formed on the barrier layer for the purpose of controlling the energy level at the outermost surface of the substrate for HEMT elements and improving the contact characteristics with the electrode. Sometimes it is done.
  • the concentration of the two-dimensional electron gas existing in the substrate for the HEMT device is It is known that it increases with an increase in the AlN mole fraction of AlGaN to be formed (see, for example, Non-Patent Document 2). If the two-dimensional electron gas concentration can be significantly increased, it is considered that the controllable current density of the HEMT element, that is, the power density that can be handled, can be significantly improved.
  • the strain is less dependent on the piezoelectric polarization effect and can generate a two-dimensional electron gas at a high concentration only by spontaneous polarization.
  • a HEMT element having a small number of structures is also attracting attention (see, for example, Non-Patent Document 3).
  • the junction between the gate electrode and the barrier layer is generally a Schottky junction.
  • a large leakage current may be generated when a reverse voltage is applied to the Schottky junction.
  • This leakage current can be reduced by forming a contact layer made of AlN on the InAlN layer.
  • the HEMT element having such a configuration has a low mobility of the two-dimensional electron gas. Occurs. This is presumed to be caused by distortion in the InAlN layer because the lattice constant of the AlN layer is smaller than that of the InAlN layer.
  • the present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor element in which reverse leakage current is suppressed and the mobility of a two-dimensional electron gas is high.
  • an epitaxial substrate in which a group (III) nitride layer group is formed on a base substrate so that the (0001) crystal plane is substantially parallel to the substrate surface;
  • the film thickness of the intermediate layer is 0.5 nm or more.
  • the film thickness of the intermediate layer is 6 nm or less.
  • the thickness of the cap layer is 0.5 nm or more and 6 nm or less.
  • the band gap of the second group III nitride is larger than the band gap of the first group III nitride. I made it bigger.
  • the Schottky electrode includes at least one of Ni, Pt, Pd, and Au.
  • the root mean square surface roughness of the cap layer is 0.5 nm or less.
  • the first group III nitride is GaN.
  • the third group III nitride is AlN.
  • an ohmic electrode is bonded to the same cap layer as the Schottky electrode.
  • the Schottky electrode is a gate electrode
  • the ohmic electrode is a source electrode and a drain electrode.
  • an epitaxial substrate obtained by stacking a group III nitride layer group on a base substrate so that a (0001) crystal plane is substantially parallel to the substrate surface, and a Schottky electrode
  • the intermediate layer is formed to a thickness of 0.5 nm or more.
  • the intermediate layer is formed to a thickness of 6 nm or less.
  • the cap layer is formed to a thickness of 0.5 nm or more and 6 nm or less.
  • the band gap of the second group III nitride is the band of the first group III nitride. It was made larger than the gap.
  • the Schottky electrode in the method for manufacturing a semiconductor device according to any one of the fifteenth to nineteenth aspects, is formed of Ni, Pt, Pd, It was formed so as to include at least one of Au.
  • the first group III nitride is GaN.
  • the third group III nitride is AlN.
  • the method for manufacturing a semiconductor device includes an ohmic property in which an ohmic electrode is bonded to the cap layer on which the Schottky electrode is formed.
  • An electrode forming step includes an ohmic property in which an ohmic electrode is bonded to the cap layer on which the Schottky electrode is formed.
  • the intermediate layer made of GaN and the cap layer made of AlN are provided in this order on the barrier layer, and electrodes are formed on the cap layer by Schottky junction,
  • the MIS junction By forming the MIS junction, the reverse leakage current is suppressed and the mobility of the two-dimensional electron gas is kept high as compared with the case where the electrode is formed directly on the barrier layer by the Schottky junction.
  • a semiconductor element is realized.
  • FIG. 1 It is a cross-sectional schematic diagram which shows roughly the structure of the HEMT element 20 which is one aspect
  • FIG. 1 is a schematic cross-sectional view schematically showing a configuration of a HEMT element 20 which is an aspect of a semiconductor element according to an embodiment of the present invention.
  • the HEMT element 20 generally has a configuration in which a source electrode 7, a drain electrode 8, and a gate electrode 9 are provided on an epitaxial substrate 10.
  • the epitaxial substrate 10 has a configuration in which a base substrate 1, a buffer layer 2, a channel layer 3, a spacer layer 4, a barrier layer 5, an intermediate layer 6a, and a cap layer 6b are stacked.
  • Have A source electrode 7, a drain electrode 8, and a gate electrode 9 are formed on the cap layer 6b.
  • the buffer layer 2, the channel layer 3, the spacer layer 4, the barrier layer 5, the intermediate layer 6a, and the cap layer 6b are all formed epitaxially using MOCVD (metal organic chemical vapor deposition). (A detail will be described later) is a suitable example.
  • MOCVD metal organic chemical vapor deposition
  • each layer will be described.
  • other epitaxial growth methods such as MBE, HVPE, and LPE can be used as long as each layer can be formed so as to have good crystallinity.
  • a method appropriately selected from various vapor phase growth methods and liquid phase growth methods may be used, or a mode in which different growth methods are used in combination may be used.
  • the base substrate 1 can be used without any particular limitation as long as a nitride semiconductor layer with good crystallinity can be formed thereon.
  • a single crystal 6H—SiC substrate is preferably used, but an embodiment using a substrate made of sapphire, Si, GaAs, spinel, MgO, ZnO, ferrite, or the like may be used.
  • the buffer layer 2 is made of several hundreds of nanometers in AlN in order to improve the crystal quality of the channel layer 3, the spacer layer 4, the barrier layer 5, the intermediate layer 6a, and the cap layer 6b formed thereon. It is a layer formed to a certain thickness. For example, it is a preferable example that the thickness is 200 nm.
  • the channel layer 3 and the barrier layer 5 have a composition range in which the band gap of the second group III nitride constituting the latter is larger than the band gap of the first group III nitride constituting the former. It is formed.
  • the intermediate layer 6a is a layer formed of GaN.
  • the cap layer 6b is a layer formed of AlN. The effect of the HEMT element 20 having these intermediate layer 6a and cap layer 6b will be described later.
  • a two-dimensional electron gas is present at a high concentration at the interface between the channel layer 3 and the spacer layer 4 (more specifically, near the interface of the channel layer 3).
  • An electron gas region 3e is formed.
  • the spacer layer 4 is a binary compound of Al and N, the alloy scattering effect is further suppressed as compared with the case of a ternary compound containing Ga, and the concentration and mobility of the two-dimensional electron gas are improved. It will be. Note that the discussion on the composition range does not exclude that the spacer layer 4 contains impurities.
  • spacer layer 4 in the epitaxial substrate 10 is not an essential aspect, and may be an aspect in which the barrier layer 5 is formed directly on the channel layer 3. In such a case, a two-dimensional electron gas region 3 e is formed at the interface between the channel layer 3 and the barrier layer 5.
  • the source electrode 7 and the drain electrode 8 are multi-layer metal electrodes in which each metal layer has a thickness of about 10 to 100 nm, and has an ohmic contact with the cap layer 6b.
  • the metal used for the source electrode 7 and the drain electrode 8 should just be formed with the metal material with which favorable ohmic contact is obtained with respect to the epitaxial substrate 10 (with respect to the cap layer 6b).
  • An embodiment in which a multilayer metal electrode made of Al or the like may be formed.
  • the source electrode 7 and the drain electrode 8 can be formed by a photolithography process and a vacuum deposition method.
  • the gate electrode 9 is a single-layer or multi-layer metal electrode in which one or a plurality of metal layers are formed so as to have a thickness of about ten to several hundreds of nanometers. It has a Schottky contact.
  • the gate electrode 9 is preferably formed using a metal having a high work function such as Pd, Pt, Ni, or Au as a forming material. Or the aspect formed as a multilayer metal film of the above-mentioned each metal or each metal, Al, etc. may be sufficient.
  • the cap layer 6b made of AlN is provided, in addition to the above, a metal material used for forming an ohmic junction with a group III nitride semiconductor such as a multilayer metal film containing Ti / Al is also used for the gate. It can be used as a material for forming the electrode 9. This is because, in this case, AlN having a large band gap and a metal material having a relatively small work function are joined, so that a Schottky contact can be obtained relatively easily.
  • the gate electrode 9 can be formed by a photolithography process and a vacuum deposition method.
  • a so-called MIS (metal-insulator-semiconductor) junction is formed by the gate electrode 9, the cap layer 6b, and the barrier layer 5 (strictly, through the intermediate layer 6a). Is formed.
  • the HEMT element 20 has, in principle, a reverse leakage current suppressed more than a conventional HEMT element in which the gate electrode 9 is directly Schottky-bonded to the barrier layer 5. Become.
  • a leakage current when -100 V is applied is directly applied to the barrier electrode in the barrier layer. Is suppressed from about 1/100 to about 1/1000 when formed.
  • FIG. 2 to 4 are diagrams for explaining the effect of providing the cap layer 6b immediately below the gate electrode 9 in the HEMT element, that is, the effect of the HEMT element having the MIS junction described above.
  • FIG. 2 shows that the composition of the barrier layer 5 is changed to three levels of In 0.14 Al 0.86 N, In 0.18 Al 0.82 N, and In 0.24 Al 0.76 N.
  • the relationship between the surface roughness of the cap layer 6b and its thickness is illustrated.
  • the intermediate layer 6a is not provided for the HEMT element for the sake of easy discussion.
  • FIG. 3 illustrates the relationship between the reverse leakage current and the thickness of the cap layer 6b for the same HEMT element.
  • FIG. 4 illustrates the relationship between the contact resistance and the thickness of the cap layer 6b for the same HEMT element.
  • the value is maximum when the thickness of the cap layer 6b is 0 nm (that is, when the cap layer 6b is not provided), and the value is between the thickness of the cap layer 6b up to 0.5 nm. Drops sharply, and at 0.5 nm or more, it is almost flat at a smaller value (0.5 nm or less) than at 0 nm. This is because the surface flatness is improved by forming the cap layer 6b to a thickness of 0.5 nm or more, and the gate electrode 9 is provided on the cap layer 6b having excellent surface flatness. This means that the reverse leakage current is reduced. Further, the surface of the cap layer 6 b is flattened more than the surface of the barrier layer 5.
  • the contact resistance is substantially constant at 1.0 ⁇ 10 ⁇ 5 / ⁇ cm 2 or less, whereas the thickness of the cap layer 6b is 6 nm. It can be seen that the contact resistance increases abruptly when the value is exceeded. This result indicates that the thickness of the cap layer 6b should be 6 nm or less from the viewpoint of keeping the contact resistance of the ohmic electrode at a sufficiently low value.
  • the cap layer 6b is preferably formed to a thickness of 0.5 nm or more and 6 nm or less.
  • the HEMT device 20 includes an intermediate layer 6a between the barrier layer 5 and the cap layer 6b. This is to keep the mobility of the two-dimensional electron gas high. More specifically, when the cap layer 6b as described above is formed directly on the barrier layer 5, the mobility of the two-dimensional electron gas is reduced. Therefore, in the present embodiment, this is suppressed.
  • an intermediate layer 6a is formed on the barrier layer 5, and a cap layer 6b is formed thereon.
  • the thickness of the intermediate layer 6a is preferably 0.5 nm or more and 6 nm or less. By forming it to a thickness of 0.5 nm or more, higher mobility is realized as compared with the case where the intermediate layer 6a is not provided.
  • the upper limit of the thickness of the intermediate layer 6a may be determined within a range that is kept low without affecting the sheet resistance. For example, if the thickness of the cap layer 6b is 0.5 nm or more and 6 nm or less, the sheet resistance is reduced to 300 ⁇ / ⁇ or less by setting the thickness of the intermediate layer 6a to (0.5 nm or more) 6 nm or less.
  • the intermediate layer 6a and the cap layer 6b are entirely formed on the barrier layer 5, and not only directly below the gate electrode 9, but also directly below the source electrode 7 and the drain electrode 8. It can be said that it is also characteristic in that it is uniformly provided. Originally, if the intermediate layer 6a and the cap layer 6b exist only directly under the gate electrode 9, the effect of reducing the reverse leakage current can be obtained, but in order to realize such a configuration, photolithography is required. A process, an etching process, and the like are required, which causes a high cost.
  • the intermediate layer 6a and the cap layer 6b are only formed on the barrier layer 5 entirely, and since such a process is not performed, a HEMT device having excellent characteristics while suppressing cost is realized. It can be said that it is done.
  • the cap layer 6b, the intermediate layer 6a, and a part of the barrier layer 5 are removed by etching before forming both electrodes. After performing ohmic, the aspect which forms the source electrode 7 and the drain electrode 8 on the barrier layer 5 exposed by this may be sufficient.
  • the epitaxial substrate 10 can be manufactured using a known MOCVD furnace. Specifically, organometallic (MO) source gases (TMI, TMA, TMG), ammonia gas (NH 3 gas), hydrogen gas, and nitrogen gas for In, Al, and Ga can be supplied into the reactor.
  • MOCVD furnace constructed as follows is used.
  • a 2 inch 6H-SiC substrate having a (0001) plane orientation is prepared as a base substrate 1, and the base substrate 1 is placed on a susceptor provided in a reactor of an MOCVD furnace. After replacing the inside of the reactor with vacuum gas, the temperature of the substrate is raised by susceptor heating after forming an atmosphere in a hydrogen / nitrogen mixed flow state while maintaining the reactor pressure at a predetermined value between 5 kPa and 50 kPa.
  • the susceptor temperature reaches a predetermined temperature (for example, 1050 ° C.) between 950 ° C. and 1250 ° C. which is the buffer layer formation temperature, Al source gas and NH 3 gas are introduced into the reactor, and the AlN layer as the buffer layer 2 is formed.
  • a predetermined temperature for example, 1050 ° C.
  • 950 ° C. and 1250 ° C. which is the buffer layer formation temperature
  • Al source gas and NH 3 gas are introduced into the reactor, and the AlN layer as the buffer layer 2 is formed.
  • the susceptor temperature is maintained at a predetermined channel layer formation temperature, an organometallic source gas and ammonia gas corresponding to the composition of the channel layer 3 are introduced into the reactor, and In x1 Al as the channel layer 3 is introduced.
  • the channel layer formation temperature T1 is a value determined according to the value of the AlN molar fraction y1 of the channel layer 3 from a temperature range of 950 ° C. or more and 1250 ° C. or less.
  • the reactor pressure at the time of forming the channel layer 3 is not particularly limited, and can be appropriately selected from the range of 10 kPa to atmospheric pressure (100 kPa).
  • the reactor When the In x1 Al y1 Ga z1 N layer is formed, the reactor is maintained in a nitrogen gas atmosphere with the susceptor temperature maintained, the reactor pressure is set to 10 kPa, and the organometallic source gas and ammonia gas are then reacted with the reactor. Then, an In x3 Al y3 Ga z3 N layer as the spacer layer 4 is formed to a predetermined thickness.
  • the susceptor temperature is maintained at a predetermined barrier layer forming temperature of 650 ° C. or higher and 800 ° C. or lower in order to form In x2 Al y2 N to be the barrier layer 5.
  • the internal pressure is maintained at a predetermined value between 1 kPa and 30 kPa.
  • ammonia gas and an organic metal source gas having a flow rate ratio corresponding to the composition of the barrier layer 5 are introduced into the reactor so that the so-called V / III ratio is a predetermined value between 3000 and 20000.
  • the susceptor temperature is set to a predetermined intermediate layer formation temperature, TMG and NH 3 gas are supplied, and the GaN layer as the intermediate layer 6a is formed. A predetermined thickness is formed.
  • TMA and NH 3 gas are supplied after the susceptor temperature is set to a predetermined cap layer forming temperature, and an AlN layer as the cap layer 6b is formed to a predetermined thickness. . If the cap layer 6b is formed, the epitaxial substrate 10 is manufactured.
  • a HEMT element is formed using this.
  • Each subsequent process is realized by a known method.
  • a multilayer metal pattern to be the source electrode 7 and the drain electrode 8 is formed at a formation target portion of the cap layer 6b by using a photolithography process and a vacuum deposition method.
  • a nitrogen gas atmosphere at a predetermined temperature of 650 ° C. to 1000 ° C. is applied to the epitaxial substrate 10 on which the source electrode 7 and the drain electrode 8 are formed. Inside, heat treatment is performed for several tens of seconds.
  • a multilayer metal pattern to be the gate electrode 9 is formed at a formation target portion of the cap layer 6b by using a photolithography process and a vacuum deposition method.
  • HEMT elements 20 are obtained by dicing into chips of a predetermined size.
  • the obtained HEMT element 20 is appropriately subjected to die bonding or wire bonding.
  • the intermediate layer made of GaN is provided on the barrier layer, the cap layer made of AlN is further provided, and the gate electrode is formed by Schottky junction to the cap layer.
  • the MIS junction By forming the MIS junction, the reverse leakage current is greatly reduced as compared with the case where the gate electrode is formed directly on the barrier layer by the Schottky junction, and the two-dimensional electron gas is formed.
  • a HEMT element having a high mobility is realized.
  • the HEMT element is described as an object.
  • an aspect in which the MIS junction is formed between the gate electrode and the barrier layer is another electronic device using a Schottky junction, for example, a shot
  • a Schottky junction for example, a shot
  • the cap layer 6b is formed of AlN, but the cap layer 6b is larger than the band gap of the second group III nitride and has an insulating group III nitride. It may be an aspect formed by.
  • the group III nitride has insulation means that the specific resistance is 10 8 ⁇ cm or more. If it has the specific resistance of the range, the MIS junction mentioned above is formed suitably. In addition, as long as the specific resistance is satisfied, the presence of conductive impurities is allowed in the cap layer 6b.
  • Example 1 Comparative Example 1, and Comparative Example
  • the epitaxial substrate 10 according to the above-described embodiment including the intermediate layer 6a and the cap layer 6b is prepared, and the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, and the sheet resistance And evaluated.
  • the epitaxial substrate 10 using this epitaxial substrate 10, four types of HEMT elements 20 having different configurations of the gate electrode 9 were produced, and the reverse leakage current when ⁇ 100 V was applied to each HEMT element 20 was evaluated.
  • Comparative Example 1 an epitaxial substrate not including both the intermediate layer 6a and the cap layer 6b was prepared, and the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, and the sheet resistance were evaluated.
  • four types of HEMT devices were fabricated by forming the gate electrode 9 on the epitaxial substrate in the same manner as in Example 1, and the reverse leakage current when -100 V was applied was evaluated for each HEMT device. .
  • Comparative Example 2 an epitaxial substrate provided with only the cap layer 6b without the intermediate layer 6a was prepared, and the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, and the sheet resistance were evaluated.
  • four types of HEMT devices were fabricated by forming the gate electrode 9 on the epitaxial substrate in the same manner as in Example 1, and the reverse leakage current when -100 V was applied was evaluated for each HEMT device. .
  • a total of 12 types of HEMT elements were obtained by forming four types of gate electrodes 9 having different configurations on three types of epitaxial substrates.
  • an epitaxial substrate 10 was produced. At that time, all the epitaxial substrates 10 were subjected to the same conditions until the formation of the spacer layer 4.
  • the base substrate 1 a plurality of 2 inch 6H—SiC substrates having a (0001) plane orientation were prepared. The thickness was 300 ⁇ m. About each board
  • the susceptor temperature was set to a predetermined temperature
  • TMG bubbling gas as an organic metal source gas and ammonia gas were introduced into the reactor at a predetermined flow ratio, and a GaN layer as a channel layer 3 was formed to a thickness of 2 ⁇ m. .
  • the reactor pressure was set to 10 kPa, then TMA bubbling gas and ammonia gas were introduced into the reactor, and an AlN layer having a thickness of 1 nm was formed as the spacer layer 4.
  • the barrier layer 5 was subsequently formed to a thickness of 15 nm.
  • the composition of the barrier layer 5 was In 0.18 Al 0.82 N.
  • the susceptor temperature was 745 ° C.
  • a GaN layer as the intermediate layer 6a is formed to a thickness of 3 nm, and then the cap layer 6b.
  • the AlN layer was formed to a thickness of 3 nm.
  • the cap layer 6b was formed to a thickness of 3 nm.
  • nothing was formed.
  • each epitaxial substrate 10 was obtained by the above procedure.
  • the gate electrode 9 includes three types of multilayer metal electrodes, Ni / Au (film thickness 6 nm / 12 nm), Pd / Au (6 nm / 12 nm), and Pt / Au (6 nm / 12 nm), and a single-layer metal made of only Au. A total of four types with electrodes (12 nm) were formed.
  • the gate electrode 9 was formed such that the gate length was 1 ⁇ m, the gate width was 100 ⁇ m, the distance from the source electrode 7 was 2 ⁇ m, and the distance from the drain electrode was 10 ⁇ m.
  • the obtained HEMT device was subjected to die bonding and wire bonding, and the reverse leakage current when -100 V was applied was measured.
  • the structure of the intermediate layer 6a and the cap layer 6b of the epitaxial substrate, the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, the sheet resistance, the structure of the gate electrode for each HEMT element, and Table 1 lists the measurement results of the reverse leakage current when 100 V is applied.
  • providing the intermediate layer 6a on the barrier layer 5 and then providing the cap layer 6b is effective in reducing the reverse leakage current while suitably maintaining the two-dimensional electron gas concentration and the sheet resistance. It shows that there is.
  • Example 2 HEMT devices were produced in which the thickness of the intermediate layer 6a was variously changed, including the case where the intermediate layer 6a was not provided. Specifically, the thickness of the intermediate layer 6a is set to eight levels of 0 nm, 0.1 nm, 0.5 nm, 1.5 nm, 3 nm, 6 nm, 8 nm, and 10 nm, while the material for forming the gate electrode 9 is Ni / Au ( A HEMT device was fabricated in the same procedure as in Example 1 except that the thickness was only 6 nm / 12 nm.
  • Example 2 the Hall effect measurement was performed in the same manner as in Example 1 when an epitaxial substrate was obtained during the HEMT element fabrication. Thereby, the two-dimensional electron gas concentration, the two-dimensional electron gas mobility, and the sheet resistance were determined for each epitaxial substrate.
  • the thickness of the epitaxial substrate For each HEMT element, the thickness of the epitaxial substrate, the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, the sheet resistance, and the measurement result of the reverse leakage current when applying ⁇ 100 V to the HEMT element are shown.
  • Table 2 shows a list.
  • the thickness of the intermediate layer 6a when the thickness of the intermediate layer 6a is 0.5 nm or more, the mobility of the two-dimensional electron gas is higher than when the intermediate layer 6a is not provided. Further, if the thickness of the intermediate layer 6a is 6 nm or less, the value of the two-dimensional electron gas concentration is almost the same as the case where the intermediate layer 6a is not provided. Furthermore, if the thickness of the intermediate layer 6a is 0.5 nm or more and 6 nm or less, the value of the sheet resistance is kept at a value of 300 ⁇ / ⁇ or lower, which is lower than when the intermediate layer 6a is not provided. .
  • the value of the leakage current is 1/1000 or less of the case of Comparative Example 1 shown in Table 1 (when the gate electrode is the same Ni / Au). Has been reduced to.
  • the intermediate layer 6a between the cap layer 6b and the barrier layer 5 is formed to a thickness of 0.5 nm or more, the leakage current is reduced and the mobility of the two-dimensional electron gas is high. It can be seen that a HEMT element is realized. Furthermore, it can be seen that a HEMT element having a high two-dimensional electron gas concentration and a low sheet resistance can be realized by setting the thickness of the intermediate layer 6a to 6 nm or less.

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Abstract

Provided is a semiconductor element wherein a reverse-direction leak current is suppressed, and mobility of a two-dimensional electron gas is high. This semiconductor element is provided with: an epitaxial substrate, which is formed by laminating, on a base substrate, a III nitride layer group such that the (0001) crystal plane is substantially parallel to the substrate surface; and a Schottky electrode. The epitaxial substrate is provided with: a channel layer formed of a first III nitride having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1, z1>0); a barrier layer formed of a second III nitride having a composition of Inx2Aly2N (x2+y2=1, x2>0, y2>0); an intermediate layer, which is formed of GaN, and which is adjacent to the barrier layer; and a cap layer, which is formed of AlN, and which is adjacent to the intermediate layer. The Schottky electrode is formed by being bonded to the cap layer.

Description

半導体素子、ＨＥＭＴ素子、および半導体素子の製造方法Semiconductor device, HEMT device, and method for manufacturing semiconductor device
　本発明は、半導体素子に関し、特に、III族窒化物半導体により構成される多層構造エピタキシャル基板と金属電極とのショットキーダイオード接合を有する半導体素子に関する。 The present invention relates to a semiconductor element, and more particularly to a semiconductor element having a Schottky diode junction between a multilayer structure epitaxial substrate made of a group III nitride semiconductor and a metal electrode.
　窒化物半導体は、高い絶縁破壊電界、高い飽和電子速度を有することから次世代の高周波／ハイパワーデバイス用半導体材料として注目されている。例えば、ＡｌＧａＮからなる障壁層とＧａＮからなるチャネル層とを積層してなるＨＥＭＴ（高電子移動度トランジスタ）素子は、窒化物材料特有の大きな分極効果（自発分極効果とピエゾ分極効果）により積層界面（ヘテロ界面）に高濃度の二次元電子ガス（２ＤＥＧ）が生成するという特徴を活かしたものである（例えば、非特許文献１参照）。 Nitride semiconductors are attracting attention as semiconductor materials for next-generation high-frequency / high-power devices because they have a high breakdown electric field and a high saturation electron velocity. For example, a HEMT (High Electron Mobility Transistor) element formed by laminating a barrier layer made of AlGaN and a channel layer made of GaN has a laminated interface due to a large polarization effect (spontaneous polarization effect and piezoelectric polarization effect) peculiar to nitride materials. This utilizes the feature that a high-concentration two-dimensional electron gas (2DEG) is generated at the (heterointerface) (see, for example, Non-Patent Document 1).
　ＨＥＭＴ素子用基板の下地基板として、例えばシリコンやＳｉＣのような、III族窒化物とは異なる組成の単結晶（異種単結晶）を用いることがある。この場合、歪み超格子層や低温成長緩衝層などの緩衝層が、初期成長層として下地基板の上に形成されるのが一般的である。よって、下地基板の上に障壁層、チャネル層、および緩衝層をエピタキシャル形成してなるのが、異種単結晶からなる下地基板を用いたＨＥＭＴ素子用基板の最も基本的な構成態様となる。これに加えて、障壁層とチャネル層の間に、二次元電子ガスの空間的な閉じ込めを促進する目的として、厚さ１ｎｍ前後のスペーサ層が設けられることもある。スペーサ層は、例えばＡｌＮなどで構成される。さらには、ＨＥＭＴ素子用基板の最表面におけるエネルギー準位の制御や、電極とのコンタクト特性の改善を目的として、例えばｎ型ＧａＮ層や超格子層からなるキャップ層が、障壁層の上に形成される場合もある。 As a base substrate of a substrate for a HEMT element, a single crystal (heterogeneous single crystal) having a composition different from that of a group III nitride such as silicon or SiC may be used. In this case, a buffer layer such as a strained superlattice layer or a low temperature growth buffer layer is generally formed on the base substrate as an initial growth layer. Therefore, epitaxially forming the barrier layer, the channel layer, and the buffer layer on the base substrate is the most basic configuration of the HEMT element substrate using the base substrate made of different single crystals. In addition, a spacer layer having a thickness of about 1 nm may be provided between the barrier layer and the channel layer for the purpose of promoting spatial confinement of the two-dimensional electron gas. The spacer layer is made of, for example, AlN. Furthermore, a cap layer made of, for example, an n-type GaN layer or a superlattice layer is formed on the barrier layer for the purpose of controlling the energy level at the outermost surface of the substrate for HEMT elements and improving the contact characteristics with the electrode. Sometimes it is done.
　チャネル層をＧａＮにて形成し、障壁層をＡｌＧａＮにて形成するという、最も一般的な構成の窒化物ＨＥＭＴ素子の場合、ＨＥＭＴ素子用基板に内在する二次元電子ガスの濃度は、障壁層を形成するＡｌＧａＮのＡｌＮモル分率の増加に伴い増加することが知られている（例えば、非特許文献２参照）。二次元電子ガス濃度を大幅に増やすことができれば、ＨＥＭＴ素子の可制御電流密度、すなわち取り扱える電力密度を大幅に向上させることが可能と考えられる。 In the case of a nitride HEMT device having the most general configuration in which the channel layer is formed of GaN and the barrier layer is formed of AlGaN, the concentration of the two-dimensional electron gas existing in the substrate for the HEMT device is It is known that it increases with an increase in the AlN mole fraction of AlGaN to be formed (see, for example, Non-Patent Document 2). If the two-dimensional electron gas concentration can be significantly increased, it is considered that the controllable current density of the HEMT element, that is, the power density that can be handled, can be significantly improved.
　また、チャネル層をＧａＮにて形成し、障壁層をＩｎＡｌＮにて形成したＨＥＭＴ素子のように、ピエゾ分極効果への依存が小さくほぼ自発分極のみにより高い濃度で二次元電子ガスを生成できる歪の少ない構造を有するＨＥＭＴ素子も注目されている（例えば、非特許文献３参照）。 In addition, unlike HEMT devices in which the channel layer is formed of GaN and the barrier layer is formed of InAlN, the strain is less dependent on the piezoelectric polarization effect and can generate a two-dimensional electron gas at a high concentration only by spontaneous polarization. A HEMT element having a small number of structures is also attracting attention (see, for example, Non-Patent Document 3).
　チャネル層をＧａＮにて形成し、障壁層をＩｎＡｌＮにて形成することにより、ＨＥＭＴ素子を作製する場合、ゲート電極と障壁層との接合はショットキー接合とされるのが一般的である。しかしながら、この場合、ＩｎＡｌＮ層の組成や形成条件によっては、ショットキー接合への逆方向電圧印加の際に、大きな漏れ電流が発生することがある。 When a HEMT device is manufactured by forming the channel layer with GaN and the barrier layer with InAlN, the junction between the gate electrode and the barrier layer is generally a Schottky junction. However, in this case, depending on the composition and formation conditions of the InAlN layer, a large leakage current may be generated when a reverse voltage is applied to the Schottky junction.
　この漏れ電流は、ＩｎＡｌＮ層上にＡｌＮからなるコンタクト層を形成することによって低減させることが可能であるが、一方で、係る構成のＨＥＭＴ素子には、二次元電子ガスの移動度が低いという問題が生じる。これは、ＡｌＮ層の格子定数がＩｎＡｌＮ層に比して小さいために、ＩｎＡｌＮ層に歪が発生することが原因であると推定される。 This leakage current can be reduced by forming a contact layer made of AlN on the InAlN layer. On the other hand, the HEMT element having such a configuration has a low mobility of the two-dimensional electron gas. Occurs. This is presumed to be caused by distortion in the InAlN layer because the lattice constant of the AlN layer is smaller than that of the InAlN layer.
　本発明は、以上の課題に鑑みてなされたものであり、逆方向漏れ電流が抑制されてなるとともに二次元電子ガスの移動度が高い半導体素子を提供することを目的とする。 The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor element in which reverse leakage current is suppressed and the mobility of a two-dimensional electron gas is high.
　上記課題を解決するため、本発明の第１の態様では、下地基板の上にIII族窒化物層群を（０００１）結晶面が基板面に対し略平行となるよう積層形成したエピタキシャル基板と、ショットキー性電極と、を備える半導体素子において、前記エピタキシャル基板が、Ｉｎｘ１Ａｌｙ１Ｇａｚ１Ｎ（ｘ１＋ｙ１＋ｚ１＝１、ｚ１＞０）なる組成の第１のIII族窒化物からなるチャネル層と、Ｉｎｘ２Ａｌｙ２Ｎ（ｘ２＋ｙ２＝１、ｘ２＞０、ｙ２＞０）なる組成の第２のIII族窒化物からなる障壁層と、ＧａＮからなり前記障壁層に隣接する中間層と、ＡｌＮからなり前記中間層に隣接するキャップ層と、を備え、前記ショットキー性電極が前記キャップ層に接合されてなるようにした。 In order to solve the above problem, in the first aspect of the present invention, an epitaxial substrate in which a group (III) nitride layer group is formed on a base substrate so that the (0001) crystal plane is substantially parallel to the substrate surface; In a semiconductor device including a Schottky electrode, the epitaxial substrate includes a channel layer made of a first group III nitride having a composition of In x1 Al y1 Ga z1 N (x1 + y1 + z1 = 1, z1> 0), In x2 Al y2 N (x2 + y2 = 1, x2> 0, y2> 0) and a barrier layer made of made of a second group III nitride having a composition, an intermediate layer adjacent to the barrier layer consists of GaN, the composed AlN A cap layer adjacent to the intermediate layer, and the Schottky electrode is bonded to the cap layer.
　本発明の第２の態様では、第１の態様に係る半導体素子において、前記中間層の膜厚が０．５ｎｍ以上であるようにした。 In the second aspect of the present invention, in the semiconductor element according to the first aspect, the film thickness of the intermediate layer is 0.5 nm or more.
　本発明の第３の態様では、第２の態様に係る半導体素子において、前記中間層の膜厚が６ｎｍ以下であるようにした。 In the third aspect of the present invention, in the semiconductor element according to the second aspect, the film thickness of the intermediate layer is 6 nm or less.
　本発明の第４の態様では、第１ないし第３のいずれかの態様に係る半導体素子において、前記キャップ層の膜厚が０．５ｎｍ以上６ｎｍ以下であるようにした。 In the fourth aspect of the present invention, in the semiconductor element according to any one of the first to third aspects, the thickness of the cap layer is 0.5 nm or more and 6 nm or less.
　本発明の第５の態様では、第１ないし第４のいずれかの態様に係る半導体素子において、前記第２のIII族窒化物のバンドギャップが前記第１のIII族窒化物のバンドギャップよりも大きいようにした。 According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the band gap of the second group III nitride is larger than the band gap of the first group III nitride. I made it bigger.
　本発明の第６の態様では、第１ないし第５のいずれかの態様に係る半導体素子において、前記ショットキー性電極がＮｉ、Ｐｔ、Ｐｄ、Ａｕの少なくとも１つを含んでなるようにした。 In the sixth aspect of the present invention, in the semiconductor element according to any one of the first to fifth aspects, the Schottky electrode includes at least one of Ni, Pt, Pd, and Au.
　本発明の第７の態様では、第１ないし第６のいずれかの態様に係る半導体素子において、前記キャップ層の自乗平均表面粗さが０．５ｎｍ以下であるようにした。 In the seventh aspect of the present invention, in the semiconductor element according to any one of the first to sixth aspects, the root mean square surface roughness of the cap layer is 0.5 nm or less.
　本発明の第８の態様では、第１ないし第７のいずれかの態様に係る半導体素子において、前記第２のIII族窒化物が、Ｉｎｘ２Ａｌｙ２Ｎ（ｘ２＋ｙ２＝１、０．１４≦ｘ２≦０．２４）であるようにした。 According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to seventh aspects, the second group III nitride is In x2 Al y2 N (x2 + y2 = 1, 0.14 ≦ x2 ≦ 0.24).
　本発明の第９の態様では、第１ないし第８のいずれかの態様に係る半導体素子において、前記第１のIII族窒化物がＡｌｙ１Ｇａｚ１Ｎ（ｙ１＋ｚ１＝１、ｚ１＞０）であるようにした。 In a ninth aspect of the present invention, in the semiconductor element according to any one of the first to eighth aspects, the first group III nitride is Al y1 Ga z1 N (y1 + z1 = 1, z1> 0). I did it.
　本発明の第１０の態様では、第９の態様に係る半導体素子において、前記第１のIII族窒化物がＧａＮであるようにした。 In the tenth aspect of the present invention, in the semiconductor element according to the ninth aspect, the first group III nitride is GaN.
　本発明の第１１の態様では、第９または第１０の態様に係る半導体素子が、前記チャネル層と前記障壁層との間に、Ｉｎｘ３Ａｌｙ３Ｇａｚ３Ｎ（ｘ３＋ｙ３＋ｚ３＝１、ｙ３＞０）なる組成を有し、前記第２のIII族窒化物よりもバンドギャップが大きい第３のIII族窒化物からなるスペーサ層を、さらに備えるようにした。 In an eleventh aspect of the present invention, the semiconductor element according to the ninth or tenth aspect includes In x3 Al y3 Ga z3 N (x3 + y3 + z3 = 1, y3> 0) between the channel layer and the barrier layer. And a spacer layer made of a third group III nitride having a composition and a band gap larger than that of the second group III nitride.
　本発明の第１２の態様では、第１１の態様に係る半導体素子において、前記第３のIII族窒化物がＡｌＮであるようにした。 In the twelfth aspect of the present invention, in the semiconductor element according to the eleventh aspect, the third group III nitride is AlN.
　本発明の第１３の態様では、第１ないし第１２のいずれかの態様に係る半導体素子において、オーミック性電極が前記ショットキー性電極と同一の前記キャップ層に接合されてなるようにした。 In the thirteenth aspect of the present invention, in the semiconductor element according to any one of the first to twelfth aspects, an ohmic electrode is bonded to the same cap layer as the Schottky electrode.
　本発明の第１４の態様では、第１３の態様に係る半導体素子であるＨＥＭＴ素子において、前記ショットキー性電極がゲート電極であり、前記オーミック性電極がソース電極およびドレイン電極であるようにした。 In the fourteenth aspect of the present invention, in the HEMT element which is a semiconductor element according to the thirteenth aspect, the Schottky electrode is a gate electrode, and the ohmic electrode is a source electrode and a drain electrode.
　本発明の第１５の態様では、下地基板の上にIII族窒化物層群を（０００１）結晶面が基板面に対し略平行となるよう積層形成したエピタキシャル基板と、ショットキー性電極と、を備える半導体素子の製造方法が、下地基板の上に、Ｉｎｘ１Ａｌｙ１Ｇａｚ１Ｎ（ｘ１＋ｙ１＋ｚ１＝１、ｚ１＞０）なる組成の第１のIII族窒化物にてチャネル層を形成するチャネル層形成工程と、前記チャネル層の上に、Ｉｎｘ２Ａｌｙ２Ｎ（ｘ２＋ｙ２＝１、ｘ２＞０、ｙ２＞０）なる組成の第２のIII族窒化物にて障壁層を形成する障壁層形成工程と、ＧａＮにて中間層を前記障壁層に隣接形成する中間層形成工程と、ＡｌＮにてキャップ層を前記中間層に隣接形成するキャップ層形成工程と、前記キャップ層にショットキー性電極を接合形成するショットキー性電極形成工程と、を備えるようにした。 In a fifteenth aspect of the present invention, an epitaxial substrate obtained by stacking a group III nitride layer group on a base substrate so that a (0001) crystal plane is substantially parallel to the substrate surface, and a Schottky electrode, A method for manufacturing a semiconductor device comprising: forming a channel layer on a base substrate by forming a channel layer with a first group III nitride having a composition of In x1 Al y1 Ga z1 N (x1 + y1 + z1 = 1, z1> 0) And a barrier layer forming step of forming a barrier layer on the channel layer with a second group III nitride having a composition of In x2 Al y2 N (x2 + y2 = 1, x2> 0, y2> 0) , An intermediate layer forming step of forming an intermediate layer adjacent to the barrier layer with GaN, a cap layer forming step of forming a cap layer adjacent to the intermediate layer with AlN, and a Schottky electrode bonded to the cap layer To And a Cottky electrode forming step.
　本発明の第１６の態様では、第１５の態様に係る半導体素子の製造方法において、前記中間層を０．５ｎｍ以上の厚みに形成するようにした。 In the sixteenth aspect of the present invention, in the method for manufacturing a semiconductor element according to the fifteenth aspect, the intermediate layer is formed to a thickness of 0.5 nm or more.
　本発明の第１７の態様では、第１６の態様に係る半導体素子の製造方法において、前記中間層を６ｎｍ以下の厚みに形成するようにした。 In the seventeenth aspect of the present invention, in the semiconductor element manufacturing method according to the sixteenth aspect, the intermediate layer is formed to a thickness of 6 nm or less.
　本発明の第１８の態様では、第１５ないし第１７のいずれかの態様に係る半導体素子の製造方法において、前記キャップ層を０．５ｎｍ以上６ｎｍ以下の厚みに形成するようにした。 In the eighteenth aspect of the present invention, in the method for manufacturing a semiconductor element according to any one of the fifteenth to seventeenth aspects, the cap layer is formed to a thickness of 0.5 nm or more and 6 nm or less.
　本発明の第１９の態様では、第１５ないし第１８のいずれかの態様に係る半導体素子の製造方法において、前記第２のIII族窒化物のバンドギャップが前記第１のIII族窒化物のバンドギャップよりも大きいようにした。 According to a nineteenth aspect of the present invention, in the semiconductor device manufacturing method according to any one of the fifteenth to eighteenth aspects, the band gap of the second group III nitride is the band of the first group III nitride. It was made larger than the gap.
　本発明の第２０の態様では、第１５ないし第１９のいずれかの態様に係る半導体素子の製造方法において、前記ショットキー性電極形成工程においては、前記ショットキー性電極をＮｉ、Ｐｔ、Ｐｄ、Ａｕの少なくとも１つを含むように形成するようにした。 In a twentieth aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the fifteenth to nineteenth aspects, in the Schottky electrode formation step, the Schottky electrode is formed of Ni, Pt, Pd, It was formed so as to include at least one of Au.
　本発明の第２１の態様では、第１５ないし第２０のいずれかの態様に係る半導体素子の製造方法において、前記第２のIII族窒化物が、Ｉｎｘ２Ａｌｙ２Ｎ（ｘ２＋ｙ２＝１、０．１４≦ｘ２≦０．２４）であるようにした。 In a twenty-first aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the fifteenth to twentieth aspects, the second group III nitride is In x2 Al y2 N (x2 + y2 = 1, 0. 14 ≦ x2 ≦ 0.24).
　本発明の第２２の態様では、第１５ないし第２１のいずれかの態様に係る半導体素子の製造方法において、前記第１のIII族窒化物がＡｌｙ１Ｇａｚ１Ｎ（ｙ１＋ｚ１＝１、ｚ１＞０）であるようにした。 According to a twenty-second aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the fifteenth to twenty-first aspects, the first group III nitride is Al y1 Ga z1 N (y1 + z1 = 1, z1> 0). ).
　本発明の第２３の態様では、第２２の態様に係る半導体素子の製造方法において、前記第１のIII族窒化物がＧａＮであるようにした。 In the twenty-third aspect of the present invention, in the method for manufacturing a semiconductor device according to the twenty-second aspect, the first group III nitride is GaN.
　本発明の第２４の態様では、第２２または第２３の態様に係る半導体素子の製造方法が、前記チャネル層と前記障壁層との間に、Ｉｎｘ３Ａｌｙ３Ｇａｚ３Ｎ（ｘ３＋ｙ３＋ｚ３＝１、ｙ３＞０）なる組成を有し、前記第２のIII族窒化物よりもバンドギャップが大きい第３のIII族窒化物にてスペーサ層を形成するスペーサ層形成工程、をさらに備えるようにした。 In a twenty-fourth aspect of the present invention, in the method for manufacturing a semiconductor element according to the twenty-second or twenty-third aspect, In x3 Al y3 Ga z3 N (x3 + y3 + z3 = 1, y3) is provided between the channel layer and the barrier layer. A spacer layer forming step of forming a spacer layer with a third group III nitride having a composition of> 0) and a band gap larger than that of the second group III nitride.
　本発明の第２５の態様では、第２４の態様に係る半導体素子の製造方法において、前記第３のIII族窒化物がＡｌＮであるようにした。 In the twenty-fifth aspect of the present invention, in the semiconductor element manufacturing method according to the twenty-fourth aspect, the third group III nitride is AlN.
　本発明の第２６の態様では、第１５ないし第２５のいずれかの態様に係る半導体素子の製造方法が、前記ショットキー性電極が形成される前記キャップ層にオーミック性電極を接合形成するオーミック性電極形成工程、をさらに備えるようにした。 In a twenty-sixth aspect of the present invention, the method for manufacturing a semiconductor device according to any one of the fifteenth to twenty-fifth aspects includes an ohmic property in which an ohmic electrode is bonded to the cap layer on which the Schottky electrode is formed. An electrode forming step.
　本発明の第１ないし第２６の態様によれば、障壁層の上にＧａＮからなる中間層とＡｌＮからなるキャップ層をこの順に設け、該キャップ層に対してショットキー接合により電極形成を行い、ＭＩＳ接合を形成することで、障壁層の上に直接にショットキー接合により電極形成を行う場合に比して、逆方向漏れ電流が抑制され、かつ二次元電子ガスの移動度が高く保たれた半導体素子が実現される。 According to the first to twenty-sixth aspects of the present invention, the intermediate layer made of GaN and the cap layer made of AlN are provided in this order on the barrier layer, and electrodes are formed on the cap layer by Schottky junction, By forming the MIS junction, the reverse leakage current is suppressed and the mobility of the two-dimensional electron gas is kept high as compared with the case where the electrode is formed directly on the barrier layer by the Schottky junction. A semiconductor element is realized.
本発明の実施の形態に係る半導体素子の一態様であるＨＥＭＴ素子２０の構成を概略的に示す断面模式図である。It is a cross-sectional schematic diagram which shows roughly the structure of the HEMT element 20 which is one aspect | mode of the semiconductor element which concerns on embodiment of this invention. キャップ層６ｂの表面粗さとその厚みとの関係を例示する図である。It is a figure which illustrates the relationship between the surface roughness of the cap layer 6b, and its thickness. 逆方向漏れ電流とキャップ層６ｂとの関係を例示する図である。It is a figure which illustrates the relationship between reverse direction leakage current and the cap layer 6b. オーミック性電極におけるコンタクト抵抗をキャップ層６ｂの厚みに対してプロットした図である。It is the figure which plotted the contact resistance in an ohmic electrode with respect to the thickness of the cap layer 6b.
　　＜ＨＥＭＴ素子の構成＞
　図１は、本発明の実施の形態に係る半導体素子の一態様であるＨＥＭＴ素子２０の構成を概略的に示す断面模式図である。ＨＥＭＴ素子２０は、概略、エピタキシャル基板１０の上に、ソース電極７、ドレイン電極８、およびゲート電極９を設けた構成を有する。具体的には、エピタキシャル基板１０は、下地基板１と、バッファ層２と、チャネル層３と、スペーサ層４と、障壁層５と、中間層６ａと、キャップ層６ｂとが積層形成された構成を有する。そして、キャップ層６ｂの上に、ソース電極７、ドレイン電極８、およびゲート電極９が形成されてなる。なお、図１における各層の厚みの比率は、実際のものを反映したものではない。バッファ層２と、チャネル層３と、スペーサ層４と、障壁層５と、中間層６ａと、キャップ層６ｂとはいずれも、ＭＯＣＶＤ法（有機金属化学的気相成長法）を用いてエピタキシャル形成される（詳細は後述）のが好適な一例である。 <Configuration of HEMT element>
FIG. 1 is a schematic cross-sectional view schematically showing a configuration of a HEMT element 20 which is an aspect of a semiconductor element according to an embodiment of the present invention. The HEMT element 20 generally has a configuration in which a source electrode 7, a drain electrode 8, and a gate electrode 9 are provided on an epitaxial substrate 10. Specifically, the epitaxial substrate 10 has a configuration in which a base substrate 1, a buffer layer 2, a channel layer 3, a spacer layer 4, a barrier layer 5, an intermediate layer 6a, and a cap layer 6b are stacked. Have A source electrode 7, a drain electrode 8, and a gate electrode 9 are formed on the cap layer 6b. In addition, the ratio of the thickness of each layer in FIG. 1 does not reflect the actual one. The buffer layer 2, the channel layer 3, the spacer layer 4, the barrier layer 5, the intermediate layer 6a, and the cap layer 6b are all formed epitaxially using MOCVD (metal organic chemical vapor deposition). (A detail will be described later) is a suitable example.
　以降においては、各層の形成にＭＯＣＶＤ法を用いる場合を対象に説明を行うが、良好な結晶性を有するように各層を形成できる手法であれば、他のエピタキシャル成長手法、例えば、ＭＢＥ、ＨＶＰＥ、ＬＰＥなど、種々の気相成長法や液相成長法の中から適宜選択した手法を用いてもよいし、異なる成長法を組み合わせて用いる態様であってもよい。 In the following description, the case where the MOCVD method is used for forming each layer will be described. However, other epitaxial growth methods such as MBE, HVPE, and LPE can be used as long as each layer can be formed so as to have good crystallinity. For example, a method appropriately selected from various vapor phase growth methods and liquid phase growth methods may be used, or a mode in which different growth methods are used in combination may be used.
　下地基板１は、その上に結晶性の良好な窒化物半導体層を形成できるものであれば、特段の制限なく用いることができる。単結晶６Ｈ－ＳｉＣ基板を用いるのが好適な一例であるが、サファイア、Ｓｉ、ＧａＡｓ、スピネル、ＭｇＯ、ＺｎＯ、フェライトなどからなる基板を用いる態様であってもよい。 The base substrate 1 can be used without any particular limitation as long as a nitride semiconductor layer with good crystallinity can be formed thereon. A single crystal 6H—SiC substrate is preferably used, but an embodiment using a substrate made of sapphire, Si, GaAs, spinel, MgO, ZnO, ferrite, or the like may be used.
　また、バッファ層２は、その上に形成されるチャネル層３、スペーサ層４、障壁層５、中間層６ａ、およびキャップ層６ｂの結晶品質を良好なものとするべく、ＡｌＮにて数百ｎｍ程度の厚みに形成される層である。例えば、２００ｎｍの厚みに形成するのが好適な一例である。 Further, the buffer layer 2 is made of several hundreds of nanometers in AlN in order to improve the crystal quality of the channel layer 3, the spacer layer 4, the barrier layer 5, the intermediate layer 6a, and the cap layer 6b formed thereon. It is a layer formed to a certain thickness. For example, it is a preferable example that the thickness is 200 nm.
　チャネル層３は、Ｉｎｘ１Ａｌｙ１Ｇａｚ１Ｎ（ｘ１＋ｙ１＋ｚ１＝１）なる組成のIII族窒化物（第１のIII族窒化物）にて、数μｍ程度の厚みに形成される層である。好ましくは、チャネル層３はＡｌｙ１Ｇａｚ１Ｎ（ｙ１＋ｚ１＝１、ｚ１＞０）組成のIII族窒化物にて形成され、より好ましくは、ＧａＮにて形成される。 The channel layer 3 is a group III nitride (first group III nitride) having a composition of In x1 Al y1 Ga z1 N (x1 + y1 + z1 = 1) and is formed to a thickness of about several μm. Preferably, the channel layer 3 is formed of a group III nitride having a composition of Al y1 Ga z1 N (y1 + z1 = 1, z1> 0), more preferably, GaN.
　一方、障壁層５は、Ｉｎｘ２Ａｌｙ２Ｎ（ｘ２＋ｙ２＝１、ｘ２＞、ｙ２＞０）なる組成を有するIII族窒化物（第２のIII族窒化物）にて、数ｎｍ～数十ｎｍ程度の厚みに形成される層である。好ましくは０．１４≦ｘ２≦０．２４である。ｘ２の値がこの範囲の外にある場合は、障壁層５に作用する歪みが±０．５％を超えることとなり、ショットキー接合の信頼性に及ぼす結晶歪みの影響が大きくなり始めるため好ましくない。 On the other hand, the barrier layer 5 is a group III nitride (second group III nitride) having a composition of In x2 Al y2 N (x2 + y2 = 1, x2>, y2> 0) and is several nm to several tens nm. It is a layer formed to a certain thickness. Preferably, 0.14 ≦ x2 ≦ 0.24. When the value of x2 is outside this range, the strain acting on the barrier layer 5 exceeds ± 0.5%, which is not preferable because the influence of crystal strain on the reliability of the Schottky junction starts to increase. .
　なお、チャネル層３と障壁層５とは、前者を構成する第１のIII族窒化物のバンドギャップよりも後者を構成する第２のIII族窒化物のバンドギャップの方が大きいという組成範囲をみたして形成される。 The channel layer 3 and the barrier layer 5 have a composition range in which the band gap of the second group III nitride constituting the latter is larger than the band gap of the first group III nitride constituting the former. It is formed.
　中間層６ａは、ＧａＮにて形成される層である。また、キャップ層６ｂは、ＡｌＮにて形成される層である。ＨＥＭＴ素子２０がこれら中間層６ａとキャップ層６ｂを有することの作用効果については後述する。 The intermediate layer 6a is a layer formed of GaN. The cap layer 6b is a layer formed of AlN. The effect of the HEMT element 20 having these intermediate layer 6a and cap layer 6b will be described later.
　さらに、チャネル層３と障壁層５の間にはスペーサ層４が設けられる。スペーサ層４は、Ｉｎｘ３Ａｌｙ３Ｇａｚ３Ｎ（ｘ３＋ｙ３＋ｚ３＝１）なる組成を有し、少なくともＡｌを含む（ｙ３＞０をみたす）III族窒化物（第３のIII族窒化物）にて、０．５ｎｍ～１．５ｎｍの範囲の厚みで形成される層である。 Further, a spacer layer 4 is provided between the channel layer 3 and the barrier layer 5. The spacer layer 4 has a composition of In x3 Al y3 Ga z3 N (x3 + y3 + z3 = 1), and includes at least Al (represents y3> 0) in a group III nitride (third group III nitride). It is a layer formed with a thickness in the range of 0.5 nm to 1.5 nm.
　このような層構成を有するエピタキシャル基板１０においては、チャネル層３とスペーサ層４の界面に（より詳細には、チャネル層３の当該界面近傍に）二次元電子ガスが高濃度に存在する二次元電子ガス領域３ｅが形成される。 In the epitaxial substrate 10 having such a layer structure, a two-dimensional electron gas is present at a high concentration at the interface between the channel layer 3 and the spacer layer 4 (more specifically, near the interface of the channel layer 3). An electron gas region 3e is formed.
　好ましくは、スペーサ層４と障壁層５とはそれぞれ、前者を構成する第３のIII族窒化物のバンドギャップが、後者を構成する第２のIII族窒化物のバンドギャップ以上という組成範囲をみたして形成される。係る場合、合金散乱効果が抑制され、二次元電子ガスの濃度および移動度が向上する。より好ましくは、スペーサ層４はＡｌＮ（ｘ３＝０、ｙ３＝１、ｚ３＝０）にて形成される。係る場合、スペーサ層４がＡｌとＮの二元系化合物となるので、Ｇａを含む３元系化合物の場合よりもさらに合金散乱効果が抑制され、二次元電子ガスの濃度および移動度が向上することとなる。なお、係る組成範囲についての議論は、スペーサ層４が不純物を含有することを除外するものではない。 Preferably, each of the spacer layer 4 and the barrier layer 5 has a composition range in which the band gap of the third group III nitride constituting the former is equal to or greater than the band gap of the second group III nitride constituting the latter. Formed. In such a case, the alloy scattering effect is suppressed, and the concentration and mobility of the two-dimensional electron gas are improved. More preferably, the spacer layer 4 is made of AlN (x3 = 0, y3 = 1, z3 = 0). In such a case, since the spacer layer 4 is a binary compound of Al and N, the alloy scattering effect is further suppressed as compared with the case of a ternary compound containing Ga, and the concentration and mobility of the two-dimensional electron gas are improved. It will be. Note that the discussion on the composition range does not exclude that the spacer layer 4 contains impurities.
　なお、エピタキシャル基板１０においてスペーサ層４を備えるのは必須の態様ではなく、チャネル層３の上に直接に障壁層５を形成する態様であってもよい。係る場合、チャネル層３と障壁層５の界面に二次元電子ガス領域３ｅが形成される。 It should be noted that providing the spacer layer 4 in the epitaxial substrate 10 is not an essential aspect, and may be an aspect in which the barrier layer 5 is formed directly on the channel layer 3. In such a case, a two-dimensional electron gas region 3 e is formed at the interface between the channel layer 3 and the barrier layer 5.
　ソース電極７とドレイン電極８とは、それぞれの金属層が十数ｎｍ～百数十ｎｍ程度の厚みを有する多層金属電極であり、キャップ層６ｂとの間にオーミック性接触を有してなる。ソース電極７およびドレイン電極８に用いる金属は、エピタキシャル基板１０に対し（キャップ層６ｂに対し）良好なオーミック性接触が得られる金属材料にて形成されればよい。Ｔｉ／Ａｌ／Ｎｉ／Ａｕからなる多層金属電極をソース電極７およびドレイン電極８として形成するのが好適であるが、これに限定されるものでなく、例えばＴｉ／Ａｌ／Ｐｔ／ＡｕあるいはＴｉ／Ａｌなどからなる多層金属電極を形成する態様であってもよい。ソース電極７およびドレイン電極８の形成は、フォトリソグラフィープロセスと真空蒸着法とにより行うことができる。 The source electrode 7 and the drain electrode 8 are multi-layer metal electrodes in which each metal layer has a thickness of about 10 to 100 nm, and has an ohmic contact with the cap layer 6b. The metal used for the source electrode 7 and the drain electrode 8 should just be formed with the metal material with which favorable ohmic contact is obtained with respect to the epitaxial substrate 10 (with respect to the cap layer 6b). It is preferable to form a multilayer metal electrode made of Ti / Al / Ni / Au as the source electrode 7 and the drain electrode 8, but the present invention is not limited to this. For example, Ti / Al / Pt / Au or Ti / An embodiment in which a multilayer metal electrode made of Al or the like may be formed. The source electrode 7 and the drain electrode 8 can be formed by a photolithography process and a vacuum deposition method.
　一方、ゲート電極９は、一または複数の金属層が十数ｎｍ～百数十ｎｍ程度の厚みを有するように形成されてなる単層または多層の金属電極であり、障壁層５との間にショットキー性接触を有してなる。ゲート電極９は、Ｐｄ、Ｐｔ、Ｎｉ、Ａｕなどの仕事関数が高い金属を形成材料として形成されるのが好適である。あるいは、上述の各金属同士の、あるいは各金属とＡｌなどとの多層金属膜として形成される態様であってもよい。なお、ＡｌＮからなるキャップ層６ｂを設けることから、上記に加えて、Ｔｉ／Ａｌを含む多層金属膜など、III族窒化物半導体との間でオーミック接合をなす場合に用いられる金属材料も、ゲート電極９の形成材料として利用可能である。なぜならば、この場合、バンドギャップが大きいＡｌＮと仕事関数が比較的小さい金属材料とが接合されるので、比較的容易にショットキー性のコンタクトが得られるからである。ゲート電極９の形成は、フォトリソグラフィープロセスと真空蒸着法とにより行うことができる。 On the other hand, the gate electrode 9 is a single-layer or multi-layer metal electrode in which one or a plurality of metal layers are formed so as to have a thickness of about ten to several hundreds of nanometers. It has a Schottky contact. The gate electrode 9 is preferably formed using a metal having a high work function such as Pd, Pt, Ni, or Au as a forming material. Or the aspect formed as a multilayer metal film of the above-mentioned each metal or each metal, Al, etc. may be sufficient. Since the cap layer 6b made of AlN is provided, in addition to the above, a metal material used for forming an ohmic junction with a group III nitride semiconductor such as a multilayer metal film containing Ti / Al is also used for the gate. It can be used as a material for forming the electrode 9. This is because, in this case, AlN having a large band gap and a metal material having a relatively small work function are joined, so that a Schottky contact can be obtained relatively easily. The gate electrode 9 can be formed by a photolithography process and a vacuum deposition method.
　　＜キャップ層とゲート電極とのショットキー接合＞
　上述のような構成を有するＨＥＭＴ素子２０においては、ゲート電極９と、キャップ層６ｂと、障壁層５とによって（厳密には中間層６ａを介して）、いわゆるＭＩＳ（metal-insulator-semiconductor）接合が形成されてなる。このようなＭＩＳ接合を有することで、ＨＥＭＴ素子２０は、障壁層５に対して直接にゲート電極９をショットキー接合させた従来のＨＥＭＴ素子よりも、原理上、逆方向漏れ電流が抑制されてなる。具体的な値は各部の組成や厚みなどによっても異なるが、本実施の形態のようにＨＥＭＴ素子２０を構成した場合には、例えば－１００Ｖ印加時の漏れ電流が、障壁層に直接にゲート電極を形成した場合の１／１００から１／１０００程度にまで抑制される。 <Schottky junction between cap layer and gate electrode>
In the HEMT device 20 having the above-described configuration, a so-called MIS (metal-insulator-semiconductor) junction is formed by the gate electrode 9, the cap layer 6b, and the barrier layer 5 (strictly, through the intermediate layer 6a). Is formed. By having such a MIS junction, the HEMT element 20 has, in principle, a reverse leakage current suppressed more than a conventional HEMT element in which the gate electrode 9 is directly Schottky-bonded to the barrier layer 5. Become. Although specific values vary depending on the composition and thickness of each part, when the HEMT device 20 is configured as in the present embodiment, for example, a leakage current when -100 V is applied is directly applied to the barrier electrode in the barrier layer. Is suppressed from about 1/100 to about 1/1000 when formed.
　図２ないし図４は、ＨＥＭＴ素子においてゲート電極９の直下にキャップ層６ｂを具備することの効果、つまりは、ＨＥＭＴ素子が上述のＭＩＳ接合を有することの効果を説明するための図である。具体的には、図２は、障壁層５の組成をＩｎ０．１４Ａｌ０．８６Ｎ、Ｉｎ０．１８Ａｌ０．８２Ｎ、Ｉｎ０．２４Ａｌ０．７６Ｎの３水準に違えた３種類のＨＥＭＴ素子について、キャップ層６ｂの表面粗さとその厚みとの関係を例示している。ただし、係るＨＥＭＴ素子については議論の簡単のため中間層６ａは設けていない。また、図３は、同じＨＥＭＴ素子について、逆方向漏れ電流とキャップ層６ｂの厚みとの関係を例示している。さらに、図４は、同じＨＥＭＴ素子についてコンタクト抵抗とキャップ層６ｂの厚みとの関係を例示している。 2 to 4 are diagrams for explaining the effect of providing the cap layer 6b immediately below the gate electrode 9 in the HEMT element, that is, the effect of the HEMT element having the MIS junction described above. Specifically, FIG. 2 shows that the composition of the barrier layer 5 is changed to three levels of In 0.14 Al 0.86 N, In 0.18 Al 0.82 N, and In 0.24 Al 0.76 N. For three types of HEMT elements, the relationship between the surface roughness of the cap layer 6b and its thickness is illustrated. However, the intermediate layer 6a is not provided for the HEMT element for the sake of easy discussion. FIG. 3 illustrates the relationship between the reverse leakage current and the thickness of the cap layer 6b for the same HEMT element. Furthermore, FIG. 4 illustrates the relationship between the contact resistance and the thickness of the cap layer 6b for the same HEMT element.
　図２および図３においてはいずれも、キャップ層６ｂの厚みが０ｎｍの場合（つまりはキャップ層６ｂを設けない場合）に値が最大で、キャップ層６ｂの厚みが０．５ｎｍまでの間で値が急落し、０．５ｎｍ以上では０ｎｍのときよりも小さな値（０．５ｎｍ以下）で概ね横ばいとなっている。このことは、キャップ層６ｂを０．５ｎｍ以上の厚みに形成することで、その表面平坦性が向上し、かつ、係る表面平坦性の優れたキャップ層６ｂの上にゲート電極９を設けることで、逆方向漏れ電流が低減されることを意味している。また、障壁層５の表面よりもキャップ層６ｂの表面の方が平坦化される。 2 and 3, the value is maximum when the thickness of the cap layer 6b is 0 nm (that is, when the cap layer 6b is not provided), and the value is between the thickness of the cap layer 6b up to 0.5 nm. Drops sharply, and at 0.5 nm or more, it is almost flat at a smaller value (0.5 nm or less) than at 0 nm. This is because the surface flatness is improved by forming the cap layer 6b to a thickness of 0.5 nm or more, and the gate electrode 9 is provided on the cap layer 6b having excellent surface flatness. This means that the reverse leakage current is reduced. Further, the surface of the cap layer 6 b is flattened more than the surface of the barrier layer 5.
　一方、図４においては、キャップ層６ｂの厚みが６ｎｍ以下の範囲ではコンタクト抵抗が１．０×１０－５／Ωｃｍ２以下でほぼ一定であるのに対して、キャップ層６ｂの厚みが６ｎｍを越えると、コンタクト抵抗が急激に増大することがわかる。係る結果は、オーミック性電極におけるコンタクト抵抗を十分に低い値に保つという観点からは、キャップ層６ｂの厚みを６ｎｍ以下とするのがよいことを示している。 On the other hand, in FIG. 4, when the thickness of the cap layer 6b is 6 nm or less, the contact resistance is substantially constant at 1.0 × 10 −5 / Ωcm 2 or less, whereas the thickness of the cap layer 6b is 6 nm. It can be seen that the contact resistance increases abruptly when the value is exceeded. This result indicates that the thickness of the cap layer 6b should be 6 nm or less from the viewpoint of keeping the contact resistance of the ohmic electrode at a sufficiently low value.
　以上のことから、キャップ層６ｂは、０．５ｎｍ以上６ｎｍ以下の厚みに形成するのが好適であることがわかる。 From the above, it can be seen that the cap layer 6b is preferably formed to a thickness of 0.5 nm or more and 6 nm or less.
　　＜中間層と二次元電子ガス濃度との関係＞
　また、本実施の形態に係るＨＥＭＴ素子２０は、障壁層５とキャップ層６ｂとの間に中間層６ａを備える。これは、二次元電子ガスの移動度を高く保つためである。より具体的には、上述のようなキャップ層６ｂを障壁層５の上に直接に形成した場合、二次元電子ガスの移動度が低下してしまうので、本実施の形態においては、これを抑制するために、障壁層５の上に中間層６ａを形成し、その上にキャップ層６ｂを形成する。 <Relationship between intermediate layer and 2D electron gas concentration>
In addition, the HEMT device 20 according to the present embodiment includes an intermediate layer 6a between the barrier layer 5 and the cap layer 6b. This is to keep the mobility of the two-dimensional electron gas high. More specifically, when the cap layer 6b as described above is formed directly on the barrier layer 5, the mobility of the two-dimensional electron gas is reduced. Therefore, in the present embodiment, this is suppressed. For this purpose, an intermediate layer 6a is formed on the barrier layer 5, and a cap layer 6b is formed thereon.
　なお、中間層６ａの厚みは、０．５ｎｍ以上６ｎｍ以下とするのが好適である。０．５ｎｍ以上の厚みに形成することで、中間層６ａを設けない場合に比して高い移動度が実現される。一方、中間層６ａの厚みの上限は、シート抵抗に影響を及ぼさない低く保たれる範囲で定めればよい。例えば、キャップ層６ｂの厚みが０．５ｎｍ以上６ｎｍ以下の場合であれば、中間層６ａの厚みを、（０．５ｎｍ以上）６ｎｍ以下とすることで、シート抵抗が３００Ω／□以下に低減される。 The thickness of the intermediate layer 6a is preferably 0.5 nm or more and 6 nm or less. By forming it to a thickness of 0.5 nm or more, higher mobility is realized as compared with the case where the intermediate layer 6a is not provided. On the other hand, the upper limit of the thickness of the intermediate layer 6a may be determined within a range that is kept low without affecting the sheet resistance. For example, if the thickness of the cap layer 6b is 0.5 nm or more and 6 nm or less, the sheet resistance is reduced to 300Ω / □ or less by setting the thickness of the intermediate layer 6a to (0.5 nm or more) 6 nm or less. The
　なお、本実施の形態に係るＨＥＭＴ素子２０は、中間層６ａおよびキャップ層６ｂが障壁層５の上に全面的に形成され、ゲート電極９の直下のみならずソース電極７およびドレイン電極８の直下にまで一様に備わっている点についても特徴的であるといえる。本来的には、ゲート電極９の直下にのみ中間層６ａおよびキャップ層６ｂが存在すれば、逆方向漏れ電流の低減という作用効果が得られるものの、そのような構成を実現するには、フォトリソグラフィープロセスやエッチングプロセスなどが必要となり、コスト高の要因となる。本実施の形態においては、中間層６ａおよびキャップ層６ｂを障壁層５の上に全面的に形成するのみであり、そうしたプロセスを行わないので、コストを抑制しつつ特性の優れたＨＥＭＴ素子が実現されているともいえる。もちろん、ソース電極７およびドレイン電極８を障壁層５の上に直接に形成するべく、両電極の形成前に、キャップ層６ｂ、中間層６ａ、障壁層５の一部をエッチングによって取り除く、いわゆるリセスオーミックを実施したうえで、これによって露出した障壁層５の上にソース電極７およびドレイン電極８を形成する態様であってもよい。 In the HEMT device 20 according to the present embodiment, the intermediate layer 6a and the cap layer 6b are entirely formed on the barrier layer 5, and not only directly below the gate electrode 9, but also directly below the source electrode 7 and the drain electrode 8. It can be said that it is also characteristic in that it is uniformly provided. Originally, if the intermediate layer 6a and the cap layer 6b exist only directly under the gate electrode 9, the effect of reducing the reverse leakage current can be obtained, but in order to realize such a configuration, photolithography is required. A process, an etching process, and the like are required, which causes a high cost. In the present embodiment, the intermediate layer 6a and the cap layer 6b are only formed on the barrier layer 5 entirely, and since such a process is not performed, a HEMT device having excellent characteristics while suppressing cost is realized. It can be said that it is done. Of course, in order to form the source electrode 7 and the drain electrode 8 directly on the barrier layer 5, the cap layer 6b, the intermediate layer 6a, and a part of the barrier layer 5 are removed by etching before forming both electrodes. After performing ohmic, the aspect which forms the source electrode 7 and the drain electrode 8 on the barrier layer 5 exposed by this may be sufficient.
　　＜ＨＥＭＴ素子の作製方法＞
　次に、上述のような構成を有するＨＥＭＴ素子２０を作製する方法を説明する。 <Method for Manufacturing HEMT Element>
Next, a method for manufacturing the HEMT device 20 having the above-described configuration will be described.
　まず、エピタキシャル基板１０の作製は、公知のＭＯＣＶＤ炉を用いて行うことができる。具体的には、Ｉｎ、Ａｌ、Ｇａについての有機金属（ＭＯ）原料ガス（ＴＭＩ、ＴＭＡ、ＴＭＧ）と、アンモニアガス（ＮＨ３ガス）と、水素ガスと、窒素ガスとをリアクタ内に供給可能に構成されてなるＭＯＣＶＤ炉を用いる。 First, the epitaxial substrate 10 can be manufactured using a known MOCVD furnace. Specifically, organometallic (MO) source gases (TMI, TMA, TMG), ammonia gas (NH 3 gas), hydrogen gas, and nitrogen gas for In, Al, and Ga can be supplied into the reactor. An MOCVD furnace constructed as follows is used.
　まず、例えば（０００１）面方位の２インチ径の６Ｈ－ＳｉＣ基板などを下地基板１として用意し、該下地基板１を、ＭＯＣＶＤ炉のリアクタ内に設けられたサセプタの上に設置する。リアクタ内を真空ガス置換した後、リアクタ内圧力を５ｋＰａ～５０ｋＰａの間の所定の値に保ちつつ、水素／窒素混合フロー状態の雰囲気を形成した上で、サセプタ加熱によって基板を昇温する。 First, for example, a 2 inch 6H-SiC substrate having a (0001) plane orientation is prepared as a base substrate 1, and the base substrate 1 is placed on a susceptor provided in a reactor of an MOCVD furnace. After replacing the inside of the reactor with vacuum gas, the temperature of the substrate is raised by susceptor heating after forming an atmosphere in a hydrogen / nitrogen mixed flow state while maintaining the reactor pressure at a predetermined value between 5 kPa and 50 kPa.
　サセプタ温度がバッファ層形成温度である９５０℃～１２５０℃の間の所定温度（例えば１０５０℃）に達すると、Ａｌ原料ガスとＮＨ３ガスをリアクタ内に導入し、バッファ層２としてのＡｌＮ層を形成する。 When the susceptor temperature reaches a predetermined temperature (for example, 1050 ° C.) between 950 ° C. and 1250 ° C. which is the buffer layer formation temperature, Al source gas and NH 3 gas are introduced into the reactor, and the AlN layer as the buffer layer 2 is formed. Form.
　ＡｌＮ層が形成されると、サセプタ温度を所定のチャネル層形成温度に保ち、チャネル層３の組成に応じた有機金属原料ガスとアンモニアガスをリアクタ内に導入し、チャネル層３としてのＩｎｘ１Ａｌｙ１Ｇａｚ１Ｎ層（ただし、ｘ１＝０、０≦ｙ１≦０．３）を形成する。ここで、チャネル層形成温度Ｔ１は、９５０℃以上１２５０℃以下の温度範囲から、チャネル層３のＡｌＮモル分率ｙ１の値に応じて定められる値である。なお、チャネル層３形成時のリアクタ圧力には特に限定はなく、１０ｋＰａから大気圧（１００ｋＰａ）の範囲から適宜選ぶことができる。 When the AlN layer is formed, the susceptor temperature is maintained at a predetermined channel layer formation temperature, an organometallic source gas and ammonia gas corresponding to the composition of the channel layer 3 are introduced into the reactor, and In x1 Al as the channel layer 3 is introduced. A y1 Ga z1 N layer (where x1 = 0, 0 ≦ y1 ≦ 0.3) is formed. Here, the channel layer formation temperature T1 is a value determined according to the value of the AlN molar fraction y1 of the channel layer 3 from a temperature range of 950 ° C. or more and 1250 ° C. or less. The reactor pressure at the time of forming the channel layer 3 is not particularly limited, and can be appropriately selected from the range of 10 kPa to atmospheric pressure (100 kPa).
　Ｉｎｘ１Ａｌｙ１Ｇａｚ１Ｎ層が形成されると、次いで、サセプタ温度を保ったまま、リアクタ内を窒素ガス雰囲気に保ち、リアクタ圧力を１０ｋＰａとした後、有機金属原料ガスとアンモニアガスとをリアクタ内に導入して、スペーサ層４としてのＩｎｘ３Ａｌｙ３Ｇａｚ３Ｎ層を所定の厚みに形成する。 When the In x1 Al y1 Ga z1 N layer is formed, the reactor is maintained in a nitrogen gas atmosphere with the susceptor temperature maintained, the reactor pressure is set to 10 kPa, and the organometallic source gas and ammonia gas are then reacted with the reactor. Then, an In x3 Al y3 Ga z3 N layer as the spacer layer 4 is formed to a predetermined thickness.
　Ｉｎｘ３Ａｌｙ３Ｇａｚ３Ｎ層が形成されると、障壁層５となるＩｎｘ２Ａｌｙ２Ｎを形成するために、サセプタ温度を６５０℃以上８００℃以下の所定の障壁層形成温度に保ち、リアクタ内圧力が１ｋＰａ～３０ｋＰａの間の所定の値に保たれるようにする。そして、アンモニアガスと、障壁層５の組成に応じた流量比の有機金属原料ガスとを、いわゆるＶ／III比が３０００以上２００００以下の間の所定の値となるようにリアクタ内に導入する。 When the In x3 Al y3 Ga z3 N layer is formed, the susceptor temperature is maintained at a predetermined barrier layer forming temperature of 650 ° C. or higher and 800 ° C. or lower in order to form In x2 Al y2 N to be the barrier layer 5. The internal pressure is maintained at a predetermined value between 1 kPa and 30 kPa. Then, ammonia gas and an organic metal source gas having a flow rate ratio corresponding to the composition of the barrier layer 5 are introduced into the reactor so that the so-called V / III ratio is a predetermined value between 3000 and 20000.
　Ｉｎｘ３Ａｌｙ３Ｇａｚ３Ｎ層が形成されると、引き続いて、サセプタ温度を所定の中間層形成温度としたうえで、ＴＭＧとＮＨ３ガスとを供給して、中間層６ａとしてのＧａＮ層を所定の厚みに形成する。 When the In x3 Al y3 Ga z3 N layer is formed, the susceptor temperature is set to a predetermined intermediate layer formation temperature, TMG and NH 3 gas are supplied, and the GaN layer as the intermediate layer 6a is formed. A predetermined thickness is formed.
　ＧａＮ層が形成されると、引き続いて、サセプタ温度を所定のキャップ層形成温度としたうえで、ＴＭＡとＮＨ３ガスとを供給して、キャップ層６ｂとしてのＡｌＮ層を所定の厚みに形成する。キャップ層６ｂが形成されれば、エピタキシャル基板１０が作製されたことになる。 When the GaN layer is formed, TMA and NH 3 gas are supplied after the susceptor temperature is set to a predetermined cap layer forming temperature, and an AlN layer as the cap layer 6b is formed to a predetermined thickness. . If the cap layer 6b is formed, the epitaxial substrate 10 is manufactured.
　エピタキシャル基板１０が形成されると、これを用いてＨＥＭＴ素子が形成される。以降の各工程は、公知の手法で実現されるものである。 When the epitaxial substrate 10 is formed, a HEMT element is formed using this. Each subsequent process is realized by a known method.
　まず、フォトリソグラフィープロセスと真空蒸着法を用いて、キャップ層６ｂの形成対象個所に、ソース電極７およびドレイン電極８となる多層金属パターンを形成する。 First, a multilayer metal pattern to be the source electrode 7 and the drain electrode 8 is formed at a formation target portion of the cap layer 6b by using a photolithography process and a vacuum deposition method.
　次いで、ソース電極７およびドレイン電極８のオーミック性を良好なものにするため、これらソース電極７およびドレイン電極８が形成されたエピタキシャル基板１０に対し、６５０℃～１０００℃の所定温度の窒素ガス雰囲気中において、数十秒間の熱処理を施す。 Next, in order to improve the ohmic property of the source electrode 7 and the drain electrode 8, a nitrogen gas atmosphere at a predetermined temperature of 650 ° C. to 1000 ° C. is applied to the epitaxial substrate 10 on which the source electrode 7 and the drain electrode 8 are formed. Inside, heat treatment is performed for several tens of seconds.
　続いて、フォトリソグラフィープロセスと真空蒸着法を用いて、キャップ層６ｂの形成対象個所に、ゲート電極９となる多層金属パターンを形成する。 Subsequently, a multilayer metal pattern to be the gate electrode 9 is formed at a formation target portion of the cap layer 6b by using a photolithography process and a vacuum deposition method.
　その後、ダイシングにより所定のサイズにチップ化することで、多数個のＨＥＭＴ素子２０が得られる。得られたＨＥＭＴ素子２０に対しては、適宜にダイボンディングやワイヤボンディングが施される。 Thereafter, a large number of HEMT elements 20 are obtained by dicing into chips of a predetermined size. The obtained HEMT element 20 is appropriately subjected to die bonding or wire bonding.
　以上、説明したように、本実施の形態によれば、障壁層の上にＧａＮからなる中間層を設け、さらに、ＡｌＮからなるキャップ層を設け、該キャップ層に対してショットキー接合によりゲート電極の形成を行い、ＭＩＳ接合を形成することで、障壁層の上に直接にショットキー接合によりゲート電極の形成を行う場合に比して、逆方向漏れ電流が大きく低減され、かつ二次元電子ガスの移動度が高いＨＥＭＴ素子が実現される。 As described above, according to the present embodiment, the intermediate layer made of GaN is provided on the barrier layer, the cap layer made of AlN is further provided, and the gate electrode is formed by Schottky junction to the cap layer. By forming the MIS junction, the reverse leakage current is greatly reduced as compared with the case where the gate electrode is formed directly on the barrier layer by the Schottky junction, and the two-dimensional electron gas is formed. A HEMT element having a high mobility is realized.
　　＜変形例＞
　上述の実施の形態においては、ＨＥＭＴ素子を対象として説明を行っているが、ゲート電極と障壁層との間にＭＩＳ接合を形成する態様は、ショットキー接合を用いる他の電子デバイス、例えば、ショットキーバリアダイオードや、フォトセンサなどにも、同様に適用が可能である。 <Modification>
In the above-described embodiment, the HEMT element is described as an object. However, an aspect in which the MIS junction is formed between the gate electrode and the barrier layer is another electronic device using a Schottky junction, for example, a shot The same applies to key barrier diodes and photosensors.
　また、上述の実施の形態においては、キャップ層６ｂをＡｌＮにて形成しているが、キャップ層６ｂは、第２のIII族窒化物のバンドギャップよりも大きく、絶縁性を有するIII族窒化物にて形成される態様であってもよい。ここで、III族窒化物が絶縁性を有するとは、比抵抗が１０８Ωｃｍ以上であることを意味する。係る範囲の比抵抗を有していれば、上述するＭＩＳ接合が好適に形成される。また、係る比抵抗をみたす限りにおいて、キャップ層６ｂにおいて導電性不純物の存在は許容される。 In the above-described embodiment, the cap layer 6b is formed of AlN, but the cap layer 6b is larger than the band gap of the second group III nitride and has an insulating group III nitride. It may be an aspect formed by. Here, that the group III nitride has insulation means that the specific resistance is 10 8 Ωcm or more. If it has the specific resistance of the range, the MIS junction mentioned above is formed suitably. In addition, as long as the specific resistance is satisfied, the presence of conductive impurities is allowed in the cap layer 6b.
　（実施例１、比較例１、および比較例）
　まず、実施例１として、中間層６ａおよびキャップ層６ｂを備える、上述の実施の形態に係るエピタキシャル基板１０を作成し、その二次元電子ガス濃度と、二次元電子ガスの移動度と、シート抵抗とを評価した。そして、係るエピタキシャル基板１０を用いて、ゲート電極９の構成が異なる、４種類のＨＥＭＴ素子２０を作製し、それぞれのＨＥＭＴ素子２０について、－１００Ｖ印加時の逆方向漏れ電流を評価した。 (Example 1, Comparative Example 1, and Comparative Example)
First, as Example 1, the epitaxial substrate 10 according to the above-described embodiment including the intermediate layer 6a and the cap layer 6b is prepared, and the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, and the sheet resistance And evaluated. Then, using this epitaxial substrate 10, four types of HEMT elements 20 having different configurations of the gate electrode 9 were produced, and the reverse leakage current when −100 V was applied to each HEMT element 20 was evaluated.
　一方、比較例１として、中間層６ａおよびキャップ層６ｂをともに備えていないエピタキシャル基板を用意し、その二次元電子ガス濃度と、二次元電子ガスの移動度と、シート抵抗とを評価した。また、係るエピタキシャル基板に対して、実施例１と同様にゲート電極９を形成することによって４種類のＨＥＭＴ素子を作製し、それぞれのＨＥＭＴ素子について、－１００Ｖ印加時の逆方向漏れ電流を評価した。 On the other hand, as Comparative Example 1, an epitaxial substrate not including both the intermediate layer 6a and the cap layer 6b was prepared, and the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, and the sheet resistance were evaluated. In addition, four types of HEMT devices were fabricated by forming the gate electrode 9 on the epitaxial substrate in the same manner as in Example 1, and the reverse leakage current when -100 V was applied was evaluated for each HEMT device. .
　さらに、比較例２として、中間層６ａを備えずキャップ層６ｂのみを備えるエピタキシャル基板を用意し、その二次元電子ガス濃度と、二次元電子ガスの移動度と、シート抵抗とを評価した。また、係るエピタキシャル基板に対して、実施例１と同様にゲート電極９を形成することによって４種類のＨＥＭＴ素子を作製し、それぞれのＨＥＭＴ素子について、－１００Ｖ印加時の逆方向漏れ電流を評価した。 Furthermore, as Comparative Example 2, an epitaxial substrate provided with only the cap layer 6b without the intermediate layer 6a was prepared, and the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, and the sheet resistance were evaluated. In addition, four types of HEMT devices were fabricated by forming the gate electrode 9 on the epitaxial substrate in the same manner as in Example 1, and the reverse leakage current when -100 V was applied was evaluated for each HEMT device. .
　すなわち、３種類のエピタキシャル基板に対してそれぞれ、構成が異なる４種類のゲート電極９を形成することにより、計１２種類のＨＥＭＴ素子を得た。 That is, a total of 12 types of HEMT elements were obtained by forming four types of gate electrodes 9 having different configurations on three types of epitaxial substrates.
　はじめに、エピタキシャル基板１０を作製した。その際、スペーサ層４の形成までは、全てのエピタキシャル基板１０について同一の条件で行った。 First, an epitaxial substrate 10 was produced. At that time, all the epitaxial substrates 10 were subjected to the same conditions until the formation of the spacer layer 4.
　具体的には、まず、下地基板１として（０００１）面方位の２インチ径の６Ｈ－ＳｉＣ基板を複数枚用意した。厚みは３００μｍであった。それぞれの基板について、ＭＯＣＶＤ炉リアクタ内に設置し、真空ガス置換した後、リアクタ内圧力を３０ｋＰａとし、水素／窒素混合フロー状態の雰囲気を形成した。次いで、サセプタ加熱によって下地基板１を昇温した。 Specifically, first, as the base substrate 1, a plurality of 2 inch 6H—SiC substrates having a (0001) plane orientation were prepared. The thickness was 300 μm. About each board | substrate, after installing in a MOCVD furnace reactor and carrying out vacuum gas substitution, the pressure in a reactor was 30 kPa and the atmosphere of the hydrogen / nitrogen mixed flow state was formed. Next, the temperature of the base substrate 1 was raised by susceptor heating.
　サセプタ温度が１０５０℃に達すると、ＴＭＡバブリングガスとアンモニアガスをリアクタ内に導入し、バッファ層として厚さ２００ｎｍのＡｌＮ層を形成した。 When the susceptor temperature reached 1050 ° C., TMA bubbling gas and ammonia gas were introduced into the reactor, and an AlN layer having a thickness of 200 nm was formed as a buffer layer.
　続いて、サセプタ温度を所定の温度とし、有機金属原料ガスとしてのＴＭＧバブリングガスとアンモニアガスとを所定の流量比でリアクタ内に導入し、チャネル層３としてのＧａＮ層を２μｍの厚みに形成した。 Subsequently, the susceptor temperature was set to a predetermined temperature, TMG bubbling gas as an organic metal source gas and ammonia gas were introduced into the reactor at a predetermined flow ratio, and a GaN layer as a channel layer 3 was formed to a thickness of 2 μm. .
　チャネル層３が得られると、リアクタ圧力を１０ｋＰａとし、次いでＴＭＡバブリングガスとアンモニアガスをリアクタ内に導入し、スペーサ層４として厚さ１ｎｍのＡｌＮ層を形成した。 When the channel layer 3 was obtained, the reactor pressure was set to 10 kPa, then TMA bubbling gas and ammonia gas were introduced into the reactor, and an AlN layer having a thickness of 1 nm was formed as the spacer layer 4.
　スペーサ層４を形成した後、続いて、障壁層５を１５ｎｍの厚みに形成した。障壁層５の組成は、Ｉｎ０．１８Ａｌ０．８２Ｎとした。また、サセプタ温度は７４５℃とした。 After the formation of the spacer layer 4, the barrier layer 5 was subsequently formed to a thickness of 15 nm. The composition of the barrier layer 5 was In 0.18 Al 0.82 N. The susceptor temperature was 745 ° C.
　障壁層５の形成後、実施例１については、サセプタ温度を障壁層形成温度である７４５℃に保ったまま、中間層６ａとしてのＧａＮ層を３ｎｍの厚みに形成し、続いて、キャップ層６ｂとしてのＡｌＮ層を３ｎｍの厚みに形成した。比較例２については、キャップ層６ｂを３ｎｍの厚みに形成した。比較例１については、何も形成しなかった。 After the formation of the barrier layer 5, in Example 1, while maintaining the susceptor temperature at 745 ° C., which is the barrier layer formation temperature, a GaN layer as the intermediate layer 6a is formed to a thickness of 3 nm, and then the cap layer 6b. The AlN layer was formed to a thickness of 3 nm. For Comparative Example 2, the cap layer 6b was formed to a thickness of 3 nm. For Comparative Example 1, nothing was formed.
　それぞれのエピタキシャル基板に対して最後の層を形成した後、サセプタ温度を室温付近まで降温し、リアクタ内を大気圧に復帰させた後、作製されたエピタキシャル基板１０を取り出した。以上の手順により、それぞれのエピタキシャル基板１０が得られた。 After the last layer was formed on each epitaxial substrate, the susceptor temperature was lowered to near room temperature, the inside of the reactor was returned to atmospheric pressure, and the fabricated epitaxial substrate 10 was taken out. Each epitaxial substrate 10 was obtained by the above procedure.
　次いで、それぞれのエピタキシャル基板の一部をダイシングにより切り出し、得られた評価用試料を対象に、ホール効果測定を行った。これにより、それぞれのエピタキシャル基板についての、二次元電子ガス濃度と、二次元電子ガス移動度と、シート抵抗とを求めた。 Next, a part of each epitaxial substrate was cut out by dicing, and the Hall effect measurement was performed on the obtained evaluation sample. Thereby, the two-dimensional electron gas concentration, the two-dimensional electron gas mobility, and the sheet resistance were determined for each epitaxial substrate.
　続いて、それぞれのエピタキシャル基板の上面の、ソース電極７およびドレイン電極８の形成対象箇所に、フォトリソグラフィープロセスと真空蒸着法とを用いて、Ｔｉ／Ａｌ／Ｎｉ／Ａｕ（それぞれの膜厚は２５／７５／１５／１００ｎｍ）からなる電極パターンを形成した。その後、窒素中で８００℃、３０秒間の熱処理を行った。 Subsequently, Ti / Al / Ni / Au (each film thickness is 25) is formed on the upper surface of each epitaxial substrate by using a photolithography process and a vacuum deposition method on the formation target portion of the source electrode 7 and the drain electrode 8. / 75/15/100 nm) was formed. Thereafter, heat treatment was performed in nitrogen at 800 ° C. for 30 seconds.
　続いて、それぞれのエピタキシャル基板の上面の、ゲート電極９の形成対象個所に、フォトリソグラフィープロセスと真空蒸着法とを用いて、ゲート電極９のパターンを形成した。ゲート電極９としては、Ｎｉ／Ａｕ（膜厚６ｎｍ／１２ｎｍ）、Ｐｄ／Ａｕ（６ｎｍ／１２ｎｍ）、およびＰｔ／Ａｕ（６ｎｍ／１２ｎｍ）の３種類の多層金属電極と、Ａｕのみの単層金属電極（１２ｎｍ）との計４種類を形成した。なお、ゲート電極９は、ゲート長を１μｍ、ゲート幅を１００μｍとし、ソース電極７との間隔が２μｍ、ドレイン電極との間隔が１０μｍとなるように形成した。 Subsequently, a pattern of the gate electrode 9 was formed on the upper surface of each epitaxial substrate at a formation target portion of the gate electrode 9 by using a photolithography process and a vacuum deposition method. The gate electrode 9 includes three types of multilayer metal electrodes, Ni / Au (film thickness 6 nm / 12 nm), Pd / Au (6 nm / 12 nm), and Pt / Au (6 nm / 12 nm), and a single-layer metal made of only Au. A total of four types with electrodes (12 nm) were formed. The gate electrode 9 was formed such that the gate length was 1 μm, the gate width was 100 μm, the distance from the source electrode 7 was 2 μm, and the distance from the drain electrode was 10 μm.
　最後に、ダイシングによりチップ化することで、ＨＥＭＴ素子を得た。 Finally, a HEMT element was obtained by dicing into chips.
　得られたＨＥＭＴ素子について、ダイボンディングおよびワイヤボンディングを行ったうえで、－１００Ｖ印加時の逆方向漏れ電流を測定した。 The obtained HEMT device was subjected to die bonding and wire bonding, and the reverse leakage current when -100 V was applied was measured.
　それぞれのＨＥＭＴ素子について、エピタキシャル基板の中間層６ａおよびキャップ層６ｂの構成と、二次元電子ガス濃度と、二次元電子ガスの移動度と、シート抵抗と、ＨＥＭＴ素子ごとのゲート電極の構成と－１００Ｖ印加時の逆方向漏れ電流の測定結果とを、表１に一覧にして示す。 For each HEMT element, the structure of the intermediate layer 6a and the cap layer 6b of the epitaxial substrate, the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, the sheet resistance, the structure of the gate electrode for each HEMT element, and Table 1 lists the measurement results of the reverse leakage current when 100 V is applied.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　表１に示す結果からは、実施例１に係る全てのＨＥＭＴ素子において、つまりは、ゲート電極９の構成によらず、その逆方向漏れ電流が、中間層６ａおよびキャップ層６ｂ以外を同一の条件として作製した比較例１に係るＨＥＭＴ素子における逆方向漏れ電流の１／１００から１／１０００程度にまで抑制されていることがわかる。また、二次元電子ガス濃度と、二次元電子ガス移動度と、シート抵抗とについては、実施例１と比較例１との間でほとんど差異がないこともわかる。 From the results shown in Table 1, in all HEMT devices according to Example 1, that is, regardless of the configuration of the gate electrode 9, the reverse leakage current is the same under the conditions except for the intermediate layer 6a and the cap layer 6b. It can be seen that the reverse leakage current in the HEMT device according to Comparative Example 1 manufactured as above is suppressed to about 1/100 to 1/1000. It can also be seen that there is almost no difference between Example 1 and Comparative Example 1 regarding the two-dimensional electron gas concentration, the two-dimensional electron gas mobility, and the sheet resistance.
　これに対して、中間層６ａを設けずキャップ層６ｂのみを設けた比較例２のＨＥＭＴ素子の場合、逆方向漏れ電流については実施例１と同程度にまで抑制されているものの、二次元電子ガス移動度は実施例１および比較例１よりもより低く、シート抵抗が実施例１および比較例１よりも高くなっていることがわかる。 On the other hand, in the case of the HEMT device of Comparative Example 2 in which only the cap layer 6b is provided without providing the intermediate layer 6a, the reverse leakage current is suppressed to the same level as in Example 1, but the two-dimensional electron It can be seen that the gas mobility is lower than in Example 1 and Comparative Example 1, and the sheet resistance is higher than in Example 1 and Comparative Example 1.
　以上の結果は、キャップ層６ｂを障壁層５の上に直接に設けることには、漏れ電流低減という効果がある一方で、二次元電子ガスの移動度やシート抵抗の低下を引き起こすという短所があること、および、中間層６ａを両層の間に介在させることで、漏れ電流低減というキャップ層６ｂの効果を維持しつつ、二次元電子ガスの移動度の低下によるシート抵抗の悪化を抑止することができるということを、指し示している。 The above results show that providing the cap layer 6b directly on the barrier layer 5 has the effect of reducing the leakage current, but also has the disadvantage of reducing the mobility of the two-dimensional electron gas and the sheet resistance. In addition, by interposing the intermediate layer 6a between the two layers, the deterioration of the sheet resistance due to the decrease in the mobility of the two-dimensional electron gas is suppressed while maintaining the effect of the cap layer 6b that reduces the leakage current. Indicates that they can
　換言すれば、障壁層５の上に中間層６ａを設けたうえでキャップ層６ｂを設けることが、二次元電子ガス濃度およびシート抵抗を好適に保ちつつ、逆方向漏れ電流を低減させるうえで効果があることを示している。 In other words, providing the intermediate layer 6a on the barrier layer 5 and then providing the cap layer 6b is effective in reducing the reverse leakage current while suitably maintaining the two-dimensional electron gas concentration and the sheet resistance. It shows that there is.
　（実施例２）
　本実施例では、中間層６ａを設けない場合を含め、中間層６ａの厚みを種々に違えたＨＥＭＴ素子を作製した。具体的には、中間層６ａの厚みを０ｎｍ、０．１ｎｍ、０．５ｎｍ、１．５ｎｍ、３ｎｍ、６ｎｍ、８ｎｍ、１０ｎｍの８水準とする一方、ゲート電極９の形成材料をＮｉ／Ａｕ（膜厚６ｎｍ／１２ｎｍ）のみとしたほかは、実施例１と同様の手順でＨＥＭＴ素子を作製した。 (Example 2)
In this example, HEMT devices were produced in which the thickness of the intermediate layer 6a was variously changed, including the case where the intermediate layer 6a was not provided. Specifically, the thickness of the intermediate layer 6a is set to eight levels of 0 nm, 0.1 nm, 0.5 nm, 1.5 nm, 3 nm, 6 nm, 8 nm, and 10 nm, while the material for forming the gate electrode 9 is Ni / Au ( A HEMT device was fabricated in the same procedure as in Example 1 except that the thickness was only 6 nm / 12 nm.
　なお、係るＨＥＭＴ素子作製の途中、エピタキシャル基板が得られた時点で実施例１と同様に、ホール効果測定を行った。これにより、それぞれのエピタキシャル基板についての、二次元電子ガス濃度と、二次元電子ガス移動度と、シート抵抗とを求めた。 In addition, the Hall effect measurement was performed in the same manner as in Example 1 when an epitaxial substrate was obtained during the HEMT element fabrication. Thereby, the two-dimensional electron gas concentration, the two-dimensional electron gas mobility, and the sheet resistance were determined for each epitaxial substrate.
　また、得られたＨＥＭＴ素子について、実施例１と同様に逆方向漏れ電流を測定した。 Further, the reverse leakage current of the obtained HEMT element was measured in the same manner as in Example 1.
　それぞれのＨＥＭＴ素子について、エピタキシャル基板の膜厚と、二次元電子ガス濃度と、二次元電子ガスの移動度と、シート抵抗と、ＨＥＭＴ素子の－１００Ｖ印加時の逆方向漏れ電流の測定結果とを、表２に一覧にして示す。 For each HEMT element, the thickness of the epitaxial substrate, the two-dimensional electron gas concentration, the mobility of the two-dimensional electron gas, the sheet resistance, and the measurement result of the reverse leakage current when applying −100 V to the HEMT element are shown. Table 2 shows a list.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　表２に示すように、中間層６ａの厚みが０．５ｎｍ以上の場合、中間層６ａを設けない場合に比して、二次元電子ガスの移動度が高い値となっている。また、中間層６ａの厚みが６ｎｍ以下の場合であれば、二次元電子ガス濃度の値が中間層６ａを設けない場合と同程度となっている。さらには、中間層６ａの厚みが０．５ｎｍ以上６ｎｍ以下の場合であれば、シート抵抗の値が、中間層６ａを設けない場合に比して低い３００Ω／□以下の値に保たれている。 As shown in Table 2, when the thickness of the intermediate layer 6a is 0.5 nm or more, the mobility of the two-dimensional electron gas is higher than when the intermediate layer 6a is not provided. Further, if the thickness of the intermediate layer 6a is 6 nm or less, the value of the two-dimensional electron gas concentration is almost the same as the case where the intermediate layer 6a is not provided. Furthermore, if the thickness of the intermediate layer 6a is 0.5 nm or more and 6 nm or less, the value of the sheet resistance is kept at a value of 300Ω / □ or lower, which is lower than when the intermediate layer 6a is not provided. .
　一方で、表２に示すように、いずれのＨＥＭＴ素子についても、漏れ電流の値は、表１に示した比較例１の場合（ゲート電極が同じＮｉ／Ａｕの場合）の１／１０００以下にまで低減されている。 On the other hand, as shown in Table 2, for any HEMT element, the value of the leakage current is 1/1000 or less of the case of Comparative Example 1 shown in Table 1 (when the gate electrode is the same Ni / Au). Has been reduced to.
　以上のことから、キャップ層６ｂと障壁層５との間に中間層６ａを０．５ｎｍ以上の厚みに形成することで、漏れ電流が低減されているとともに、二次元電子ガスの移動度が高いＨＥＭＴ素子が実現されることがわかる。さらに、中間層６ａの厚みを６ｎｍ以下とすることで、二次元電子ガス濃度が高く、かつシート抵抗が小さいＨＥＭＴ素子が実現されることがわかる。 From the above, by forming the intermediate layer 6a between the cap layer 6b and the barrier layer 5 to a thickness of 0.5 nm or more, the leakage current is reduced and the mobility of the two-dimensional electron gas is high. It can be seen that a HEMT element is realized. Furthermore, it can be seen that a HEMT element having a high two-dimensional electron gas concentration and a low sheet resistance can be realized by setting the thickness of the intermediate layer 6a to 6 nm or less.

Claims (26)

  1. 　下地基板の上にIII族窒化物層群を（０００１）結晶面が基板面に対し略平行となるよう積層形成したエピタキシャル基板と、
    　ショットキー性電極と、
    を備える半導体素子であって、
    　前記エピタキシャル基板が、
    　　Ｉｎｘ１Ａｌｙ１Ｇａｚ１Ｎ（ｘ１＋ｙ１＋ｚ１＝１、ｚ１＞０）なる組成の第１のIII族窒化物からなるチャネル層と、
    　　Ｉｎｘ２Ａｌｙ２Ｎ（ｘ２＋ｙ２＝１、ｘ２＞０、ｙ２＞０）なる組成の第２のIII族窒化物からなる障壁層と、
    　　ＧａＮからなり前記障壁層に隣接する中間層と、
    　　ＡｌＮからなり前記中間層に隣接するキャップ層と、
    を備え、
    　前記ショットキー性電極が前記キャップ層に接合されてなる、
    ことを特徴とする半導体素子。     An epitaxial substrate in which a group III nitride layer group is laminated on the base substrate so that the (0001) crystal plane is substantially parallel to the substrate surface;
    A Schottky electrode,
    A semiconductor device comprising:
    The epitaxial substrate is
    A channel layer made of a first group III nitride having a composition of In x1 Al y1 Ga z1 N (x1 + y1 + z1 = 1, z1>0);
    A barrier layer made of a second group III nitride having a composition of In x2 Al y2 N (x2 + y2 = 1, x2> 0, y2>0);
    An intermediate layer made of GaN and adjacent to the barrier layer;
    A cap layer made of AlN and adjacent to the intermediate layer;
    With
    The Schottky electrode is joined to the cap layer,
    The semiconductor element characterized by the above-mentioned.
  2. 　請求項１に記載の半導体素子であって、
    　前記中間層の膜厚が０．５ｎｍ以上である、
    ことを特徴とする半導体素子。     The semiconductor device according to claim 1,
    The intermediate layer has a thickness of 0.5 nm or more.
    The semiconductor element characterized by the above-mentioned.
  3. 　請求項２に記載の半導体素子であって、
    　前記中間層の膜厚が６ｎｍ以下である、
    ことを特徴とする半導体素子。     The semiconductor device according to claim 2,
    The intermediate layer has a thickness of 6 nm or less.
    The semiconductor element characterized by the above-mentioned.
  4. 　請求項１ないし請求項３のいずれかに記載の半導体素子であって、
    　前記キャップ層の膜厚が０．５ｎｍ以上６ｎｍ以下である、
    ことを特徴とする半導体素子。     A semiconductor device according to any one of claims 1 to 3,
    The film thickness of the cap layer is 0.5 nm or more and 6 nm or less,
    The semiconductor element characterized by the above-mentioned.
  5. 　請求項１ないし請求項４のいずれかに記載の半導体素子であって、
    　前記第２のIII族窒化物のバンドギャップが前記第１のIII族窒化物のバンドギャップよりも大きい、
    ことを特徴とする半導体素子。     A semiconductor device according to any one of claims 1 to 4,
    The band gap of the second group III nitride is larger than the band gap of the first group III nitride;
    The semiconductor element characterized by the above-mentioned.
  6. 　請求項１ないし請求項５のいずれかに記載の半導体素子であって、
    　前記ショットキー性電極がＮｉ、Ｐｔ、Ｐｄ、Ａｕの少なくとも１つを含んでなる、
    ことを特徴とする半導体素子。     A semiconductor device according to any one of claims 1 to 5,
    The Schottky electrode comprises at least one of Ni, Pt, Pd, Au,
    The semiconductor element characterized by the above-mentioned.
  7. 　請求項１ないし請求項６のいずれかに記載の半導体素子であって、
    　前記キャップ層の自乗平均表面粗さが０．５ｎｍ以下である、
    ことを特徴とする半導体素子。     A semiconductor device according to any one of claims 1 to 6,
    The root mean square surface roughness of the cap layer is 0.5 nm or less.
    The semiconductor element characterized by the above-mentioned.
  8. 　請求項１ないし請求項７のいずれかに記載の半導体素子であって、
    　前記第２のIII族窒化物が、Ｉｎｘ２Ａｌｙ２Ｎ（ｘ２＋ｙ２＝１、０．１４≦ｘ２≦０．２４）である、
    ことを特徴とする半導体素子。     A semiconductor device according to any one of claims 1 to 7,
    The second group III nitride is In x2 Al y2 N (x2 + y2 = 1, 0.14 ≦ x2 ≦ 0.24).
    The semiconductor element characterized by the above-mentioned.
  9. 　請求項１ないし請求項８のいずれかに記載の半導体素子であって、
    　前記第１のIII族窒化物がＡｌｙ１Ｇａｚ１Ｎ（ｙ１＋ｚ１＝１、ｚ１＞０）である、
    ことを特徴とする半導体素子。     A semiconductor device according to any one of claims 1 to 8,
    The first group III nitride is Al y1 Ga z1 N (y1 + z1 = 1, z1> 0).
    The semiconductor element characterized by the above-mentioned.
  10. 　請求項９に記載の半導体素子であって、
    　前記第１のIII族窒化物がＧａＮである、
    ことを特徴とする半導体素子。     The semiconductor element according to claim 9,
    The first group III nitride is GaN;
    The semiconductor element characterized by the above-mentioned.
  11. 　請求項９または請求項１０に記載の半導体素子であって、
    　前記チャネル層と前記障壁層との間に、Ｉｎｘ３Ａｌｙ３Ｇａｚ３Ｎ（ｘ３＋ｙ３＋ｚ３＝１、ｙ３＞０）なる組成を有し、前記第２のIII族窒化物よりもバンドギャップが大きい第３のIII族窒化物からなるスペーサ層をさらに備える、
    ことを特徴とする半導体素子。     The semiconductor device according to claim 9 or 10, wherein
    A third layer having a composition of In x3 Al y3 Ga z3 N (x3 + y3 + z3 = 1, y3> 0) between the channel layer and the barrier layer and having a band gap larger than that of the second group III nitride. A spacer layer made of Group III nitride of
    The semiconductor element characterized by the above-mentioned.
  12. 　請求項１１に記載の半導体素子であって、
    　前記第３のIII族窒化物がＡｌＮである、
    ことを特徴とする半導体素子。     The semiconductor device according to claim 11,
    The third group III nitride is AlN;
    The semiconductor element characterized by the above-mentioned.
  13. 　請求項１ないし請求項１２のいずれかに記載の半導体素子であって、
    　オーミック性電極が前記ショットキー性電極と同一の前記キャップ層に接合されてなる、
    ことを特徴とする半導体素子。     A semiconductor device according to any one of claims 1 to 12,
    An ohmic electrode is joined to the same cap layer as the Schottky electrode;
    The semiconductor element characterized by the above-mentioned.
  14. 　請求項１３に記載の半導体素子であるＨＥＭＴ素子であって、
    　前記ショットキー性電極がゲート電極であり、前記オーミック性電極がソース電極およびドレイン電極である、
    ことを特徴とするＨＥＭＴ素子。     A HEMT device which is a semiconductor device according to claim 13,
    The Schottky electrode is a gate electrode, and the ohmic electrode is a source electrode and a drain electrode,
    The HEMT element characterized by the above-mentioned.
  15. 　下地基板の上にIII族窒化物層群を（０００１）結晶面が基板面に対し略平行となるよう積層形成したエピタキシャル基板と、
    　ショットキー性電極と、
    を備える半導体素子の製造方法であって、
    　下地基板の上に、Ｉｎｘ１Ａｌｙ１Ｇａｚ１Ｎ（ｘ１＋ｙ１＋ｚ１＝１、ｚ１＞０）なる組成の第１のIII族窒化物にてチャネル層を形成するチャネル層形成工程と、
    　前記チャネル層の上に、Ｉｎｘ２Ａｌｙ２Ｎ（ｘ２＋ｙ２＝１、ｘ２＞０、ｙ２＞０）なる組成の第２のIII族窒化物にて障壁層を形成する障壁層形成工程と、
    　ＧａＮにて中間層を前記障壁層に隣接形成する中間層形成工程と、
    　ＡｌＮにてキャップ層を前記中間層に隣接形成するキャップ層形成工程と、
    　前記キャップ層にショットキー性電極を接合形成するショットキー性電極形成工程と、
    を備えることを特徴とする半導体素子の製造方法。     An epitaxial substrate in which a group III nitride layer group is laminated on the base substrate so that the (0001) crystal plane is substantially parallel to the substrate surface;
    A Schottky electrode,
    A method for manufacturing a semiconductor device comprising:
    A channel layer forming step of forming a channel layer on a base substrate with a first group III nitride having a composition of In x1 Al y1 Ga z1 N (x1 + y1 + z1 = 1, z1>0);
    A barrier layer forming step of forming a barrier layer on the channel layer with a second group III nitride having a composition of In x2 Al y2 N (x2 + y2 = 1, x2> 0, y2>0);
    An intermediate layer forming step of forming an intermediate layer adjacent to the barrier layer with GaN;
    A cap layer forming step of forming a cap layer adjacent to the intermediate layer with AlN;
    A Schottky electrode forming step of bonding a Schottky electrode to the cap layer;
    The manufacturing method of the semiconductor element characterized by the above-mentioned.
  16. 　請求項１５に記載の半導体素子の製造方法であって、
    　前記中間層を０．５ｎｍ以上の厚みに形成する、
    ことを特徴とする半導体素子の製造方法。     A method of manufacturing a semiconductor device according to claim 15,
    Forming the intermediate layer to a thickness of 0.5 nm or more;
    A method for manufacturing a semiconductor device, comprising:
  17. 　請求項１６に記載の半導体素子の製造方法であって、
    　前記中間層を６ｎｍ以下の厚みに形成する、
    ことを特徴とする半導体素子の製造方法。     A method of manufacturing a semiconductor device according to claim 16,
    Forming the intermediate layer to a thickness of 6 nm or less;
    A method for manufacturing a semiconductor device, comprising:
  18. 　請求項１５ないし請求項１７のいずれかに記載の半導体素子の製造方法であって、
    　前記キャップ層を０．５ｎｍ以上６ｎｍ以下の厚みに形成する、
    ことを特徴とする半導体素子の製造方法。     A method of manufacturing a semiconductor device according to any one of claims 15 to 17,
    Forming the cap layer in a thickness of 0.5 nm to 6 nm;
    A method for manufacturing a semiconductor device, comprising:
  19. 　請求項１５ないし請求項１８のいずれかに記載の半導体素子の製造方法であって、
    　前記第２のIII族窒化物のバンドギャップが前記第１のIII族窒化物のバンドギャップよりも大きい、
    ことを特徴とする半導体素子の製造方法。     A method for manufacturing a semiconductor device according to any one of claims 15 to 18, comprising:
    The band gap of the second group III nitride is larger than the band gap of the first group III nitride;
    A method for manufacturing a semiconductor device, comprising:
  20. 　請求項１５ないし請求項１９のいずれかに記載の半導体素子の製造方法であって、
    　前記ショットキー性電極形成工程においては、前記ショットキー性電極をＮｉ、Ｐｔ、Ｐｄ、Ａｕの少なくとも１つを含むように形成する、
    ことを特徴とする半導体素子の製造方法。     A method of manufacturing a semiconductor device according to any one of claims 15 to 19,
    In the Schottky electrode forming step, the Schottky electrode is formed so as to include at least one of Ni, Pt, Pd, and Au.
    A method for manufacturing a semiconductor device, comprising:
  21. 　請求項１５ないし請求項２０のいずれかに記載の半導体素子の製造方法であって、
    　前記第２のIII族窒化物が、Ｉｎｘ２Ａｌｙ２Ｎ（ｘ２＋ｙ２＝１、０．１４≦ｘ２≦０．２４）である、
    ことを特徴とする半導体素子の製造方法。     A method of manufacturing a semiconductor device according to any one of claims 15 to 20,
    The second group III nitride is In x2 Al y2 N (x2 + y2 = 1, 0.14 ≦ x2 ≦ 0.24).
    A method for manufacturing a semiconductor device, comprising:
  22. 　請求項１５ないし請求項２１のいずれかに記載の半導体素子の製造方法であって、
    　前記第１のIII族窒化物がＡｌｙ１Ｇａｚ１Ｎ（ｙ１＋ｚ１＝１、ｚ１＞０）である、
    ことを特徴とする半導体素子の製造方法。     A method of manufacturing a semiconductor device according to any one of claims 15 to 21,
    The first group III nitride is Al y1 Ga z1 N (y1 + z1 = 1, z1> 0).
    A method for manufacturing a semiconductor device, comprising:
  23. 　請求項２２に記載の半導体素子の製造方法であって、
    　前記第１のIII族窒化物がＧａＮである、
    ことを特徴とする半導体素子の製造方法。     A method of manufacturing a semiconductor device according to claim 22,
    The first group III nitride is GaN;
    A method for manufacturing a semiconductor device, comprising:
  24. 　請求項２２または請求項２３に記載の半導体素子の製造方法であって、
    　前記チャネル層と前記障壁層との間に、Ｉｎｘ３Ａｌｙ３Ｇａｚ３Ｎ（ｘ３＋ｙ３＋ｚ３＝１、ｙ３＞０）なる組成を有し、前記第２のIII族窒化物よりもバンドギャップが大きい第３のIII族窒化物にてスペーサ層を形成するスペーサ層形成工程、
    をさらに備えることを特徴とする半導体素子の製造方法。     A method of manufacturing a semiconductor device according to claim 22 or claim 23,
    A third layer having a composition of In x3 Al y3 Ga z3 N (x3 + y3 + z3 = 1, y3> 0) between the channel layer and the barrier layer and having a band gap larger than that of the second group III nitride. A spacer layer forming step of forming a spacer layer with a group III nitride of
    A method for manufacturing a semiconductor device, further comprising:
  25. 　請求項２４に記載の半導体素子の製造方法であって、
    　前記第３のIII族窒化物がＡｌＮである、
    ことを特徴とする半導体素子の製造方法。     A method of manufacturing a semiconductor device according to claim 24,
    The third group III nitride is AlN;
    A method for manufacturing a semiconductor device, comprising:
  26. 　請求項１５ないし請求項２５のいずれかに記載の半導体素子の製造方法であって、
    　前記ショットキー性電極が形成される前記キャップ層にオーミック性電極を接合形成するオーミック性電極形成工程、
    をさらに備えることを特徴とする半導体素子の製造方法。     A method for manufacturing a semiconductor device according to any one of claims 15 to 25, wherein:
    An ohmic electrode forming step of bonding an ohmic electrode to the cap layer where the Schottky electrode is formed;
    A method for manufacturing a semiconductor device, further comprising:
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