WO2013159541A1 - 一种三电平逆变器 - Google Patents
一种三电平逆变器 Download PDFInfo
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- WO2013159541A1 WO2013159541A1 PCT/CN2012/086388 CN2012086388W WO2013159541A1 WO 2013159541 A1 WO2013159541 A1 WO 2013159541A1 CN 2012086388 W CN2012086388 W CN 2012086388W WO 2013159541 A1 WO2013159541 A1 WO 2013159541A1
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- switch tube
- level inverter
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
- H02M1/15—Arrangements for reducing ripples from dc input or output using active elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
Definitions
- the present invention relates to the field of power system technologies, and in particular, to a three-level inverter.
- a conventional three-level inverter includes four switching tubes, one, two, three, and four switching tubes Q1, Q2, Q3, and Q4, which are sequentially connected in series at the positive and negative ends of the DC bus.
- the first and fourth switch tubes Q1 and Q4 are outer tubes, and the second and third switch tubes Q2 and Q3 are inner tubes.
- Each switch has a drive control signal.
- the second switching transistor Q2 is normally turned on, the fourth switching transistor Q4 is normally closed, and the first switching transistor Q1 and the third switching transistor Q3 are electrically connected according to the SP and are guaranteed to die. Area.
- the third switching transistor Q3 is normally turned on, the first switching transistor Q1 is normally closed, and the fourth switching transistor Q4 and the second switching transistor Q2 are electrically connected in accordance with the SP and are guaranteed to be dead.
- the current current limiting method is to forcibly close the first, second, third, and fourth switching tubes Ql, Q2, Q3, and Q4 according to a certain timing. Take the positive half cycle of the output voltage as an example: Enter the current limit to forcibly turn off the first, second, third, and fourth switch tubes Ql, Q2, Q3, and Q4. When the current decays below the set current threshold, the current limit is exited and Q2 is turned on first. This causes the reverse recovery of the body diodes D3, D4 of the third and fourth switch tubes, causing voltage stress problems on the switch tubes on the bridge arms.
- the inductor is required to have a large enough inductance. Otherwise, when the nonlinear load is suddenly applied, the inverter inductor L will flow a large surge current, causing the current stress of the power switch tube to be excessively damaged.
- the output capacitor C When a non-linear load is suddenly applied, the output capacitor C will resonate with the load to make the output voltage change from positive to negative or negative, and then enter the current limit. If only the outer tube (Ql, Q4) is turned off, the inductor L will continue to flow. Still suffering from a positive voltage, I L continues to rise. If the inductance L of the inverter does not have a large enough inductance to slow the rise of I L , it will cause the current stress of the switch to be over-regulated. Add the inductance L of the inverter When it is large enough, it will increase the cost and increase the volume. This phenomenon is generally not allowed.
- the present invention provides a three-level inverter, comprising: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, a second capacitor, a first diode, and a second a diode, an inductor, and a third capacitor;
- the first capacitor and the second capacitor are connected in series, and the first capacitor and the second capacitor are connected to a fourth node;
- the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are sequentially connected in series between the first capacitor and the second capacitor;
- the first switch tube and the second switch tube are connected to the first node;
- the second switch tube and the third switch tube are connected to the second node, the third switch tube and the fourth switch The tube is connected to the third node;
- the anode of the first diode is connected to the fourth node, the cathode of the first diode is connected to the first node, and the cathode of the second diode is connected to the fourth node, the second The anode of the pole tube is connected to the third node;
- the inductor and the third capacitor are connected in series between the second node and the fourth node, and the inductor and the third capacitor are connected to the fifth node;
- a clamp circuit is connected in parallel across the third capacitor.
- the clamping circuit comprises a first clamping diode and a second clamping diode; an anode of the first clamping diode is connected to the second fifth node; a cathode connection of the first clamping diode Fourth node;
- a cathode of the second clamping diode is connected to the fifth node; an anode of the second clamping diode is connected to a fourth node;
- the controllable poles of the first clamping diode and the second clamping diode are respectively configured to receive a driving signal.
- the controllable pole receiving the driving signal of the second clamping diode is enabled; the controllable pole receiving the driving signal of the first clamping diode is not enabled ;
- controllable pole receiving the driving signal of the first clamping diode is enabled; and the controllable pole receiving the driving signal of the second clamping diode is not enabled.
- entering the current limit only forcibly turns off the first switch tube and the fourth switch tube.
- the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are identical to the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube.
- the present invention discloses the following technical effects: According to the three-level inverter of the embodiment of the present invention, since a clamp circuit is connected in parallel across the third capacitor (output capacitor), When the output voltage of the inverter is positive for half a cycle, the output voltage is clamped between the voltage of the fourth node and the positive terminal voltage of the DC bus; when the output voltage of the inverter is negative for half a cycle, the output voltage is clamped. Between the negative terminal voltage of the DC bus and the fourth node voltage.
- FIG. 1 is a top structural view of a level inverter according to a first embodiment of the present invention
- FIG. 2 is a top structural view of a level inverter according to a first embodiment of the present invention
- FIG. 3 is a logic diagram of control of first and second clamp diodes of a level inverter according to a first embodiment of the present invention
- FIG. 4 is a first modal view of a level inverter according to a first embodiment of the present invention.
- Fig. 5 is a second modal view of the level inverter of the first embodiment of the present invention. The present invention will be further described in detail with reference to the drawings and specific embodiments.
- FIG. 1 there is shown a top view of a three-level inverter of the first embodiment of the present invention.
- the three-level inverter includes: a first switching transistor Q1, a second switching transistor Q2, a third switching transistor Q3, a fourth switching transistor Q4, a first capacitor C1, and a second capacitor C2. a first diode D5, a second diode D6, and an inductor L and a third capacitor C (ie, an output capacitor).
- the positive terminal +BUS of the DC bus and the negative terminal of the DC bus -BUS are connected in series with a first capacitor C1 and a second capacitor C2, and a connection between the first capacitor C1 and the second capacitor C2 is connected to the fourth node N.
- the first switching transistor Q1, the second switching transistor Q2, the third switching transistor Q3, and the fourth switching transistor Q4 are sequentially connected in series between the first capacitor C1 and the second capacitor C2.
- the first switch tube Q1 and the second switch tube Q2 are connected to the first node ml; the second switch tube Q2 and the third switch tube Q3 are connected to the second node m2, and the third switch tube Q3 and The fourth switch tube Q4 is connected to the third node m3.
- the anode of the first diode D5 is connected to the fourth node N
- the cathode of the first diode D5 is connected to the first node ml
- the cathode of the second diode is connected to the fourth node N.
- the anode of the second diode is connected to the third node m3.
- the anode of the first diode D5 is connected to the fourth node N, the cathode of the first diode D5 is connected to the first node ml; the cathode of the second diode D6 is connected to the fourth node N.
- the anode of the second diode D6 is connected to the third node m3.
- the inductor L and the third capacitor C are connected in series between the second node m2 and the fourth node N, and the inductor L and the third capacitor C are connected to the fifth node m5.
- a clamp circuit 1 is connected in parallel across the third capacitor C.
- the clamp circuit 1 since the clamp circuit 1 is connected in parallel across the third capacitor C (output capacitor), the output voltage can be clamped when the output voltage is positive for half a cycle. Bit to the fourth node N voltage and the positive terminal +BUS voltage of the DC bus; at the negative half cycle of the output voltage, the output voltage is clamped to the negative terminal voltage of the DC bus -BUS and the fourth node N Between pressure.
- the first switching tube Q1 and the fourth switching tube Q4 when the current limiting is entered, only the outer tube, the first switching tube Q1 and the fourth switching tube Q4 can be forcibly turned off, thereby avoiding the exit of the current limiting in the positive half cycle of the output voltage.
- clamp circuit 1 In order to facilitate the understanding of those skilled in the art, the specific structure of the clamp circuit 1 will be exemplified below.
- FIG. 2 is a topological structural view of a three-level inverter according to a second embodiment of the present invention.
- the three-level inverter of the second embodiment of the present invention is different from the first embodiment in that the clamp circuit 1 includes two clamp diodes.
- the clamp circuit 1 of the three-level inverter of the second embodiment of the present invention specifically includes a first clamp diode D7 and a second clamp diode D8.
- the anode of the first clamping diode D7 is connected to the fifth node m5; the cathode of the first clamping diode D7 is connected to the fourth node N.
- the cathode of the second clamping diode D8 is connected to the fifth node m5; the anode of the second clamping diode D8 is connected to the fourth node N.
- the controllable poles of the first and second clamping diodes D7, D8 are respectively used to receive a driving signal.
- the driving signals of the first and second clamping diodes D7 and D8 can be specifically shown in FIG. 3. Referring to Fig. 3, there is shown a logic diagram of first and second clamp diode control of a three-level inverter according to a second embodiment of the present invention.
- the controllable pole receiving the driving signal of the second clamping diode D8 is enabled; the first clamp The controllable pole of the diode D7 receives the drive signal as disabled.
- the controllable pole receiving the driving signal of the first clamping diode D7 is enabled during a negative half cycle of the output voltage of the inverter (ie, the output filter capacitor - the voltage on the third capacitor C); the second clamp The controllable pole receiving the drive signal of diode D8 is not enabled. In order to prevent the occurrence of dead zones, the above drive signals need to ensure dead time.
- the output voltage can be clamped between the fourth node N voltage and the positive terminal +BUS voltage of the DC bus during the positive half cycle of the output voltage.
- the output voltage is negative for half a cycle, the output voltage is clamped between the negative terminal of the DC bus, the -BUS voltage, and the voltage at the fourth node, N.
- the output voltage will not resonate to 0, so that when the inductor L is freewheeled after entering the current limit, the forward voltage is no longer withstand, and the inductor L current is prevented from rising further, which solves the problem of current stress of the switch tube and saves inductance. cost.
- the three-level inverter according to the embodiment of the present invention can use an inverter inductor with a small inductance and a current stress of the switch tube under the condition of medium power, large current, and limited volume and inductance of the inductor. Not overstated.
- FIG. 4 the figure is a first modal view of a three-level inverter according to a second embodiment of the present invention.
- the first mode of the three-level inverter of the second embodiment of the present invention is an operating state in which the inductor L is freewheeled and the output voltage is clamped during the positive half cycle of the voltage.
- the first and fourth switch tubes Ql, Q4 When entering the current limit, whether the output voltage of the inverter is positive half cycle or negative half cycle, the first and fourth switch tubes Ql, Q4 can be forcibly turned off.
- the freewheeling path of L is the fourth node of the first diode D5, the second switching transistor Q2, and the third capacitor of the inductor.
- the inductor L is not 7-biased by the forward voltage, preventing further rise of the current. Therefore, the switching tube current is effectively controlled, and the current stress is not oversized.
- FIG. 5 there is shown a second modal view of a three-level inverter according to a second embodiment of the present invention.
- the second mode of the three-level inverter of the second embodiment of the present invention is an operating state in which the inductor L is freewheeling and the output voltage is clamped during the negative half cycle of the voltage.
- the inner tube that is, the second and third switch tubes Q2 and Q3 can be selected as the body. Tubes with low diode characteristics are required to reduce the cost of switching devices.
- the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, and the fourth switch tube Q4 described herein may all be IGBT tubes.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
一种三电平逆变器,包括:第一、二、三、四开关管(Q1、Q2、Q3、Q4)、第一、二电容(C1、C2)、第一、二二极管(D5、D6)、电感(L)和第三电容(C)。第一电容和第二电容串联,第一电容和第二电容连接于第四节点(N)。第一、二、三、四开关管依次串联在第一、二电容之间。第一、二开关管连接于第一节点(m1),第二、三开关管连接于第二节点(m2),第三、四开关管连接于第三节点(m3)。第一二极管的正极连接于第四节点,第一二极管的负极连接于第一节点。第二二极管的负极连接于第四节点,第二二极管的正极连接于第三节点。电感和第三电容串联于第二、四节点之间,电感和第三电容连接于第五节点(m5)。第三电容两端并联有钳位电路(1)。该三电平逆变器在进入限流时只关闭第一和第四开关管,并控制开关管的电流应力。
Description
种三电平逆变器 技术领域 本发明涉及电源***技术领域, 特别是涉及一种三电平逆变器。
背景技术 现有三电平逆变器包括依次串联在直流母线正、负端的四个开关管一一 第一、 二、 三、 四开关管 Ql、 Q2、 Q3、 Q4。 第一、 四开关管 Ql、 Q4为外管, 第二、 三开关管 Q2、 Q3为内管。 每个开关管有一路驱动控制信号。
在逆变器的输出电压的正半周时, 控制第二开关管 Q2常通、 第四开关 管 Q4常闭, 第一开关管 Q1和第三开关管 Q3按 SP醫互补导通并保证其死 区。
在输出电压的负半周时,控制第三开关管 Q3常通、第一开关管 Q1常闭, 第四开关管 Q4和第二开关管 Q2按 SP醫互补导通并保证其死区。
当突加负载,且检测到开关管电流大于设定电流阔值时,需要釆用限流 处理。 目前常见的限流方式是按照一定时序强制关闭第一、 二、 三、 四开 关管 Ql、 Q2、 Q3、 Q4。 以输出电压正半周为例: 进入限流强制关闭第一、 二、 三、 四开关管 Ql、 Q2、 Q3、 Q4。 当电流衰减至低于设定电流阔值, 即 退出限流, 此时 Q2 先开通。 这会造成第三、 四开关管的体二极管 D3、 D4 的反向恢复, 引起桥臂上开关管电压应力问题。
如果进入限流时只强制关闭外管 (Ql、 Q4 )、 内管 (Q2、 Q3 )导通, 则 当退出限流时桥臂上虽然不存在二极管反向恢复的问题, 但此限流方案要 求电感有足够大的感量, 否则突加非线性负载时, 逆变电感 L将流过很大 的浪涌电流, 导致功率开关管电流应力过大而损坏。
突加非线性负载时, 输出电容 C会与负载产生谐振使输出电压由正变 负或由负变正, 此时进入限流如果只关闭外管(Ql、 Q4 ) , 则电感 L续流 时仍承受正电压, IL继续上升, 如果逆变器的电感 L没有足够大的感量来 减緩 IL上升的速度, 将会导致开关管电流应力超规。 将逆变器的电感 L加
到足够大, 就会使成本提高, 且体积增大, 一般不允许这种现象发生。 因此, 在进入限流时只需关闭外管, 控制开关管的电流应力, 是本领 域技术人员亟需解决的技术问题。 发明内容 有鉴于此,本发明的目的在于提供一种三电平逆变器,用于实现在进入 限流时只关闭外管, 并控制开关管的电流应力。
本发明提供一种三电平逆变器, 包括: 第一开关管、 第二开关管、 第三 开关管、 第四开关管、 第一电容、 第二电容、 第一二极管、 第二二极管、 电感和第三电容;
所述第一电容和所述第二电容串联,所述第一电容和所述第二电容连接 于第四节点;
所述第一开关管、 所述第二开关管、 所述第三开关管、 所述第四开关管 依次串联在所述第一电容和所述第二电容之间;
所述第一开关管和所述第二开关管连接于第一节点;所述第二开关管和 所述第三开关管连接于第二节点, 所述第三开关管和所述第四开关管连接 于第三节点;
所述第一二极管的正极连接于第四节点,所述第一二极管的负极连接于 第一节点; 所述第二二极管的负极连接于第四节点, 所述第二二极管的正 极连接于第三节点;
所述电感和所述第三电容串联于第二节点和第四节点之间,所述电感和 所述第三电容连接于第五节点;
所述第三电容两端并联有钳位电路。
优选地,所述钳位电路包括第一钳位二极管和第二钳位二极管; 所述第 一钳位二极管的阳极与所述第二第五节点相连; 所述第一钳位二极管的阴 极连接第四节点;
所述第二钳位二极管的阴极与所述第五节点相连;所述第二钳位二极管 的阳极连接第四节点;
所述第一钳位二极管、所述第二钳位二极管的可控极分别用于接收驱动 信号。
优选地,在逆变器的输出电压的正半周,所述第二钳位二极管的可控极 接收驱动信号为使能; 所述第一钳位二极管的可控极接收驱动信号为不使 能;
在输出电压的负半周 ,所述第一钳位二极管的可控极接收驱动信号为使 能; 所述第二钳位二极管的可控极接收驱动信号为不使能。
优选地, 当所述电感的电流达到设定的保护阔值点时,进入限流仅强制 关闭所述第一开关管、 所述第四开关管。
优选地, 所述第一开关管、 第二开关管、 第三开关管和第四开关管均为
IGBT管。
根据本发明提供的具体实施例, 本发明公开了以下技术效果: 本发明实施例所述三电平逆变器, 由于在所述第三电容(输出电容)两 端并联有钳位电路, 可以实现在逆变器的输出电压正半周时, 使得输出电 压被钳位到第四节点电压和直流母线的正端电压之间; 在逆变器的输出电 压负半周时, 使得输出电压被钳位到直流母线的负端电压和第四节点电压 之间。 当突加非线性负载时, 输出电压不会谐振过 0点, 使得进入限流后 的电感续流时, 不再承受正向电压, 阻止电感电流进一步上升, 解决了开 关管电流应力问题。
本发明实施例所述三电平逆变器,在进入限流时可以只强制关闭外管一 一第一开关管和第四开关管, 避免了在输出电压正半周退出限流时第三、 四开关管的体二极管反向恢复引起的电压应力问题, 以及在输出电压负半 周退出限流时第一、 二开关管的体二极管反向恢复引起的电压应力问题。 附图说明 图 1为本发明第 实施例的 电平逆变器拓朴结构图;
图 2为本发明第 实施例的 电平逆变器拓朴结构图;
图 3为本发明第 实施例的 电平逆变器的第一、二钳位二极管控制逻 辑图;
图 4为本发明第 实施例的 电平逆变器第一模态图;
图 5为本发明第 实施例的 电平逆变器第二模态图。
具体实施方式 为使本发明的上述目的、 特征和优点能够更加明显易懂, 下面结合附 图和具体实施方式对本发明作进一步详细的说明。
有鉴于此,本发明的目的在于提供一种三电平逆变器,用于实现在进入 限流时只关闭外管, 并控制开关管的电流应力。
参见图 1 , 该图为本发明第一实施例的三电平逆变器拓朴结构图。
本发明第一实施例所述三电平逆变器, 包括: 第一开关管 Ql、 第二开 关管 Q2、 第三开关管 Q3、 第四开关管 Q4、 第一电容 Cl、 第二电容 C2、 第 一二极管 D5、 第二二极管 D6、 以及电感 L和第三电容 C (即输出电容)。
直流母线的正端 +BUS 和直流母线的负端 -BUS 之间串联有第一电容 C1 和第二电容 C2 , 第一电容 C1和第二电容 C2之间的连接于第四节点 N。
第一开关管 Ql、 第二开关管 Q2、 第三开关管 Q3、 第四开关管 Q4依次 串联在所述第一电容 C1和所述第二电容 C2之间。
所述第一开关管 Q1和第二开关管 Q2连接于第一节点 ml ; 所述第二开 关管 Q2和所述第三开关管 Q3连接于第二节点 m2 ,所述第三开关管 Q3和所 述第四开关管 Q4连接于第三节点 m3。
所述第一二极管 D5的正极连接于第四节点 N,所述第一二极管 D5的负 极连接于第一节点 ml ; 所述第二二极管的负极连接于第四节点 N, 所述第 二二极管的正极连接于第三节点 m3。
所述第一二极管 D5的正极连接于第四节点 N,所述第一二极管 D5的负 极连接于第一节点 ml ; 所述第二二极管 D6的负极连接于第四节点 N, 所述 第二二极管 D6的正极连接于第三节点 m3。
所述电感 L和所述第三电容 C串联于第二节点 m2和第四节点 N之间, 所述电感 L和所述第三电容 C连接于第五节点 m5。
所述第三电容 C两端并联有钳位电路 1。
本发明第一实施例所述三电平逆变器, 由于在所述第三电容 C (输出电 容)两端并联有钳位电路 1 , 可以实现在输出电压正半周时, 使得输出电压 被钳位到第四节点 N电压和直流母线的正端 +BUS电压之间; 在输出电压负 半周时, 使得输出电压被钳位到直流母线的负端电压 -BUS和第四节点 N电
压之间。 当突加非线性负载时, 输出电压不会谐振过 0 点, 使得进入限流 后的电感 L续流时, 不再承受正向电压, 阻止电感 L电流进一步上升, 解 决了开关管电流应力问题。
本发明第一实施例所述三电平逆变器,在进入限流时可以只强制关闭外 管一一第一开关管 Q1和第四开关管 Q4 ,避免了在输出电压正半周退出限流 时第三、 四开关管 Q3、 Q4的体二极管 D3、 D4反向恢复引起的电压应力问 题, 以及在输出电压负半周退出限流时第一、 二开关管 Ql、 Q2的体二极管 Dl、 D2反向恢复引起的电压应力问题。
为了便于本领域技术人员的理解, 下面举例说明钳位电路 1 的具体结 构。
参见图 2为本发明第二实施例的三电平逆变器拓朴结构图。
本发明第二实施例的三电平逆变器与第一实施例的区别在于,所述钳位 电路 1包括两个钳位二极管。
本发明第二实施例的三电平逆变器的钳位电路 1 具体包括第一钳位二 极管 D7和第二钳位二极管 D8。
所述第一钳位二极管 D7的阳极与所述第五节点 m5相连;所述第一钳位 二极 D7管的阴极连接第四节点 N。
所述第二钳位二极管 D8的阴极与所述第五节点 m5相连;所述第二钳位 二极 D8管的阳极连接第四节点 N。
所述第一、 二钳位二极管 D7、 D8的可控极分别用于接收驱动信号。 所述第一、 二钳位二极管 D7、 D8的驱动信号具体可以参见图 3所示。 参见图 3, 该图为本发明第二实施例的三电平逆变器的第一、 二钳位二 极管控制逻辑图。
在逆变器的输出电压 (即输出滤波电容-第三电容 C上的电压) 的正半 周, 所述第二钳位二极管 D8的可控极接收驱动信号为使能; 所述第一钳位 二极管 D7的可控极接收驱动信号为不使能。
在逆变器的输出电压 (即输出滤波电容-第三电容 C上的电压) 的负半 周, 所述第一钳位二极管 D7的可控极接收驱动信号为使能; 所述第二钳位 二极管 D8的可控极接收驱动信号为不使能。
为了防止死区出现, 上述的驱动信号均需要保证死区时间。
由于第一、 二钳位二极管 D7、 D8釆用上述控制逻辑, 可以实现在输出 电压正半周时, 输出电压被箝位在第四节点 N 电压到直流母线的正端 +BUS 电压之间, 在输出电压负半周时, 输出电压被箝位在直流母线的负端 -BUS 电压到第四节点 N电压之间。 当突加非线性负载时输出电压不会谐振过 0 , 使进入限流后电感 L续流时, 不再承受正向电压, 阻止电感 L电流进一步 上升, 解决了开关管电流应力问题, 节省电感成本。
本发明实施例所述三电平逆变器在应用于中等功率,电流较大且电感的 体积与感量有限的条件下, 可以使用电感量很小的逆变电感, 同时保障开 关管电流应力不超规。
参见图 4 , 该图为本发明第二实施例的三电平逆变器第一模态图。
本发明第二实施例的三电平逆变器第一模态为在电压正半周, 电感 L 续流及输出电压被箝位的工作状态。
当突加非线性负载, 由于输出电容一一第三电容 C与负载谐振, 使第 三电容 C的电压 Uc跌落到负时, 第二钳位二极管 D8将导通, 使第三电容 C的电压 Uc被箝位至第四节点 N的电压。
如果检测到电感电流达到设定保护阔值点时, 则进入限流。
进入限流时,不管是逆变器的输出电压正半周或负半周,可以强制关外 管一一第一、 四开关管 Ql、 Q4。
在逆变器的输出电压正半周, 由于第四开关管 Q4为关闭状态, 只需强 制第一开关管 Q1 (当然提供强制关闭第一、 四开关管 Ql、 Q4的控制信号也 可),电感 L的续流路径第四节点 第一二极管 D5 第二开关管 Q2 电 感 第三电容(。
此时第三电容 C的电压 Uc已被第二钳位二极管 D7箝位至第四节点 N 的电压,则电感 L两端电压 Ui=UN-Uc即为 0。电感 L两端不 7 受正向电压, 阻止了电流的进一步上升。 因此开关管电流得到有效控制, 电流应力不会 超规。
当检测到电感电流低于设定保护阔值后, 则退出限流模式, 恢复开关 管正常 PWM发波。
电压负半周同理可实现, 如图 5所示。
参见图 5 , 该图为本发明第二实施例的三电平逆变器第二模态图。
本发明第二实施例的三电平逆变器第二模态为在电压负半周, 电感 L 续流及输出电压箝位的工作状态。
在逆变器的输出电压负半周, 由于第一开关管 Q1为关闭状态, 只需强 制第四开关管 Q4 (当然提供强制关闭第一、 四开关管 Ql、 Q4的控制信号也 可), 电感 L续流路径第三电容 电感 第三开关管 Q3 第二二极管 D6 第四节点 N。
这样就避免了在电压正半周退出限流时第三、 四开关管 Q3、 Q4的体二 极管 D3、 D4反向恢复引起的电压应力问题;以及在电压负半周退出限流时, 第一、 二开关管 Ql、 Q2的体二极管 Dl、 D2反向恢复引起的电压应力问题。
由于本发明实施例所述三电平逆变器,在退出限流时桥臂上不存在开关 管体二极管反向恢复的问题, 因此内管即第二、 三开关管 Q2、 Q3可以选用 体二极管特性要求不高的管子, 降低了开关器件成本。
本文所述第一开关管 Ql、 第二开关管 Q2、 第三开关管 Q3和第四开关 管 Q4可以均为 IGBT管。
以上对本发明所提供的三电平逆变器, 进行了详细介绍, 本文中应用 是用于帮助理解本发明的方法及其核心思想; 同时, 对于本领域的一般技 术人员, 依据本发明的思想, 在具体实施方式及应用范围上均会有改变之 处。 综上所述, 本说明书内容不应理解为对本发明的限制。
Claims
1、 一种三电平逆变器, 其特征在于, 包括: 第一开关管、 第二开关管、 第三开关管、 第四开关管、 第一电容、 第二电容、 第一二极管、 第二二极 管、 电感和第三电容;
所述第一电容和所述第二电容串联,所述第一电容和所述第二电容连接 于第四节点;
所述第一开关管、 所述第二开关管、 所述第三开关管、 所述第四开关管 依次串联在所述第一电容和所述第二电容之间;
所述第一开关管和所述第二开关管连接于第一节点;所述第二开关管和 所述第三开关管连接于第二节点, 所述第三开关管和所述第四开关管连接 于第三节点;
所述第一二极管的正极连接于第四节点,所述第一二极管的负极连接于 第一节点; 所述第二二极管的负极连接于第四节点, 所述第二二极管的正 极连接于第三节点;
所述电感和所述第三电容串联于第二节点和第四节点之间,所述电感和 所述第三电容连接于第五节点;
所述第三电容两端并联有钳位电路。
2、 根据权利要求 1所述的三电平逆变器, 其特征在于, 所述钳位电路 包括第一钳位二极管和第二钳位二极管; 所述第一钳位二极管的阳极与所 述第二第五节点相连; 所述第一钳位二极管的阴极连接第四节点;
所述第二钳位二极管的阴极与所述第五节点相连;所述第二钳位二极管 的阳极连接第四节点;
所述第一钳位二极管、所述第二钳位二极管的可控极分别用于接收驱动 信号。
3、 根据权利要求 2所述的三电平逆变器, 其特征在于,
在逆变器的输出电压的正半周,所述第二钳位二极管的可控极接收驱动 信号为使能; 所述第一钳位二极管的可控极接收驱动信号为不使能;
在输出电压的负半周 ,所述第一钳位二极管的可控极接收驱动信号为使 能; 所述第二钳位二极管的可控极接收驱动信号为不使能。
4、 根据权利要求 3所述的三电平逆变器, 其特征在于,
当所述电感的电流达到设定的保护阔值点时,进入限流仅强制关闭所述 第一开关管、 所述第四开关管。
5、 根据权利要求 1至 4任一项所述的三电平逆变器, 其特征在于, 所 述第一开关管、 第二开关管、 第三开关管和第四开关管均为 IGBT管。
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