WO2013121954A1 - Transistor à effet de champ au graphène et élément à semi-conducteur au graphène - Google Patents

Transistor à effet de champ au graphène et élément à semi-conducteur au graphène Download PDF

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WO2013121954A1
WO2013121954A1 PCT/JP2013/052766 JP2013052766W WO2013121954A1 WO 2013121954 A1 WO2013121954 A1 WO 2013121954A1 JP 2013052766 W JP2013052766 W JP 2013052766W WO 2013121954 A1 WO2013121954 A1 WO 2013121954A1
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graphene
channel layer
layer
insulator layer
effect transistor
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PCT/JP2013/052766
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English (en)
Japanese (ja)
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将 鷹林
泰一 尾辻
雄二 ▲高▼桑
修一 小川
猛 楊
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国立大学法人東北大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/05—Preparation or purification of carbon not covered by groups C01B32/15, C01B32/20, C01B32/25, C01B32/30
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys

Definitions

  • the present invention relates to a graphene field effect transistor and a graphene semiconductor member.
  • Graphite is a kind of carbon allotrope, and is a laminated film in which a six-membered ring unit composed of sp 2 carbon hybrid orbitals is two-dimensionally expanded.
  • Graphene is defined as a single layer film of graphite as shown in FIG.
  • the graphene energy (E) -momentum (p) (or wave number k) relationship (dispersion curve) is linear, and is completely symmetric with respect to both the E and p axes.
  • FIG. 10B in the case of a general semiconductor, both the conduction band and the valence band have a parabolic shape, and the valence band has a gentler slope.
  • m * effective mass of electrons in the conduction band and holes in the valence band
  • a current IDS flowing between a drain and a source is expressed by the following equation.
  • W is the width of the gate electrode (depth)
  • e is the elementary charge
  • n represents carrier density
  • C is the capacitance between the gate insulating film
  • V DS is the drain - source voltage
  • L G is the gate electrode Length.
  • n increases the electrostatic capacitance C between the gate insulating film, or to increase the carrier mobility mu, geometrically shorter L G (miniaturization) or Then, the carrier velocity v may be increased by increasing the electric field strength.
  • the signal processing speed (frequency) is represented by the following equation, where f T (cutoff frequency) is defined as a frequency at which the current amplification factor falls to 1 without being able to follow the current response.
  • f T cutoff frequency
  • V GS and C GS are a gate-source voltage and a capacitance, respectively. From this equation, it can be seen that if the capacitance C between the gate insulating films and the carrier mobility ⁇ are large, a high operating frequency can be obtained.
  • the field effect transistor using a conventional Si has reached the miniaturization limit, can not be reduced L G more, alternate channel materials have been desired large mu, graphene is one of the promising materials is there.
  • the so-called GFET graphene field effect transistor
  • GFET graphene field effect transistor
  • the ohmic junction resistance (contact resistance) between the source / drain electrode and the graphene channel is reduced, the resistance between the gate and the drain (source) (access resistance) is reduced, It is necessary to solve various problems such as establishment of p / n-channel doping technology to solve the problem and gate stack / channel interface control.
  • the current cannot be made zero, the current ON / OFF ratio necessary for digital circuit application cannot be obtained, digital switching operation is difficult, and high speed Problems such as the lack of the saturation region necessary for conversion must also be solved.
  • III-V compound semiconductor devices represented by GaAs use a high electron mobility transistor (HEMT) structure in which a carrier-doped layer and a carrier-running layer (channel) are separated.
  • HEMT high electron mobility transistor
  • This is a semiconductor in which a semiconductor layer having a wider band gap and lower electron affinity is stacked on a channel material, and impurities are doped in layers ( ⁇ -dope) at a position slightly away from the channel in the layer. Is formed, and carriers from there are dropped at the interface with the channel and stored (modulation doping). This is because the channel is not directly modified, so that the introduced carrier is not impurity-scattered in the channel, and the carrier mobility in the channel does not decrease.
  • DLC diamond-like carbon
  • This DLC is doped with a DLC film formed by mixing a different element gas with a carbon-based gas, mainly for mechanical engineering purposes such as low friction, and incorporating the different element into the entire film (for example, Non-Patent Document 4 or 5), by changing the film forming conditions to control the dielectric constant of the DLC, the DLC is mainly made to have a low dielectric constant (low- ⁇ ) and used for an interlayer insulating film (for example, Non-Patent Document 6 or 7), in order to reduce the interface state, a metal element is doped into DLC, and DLC is used as a conductive channel thin film material for a thin film transistor (TFT) (for example, Non-Patent Documents 8 to 8). 11).
  • TFT thin film transistor
  • PA-PECVD photoelectron-controlled plasma CVD
  • Patent Documents 5 to 7 or non-patent documents Patent Documents 5 to 7 or non-patent documents.
  • Reference 12 The PA-PECVD method is a DC plasma film forming method using photoelectrons generated by ultraviolet light irradiation on a sample substrate as a trigger, unlike a method using normal floating electrons as a plasma trigger. Since the plasma generation is limited to the light irradiation site, the film formation site can be precisely controlled, and the generation of soot that becomes a major enemy to the clean room process can be prevented.
  • a PA-PECVD apparatus used in the PA-PECVD method is shown in FIG.
  • the relative dielectric constant of the DLC is about 1 to 5 depending on the concentration ratio of the CH 4 gas in the growth atmosphere (Ar + CH 4 ).
  • the possibility of being able to control and modulate in a wide range up to the vicinity is shown (for example, see Non-Patent Document 13).
  • An object of the present invention is to provide a graphene field effect transistor and a graphene semiconductor member capable of realizing a digital switching operation.
  • the graphene field effect transistor according to the present invention is electrically connected to a channel layer made of graphene, an insulator layer provided on the channel layer and made of a material having low reactivity with graphene, and the channel layer. And a source electrode and a drain electrode which are arranged apart from each other at a position sandwiching the insulator layer, and a gate electrode provided on the insulator layer, and the insulator layer has a carrier in the channel layer. It has the thin film-like modulation
  • the thin film-like modulation doped portion in the insulator layer provided on the channel layer made of graphene can supply carriers to the channel layer.
  • the density can be increased.
  • the channel layer is not directly modified, carriers are not scattered by impurities in the channel layer, and carrier mobility does not decrease.
  • the insulator layer is made of a material having low reactivity with graphene, the channel layer is not damaged even if the insulator layer is provided directly on the channel layer made of graphene.
  • the graphene field-effect transistor according to the present invention can increase the carrier density and the carrier mobility without directly damaging the graphene channel layer as in the HEMT structure, and can improve the operation speed. it can.
  • the channel layer is made of graphene, so that the operation speed is higher than that of a conventional FET using Si or the like, and the operation in the terahertz region that cannot be realized by the conventional FET is achieved. Can be possible. For this reason, it is expected that the amount of information communication in the information society that will develop in the future can be covered.
  • the modulation doped portion is formed by doping an impurity element (hetero element) in the insulator layer.
  • an insulator layer and a material having low reactivity with graphene are carriers in the channel layer with respect to the channel layer, even if the material is in direct contact with the channel layer made of graphene. It is a material that does not damage to the extent that hinders movement.
  • 1) chemical reactivity with graphene, 2) stress due to lattice mismatch or surface non-planarity with graphene, generation of defects and defect levels, and 3) scattering effect at the interface with graphene 4) is a material that is mechanically, chemically, and electrically stable against environmental changes such as temperature and humidity. Specific examples include diamond-like carbon (DLC) and hBN (hexagonal Boron Nitride).
  • the thin film-like modulation dope portion only needs to be thinly distributed at least at a certain local position in the thickness direction of the insulator layer, and the distribution is uniform and planar.
  • the distribution may be uneven and formed in an island shape, or may be formed in a stripe shape.
  • the modulation doped portion is provided between the channel layer with a distance capable of supplying carriers to the channel layer by a tunnel effect.
  • the modulation doped portion is provided with a distance of 3 to 6 nm between the channel layer and the channel layer.
  • carriers can be efficiently supplied from the modulation doped portion to the channel layer without directly modifying the channel layer. For this reason, the carrier density and carrier mobility can be particularly effectively increased, and the operation speed can be improved.
  • the insulator layer is preferably made of diamond-like carbon.
  • Diamond-like carbon is an amorphous carbon material composed of sp 2 carbon, sp 3 carbon, and hydrogen, and has a high chemical affinity for graphene because it is the same carbonaceous material as graphene. Specifically, 1) chemical reactivity with graphene, 2) generation of stresses and defects due to lattice mismatch and surface non-uniformity with graphene, and 3) graphene / insulator interface Scattering effects are extremely low, and 4) they are mechanically, chemically and electrically stable against environmental changes such as temperature and humidity.
  • the insulator layer can be provided directly on the channel layer without damaging the channel layer made of graphene. For this reason, a decrease in carrier density and carrier mobility can be prevented, and a high operating speed can be realized. Moreover, since DLC forms an amorphous and flat film, an insulator layer having a uniform film quality can be obtained.
  • the DLC is made of an insulating material, and is preferably made of, for example, ta-C, ta-C: H, or aC: H.
  • the insulator layer has a high dielectric constant portion extending from immediately below the gate electrode to the channel layer, and the high dielectric constant portion, the source electrode, and the drain electrode,
  • the low dielectric constant portion may have a lower dielectric constant than the high dielectric constant portion, and the modulation doped portion may be included in the low dielectric constant portion.
  • the high dielectric constant portion can provide a high electrostatic induction effect directly below the gate electrode, and channel interface control can be performed with high accuracy.
  • the low dielectric constant portion can reduce the parasitic capacitance between the respective electrodes, and can increase the speed. Since the modulation doped portion is provided between the high dielectric constant portion and the source and drain electrodes, carriers can be effectively supplied to the channel layer in the access region, and the access resistance can be reduced.
  • the insulator layer may have the modulation doped portion in the high dielectric constant portion.
  • the modulation doped portion in the high dielectric constant portion.
  • Pnp junctions or npn junctions can be made. Thereby, current rectification in the channel layer can be provided, and digital switching operation can be realized.
  • the modulation dope portions of the low dielectric constant portion and the high dielectric constant portion may be the same distance from the channel layer or may be different.
  • the graphene semiconductor member according to the present invention includes a channel layer made of graphene and an insulator layer formed on the channel layer and made of a material having low reactivity with graphene. It has a thin film-like modulation doped portion capable of supplying carriers to the channel layer.
  • the graphene semiconductor member according to the present invention can be used as a member for a touch panel, for example, by using a highly transparent material for the insulator layer.
  • the graphene semiconductor member according to the present invention can constitute the graphene field effect transistor according to the present invention by connecting the source electrode, the drain electrode, and the gate electrode.
  • the graphene semiconductor member according to the present invention since the thin film-like modulation doped portion in the insulator layer provided on the channel layer made of graphene can supply carriers to the channel layer, the carrier density of the channel layer Can be increased. At this time, since the channel layer is not directly modified, impurities are not scattered even if carriers are moved in the channel layer, and the carrier mobility is not lowered. In addition, since the insulator layer is made of a material having low reactivity with graphene, the channel layer is not damaged even if the insulator layer is provided directly on the channel layer made of graphene. As described above, the graphene semiconductor member according to the present invention can increase the carrier density and the carrier mobility without directly damaging the graphene channel layer as in the HEMT structure, and can improve the operation speed. .
  • the modulation dope portion is provided between the channel layer with a distance capable of supplying carriers to the channel layer by a tunnel effect. It is preferable that a distance of 3 to 6 nm is provided between them. In this case, carriers can be efficiently supplied from the modulation doped portion to the channel layer without directly modifying the channel layer. For this reason, the carrier density and carrier mobility can be particularly effectively increased, and the operation speed can be improved.
  • the insulator layer is made of, for example, diamond-like carbon or hBN having low reactivity with graphene, and particularly preferably made of diamond-like carbon.
  • diamond-like carbon has a high chemical affinity for graphene
  • an insulator layer is provided directly on the channel layer without damaging the channel layer made of graphene. Can do. For this reason, a decrease in carrier density and carrier mobility can be prevented, and a high operating speed can be realized.
  • DLC forms an amorphous and flat film, an insulator layer having a uniform film quality can be obtained.
  • the DLC is transparent to visible light and infrared light, and can increase carrier density and carrier mobility without lowering transparency, so that it can be used as a low-resistance touch panel.
  • the DLC is made of an insulating material, and is preferably made of, for example, ta-C, ta-C: H, or aC: H.
  • a field effect transistor and a graphene semiconductor member can be provided.
  • the CO of the DLC film withstand voltage when the CO 2 gas is introduced in addition to CH 4 + Ar. It is a graph which shows 2 flow rate ratio dependence.
  • 4 is a graph showing (a) SIMS element depth profile and (b) I DS -V GS characteristics of an example ( ⁇ -doped element) of a graphene field effect transistor corresponding to FIG. 5 is a graph showing (a) SIMS element depth profile and (b) I DS -V GS characteristics of an example (interface adsorption element) of a graphene field effect transistor corresponding to FIGS.
  • FIG. 11 is a schematic side view showing a PA-PECVD apparatus (cited from Non-Patent Document 12).
  • FIG. 1 to 8 show a graphene field effect transistor and a graphene semiconductor member according to an embodiment of the present invention.
  • a graphene field effect transistor 10 includes a channel layer 11 made of graphene provided on a substrate, and a source electrode 12 and a drain electrode 13 provided on the channel layer 11 and insulated from each other. It has a body layer 14 and a gate electrode 15 provided on the insulator layer 14.
  • the source electrode 12 and the drain electrode 13 are disposed apart from each other at both ends of the channel layer 11.
  • the source electrode 12 and the drain electrode 13 are electrically connected to the channel layer 11.
  • the insulator layer 14 is made of diamond-like carbon (DLC) having low reactivity with graphene, and is provided between the source electrode 12 and the drain electrode 13 and around the source electrode 12 and the drain electrode 13. .
  • the insulator layer 14 is doped in the DLC with an impurity such as oxygen or nitrogen that is provided in parallel to the surface of the channel layer 11 and has a thin film-like shape and capable of supplying carriers to graphene. It has a modulation dope section 14a.
  • the modulation doped portion 14a is provided between the channel layer 11 and a distance that can supply carriers to the channel layer 11 by a tunnel effect. In a specific example shown in FIG.
  • the modulation dope portion 14 a is provided with a distance of about 5 nm between the channel layer 11. Note that the thin film-like modulation doped portion 14a only needs to be thinly distributed at a certain local position in the thickness direction of the insulator layer 14, and the distribution is uniform and formed in a planar shape. Alternatively, the distribution may be uneven and formed in an island shape, or may be formed in a stripe shape.
  • the modulation dope portion 14 a can supply carriers to the channel layer 11, so that the carrier density of the channel layer 11 can be increased. At this time, since the channel layer 11 is not directly modified, carriers are not scattered in the channel layer 11 and the carrier mobility does not decrease. Further, since the insulator layer 14 is made of DLC having high chemical affinity for graphene, the channel layer 11 is damaged even if the insulator layer 14 is provided directly on the channel layer 11 made of graphene. Absent. As described above, the graphene field-effect transistor 10 can increase the carrier density and carrier mobility without directly damaging the graphene channel layer 11 unlike the HEMT structure, and can improve the operation speed.
  • the graphene field-effect transistor 10 has a channel layer 11 made of graphene, so that a higher operating speed than that of a conventional FET using Si or the like can be obtained, and operation in a terahertz region that cannot be realized by a conventional FET is possible. can do. For this reason, it is expected that the amount of information communication in the information society that will develop in the future can be covered.
  • the graphene field-effect transistor 10 is, for example, a next-generation ultra-high-speed central processing unit (CPU) that significantly improves the calculation speed of a computer, an ultra-compact ultra-high-speed communication device such as a smartphone that significantly increases communication capacity, and an available radio wave region. It can be used for terahertz wave transmitters.
  • CPU central processing unit
  • the graphene semiconductor member according to the embodiment of the present invention has a configuration in which the gate electrode 15, the source electrode 12, and the drain electrode 13 of the graphene field effect transistor 10 are removed.
  • the graphene semiconductor member according to the embodiment of the present invention not only constitutes the graphene field-effect transistor 10, but also has high DLC transparency, and thus can be used as a member for a touch panel.
  • the graphene field-effect transistor 10 was manufactured by directly forming a DLC thin film as a top gate insulating film (insulator layer 14) on the graphene of the channel layer 11, and the characteristics and the like were evaluated. .
  • the graphene field effect transistor 10 was manufactured by the following method. As the channel layer 11, a 6H-SiC (0001) substrate (Si surface) was ultrahigh-vacuum annealed at 1700 ° C. for 15 minutes, thereby producing an epitaxial several-layer graphene (epitaxial five-layer graphene, EFLG) on the substrate. .
  • Gold (Au) -made gate electrode 15, source electrode 12, and drain electrode 13 were produced using Pt as the ohmic contact metal.
  • the insulator layer 14 made of DLC is formed on the channel layer 11 made of graphene by the photoelectron-controlled plasma CVD (PA-PECVD) method using CH 4 / Ar gas.
  • PA-PECVD photoelectron-controlled plasma CVD
  • the film was formed directly on the top.
  • the manufactured graphene field effect transistor 10 has a channel width (W C ) of 11 ⁇ m, a channel length (L C ) of 6 ⁇ m, and a gate length (L G ) of 5 ⁇ m.
  • the film thickness of the insulator layer 14 was estimated to be 48 nm from the depth profile of secondary ion mass spectrometry (SIMS). From the capacitance (CV) measurement, it was determined that the relative dielectric constant was 5.1 and the equivalent oxide thickness (EOT) was 37 nm.
  • the Dirac voltage (V Dirac ) which is a charge neutral point, is theoretically given by (1/2) V DS , but slightly shifts positive in FIG. This shows that the channel layer 11 has weak p property.
  • FIG. 3 shows a Raman spectrum of the 2D band region of the graphene channel layer 11.
  • FIG. 3 when compared with the spectrum immediately after graphene growth (As-grown), it can be seen that the 2D band peak after deposition of the DLC insulator layer 14 (After DLC forming) is shifted to a high wavenumber. . This suggests that the DLC insulator layer 14 is p-doped from the graphene channel layer 11.
  • the cause of the ambipolar characteristics in the graphene on the 6H-SiC substrate exhibiting strong n-type characteristics is thought to be “unintentional p-doping” from the DLC insulator layer 14 to the graphene channel layer 11.
  • FIG. 4 shows a SIMS element depth profile of the DLC insulator layer 14.
  • the depth (Depth) in the vicinity of the graphene channel layer 11 is 40 to 56 nm and a rapid increase in the number of oxygen atoms is observed, the unintentional p-doping is performed in the insulator layer 14. It is thought that it originates from the oxygen atom. This oxygen atom is considered to be derived from water (H 2 O) molecules remaining in the chamber of the PA-PECVD apparatus used for film formation.
  • the amount of carbon / hydrogen constituting the DLC insulator layer 14 is uniformly obtained in the depth direction of the layer. Can be expected.
  • FIG. 5 shows a band prediction diagram of the graphene field-effect transistor 10 predicted from the above results. As shown in FIG. 5, it is expected that holes in the DLC insulator layer 14 (gate insulating film) are supplied to the graphene channel layer 11 to tunnel through the depletion layer barrier.
  • the region where the concentration of Si atoms suddenly increases and settles to a certain high value is the SiC substrate. Since the position where the Si atom reaches a high value and the position where the concentration of C atoms starts to rise slightly coincide with the position of the dotted line in FIG. 4, the position of the dotted line is the graphene channel on the SiC substrate. It can be identified as the interface between the layer 11 and the DLC insulator layer 14. Note that the thickness of the graphene channel layer 11 is sub-nm and cannot be determined in FIG.
  • the concentration of oxygen atoms is the highest value at the interface between the DLC insulator layer 14 and the graphene channel layer 11 / SiC substrate, the oxygen atoms are localized at the interface position in direct contact with the graphene, It can be seen that they are distributed in both directions of the SiC substrate and the DLC insulator layer 14 while drawing a tail. Note that the seepage to the SiC substrate side is due to a knock on effect or a mixing effect due to etching ions.
  • the carrier supply capacity to the graphene channel layer 11 from the oxygen impurity existing in the vicinity of the interface is the highest, and at the same time, the oxygen impurity present in the interface is Since it acts strongly as a scattering factor, it is presumed to inhibit the transport properties of carriers traveling in the graphene channel layer 11.
  • the insulator layer 14 can be formed with high accuracy, such as the formation of the modulation doped portion 14a, and the graphene shown in FIGS.
  • the field effect transistor 10 can be manufactured with high quality and high accuracy. An example is shown below.
  • a mixed gas source of CH 4 and Ar is generally introduced into the PA-PECVD apparatus chamber.
  • a Xe excimer lamp By irradiating ultraviolet rays with a Xe excimer lamp, atoms in the deposition substrate are excited and photoelectrons are emitted from the substrate surface.
  • CH 4 is ionized by the photoelectrons, and the ionized carbon ions are deposited in an amorphous state on the substrate surface.
  • the film forming speed is controlled to be constant by the degree of vacuum, temperature, gas mixing ratio and flow rate.
  • an oxygen impurity that acts as an acceptor can be obtained by opening a valve of a CO 2 gas source prepared in advance and introducing CO 2 gas into the chamber. Can be implanted as a dopant. The doping concentration can be controlled by the flow rate of CO 2 gas.
  • the DLC insulator layer 14 having the modulation doped portion 14a can be formed by closing the valve of the CO 2 gas source and continuously forming the DLC. it can.
  • an oxygen impurity gas source H 2 O may be used in addition to CO 2 .
  • the modulation dope portion 14a doped with nitrogen impurities acting as a donor.
  • the modulation doped portion 14a having a thickness of several nanometers can be formed at a position in the DLC insulator layer 14 that is about 10 nm away from the interface with the graphene channel layer 11.
  • the impurity atoms in the modulation doped portion 14a are not in direct contact with the graphene, they do not contribute to the carriers in the graphene channel layer 11 as impurity scattering factors. For this reason, it cannot be a factor that hinders the carrier transport characteristics in the graphene channel layer 11.
  • the impurity atoms have a hole carrier supply capability with respect to graphene, a depletion layer at the interface between the DLC insulator layer 14 and the graphene channel layer 11 accompanying the curvature of the band of the DLC insulator layer 14
  • holes in the DLC insulator layer 14 can be quantum mechanically tunneled to the graphene channel layer 11, and a desired effect can be obtained. That is, the carrier density and the carrier mobility can be increased without directly damaging the graphene channel layer 11, and the operation speed can be improved.
  • the above-described oxygen impurity atoms have almost no ability to supply hole carriers into the valence band at room temperature simply by being present in the DLC.
  • the unit of the horizontal axis in FIG. 6 is SCCM (Standard Cubic Centimeter per Minute), and indicates the flow rate (cm 3 ) per minute under an environment of 0 ° C. and 1 atm.
  • SCCM Standard Cubic Centimeter per Minute
  • the introduction of oxygen impurities improves the insulating properties of DLC, which indicates that oxygen impurities do not have a carrier supply capability for DLC. This is because the activation energy required for ionization of oxygen impurities to capture electrons (thus supplying holes to the valence band) is higher than thermal energy (about 26 meV at room temperature). it is conceivable that.
  • the DLC insulator layer 14 formed on the graphene has an ability to supply holes by oxygen impurities. As shown in FIG. 5, this is achieved by bending of the conduction band and valence band of DLC caused by the difference in electron affinity between graphene and deposited DLC. That is, when applying a negative bias to the gate electrode, the Fermi level E F of the gate electrode is raised by applying bias amount, with it, DLC bands gate electrode end is lifted, as shown in FIG. 5 is a graphene interface Band bending occurs.
  • the energy level of the oxygen impurity and the value of the DLC are accompanied by the curvature of the band.
  • the energy difference from the upper end of the electron band (VBM) is effectively reduced by the inclination of the band.
  • this energy difference falls below the activation (ionization) energy of the oxygen impurity atoms, electrons in the valence band are captured and holes are generated in the valence band (“1” in FIG. 5).
  • the thinning of the depletion layer barrier at the DLC-graphene interface accompanying the curvature of the DLC band enables a quantum mechanical tunnel from DLC to graphene, thereby supplying holes to the graphene channel layer 11. ("2" in FIG. 5).
  • the distance between the interface of the graphene channel layer 11 and the modulation doped portion 14a needs to be set narrow so that carriers can tunnel to the graphene in a room temperature operating environment. Since the spread of the electron wave function is generally about 10 nm at room temperature, the interval needs to be set to about 10 nm or less in order to have a sufficiently high quantum mechanical tunnel probability. In addition, in the supply of hole carriers accompanying the curvature of the band of the DLC insulator layer 14 in the vicinity of the interface of the graphene channel layer 11, the upper end (VBM) of the valence band is high, and the region away from the interface of the graphene channel layer 11 is used.
  • the carrier supply region since the carrier supply region has an expansion, it is desirable that the carrier supply region be formed in a region closer to the interface of the graphene channel layer 11 by the expansion.
  • the position that can be closest to the interface of the graphene channel layer 11 needs to be set at a position where the depth distribution of oxygen impurity atoms can be sufficiently attenuated at the interface of the graphene channel layer 11. This closest position also depends on the controllability of the impurity concentration distribution of the manufacturing apparatus used for film formation. Assuming the above points and the current film forming apparatus, it is desirable to form the modulation doped portion 14a at a position of about 3 to 6 nm from the interface of the graphene channel layer 11.
  • a graphene field effect transistor 10 (hereinafter referred to as “ ⁇ -doped element”) having a structure corresponding to FIG. 1A and a DLC insulator layer 14 similar to that shown in FIGS.
  • a graphene field effect transistor 10 (hereinafter referred to as an “interface adsorbing element”) having a structure in which many oxygen impurity atoms are localized at the interface between the graphene channel layer 11 and the graphene channel layer 11 is formed on the same substrate, and the characteristics of both are compared. Verified.
  • FIG. 7 shows the SIMS element depth profile and I DS -V GS characteristics of the ⁇ -doped element.
  • FIG. 8 shows the SIMS element depth profile and I DS -V GS characteristics of the interface adsorption element.
  • the thickness of the DLC insulator layer 14 can be identified as about 44 nm (position of the dotted line in FIG. 7A). Further, the concentration peak of oxygen impurity atoms is located in the DLC insulator layer 14 by about 6 nm from the interface of the graphene channel layer 11, and it can be confirmed that the modulation doped portion 14a can be formed. The concentration distribution of oxygen impurity atoms spreads in the thickness direction and cannot be completely reduced even at the interface of the graphene channel layer 11, but a situation close to the structure shown in FIG.
  • the thickness of the DLC insulator layer 14 is about 31 nm (the position of the dotted line in FIG. 8A), and the ⁇ shown in FIG. It is thinner than the doping element, and the peak of the oxygen impurity atom concentration is located at the interface between the DLC insulator layer 14 and the graphene channel layer 11 as in FIG. This peak is considered to be due to adsorbed water (H 2 O) as shown in FIG. 4 as indicated by the circles (broken lines) in FIG.
  • the gate capacitance C due to the gate insulating film is a simple parallel plate approximation
  • the oxygen impurity concentration peak is smaller than the gate capacitance C of the interface adsorption element located at the interface of the graphene channel layer 11.
  • the mutual conductance g m is proportional to the gate capacitance C and the carrier mobility ⁇ as described above. Further, the carrier mobility ⁇ is proportional to the average lifetime ⁇ of carriers. From these, the following two things are inferred.
  • the carrier mobility ⁇ of the ⁇ -doped element is higher than that of the interface adsorption element.
  • the effective gate capacitance C of the ⁇ -doped element is higher than the gate capacitance value assuming a simple parallel plate approximation due to the carrier injection effect from the modulation doped portion 14a. Since the oxygen impurity concentration at the interface of the graphene channel layer 11 is low in the ⁇ -doped element, it is easily inferred that carrier scattering is reduced and that it has a longer average lifetime and thus a higher carrier mobility ⁇ . At the same time, it is presumed that the carrier concentration in the graphene channel layer 11 can be increased with the application of the gate bias due to the carrier supply capability of oxygen impurities.
  • the insulator layer 14 has a high dielectric constant portion (high- ⁇ film) 14 b extending from immediately below the gate electrode 15 to the channel layer 11.
  • a low dielectric constant portion (low- ⁇ film) 14c having a dielectric constant lower than that of the high dielectric constant portion 14b is provided between the high dielectric constant portion 14b and the source electrode 12 and the drain electrode 13.
  • the modulation dope part 14a may be included in 14c.
  • the high dielectric constant portion 14b and the low dielectric constant can be obtained by applying the technique described in Non-Patent Document 13 and using the selective etching technique by light exposure or electron beam exposure used in a normal FET manufacturing process.
  • a DLC insulator layer 14 having a rate portion 14c can be formed.
  • a DLC film having a high dielectric constant is first formed on the entire surface of the substrate, and the DLC film in a region other than directly under the gate electrode is removed by exposure and etching in which an intrinsic channel region directly under the gate electrode is masked with a resist film.
  • a DLC film having a low dielectric constant is formed on the entire surface, and the resist film in the intrinsic channel region immediately below the gate electrode is removed by lift-off, thereby forming a DLC composed of the high dielectric constant portion 14b and the low dielectric constant portion 14c.
  • An insulator layer 14 can be formed.
  • the high dielectric constant portion 14b can provide a high electrostatic induction effect directly below the gate electrode 15, and the channel interface can be controlled with high accuracy. Further, the low dielectric constant portion 14c can reduce the parasitic capacitance between the electrodes, and can increase the speed. Since the modulation doped portion 14a is provided between the high dielectric constant portion 14b and the source electrode 12 and the drain electrode 13, carriers can be effectively supplied to the channel layer 11 in the access region, and the access resistance is reduced. can do.
  • the insulator layer 14 may have the modulation doped portion 14a in the high dielectric constant portion 14b.
  • the method of forming the modulation dope portion 14a in the above-described PA-PECVD method can be realized by introducing each of the high dielectric constant portion 14b and the low dielectric constant portion 14c during film formation.
  • a high carrier density and a high mobility can be obtained by distinguishing the polarities of the modulation doped portion 14a of the low dielectric constant portion 14c and the high dielectric constant portion 14b from p-type and n-type, or n-type and p-type, respectively. While maintaining, a pnp junction or an npn junction can be made. Thereby, the current rectification in the channel layer 11 can be provided, and a digital switching operation can be realized.
  • the modulation dope portions 14a of the low dielectric constant portion 14c and the high dielectric constant portion 14b may be the same distance or different from the channel layer 11.
  • the graphene field effect transistor 10 manufactured with high quality and high accuracy as shown in FIGS. 1A to 1C has oxygen impurities present at the interface between the insulator layer 14 and the graphene channel layer 11.
  • the operation speed is extremely high. It is thought that it shows high performance.

Abstract

L'invention concerne un transistor à effet de champ au graphène et un élément à semi-conducteur au graphène qui puissent augmenter la densité et la mobilité des porteurs, sans endommager directement un canal de graphène, afin d'augmenter la vitesse de fonctionnement, réduire une résistance d'accès et effectuer une opération de commutation numérique. Selon l'invention, une couche isolante (14) est faite de carbone sous forme de diamant amorphe ayant une faible réactivité avec le graphène et placée sur une couche de canal (11) faite de graphène. La couche isolante (14) présente une partie dopée par modulation en couche mince (14a) pouvant fournir des porteurs à la couche de canal (11) par effet tunnel. Une électrode de source (12) et une électrode déversoir (13) sont électriquement connectées à la couche de canal (11) et agencées séparées l'une de l'autre sur des côtés mutuellement opposés de la couche isolante (14). Une électrode de grille (15) est placée sur la couche isolante (14).
PCT/JP2013/052766 2012-02-16 2013-02-06 Transistor à effet de champ au graphène et élément à semi-conducteur au graphène WO2013121954A1 (fr)

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JP2015069127A (ja) * 2013-09-30 2015-04-13 日本電信電話株式会社 炭化ケイ素導波路素子
JP2015119178A (ja) * 2013-12-18 2015-06-25 アイメックＩｍｅｃ 二層グラフェントンネル電界効果トランジスタ
JP2016194424A (ja) * 2015-03-31 2016-11-17 富士通株式会社 ガスセンサ及びその製造方法
EP3076422A4 (fr) * 2014-07-02 2017-09-27 Fuji Electric Co., Ltd. Procédé de fabrication d'élément à semi-conducteur au carbure de silicium
JP7423879B2 (ja) 2018-03-02 2024-01-30 テキサス インスツルメンツ インコーポレイテッド グラフェン及びボロン窒化物ヘテロ構造デバイスの統合

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JP2015069127A (ja) * 2013-09-30 2015-04-13 日本電信電話株式会社 炭化ケイ素導波路素子
JP2015119178A (ja) * 2013-12-18 2015-06-25 アイメックＩｍｅｃ 二層グラフェントンネル電界効果トランジスタ
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JP7423879B2 (ja) 2018-03-02 2024-01-30 テキサス インスツルメンツ インコーポレイテッド グラフェン及びボロン窒化物ヘテロ構造デバイスの統合

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