WO2013061929A1 - 液晶表示素子および液晶表示装置 - Google Patents
液晶表示素子および液晶表示装置 Download PDFInfo
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- WO2013061929A1 WO2013061929A1 PCT/JP2012/077248 JP2012077248W WO2013061929A1 WO 2013061929 A1 WO2013061929 A1 WO 2013061929A1 JP 2012077248 W JP2012077248 W JP 2012077248W WO 2013061929 A1 WO2013061929 A1 WO 2013061929A1
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- crystal display
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
Definitions
- the present invention relates to a liquid crystal display element and a liquid crystal display device, and more particularly to a vertical electric field type liquid crystal display element and a liquid crystal display device typified by a TN mode and a VA mode.
- a liquid crystal display device is a display device that includes a liquid crystal display element that controls the alignment of liquid crystal by controlling an electric field generated between electrodes and, as a result, controls light transmittance.
- the liquid crystal display element there are various methods for controlling the alignment of the liquid crystal. If these methods are classified from the viewpoint of the direction in which the electric field is generated, they can be roughly divided into a vertical electric field type and a horizontal electric field type.
- the vertical electric field type liquid crystal display element includes a pair of transparent substrates disposed opposite to each other and a liquid crystal layer sandwiched between the pair of transparent substrates.
- One of the pair of transparent substrates includes a pixel electrode.
- the other has a counter electrode.
- a voltage between the pixel electrode and the counter electrode an electric field perpendicular to the liquid crystal layer, in other words, a vertical direction is generated.
- Typical vertical electric field type liquid crystal display elements include TN (twisted nematic) mode and VA (vertical alignment) mode liquid crystal display elements.
- FIG. 5 and FIG. 6 schematically show a liquid crystal display element 100 as an example of a vertical electric field type liquid crystal display element.
- FIG. 5A is a plan view of the liquid crystal display element 100
- FIG. 5B is a cross-sectional view taken along line AA shown in FIG. 6A is an enlarged view of a part of FIG. 5B
- FIG. 6B is an enlarged cross-sectional view taken along a line on the scanning line 120 parallel to the line AA in FIG. 5A.
- FIG. 5A is a plan view of the liquid crystal display element 100
- FIG. 5B is a cross-sectional view taken along line AA shown in FIG. 6A is an enlarged view of a part of FIG. 5B
- FIG. 6B is an enlarged cross-sectional view taken along a line on the scanning line 120 parallel to the line AA in FIG. 5A.
- FIG. 5A is a plan view of the liquid crystal display element 100
- FIG. 5B is a cross-sectional view taken along
- the liquid crystal display element 100 includes a glass substrate 111 and a glass substrate 112 which are a pair of transparent substrates, and a liquid crystal layer 113 sandwiched between the glass substrate 111 and the glass substrate 112. .
- the glass substrate 111 includes a plurality of signal lines 119, a plurality of scanning lines 120, a plurality of TFTs (thin films) transistors 123, a plurality of pixel electrodes 130, and a plurality of common electrodes 140. Yes.
- the plurality of signal lines 119 are arranged in parallel and at equal intervals.
- the plurality of scanning lines 120 are also arranged in parallel and at equal intervals.
- each signal line 119 and each scanning line 120 are orthogonal.
- rectangular regions defined by the signal lines 119 and the scanning lines 120 are formed in a matrix on the surface of the glass substrate 111.
- One rectangular area corresponds to one subpixel.
- One pixel is composed of three sub-pixels (red, green and blue).
- the TFT is a top gate type coplanar TFT, and includes a gate electrode 123, an SI path 121, and an SI path 122 formed in a part of the scanning line 120.
- a source electrode (not shown) is formed at one end of the SI path 121.
- the source electrode and the signal line 119 are connected via a contact hole (not shown).
- the SI path 122 is connected to the drain electrode 124.
- the drain electrode 124 is connected to the pixel electrode 130 through a contact hole (not shown).
- an address signal is input to the scanning line 120, and a data signal is sequentially input to the plurality of signal lines 119.
- a voltage corresponding to the data signal is output to the SI path 122 and the pixel electrode 130, and an electric field corresponding to the data signal is generated between the pixel electrode 130 and the counter electrode 125.
- a plurality of common electrodes 140 are provided.
- the common electrode 140 is provided in the same layer as the layer on which the scanning line 120 is provided, and is made of an opaque metal conductive material, like the scanning line 120.
- the plurality of common electrodes 140 are arranged in parallel with the scanning line 120. Further, one common electrode 140 is arranged between adjacent scanning lines 120.
- the horizontal electric field type liquid crystal display element includes a liquid crystal layer sandwiched between a pair of transparent substrates, like the vertical electric field type liquid crystal display element. However, it differs from the vertical electric field type liquid crystal display element in that one of the pair of transparent substrates includes a pixel electrode and a common electrode.
- the horizontal electric field type liquid crystal display element generates an electric field in the in-plane direction of the liquid crystal layer, in other words, in the horizontal direction by applying a voltage between the pixel electrode and the common electrode provided on one transparent substrate.
- Examples of the horizontal electric field type liquid crystal display element include an IPS (in-plane switching) mode liquid crystal display element and an FFS (fringe field switching) mode liquid crystal display element.
- Patent Document 1 describes a liquid crystal display element that reduces the influence of parasitic capacitance in an FFS mode liquid crystal display element. The features of the present invention will be described below with reference to FIGS.
- FIG. 7 shows a schematic diagram of the liquid crystal display element 200 in the FFS mode.
- FIG. 7A is a plan view of the liquid crystal display element 200
- FIG. 7B is a cross-sectional view taken along line AA shown in FIG. 7A.
- FIG. 8 is an enlarged view of a part of FIG.
- the liquid crystal display element 200 includes a glass substrate 211 and a glass substrate 212 which are a pair of transparent substrates, and a liquid crystal layer 213 sandwiched between the glass substrate 211 and the glass substrate 212.
- the glass substrate 211 includes a plurality of signal lines 219, a plurality of scanning lines 220, a plurality of TFTs, a plurality of pixel electrodes 230, and a common electrode 240.
- the common electrode 240 is made of a conductive material that is transparent in the visible region.
- the plurality of signal lines 219 are arranged in parallel and at equal intervals.
- the plurality of scanning lines 220 are also arranged in parallel and at equal intervals.
- each signal line 219 and each scanning line 220 are orthogonal to each other.
- rectangular regions defined by the signal lines 219 and the scanning lines 220 are formed in a matrix on the surface of the glass substrate 211.
- One rectangular area corresponds to one subpixel.
- One pixel is composed of three sub-pixels (red, green and blue).
- the TFT is a top-gate type coplanar TFT, and includes a gate electrode 223, an SI path 221, and an SI path 222 formed in part of the scanning line 220.
- SI path 221 is connected to source electrode and signal line 219 via a contact hole (not shown).
- the SI path 222 is connected to the drain electrode 224.
- the drain electrode 224 is connected to the pixel electrode 230 through a contact hole (not shown).
- the pixel electrode 230 is provided with a slit for forming an electric field between the pixel electrode 230 and a common electrode 240 described later.
- the parasitic capacitance generated between the signal line 119 and the scanning line 120 and the pixel electrode 130 causes the display quality to deteriorate. This point will be described with reference to FIG.
- FIG. 6A is an enlarged view of a part of FIG. 5B
- FIG. 6B is an enlarged cross-sectional view taken along a line on the scanning line 120 parallel to the line AA in FIG. 5A.
- One subpixel has a liquid crystal capacitor and an auxiliary capacitor in addition to Csd127 and Cgd128.
- a liquid crystal capacitor is formed between the pixel electrode 130 and the counter electrode 125.
- the auxiliary capacitance is formed between the common electrode 140 and the SI path 122.
- the sum of these liquid crystal capacitance, auxiliary capacitance, Csd127 and Cgd128 is defined as the pixel capacitance.
- the ratio of the parasitic capacitance to the pixel capacitance increases, the influence of the parasitic capacitance on the display quality of the liquid crystal display element 100 increases. In other words, if the pixel capacitance is increased by increasing the auxiliary capacitance, the ratio of the parasitic capacitance to the pixel capacitance can be reduced. Therefore, the influence of the parasitic capacitance on the display quality can be suppressed.
- the width of the common electrode 140 (the length in the direction parallel to the signal line 119) widely. Since the common electrode 140 is made of an opaque material, when the width of the common electrode 140 is increased, a region through which the backlight is transmitted is reduced. Therefore, when the auxiliary capacitance is designed to be large in order to suppress the influence due to the parasitic capacitance, another problem that the luminance of the liquid crystal display element 100 is lowered occurs.
- the liquid crystal display element 200 which is a horizontal electric field type liquid crystal display element, includes a common electrode 240 in order to suppress the influence of parasitic capacitance, and is characterized by the shape and the position of the common electrode 240.
- the common electrode 240 is formed in the entire region excluding the drain electrode 224 and the contact hole (see FIG. 7A).
- the common electrode 240 is formed between the layer where the signal line 219 and the scanning line 220 are provided, and the layer where the pixel electrode 230 is provided (FIG. 7 (b)).
- the signal line 219, the scanning line 220, and the pixel electrode 230 are shielded by the common electrode 240.
- Csd which is a parasitic capacitance generated between the signal line 219 and the pixel electrode 230
- Cgd which is a parasitic capacitance generated between the scanning line 220 and the pixel electrode 230
- the voltage held in the common electrode 240 can be stabilized. Therefore, deterioration of display quality in the liquid crystal display element 200 can be prevented.
- the common electrode 240 since the common electrode 240 is formed in the entire region except the drain electrode 224 and the contact hole, the backlight 229a needs to pass through the common electrode 240.
- the common electrode 240 has an absorptance determined by the absorption coefficient of the transparent conductive material forming the common electrode 240 and the film thickness of the common electrode 240.
- the backlight 229a light corresponding to the absorptance is absorbed by the common electrode 240, and light transmitted through the common electrode 240 becomes the backlight 229b.
- the liquid crystal display element 200 has a problem that the luminance is reduced by the backlight 229 a being absorbed by the common electrode 240.
- absorption of the backlight 229b by the pixel electrode 230 is not considered.
- Patent Document 1 is based on an FFS mode liquid crystal display element and cannot be applied to a vertical electric field type liquid crystal display element.
- An object of the present invention is to provide a liquid crystal display capable of suppressing parasitic capacitance generated between scanning lines and signal lines and pixel electrodes without sacrificing luminance of the liquid crystal display element in a vertical electric field type liquid crystal display element.
- An element and a liquid crystal display device are provided.
- a liquid crystal display element comprising a pair of transparent substrates and a liquid crystal layer disposed between the pair of transparent substrates, One of the transparent substrates is Scanning lines; A signal line orthogonal to the scanning line; A driving element connected to the signal line and the scanning line; A transparent pixel electrode disposed above the scanning line and the signal line and connected to the driving element; Disposed in a layer between the scanning line and the signal line and the transparent pixel electrode, covering at least one of the scanning line and at least one of the signal line, and covering the transparent A transparent common electrode having an opening at a position facing the pixel electrode, The other transparent substrate is provided with a counter electrode.
- the transparent common electrode is disposed in a layer between the scanning line and the signal line and the transparent pixel electrode. Further, at least one of the scanning lines and at least a part of the signal lines is covered with a transparent common electrode.
- the transparent common electrode covers a position facing at least a part of the scanning line, the part of the scanning line and the pixel electrode are shielded from each other by the transparent common electrode.
- the transparent common electrode covers a position facing at least part of the signal line, the part of the signal line and the pixel electrode are shielded from each other by the transparent common electrode.
- parasitic capacitance formed between at least one of the scanning lines and at least one of the signal lines and the pixel electrode is suppressed.
- the transparent common electrode has an opening at a position facing the transparent pixel electrode. This increases the light incident on the liquid crystal layer without passing through the transparent common electrode. As a result, the luminance of the liquid crystal display element is improved.
- the luminance of the liquid crystal display element is not sacrificed between the scan line and the signal line and the pixel electrode. Can be suppressed.
- the liquid crystal display device preferably includes any one of the above liquid crystal display elements.
- the present invention suppresses parasitic capacitance generated between a scanning line and a pixel electrode and parasitic capacitance generated between a signal line and the pixel electrode without sacrificing luminance in a vertical electric field type liquid crystal display element. be able to. Therefore, the vertical electric field type liquid crystal display element and the liquid crystal display device have an effect of improving display quality without sacrificing luminance.
- (A) is a top view which shows the outline of the liquid crystal display element which concerns on one Embodiment of this invention
- (b) is sectional drawing which shows the outline of the said liquid crystal display element.
- (A) is the schematic which shows a mode that the parasitic capacitance Csd produced between a signal line and a pixel electrode is suppressed by a common electrode in the said liquid crystal display element
- (b) is between a scanning line and a pixel electrode. It is the schematic which shows a mode that the parasitic capacitance Cgd which arises in is suppressed by the common electrode.
- (C) is the schematic which shows a mode that a backlight permeate
- FIG. 1 It is a top view which shows the outline of the liquid crystal display element which concerns on another embodiment of this invention. It is a top view which shows the outline of the liquid crystal display element which concerns on another embodiment of this invention.
- (A) is a top view which shows the outline of the conventional liquid crystal display element
- (b) is sectional drawing which shows the outline of the said liquid crystal display element.
- (A) is the schematic which shows the parasitic capacitance Csd which arises between a signal line and a pixel electrode in the conventional liquid crystal display element
- (b) shows the parasitic capacitance Cgd which arises between a scanning line and a pixel electrode.
- (A) is a top view which shows the outline of another conventional liquid crystal display element
- (b) is sectional drawing which shows the outline of the said liquid crystal display element.
- another conventional liquid crystal display element it is the schematic which shows a mode that a backlight permeate
- FIG. 1A is a plan view showing an outline of the liquid crystal display element 10
- FIG. 1B is a cross-sectional view showing an outline of a cross section taken along the line AA shown in FIG. 2A is an enlarged view of a part of FIG. 1B.
- FIG. 2B is a cross-sectional view taken along a line on the scanning line 20 parallel to the line AA in FIG. It is an enlarged view.
- FIG. 2C is an enlarged view of a part of FIG. 1B as in FIG. 2A, and shows a state where the backlight 29 is incident on the liquid crystal layer 13.
- the liquid crystal display element 10 is a VA mode liquid crystal display element which is one of the vertical electric field type liquid crystal display elements, and uses dot inversion driving as a driving method. As shown in FIG. 1B, the liquid crystal display element 10 is sandwiched between a glass substrate 11 (one transparent substrate), a glass substrate 12 (the other transparent substrate), the glass substrate 11 and the glass substrate 12. And a liquid crystal layer 13. A polarizing plate (not shown) is placed on the surface of the glass substrate 11 opposite to the surface on the liquid crystal layer 13 side in close contact with the surface. Similarly, a polarizing plate (not shown) is provided on the surface of the glass substrate 12 opposite to the surface on the liquid crystal layer 13 side in close contact with the surface. Furthermore, the liquid crystal display element 10 includes a backlight (not shown) for irradiating the polarizing plate included in the glass substrate 11 with white light.
- a color filter 26 and a counter electrode 25 are laminated on the surface of the glass substrate 12 on the liquid crystal layer 13 side.
- the color filter 26 is a filter that selectively transmits light in any one of the red, green, and blue wavelength regions among the white light backlight that passes through the liquid crystal layer 13.
- the color filter 26 is configured by arranging red, green and blue color filters in a matrix.
- the color filter 26 is preferably formed with a black matrix together with red, green and blue color filters.
- the liquid crystal display element 10 is characterized by the shape of the common electrode 40 (transparent common electrode) provided in the glass substrate 11 and the position where the common electrode 40 is formed. Therefore, in the following, each component member laminated on the glass substrate 11 will be described in detail.
- a configuration known as a VA mode liquid crystal display element can be applied.
- a base coat (BC) 14 On the surface of the glass substrate 11 on the liquid crystal layer 13 side, a base coat (BC) 14, a plurality of SI paths 21, a SI path 22, a first insulating film 15, a plurality of scanning lines 20, a second insulating film 16, and a plurality of The signal line 19, the JAS film 17, the common electrode 40, the third insulating film 18, and the pixel electrode 30 (transparent pixel electrode) are sequentially stacked.
- BC base coat
- the plurality of signal lines 19 are formed in parallel and at equal intervals.
- the plurality of scanning lines 20 are formed in parallel and at equal intervals.
- each signal line 19 and each scanning line 20 are formed so as to be orthogonal to each other in plan view.
- One rectangular region delimited by each signal line 19 and each scanning line 20 corresponds to one subpixel.
- FIG. 1B is a cross-sectional view taken along the line AA, the scanning line 20 is not shown in FIG.
- the scanning line 20 is formed in the same layer as the first insulating layer 15.
- a plurality of SI paths 21 are not described in FIG.
- the SI path 21 is formed in the same layer as the SI path 22.
- TFT A plurality of TFTs that are driving elements of the liquid crystal display element 10 are provided for each sub-pixel region.
- Each TFT includes a gate electrode 23, an SI path 21, an SI path 22, a drain electrode 24, and a source electrode (not shown).
- the SI path 21 is connected to the source electrode and the signal line 19 through a contact hole (not shown).
- One end of the SI path 22 is connected to the drain electrode 24.
- the drain electrode 24 is connected to the pixel electrode 30 through a contact hole (not shown).
- BC14 On the surface of the glass substrate 11, BC14, SI path
- BC14 is made of, for example, Ta 2 O 5 .
- the BC 14 functions as a protective film that protects the surface of the glass substrate 11. Further, when forming the pattern of the SI paths 21 and 22, it functions as an etching stopper.
- a gate insulating layer and a channel layer are formed at the interface between the gate electrode 23 formed of a part of the scanning line 20 and the SI path 21 and the SI path 22.
- a plurality of scanning lines 20 and a first insulating film 15 are formed on the SI path 21, the SI path 22, and the BC 14.
- the plurality of scanning lines 20 are formed in parallel and at equal intervals.
- the direction of the plurality of scanning lines 20 is orthogonal to the direction of the SI path 22.
- Each TFT described above is disposed in the vicinity of the intersection between each scanning line 20 and each signal line 19.
- the scanning line 20 preferably has high conductivity, and is preferably made of a metal material.
- the metal material used for the scanning line 20 include aluminum, molybdenum, chromium, tungsten, and titanium.
- a scanning line 20 having high conductivity can be formed by selecting a plurality of metals from these metal groups and forming a laminated film.
- a compound having conductivity may be used as another material for forming the scanning line 20.
- a first insulating film 15 is formed between the scanning lines 20.
- the first insulating film 15 is made of SiN x or SiO 2 .
- the backlight incident on the liquid crystal display element 10 needs to pass through the first insulating film 15.
- the first insulating film 15 preferably has a low light absorption rate with respect to light in the visible region.
- a second insulating film 16 is formed on the first insulating film 15.
- the second insulating film 16 is an interlayer insulating film for insulating the scanning line 20 from a signal line 19 described later. Similar to the first insulating film 15, the second insulating film 16 is made of SiN x or SiO 2 . Like the first insulating film 15, the second insulating film 16 preferably has a low light absorptance with respect to light in the visible region.
- a plurality of signal lines 19 are formed on the second insulating film 16.
- the plurality of signal lines 19 are formed in parallel and at equal intervals.
- Each signal line 19 and each scanning line 20 are orthogonal to each other (see FIG. 1A). Therefore, a rectangular region defined by the signal lines 19 and the scanning lines 20 is formed in a matrix on the glass substrate 11.
- One rectangular area corresponds to one subpixel.
- One pixel is composed of three sub-pixels (red, green and blue).
- Each subpixel includes the TFT described above.
- the SI path 21 provided in the TFT and the signal line 19 are electrically connected via a source electrode and a contact hole (not shown).
- the contact hole has a shape penetrating the first insulating film 15 and the second insulating film 16.
- the signal line 19 preferably has a high conductivity like the scanning line 20, and is preferably made of a metal material.
- the metal material used for the signal line 19 include aluminum, molybdenum, chromium, tungsten, and titanium.
- a signal line 19 having high conductivity can be formed by selecting a plurality of metals from these metal groups and forming a laminated film.
- a compound having conductivity may be used as another material for forming the signal line 19, a compound having conductivity may be used.
- a JAS film 17 that is a transparent organic insulating film is formed on the signal line 19.
- the JAS film 17 is provided as an interlayer insulating film between the signal line 19 and a common electrode 40 described later.
- the thickness of the JAS film 17 is preferably thicker than the thicknesses of the first insulating film 15, the second insulating film 16, and the third insulating film 18.
- region where the pixel is formed in the matrix form on the surface of the glass substrate 11 is called a pixel formation area
- a common electrode 40 is formed on the JAS film 17. As shown in FIG. 1A, the common electrode 40 includes one opening 41 for each sub-pixel. A drain electrode 24 and a contact hole (not shown) for electrically connecting the SI path 22 and a pixel electrode 30 described later are formed in a part of the region where the opening 41 is formed. In other words, the common electrode 40 has an opening 41 at least in a region where a contact hole is formed.
- the SI path 22, the drain electrode 24, the pixel electrode 30, and the common electrode 40 can be in an electrically insulated state. Since the SI path 22, the drain electrode 24, the pixel electrode 30, and the common electrode 40 have different potentials, it is necessary to insulate them so that no leakage occurs between them.
- the shape and number of the openings 41 are not limited as long as electrical insulation can be secured in the SI path 22, the drain electrode 24, the pixel electrode 30, and the common electrode 40. However, if the plurality of openings 41 are formed for each sub-pixel in the common electrode 40, the size of the auxiliary capacitance between the sub-pixels may be nonuniform. If the size of the auxiliary capacitance between the sub-pixels is non-uniform, the non-uniformity may be recognized by the user as display unevenness. Therefore, the number of openings 41 provided in the common electrode 40 is preferably one for each subpixel.
- the common electrode 40 is an electrode formed because each sub-pixel has an auxiliary capacitance. This auxiliary capacitance is necessary for holding the electric field generated in the liquid crystal layer 13 included in each sub-pixel during a period when no address signal is input to each signal line 19.
- the common electrode 40 is formed in the entire region except the opening 41. Therefore, the liquid crystal display device 10 has one common electrode 40, and the common electrode 40 corresponding to each sub-pixel has the same potential.
- the common electrode 40 is made of indium tin oxide (ITO) or indium zinc oxide (IZO) which is a transparent conductive material. Since the common electrode 40 is formed in the pixel formation region excluding the opening 41, the common electrode 40 preferably has good light transmittance in the visible region. In addition, the common electrode 40 preferably has a good electrical conductivity. Any material other than ITO and IZO can be used as the common electrode 40 as long as it is a transparent conductive material having such good light transmittance and conductivity.
- the liquid crystal display element 10 is characterized by a common electrode 40. The effect obtained when the liquid crystal display element 10 includes the common electrode 40 will be described later.
- a third insulating film 18 is formed on the common electrode 40.
- the third insulating film 18 is an interlayer insulating film that insulates the common electrode 40 and the pixel electrode 30.
- the third insulating film 18 is made of SiN x or SiO 2 like the first insulating film 15 and the second insulating film 16.
- the third insulating film 18 preferably has a low light absorptance with respect to light in the visible region.
- Pixel electrode 30 A plurality of pixel electrodes 30 are formed on the third insulating film 18. One pixel electrode is provided for one subpixel. As a result, matrix pixel electrodes 30 are formed in the pixel formation region.
- the pixel electrode 30 is electrically connected to the SI path 22 provided in the TFT through the drain electrode 24 and the contact hole. It is preferable that the drain electrode 24 and the contact hole are formed in the central portion of the sub-pixel region partitioned by each signal line 19 and each scanning line 20 (see FIG. 1A). This is related to the fact that the region where the drain electrode 24 and the contact hole are provided does not transmit light.
- the liquid crystal display element 10 adopting the VA mode it is preferable to provide a hole in the center of the sub-pixel region in the counter electrode 25.
- the hole has an effect of regulating the alignment of the liquid crystal. While the orientation of the liquid crystal can be improved, the light transmittance is reduced in the region where the hole is provided.
- loss of transmitted light in the liquid crystal display element 10 can be suppressed. . That is, the luminance of the liquid crystal display element 10 can be improved.
- the position of the hole provided in the counter electrode 25 may not be the center of the sub-pixel region.
- the counter electrode 25 may include a plurality of holes for each sub-pixel region.
- the shape of the hole is arbitrary, and may be elliptical, for example. In these cases, it is preferable that the position where the drain electrode 24 and the contact hole are provided not coincide with the center of the sub-pixel region but the position where the hole is formed.
- the counter electrode 25 may be provided with a protrusion instead of the hole. In this case, it is preferable that the positions of the drain electrode 24 and the contact hole coincide with the positions of the protrusions.
- the drain electrode 24 and the contact hole are provided in the vicinity of the outer edge portion of the sub-pixel region. As a result, the influence on the orientation of the liquid crystal can be reduced.
- the contact hole connects the drain electrode 24 and the pixel electrode 30 by penetrating the first insulating film 15, the second insulating film 16, the JAS film 17 and the third insulating film 18.
- the pixel electrode 30 is made of ITO or IZO.
- the pixel electrode 30 is provided in a region that transmits light in the liquid crystal display element 10. Accordingly, the pixel electrode 30 preferably has a good light transmittance in the visible region. In addition, the pixel electrode 30 preferably has good electrical conductivity. Any material other than ITO and IZO can be used as the pixel electrode 30 as long as it is a transparent conductive material having such good light transmittance and conductivity.
- an alignment film (not shown) for improving the alignment of the liquid crystal is formed on the pixel electrode 30 and the third insulating film 18.
- the common electrode 40 is provided between the signal line 19 and the pixel electrode 30 and between the scanning line 20 and the pixel electrode 30 (see FIG. 1B). .
- the common electrode is provided in the entire region of the pixel formation region excluding the opening 41 in plan view (see FIG. 1A).
- the signal line 19 and the pixel electrode 30 are shielded by the common electrode 40 (see FIG. 2A).
- Csd27 which is a parasitic capacitance generated between the signal line 19 and the pixel electrode 30 is suppressed.
- the scanning line 20 and the pixel electrode 30 are shielded by the common electrode 40 (see FIG. 2B).
- Cgd28 which is a parasitic capacitance generated between the scanning line 20 and the pixel electrode 30 is suppressed.
- the common electrode 40 when the liquid crystal display element 10 includes the common electrode 40, the parasitic capacitances Csd27 and Cgd28 are suppressed. As a result, deterioration of display quality in the liquid crystal display element 10 caused by Csd27 and Cgd28 is suppressed. That is, the common electrode 40 is effective in improving the display quality of the liquid crystal display element 10.
- Ccs that is an auxiliary capacitor is formed between the common electrode 40 and the pixel electrode 30.
- the common electrode 40 and the pixel electrode 30 overlap in a wide region excluding the opening 41. Accordingly, it is easy to form a sufficiently large Ccs in the liquid crystal display element 10.
- a thick JAS film 17 is formed between the common electrode 40 and the SI path. Therefore, the capacitance formed between the common electrode 40 and the SI path is very small.
- Ccs can be arbitrarily changed by changing the size of the opening 41 included in the common electrode 40.
- the opening 41 is formed large, the region where the common electrode 40 and the pixel electrode 30 overlap becomes narrow. Therefore, Ccs becomes small.
- the opening 41 is formed small, a region where the common electrode 40 and the pixel electrode 30 overlap is widened. Therefore, Ccs increases.
- the liquid crystal display element 10 can be provided with Ccs having a sufficient size to satisfy the display quality. In other words, a stable electric field can be maintained even when no address signal is input to each scanning line 20. Therefore, the occurrence of flicker can be suppressed, and the liquid crystal display element 10 can obtain satisfactory display quality.
- Increasing the area of the common electrode 40 means reducing the area of the opening 41.
- the electrical resistance values at the left and right ends of the common electrode 40 are reduced. Therefore, occurrence of crosstalk between the sub-pixels can be suppressed. As a result, the liquid crystal display element 10 can obtain satisfactory display quality.
- the storage capacitor can be sufficiently charged during the period in which the address signal is input to each scanning line 20. Accordingly, it is possible to appropriately hold the electric field for controlling the liquid crystal layer 13 even during a period when no address signal is input to each scanning line 20.
- the area of the opening 41 needs to be set large in order to set Ccs within an appropriate range.
- the area of the common electrode 40 is reduced, and there is a possibility that the electric resistance value at both ends of the common electrode 40 increases.
- the electric resistance value generated at both ends of the common electrode 40 can be reduced.
- the common electrode 40 included in the liquid crystal display element 10 is made of a transparent conductive material of ITO or IZO. Furthermore, the common electrode 40 includes an opening 41. When the glass substrate 11 is viewed in plan, at least a part of the opening 41 is provided in a region where the pixel electrode 30 is formed.
- the opening 41 is provided, so that the backlight 29 incident on the liquid crystal display device 10 is incident on the liquid crystal layer 13 without being absorbed by the common electrode 40. .
- the common electrode 40 has good light transmittance. The luminance of 10 does not decrease significantly.
- the common electrode 40 included in the liquid crystal display device 10 is formed of a transparent conductive material and includes the opening 41, so that unlike the conventional liquid crystal display element including the common electrode formed of a metal material, The liquid crystal display device 10 does not sacrifice luminance.
- a part of the opening 41 may be provided in a region other than the region where the pixel electrode 30 is installed. However, at least a part of the opening 41 is preferably provided in a region where the pixel electrode 30 including the contact hole 24 is provided.
- the vertical electric field type liquid crystal display device 10 includes the common electrode 40, the scanning line, the signal line, and the pixel electrode are provided without sacrificing the luminance while providing a preferable auxiliary capacity for satisfying the display quality. Can be suppressed. As a result, the display quality in the vertical electric field type liquid crystal display element 10 can be improved.
- the liquid crystal display element 10 is not limited to a VA mode liquid crystal display element, and the present invention can be implemented as long as it is a vertical electric field type liquid crystal display element.
- the liquid crystal display device may include the liquid crystal display element 10.
- the display quality of the liquid crystal display device can be improved without sacrificing luminance.
- FIG. 3 is a plan view schematically showing the liquid crystal display element 50.
- the liquid crystal display element 50 is different from the liquid crystal display element 10 in the shapes of the common electrode 51 and the TFT 53. Therefore, in this embodiment, the common electrode 51 and the TFT 53 will be described.
- the same number is attached
- the liquid crystal display element 50 is a VA mode liquid crystal display element as in the liquid crystal display element 10. However, while the liquid crystal display element 10 is driven by dot inversion driving, the liquid crystal display element 50 is driven by row line inversion driving. Due to the difference in driving method, the shape of the common electrode 51 provided in the liquid crystal display device 50 is different from the shape of the common electrode 40 provided in the liquid crystal display device 10.
- One common electrode 51 is formed corresponding to a plurality of sub-pixels connected to one scanning line 20. Therefore, the liquid crystal display element 50 has an independent shape for each row line, and as a result, each common electrode 51 is electrically insulated.
- Each common electrode 51 is connected to a CS driver for controlling the auxiliary capacitance.
- the CS driver outputs an appropriate signal to each common electrode 51 so that each sub-pixel connected to each scanning line 20 can have an appropriate auxiliary capacitance.
- each common electrode 51 is a shape that covers the entire region where each scanning line 20 is formed and a partial region where each signal line 19 is formed.
- the common electrode 51 according to this embodiment is rectangular, the shape is not limited to a rectangle as long as the above configuration is satisfied.
- the common electrode 51 Since the common electrode 51 has the shape as described above, it is generated between the signal line 19 and the pixel electrode 30 as well as Cgd, which is a parasitic capacitance generated between the scanning line 20 and the pixel electrode 30. Part of Csd, which is a parasitic capacitance, can be suppressed.
- the display quality of the liquid crystal display element 50 can be improved.
- the TFT provided in the liquid crystal display element 50 is a top gate type TFT. In each sub-pixel region, two TFTs are provided in the vicinity of the intersection between each scanning line 20 and the signal line 19.
- the TFT includes a gate electrode 53, a drain electrode 54, an SI path 55 and an SI path 56.
- the TFT has a different SI path and gate electrode shape as compared with the TFT included in the liquid crystal display element 10.
- a conductive film for forming one gate electrode 53 is formed in a direction perpendicular to the scanning line 20 from the scanning line 20 (see FIG. 3).
- This conductive film is made of the same material as the scanning line 20.
- the SI path 55 and the scanning line 20 intersect, and another gate electrode 53 is formed at this intersection.
- the SI path 55 connects the one gate electrode 53 to the other gate electrode 53. Further, the SI path 55 is connected to the signal line 19 that also serves as the source electrode in a portion that crosses the scanning line 20.
- the SI path 56 is formed so as to connect one TFT and the drain electrode 54.
- a gate insulating film and a channel layer are formed at the interface between the gate electrode 53 and the SI path 55 and SI path 56.
- the SI path 55 and the SI path 56 are made of silicon.
- a liquid crystal display element 60 according to still another embodiment of the present invention will be described with reference to FIG.
- the common electrode 61 provided in the liquid crystal display device 60 has a different opening shape from the common electrode 51 provided in the liquid crystal display device 50.
- the shape of the common electrode 51 is a rectangle. Therefore, when the length in the direction parallel to the signal line of the common electrode 51 is defined as the width, the width is always constant.
- the width of the common electrode 61 is not constant.
- the width of the common electrode 61 in the region where the signal line 19 is installed and the peripheral region where the signal line 19 is installed is formed wider than the width of the common electrode 61 in the region excluding the region.
- the common electrode 61 can cover a wider area in the area where the signal line 19 is installed. Therefore, the liquid crystal display element 60 can more effectively suppress Csd, which is a parasitic capacitance formed between the signal line 19 and the pixel electrode 30, compared to the liquid crystal display element 50. That is, the liquid crystal display element 60 can further improve display quality as compared with the liquid crystal display element 50.
- a liquid crystal display element comprising a pair of transparent substrates and a liquid crystal layer disposed between the pair of transparent substrates, One of the transparent substrates is Scanning lines; A signal line orthogonal to the scanning line; A driving element connected to the signal line and the scanning line; A transparent pixel electrode disposed above the scanning line and the signal line and connected to the driving element; Disposed in a layer between the scanning line and the signal line and the transparent pixel electrode, covering at least one of the scanning line and at least one of the signal line, and covering the transparent A transparent common electrode having an opening at a position facing the pixel electrode, The other transparent substrate is provided with a counter electrode.
- the transparent common electrode is disposed in a layer between the scanning line and the signal line and the transparent pixel electrode. Further, at least one of the scanning lines and at least a part of the signal lines is covered with a transparent common electrode.
- the transparent common electrode covers a position facing at least a part of the scanning line, the part of the scanning line and the pixel electrode are shielded from each other by the transparent common electrode.
- the transparent common electrode covers a position facing at least part of the signal line, the part of the signal line and the pixel electrode are shielded from each other by the transparent common electrode.
- parasitic capacitance formed between at least one of the scanning lines and at least one of the signal lines and the pixel electrode is suppressed.
- the transparent common electrode has an opening at a position facing the transparent pixel electrode. This increases the light incident on the liquid crystal layer without passing through the transparent common electrode. As a result, the luminance of the liquid crystal display element is improved.
- the luminance of the liquid crystal display element is not sacrificed between the scan line and the signal line and the pixel electrode. Can be suppressed.
- the transparent common electrode covers a position facing the entire scanning line and a position facing the entire signal line.
- the liquid crystal display element can more effectively suppress the parasitic capacitance generated between the scanning line and the signal line and the pixel electrode. As a result, in the liquid crystal display element according to one embodiment of the present invention, display quality can be further improved.
- the one transparent substrate includes a plurality of the scanning lines,
- the transparent common electrode is provided for each scanning line,
- Each of the transparent common electrodes preferably covers at least a position facing all of the corresponding scanning lines.
- the liquid crystal display element includes a plurality of transparent common electrodes corresponding to each scanning line. Further, the entire region where each scanning line is formed is covered with each corresponding transparent common electrode.
- the transparent common electrode is provided independently for each scanning line. In other words, each transparent common electrode is formed in a shape that is not electrically conductive. Therefore, a separate signal can be input to each transparent common electrode.
- the liquid crystal display element according to one embodiment of the present invention can suppress deterioration in display quality due to the influence of parasitic capacitance while adopting row line inversion driving as a driving method.
- the width at the position where the corresponding scanning line and the signal line intersect is preferably wider than the width at the position where the corresponding scanning line and the signal line do not intersect.
- the transparent common electrode can cover a wider signal line without narrowing the opening provided in the transparent common electrode in the region where the transparent pixel electrode is formed. Therefore, the liquid crystal display element according to one embodiment of the present invention can more effectively suppress the parasitic capacitance generated between the signal line and the pixel electrode without sacrificing luminance. That is, deterioration of display quality due to the parasitic capacitance can be more effectively suppressed.
- the liquid crystal display device preferably includes any one of the above liquid crystal display elements.
- the present invention can be widely used as a liquid crystal display element and a liquid crystal display device.
- Liquid crystal display element 11 Glass substrate (one transparent substrate) 12 Glass substrate (the other transparent substrate) 13 Liquid crystal layer 14 Base coat 15 First insulating film 16 Second insulating film 17 JAS film 18 Third insulating film 19 Signal line 20 Scan line 21 SI path 22 SI path 23 Gate electrode 24 Drain electrode 25 Counter electrode 26 Color filter 27 Csd 28 Cgd 30 pixel electrode (transparent pixel electrode) 40 Common electrode (transparent common electrode) 41 opening
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Abstract
Description
一対の透明基板と、当該一対の透明基板の間に配置される液晶層とを備えた液晶表示素子であって、
一方の上記透明基板は、
走査線と、
上記走査線に直交する信号線と、
上記信号線と上記走査線とに接続される駆動素子と、
上記走査線および信号線よりも上層に配置され、かつ、上記駆動素子に接続される透明画素電極と、
上記走査線および信号線と上記透明画素電極との間の層に配置され、上記走査線の少なくとも一部および上記信号線の少なくとも一部のうち少なくとも一方に対向する位置を覆い、かつ、上記透明画素電極に対向する位置に開口部を有する透明共通電極とを備え、
他方の上記透明基板は、対向電極を備えていることを特徴としている。
(液晶表示素子10の概要)
本発明の一実施形態に係る液晶表示素子10について、図1および2を参照しながら説明する。図1(a)は液晶表示素子10の概略を示す平面図であり、図1(b)は図1(a)に示すA-A線における断面の概略を示す断面図である。図2(a)は、図1(b)の一部を拡大した図であり、図2(b)は図1(a)におけるA-A線と平行な走査線20上の線における断面の拡大図である。図2(c)は、図2(a)と同様に図1(b)の一部を拡大した図であり、バックライト29が液晶層13に入射する様子を示している。
ガラス基板11における液晶層13側の表面上には、ベースコート(BC)14、複数のSI経路21、SI経路22、第1絶縁膜15、複数の走査線20、第2絶縁膜16、複数の信号線19、JAS膜17、共通電極40、第3絶縁膜18および画素電極30(透明画素電極)が逐次積層されている。
液晶表示素子10の駆動素子である複数のTFTは、各サブ画素領域に対して2つ設けられている。各TFTは、それぞれゲート電極23、SI経路21、SI経路22、ドレイン電極24およびソース電極(図示せず)を備える。SI経路21と、ソース電極および信号線19とは、図示しないコンタクトホールを介して接続されている。SI経路22の一端は、ドレイン電極24に接続されている。ドレイン電極24は、図示していないコンタクトホールを介して画素電極30と接続されている。
SI経路21、SI経路22およびBC14の上には、複数の走査線20および第1絶縁膜15が形成されている。複数の走査線20は、それぞれが平行かつ等間隔になるように形成されている。複数の走査線20の方向は、SI経路22の方向に対して直交している。
第2絶縁膜16の上には、複数の信号線19が形成されている。複数の信号線19は、それぞれが平行かつ等間隔になるように形成されている。各信号線19と各走査線20とはお互いに直交している(図1(a)参照)。したがって、ガラス基板11には各信号線19と各走査線20とによって区切られた長方形の領域がマトリクス状に形成される。この長方形の領域1つが、1つのサブ画素に対応している。1つの画素は3つのサブ画素(赤、緑および青)から構成されている。
JAS膜17の上には、共通電極40が形成される。図1(a)に示すように、共通電極40は各サブ画素に対して1つの開口部41を備えている。開口部41が形成されている領域の一部には、SI経路22と後述する画素電極30とを電気的に接続するためのドレイン電極24およびコンタクトホール(図示せず)が形成されている。言い換えると、共通電極40は、少なくともコンタクトホールが形成されている領域に開口部41を有している。
第3絶縁膜18の上には複数の画素電極30が形成されている。サブ画素1つに対して1つの画素電極が設けられている。その結果として、画素形成領域にはマトリクス状の画素電極30が形成されている。
液晶表示素子10が共通電極40を備えることによって得られる効果は、寄生容量を抑制すること、適切な補助容量を確保すること、および、液晶表示素子の輝度を向上させることである。それぞれの効果について以下に説明する。
液晶表示素子10を断面視したときに、共通電極40は、信号線19と画素電極30との間かつ走査線20と画素電極30との間に設けられている(図1(b)参照)。一方、平面視において、開口部41を除く画素形成領域の全領域に共通電極は設けられている(図1(a)参照)。
液晶表示素子10において、補助容量であるCcsは、共通電極40と画素電極30との間に形成される。共通電極40と画素電極30とは、開口部41を除く広い領域において重なっている。したがって、液晶表示素子10において、十分な大きさのCcsを形成することは容易である。なお、共通電極40とSI経路との間には、膜厚の厚いJAS膜17が形成されている。よって、共通電極40とSI経路との間に形成される容量は非常に小さい。
液晶表示素子10が備える共通電極40は、ITOまたはIZOの透明導電性材料からなる。さらに、共通電極40は開口部41を備えており、ガラス基板11を平面視したときに、開口部41の少なくとも一部は、画素電極30が形成されている領域に設けられている。
(液晶表示素子50)
本発明の別の実施形態である液晶表示素子50について、図3を参照しながら説明する。図3は、液晶表示素子50の概略を示す平面図である。液晶表示素子50は、共通電極51およびTFT53の形状において液晶表示素子10と異なる。したがって、本実施形態においては共通電極51およびTFT53について説明する。なお、液晶表示装置10が備える部材と共通の部材に対しては同一の番号を付し、その説明を省略する。
液晶表示素子50は、液晶表示素子10と同様にVAモードの液晶表示素子である。しかし、液晶表示素子10がドット反転駆動によって駆動されるのに対して、液晶表示素子50は行ライン反転駆動によって駆動される。この駆動方法の違いに起因して、液晶表示装置50が備える共通電極51の形状と、液晶表示装置10が備える共通電極40の形状とは異なる。
液晶表示素子50が備えるTFTはトップゲート方式のTFTである。各サブ画素領域において、各走査線20と信号線19との交差部近辺に2つのTFTが設けられている。当該TFTは、ゲート電極53、ドレイン電極54、SI経路55およびSI経路56を備えている。当該TFTは、液晶表示素子10が備えるTFTと比較して、SI経路およびゲート電極の形状が異なっている。
本発明のさらに別の実施形態である液晶表示素子60について、図4を参照しながら説明する。液晶表示装置60が備える共通電極61は、液晶表示装置50が備える共通電極51に対して開口部の形状が異なる。共通電極51の形状は長方形である。したがって、共通電極51の信号線に対して平行方向の長さを幅としたときに、その幅は常に一定である。
本発明の一態様に係る液晶表示素子は、上記の課題を解決するために、
一対の透明基板と、当該一対の透明基板の間に配置される液晶層とを備えた液晶表示素子であって、
一方の上記透明基板は、
走査線と、
上記走査線に直交する信号線と、
上記信号線と上記走査線とに接続される駆動素子と、
上記走査線および信号線よりも上層に配置され、かつ、上記駆動素子に接続される透明画素電極と、
上記走査線および信号線と上記透明画素電極との間の層に配置され、上記走査線の少なくとも一部および上記信号線の少なくとも一部のうち少なくとも一方に対向する位置を覆い、かつ、上記透明画素電極に対向する位置に開口部を有する透明共通電極とを備え、
他方の上記透明基板は、対向電極を備えていることを特徴としている。
上記透明共通電極は、上記走査線の全部に対向する位置と、上記信号線の全部とに対向する位置と、を覆うことが好ましい。
上記一方の透明基板は、複数の上記走査線を備えており、
上記透明共通電極は、上記走査線ごとに設けられており、
各上記透明共通電極は、対応する上記走査線の全部に対向する位置を少なくとも覆うことが好ましい。
各上記透明共通電極において、対応する上記走査線と上記信号線とが交差する位置における幅は、対応する上記走査線と上記信号線とが交差しない位置における幅より広いことが好ましい。
11 ガラス基板(一方の透明基板)
12 ガラス基板(他方の透明基板)
13 液晶層
14 ベースコート
15 第1絶縁膜
16 第2絶縁膜
17 JAS膜
18 第3絶縁膜
19 信号線
20 走査線
21 SI経路
22 SI経路
23 ゲート電極
24 ドレイン電極
25 対向電極
26 カラーフィルター
27 Csd
28 Cgd
30 画素電極(透明画素電極)
40 共通電極(透明共通電極)
41 開口部
Claims (5)
- 一対の透明基板と、当該一対の透明基板の間に配置される液晶層とを備えた液晶表示素子であって、
一方の上記透明基板は、
走査線と、
上記走査線に直交する信号線と、
上記信号線と上記走査線とに接続される駆動素子と、
上記走査線および信号線よりも上層に配置され、かつ、上記駆動素子に接続される透明画素電極と、
上記走査線および信号線と上記透明画素電極との間の層に配置され、上記走査線の少なくとも一部および上記信号線の少なくとも一部のうち少なくとも一方に対向する位置を覆い、かつ、上記透明画素電極に対向する位置に開口部を有する透明共通電極とを備え、
他方の上記透明基板は、対向電極を備えていることを特徴とする液晶表示素子。 - 上記透明共通電極は、上記走査線の全部に対向する位置と、上記信号線の全部とに対向する位置と、を覆うことを特徴とする請求項1に記載の液晶表示素子。
- 上記一方の透明基板は、複数の上記走査線を備えており、
上記透明共通電極は、上記走査線ごとに設けられており、
各上記透明共通電極は、対応する上記走査線の全部に対向する位置を少なくとも覆うことを特徴とする請求項1に記載の液晶表示素子。 - 各上記透明共通電極において、対応する上記走査線と上記信号線とが交差する位置における幅は、対応する上記走査線と上記信号線とが交差しない位置における幅より広いことを特徴とする請求項3に記載の液晶表示素子。
- 請求項1~4のいずれか一項に記載の液晶表示素子を備えていることを特徴とする液晶表示装置。
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CN105739196A (zh) * | 2016-04-28 | 2016-07-06 | 深圳市华星光电技术有限公司 | 液晶面板及液晶显示器 |
US10673481B1 (en) * | 2018-11-13 | 2020-06-02 | Innolux Corporation | Electronic modulating device |
JP7183028B2 (ja) * | 2018-12-21 | 2022-12-05 | 株式会社ジャパンディスプレイ | カメラ及び表示装置を組み込んだ電子機器 |
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JPH0263020A (ja) * | 1988-08-30 | 1990-03-02 | Toshiba Corp | アクティブマトリクス型液晶表示素子 |
JP2005128053A (ja) * | 2003-10-21 | 2005-05-19 | Sharp Corp | 液晶表示装置 |
JP2006343612A (ja) * | 2005-06-10 | 2006-12-21 | Casio Comput Co Ltd | 液晶表示装置 |
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JPH11337963A (ja) * | 1998-05-27 | 1999-12-10 | Sanyo Electric Co Ltd | 垂直配向型液晶表示装置 |
JP4099324B2 (ja) * | 2000-11-27 | 2008-06-11 | シャープ株式会社 | 液晶表示装置 |
JP2003091019A (ja) * | 2001-09-19 | 2003-03-28 | Fujitsu Ltd | 液晶表示装置 |
KR20050031478A (ko) * | 2003-09-29 | 2005-04-06 | 삼성전자주식회사 | Ocb 모드 액정 표시 장치 |
TWI327239B (en) * | 2006-01-20 | 2010-07-11 | Au Optronics Corp | Pixel and liquid crystal display and method for manufacturing the same |
JP4544251B2 (ja) | 2007-02-27 | 2010-09-15 | ソニー株式会社 | 液晶表示素子および表示装置 |
-
2012
- 2012-10-22 JP JP2013540770A patent/JP5868993B2/ja not_active Expired - Fee Related
- 2012-10-22 CN CN201280050435.6A patent/CN103874957B/zh not_active Expired - Fee Related
- 2012-10-22 WO PCT/JP2012/077248 patent/WO2013061929A1/ja active Application Filing
- 2012-10-22 US US14/349,782 patent/US9335590B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0263020A (ja) * | 1988-08-30 | 1990-03-02 | Toshiba Corp | アクティブマトリクス型液晶表示素子 |
JP2005128053A (ja) * | 2003-10-21 | 2005-05-19 | Sharp Corp | 液晶表示装置 |
JP2006343612A (ja) * | 2005-06-10 | 2006-12-21 | Casio Comput Co Ltd | 液晶表示装置 |
Also Published As
Publication number | Publication date |
---|---|
CN103874957B (zh) | 2016-05-25 |
JP5868993B2 (ja) | 2016-02-24 |
US9335590B2 (en) | 2016-05-10 |
CN103874957A (zh) | 2014-06-18 |
US20140307214A1 (en) | 2014-10-16 |
JPWO2013061929A1 (ja) | 2015-04-02 |
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