WO2013061556A1 - Liquid-crystal panel and manufacturing method thereof - Google Patents
Liquid-crystal panel and manufacturing method thereof Download PDFInfo
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- WO2013061556A1 WO2013061556A1 PCT/JP2012/006723 JP2012006723W WO2013061556A1 WO 2013061556 A1 WO2013061556 A1 WO 2013061556A1 JP 2012006723 W JP2012006723 W JP 2012006723W WO 2013061556 A1 WO2013061556 A1 WO 2013061556A1
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G02F1/136259—Repairing; Defects
- G02F1/136268—Switch defects
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- G—PHYSICS
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a liquid crystal display panel and a manufacturing method thereof, and in particular, in a liquid crystal display panel including a thin film transistor substrate, a short-circuit defect generated between the source electrode of each thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate is corrected. It is related to the technology.
- An active matrix liquid crystal display panel includes, for example, a TFT substrate having a thin film transistor (hereinafter referred to as “TFT”) and a pixel electrode connected to the TFT for each pixel which is the minimum unit of an image. And a counter substrate provided to face the TFT substrate and having a common electrode, and a liquid crystal layer provided between each pixel electrode of the TFT substrate and the common electrode of the counter substrate.
- TFT thin film transistor
- a counter substrate provided to face the TFT substrate and having a common electrode, and a liquid crystal layer provided between each pixel electrode of the TFT substrate and the common electrode of the counter substrate.
- an auxiliary capacitor is provided for each pixel in order to stably hold charges charged in the liquid crystal layer of each pixel, that is, the liquid crystal capacitor of each pixel.
- each unit pixel arranged in a matrix (corresponding to the above-described pixel) is divided into a plurality of subpixel regions, and each subpixel region is divided.
- An active element (corresponding to the TFT), a liquid crystal capacitor (corresponding to the liquid crystal capacitor), and a storage capacitor (corresponding to the auxiliary capacitor) are arranged in the same unit pixel,
- a liquid crystal display panel in which a capacitance ratio with a liquid crystal capacitor is varied for each sub-pixel region.
- the source electrode and the drain electrode are short-circuited, and the pixel is
- the substrate inspection process when a short-circuit defect in which the source electrode and the drain electrode are short-circuited is detected in any of the TFTs of each pixel, the laser is corrected in the correction process.
- the pixel electrode of the pixel in which the short-circuit defect is detected and the short-circuited drain electrode are separated from each other and become a black spot by light irradiation.
- the present invention has been made in view of such a point, and an object of the present invention is to minimize a short-circuit defect generated between the source electrode of each thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate. It is easy to modify.
- a liquid crystal display panel includes a pixel having a first subpixel and a second subpixel adjacent to each other, a gate line disposed between the first subpixel and the second subpixel, A source line disposed along an edge of the pixel in a direction intersecting with the gate line, a first thin film transistor provided in the first sub-pixel, a first source electrode provided in the first thin film transistor, and A thin film transistor substrate provided with a second thin film transistor provided in the second subpixel; a second source electrode provided in the second thin film transistor; and a counter substrate provided opposite to the thin film transistor substrate and having a common electrode; A liquid crystal layer provided between the thin film transistor substrate and the counter substrate, the source line extending along the gate line, and an upper side from the drawer It has a branching portion that branches to the first source electrode and the second source electrode, the gate line is open at the bifurcation.
- the source line has a lead portion extending along the gate line, and a branch portion branching from the lead portion to the first source electrode and the second source electrode, and the gate line is a branch portion of the source line.
- the first source electrode of the first thin film transistor on the thin film transistor substrate side or the second source electrode of the second thin film transistor and the common electrode of the counter substrate are short-circuited in each pixel of the liquid crystal display panel.
- the first source electrode or the second source electrode that has been short-circuited is cut by irradiating a laser beam through the opening of the gate line in the pixel in which the short-circuit defect is detected.
- the corresponding first thin film transistor or second thin film transistor is separated from the source line to which the thin film transistor is connected.
- the signal input to the common electrode is not input to the source line, so that the signal is generated between the source electrode of the thin film transistor provided on the thin film transistor substrate and the common electrode of the counter substrate.
- the short-circuit defect is corrected.
- a portion irradiated with laser light (a branch portion branched to the first source electrode or the second source electrode) is separated from a portion extending in a direction intersecting with each gate line of each source line.
- the liquid crystal display panel according to the present invention includes a first subpixel and a second subpixel arranged so as to be adjacent to each other, a plurality of pixels provided in a matrix, and a first subpixel of each pixel.
- a plurality of gate lines provided between the first sub-pixel and the second sub-pixel so as to extend in parallel with each other, and each of the pixels in a direction intersecting with each gate line so as to extend in parallel with each other.
- a plurality of source lines provided respectively, a plurality of first thin film transistors provided for each first sub-pixel of each pixel, and a plurality of second thin film transistors provided for each second sub-pixel of each pixel
- the thin film transistor substrate includes a portion of each of the first thin film transistors branching to the first sub-pixel side after each source line is drawn out along the gate lines in each pixel.
- a first source electrode to be configured; and a second source electrode that is branched to the second sub-pixel side to form a part of each of the second thin film transistors.
- the gate lines are branched from the source lines. Opened at the part.
- each source line is led out along each gate line and then branched to the first subpixel side and branched to the second subpixel side.
- a thin film transistor substrate in each pixel of the liquid crystal display panel since each gate line is opened at a portion where each source line branches, that is, a portion of the first source electrode and the second source electrode.
- the signal input to the common electrode is not input to the source line, so that the thin film transistor substrate provided between the source electrode of each thin film transistor and the common electrode of the counter substrate is interposed. Any short circuit defects that occur are corrected.
- the portion (first source electrode or second source electrode) irradiated with laser light when correcting the short-circuit defect is separated from the portion extending in the direction intersecting with each gate line of each source line, and Since it does not overlap with the gate line, damage to each source line and each gate line due to laser light irradiation is suppressed, and, for example, a short-circuit defect than when a thin film transistor is arranged near the intersection of the source line and the gate line Is easily corrected. Therefore, a short-circuit defect that has occurred between the source electrode of each thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate can be corrected as easily as possible.
- the gate lines may be opened at a single lead-out portion of the source lines.
- each gate line is opened at a single drawn portion of each source line, the overlapping area between each gate line and each source line is suppressed, and each gate line and each source are suppressed.
- the parasitic capacitance formed at the intersection with the line is reduced.
- Each of the first thin film transistors includes a first semiconductor layer provided in an island shape, and the first source electrode is a portion to be cut formed in a linear shape of 3 ⁇ m or more so as not to overlap the first semiconductor layer.
- Each of the second thin film transistors has a second semiconductor layer provided in an island shape, and the second source electrode is formed in a linear shape of 3 ⁇ m or more so as not to overlap the second semiconductor layer. It may have a part to be cut.
- each of the cut portions is irradiated with laser light to correct the short-circuited first source electrode or the first source electrode. 2 The source electrode is cut reliably.
- the first thin film transistors and the second thin film transistors may be provided in an intermediate portion between the pair of adjacent source lines.
- each 1st thin-film transistor and each 2nd thin-film transistor are provided in the intermediate part of a pair of adjacent source line, the location (1st source) irradiated with a laser beam when correcting a short circuit defect Electrode or second source electrode) is specifically separated from a portion of each source line extending in a direction intersecting with each gate line.
- a + -shaped dark portion is formed around the center of each sub-pixel.
- each first thin film transistor and each second thin film transistor Utilizing each first thin film transistor and each second thin film transistor, the capacitance line, and the extension of the drain electrode that overlaps the capacitance line are arranged to reduce the aperture ratio of each pixel due to the arrangement of the auxiliary capacitance. Is suppressed.
- the method for manufacturing a liquid crystal display panel according to the present invention includes a plurality of pixels each having a first subpixel and a second subpixel arranged adjacent to each other and arranged in a matrix, A plurality of gate lines provided between the first sub-pixel and the second sub-pixel of the pixel so as to extend in parallel with each other, and the respective pixels in a direction intersecting with each gate line, in parallel with each other.
- a plurality of source lines provided to extend, a plurality of first thin film transistors provided for each first sub-pixel of each pixel, and a plurality of first thin-film transistors provided for each second sub-pixel of each pixel A second thin film transistor, and in each of the pixels, the source lines are led out along the gate lines and then branched to the first sub-pixel side so that a part of the first thin film transistors is formed.
- Thin film transistor substrate manufacturing process a counter substrate manufacturing process for manufacturing a counter substrate having a common electrode, a thin film transistor substrate manufactured in the thin film transistor substrate manufacturing process, and a counter substrate manufactured in the counter substrate manufacturing process
- said 1st source electrode or 2nd source electrode In each pixel of the bonded body manufacturing process which manufactures a bonded body by bonding a board
- each source line is drawn out along each gate line and then branched to the first subpixel side.
- a source electrode and a second source electrode branched to the second subpixel side are provided, and each gate line opens at a branched portion of each source line, that is, a portion of the first source electrode and the second source electrode. Therefore, in the defect detection step, the first source electrode of the first thin film transistor on the thin film transistor substrate side or the second source electrode of the second thin film transistor in each pixel of the liquid crystal display panel in the bonded body manufactured in the bonded body manufacturing step. And a common electrode on the counter substrate are detected, a short-circuit defect is detected.
- the first source electrode or the second source electrode that is short-circuited is cut by irradiating the laser beam through the opened portion of each gate line, and the corresponding first thin film transistor or second thin film transistor is connected to the thin film transistor.
- the source line is separated.
- a portion (first source electrode or second source electrode) irradiated with laser light when correcting a short-circuit defect is separated from a portion extending in a direction intersecting with each gate line of each source line.
- a thin film transistor is disposed in the vicinity of a portion where the source line and the gate line intersect. Short circuit defects are more easily corrected than in the case. Therefore, a short-circuit defect that has occurred between the source electrode of each thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate can be corrected as easily as possible.
- the thin film transistor substrate includes a first gate electrode in which each gate line forms a part of each first thin film transistor in each pixel, and a part of each second thin film transistor separated from the first gate electrode.
- the gate electrode is connected to the first gate electrode or the second gate electrode corresponding to the shorted first source electrode or the second source electrode. It may be separated from the gate line.
- the first gate electrode or the second gate electrode corresponding to the shorted first source electrode or the second source electrode is separated from the gate line to which the gate electrode is connected.
- FIG. 1 is a plan view of a TFT substrate constituting the liquid crystal display panel according to the first embodiment.
- FIG. 2 is a plan view of the TFT substrate in which the region A in FIG. 1 is enlarged.
- FIG. 3 is a cross-sectional view of the TFT substrate and a liquid crystal display panel including the TFT substrate along the line III-III in FIG.
- FIG. 4 is an enlarged plan view of a region where the TFT is formed on the TFT substrate.
- FIG. 5 is a cross-sectional view of a liquid crystal display panel in which a short-circuit defect has occurred between the source electrode and the common electrode.
- FIG. 6 is a cross-sectional view of a liquid crystal display panel in which a short-circuit defect has occurred between the source electrode and the drain electrode.
- FIG. 7 is a plan view of the TFT substrate illustrating the method for manufacturing the liquid crystal display panel according to the first embodiment.
- FIG. 8 is a plan view of a TFT substrate showing a method for manufacturing a liquid crystal display panel according to Embodiment 2.
- FIG. 7 is a plan view of the TFT substrate illustrating the method for manufacturing the liquid crystal display panel according to the first embodiment.
- FIG. 8 is a plan view of a TFT substrate showing a method for manufacturing a liquid crystal display panel according to Embodiment 2.
- FIG. 8 is a plan view of a TFT substrate showing a method for manufacturing a liquid crystal display panel according to Embodiment 2.
- Embodiment 1 of the Invention 1 to 7 show Embodiment 1 of a liquid crystal display panel and a method for manufacturing the same according to the present invention.
- FIG. 1 is a plan view of the TFT substrate 20 constituting the liquid crystal display panel 50 of the present embodiment
- FIG. 2 is a plan view of the TFT substrate 20 in which a region A in FIG. 1 is enlarged.
- 3 is a cross-sectional view of the TFT substrate 20 and the liquid crystal display panel 50 including the same along the line III-III in FIG.
- FIG. 4 is an enlarged plan view of a region of the TFT substrate 20 where the first TFT 5a and the second TFT 5b are formed, that is, the vicinity of a region irradiated with laser light when correcting a short-circuit defect.
- the liquid crystal display panel 50 includes a TFT substrate 20 and a counter substrate 30 provided so as to face each other, a liquid crystal layer 40 provided between the TFT substrate 20 and the counter substrate 30, and a TFT substrate. 20 and the counter substrate 30 are bonded to each other, and a sealing material (not shown) for sealing the liquid crystal layer 40 between the TFT substrate 20 and the counter substrate 30 is provided.
- a sealing material (not shown) for sealing the liquid crystal layer 40 between the TFT substrate 20 and the counter substrate 30 is provided.
- first sub-pixels Pa and A plurality of pixels P having the second sub-pixel Pb are provided in a matrix.
- the TFT substrate 20 is respectively formed on the transparent substrate 10a so as to extend in parallel between the transparent substrate 10a and the first subpixel Pa and the second subpixel Pb of each pixel P.
- a plurality of capacitors provided on the transparent substrate 10a so as to extend in parallel with each other between the provided gate lines 11a and the pixels P in the extending direction of the gate lines 11a (lateral direction in FIG. 1).
- a plurality of first source lines 14a provided so as to extend in parallel with each other between the pixels 11 in a direction (vertical direction in FIG. 1) perpendicular to the gate lines 11a and the capacitor lines 11b.
- a plurality of second source lines 14b that extend in parallel to each other between the pixels P in a direction orthogonal to the gate lines 11a and the capacitor lines 11b and are adjacent to the first source lines 14a, respectively.
- the capacitor line 11b is provided in a two-row lattice form between a pair of adjacent gates 11a.
- the first TFT 5a includes a first gate electrode 11aa provided as a part of the gate line 11a on the transparent substrate 10a and a gate insulation provided so as to cover the first gate electrode 11aa.
- a first source electrode 14aba and a first drain electrode 14ca provided to face each other.
- the first source electrode 14 ab is drawn out from the first source line 14 a or the second source line 14 b along the gate line 11 a, and then on the first subpixel Pa side. It is a portion branched in a U-shape.
- the portion of the first source line 14a or the second source line 14b that is led out along the gate line 11a is gated by the first source line 14a or the second source line 14b.
- the lead portion 14ab extends along the line 11a.
- each first subpixel Pa the first drain electrode 14ca is extended in a + -shape around the center thereof, and an interlayer insulation is formed in the center of the portion extended in the + -shape.
- the auxiliary capacitor of each first subpixel Pa is configured by being connected to the first pixel electrode 16a through the contact hole 15a formed in the film 15 and overlapping the capacitor line 11b through the gate insulating film 12. is doing.
- the second TFT 5b includes a second gate electrode 11ab provided as a part of the gate line 11a on the transparent substrate 10a and a gate insulation provided so as to cover the second gate electrode 11ab.
- a second source electrode 14abb and a second drain electrode 14cb provided to face each other.
- the second source electrode 14abb is led out along the gate line 11a from the first source line 14a or the second source line 14b to the second subpixel Pa side. It is a portion branched in a U-shape.
- the branch portion 14 abc branches from the lead portion 14 ab to the first source electrode 14 aba and the second source electrode 14 abb. .
- each second subpixel Pb the second drain electrode 14cb extends in a + -shape around the center thereof, and an interlayer insulation is formed in the center of the portion extended in the + -shape.
- the auxiliary capacitor of each second subpixel Pb is configured by being connected to the second pixel electrode 16b through the contact hole 15a formed in the film 15 and overlapping the capacitor line 11b through the gate insulating film 12. is doing.
- the first TFT 5a and the second TFT 5b have source lines (first source line 14a and second source different from each other) that are adjacent to each other along a direction orthogonal to the gate line 11a (vertical direction in the drawing).
- the connection structure of the first TFT 5a and the second TFT 5b and the first source line 14a or the second source line 14b is arranged in a staggered manner. That is, as shown in FIG. 1, the first TFT 5a and the second TFT 5b on the lower right side in the drawing are connected to the first source line 14a extending in the center in the drawing and are adjacent to each other along the vertical direction in the drawing.
- the first TFT 5a and the second TFT 5b on the upper right side in the drawing are connected to the second source line 14b extending on the right side in the drawing, and the first TFT 5a and the second TFT 5b on the lower left side in the drawing are the second source extending in the center in the drawing.
- a first TFT 5a and a second TFT 5b on the upper left side in the figure that are connected to the line 14b and are adjacent to each other along the vertical direction in the figure are connected to a first source line 14a that extends to the left side in the figure.
- the gate line 11a includes a branched portion of the first source line 14a and the second source line 14b (a branched portion 14abc between the first source electrode 14aba and the second source electrode 14abb). , A single lead-out portion (drawing portion 14ab) opens.
- the first gate electrode 11aa and the second gate electrode 11ab are separated from each other through the open region of the gate line 11a.
- the first source electrode 14aba and the second source electrode 14abb are to be cut in a line shape of 3 ⁇ m or more so as not to overlap the first semiconductor layer 13a and the second semiconductor layer 13b, respectively.
- Each has C.
- specific dimensions in the vicinity of the first TFT 5a and the second TFT 5b are illustrated.
- Da is about 10 ⁇ m
- Db is about 15 ⁇ m
- Dc is about 6 ⁇ m
- Dd is 7 ⁇ m.
- De is about 4 ⁇ m
- Df is about 7 ⁇ m
- Dg is about 10 ⁇ m
- Dh is about 4.5 ⁇ m.
- Each size of the first subpixel Pa and the second subpixel Pb is about 375 ⁇ m long ⁇ about 250 ⁇ m wide.
- the counter substrate 30 includes a transparent substrate 10 b, a black matrix 21 provided in a frame shape on the transparent substrate 10 b and in a lattice shape in the frame, and between the lattices of the black matrix 21.
- a plurality of colored layers such as a red layer, a green layer and a blue layer provided, a common electrode 22 provided so as to cover the black matrix 21 and each colored layer, and a columnar shape provided on the common electrode 22
- a plurality of photo spacers (not shown) and an alignment film (not shown) provided so as to cover the common electrode and each photo spacer.
- the liquid crystal layer 40 is made of a nematic liquid crystal material having electro-optical characteristics, and includes liquid crystal molecules having negative dielectric anisotropy ( ⁇ ⁇ 0).
- the liquid crystal display panel 50 having the above-described configuration is provided for each pixel P in the liquid crystal layer 40 disposed between each first pixel electrode 16 a and each second pixel electrode 16 b on the TFT substrate 20 and the common electrode 22 on the counter substrate 30.
- the transmittance of light transmitted through the panel is adjusted for each pixel P, and an image is displayed.
- the first subpixel Pa and the second subpixel Pb of each pixel P are individually driven, so that the luminance of the first subpixel Pa and the second subpixel Pb of each pixel P is increased. It is controlled to be different from each other.
- FIG. 5 is a cross-sectional view of the liquid crystal display panel 50 in which a short-circuit defect Sa has occurred between the first source electrode 14 aba and the common electrode 22.
- FIG. 6 is a cross-sectional view of the liquid crystal display panel 50 in which a short-circuit defect Sb has occurred between the first source electrode 14aba and the first drain electrode 14ca.
- FIG. 7 is a plan view of the TFT substrate 20 showing a method for manufacturing the liquid crystal display panel 50 of the present embodiment.
- the manufacturing method of this embodiment includes a TFT substrate manufacturing process, a counter substrate manufacturing process, a bonded body manufacturing process, a defect detection process, and a defect correction process.
- ⁇ TFT substrate manufacturing process> First, a titanium film (thickness of about 25 nm) and a copper film (thickness of about 400 nm) are sequentially formed on the entire substrate of the transparent substrate 10a such as a glass substrate by, for example, sputtering to form a metal laminated film. After that, the metal laminated film is subjected to photolithography, etching, and resist pattern peeling cleaning to form the gate line 11a having the first gate electrode 11aa and the second gate electrode 11ab, and the capacitor line 11b. .
- a silicon nitride film (having a thickness of about 400 nm) or the like is formed on the entire substrate on which the gate lines 11a and the capacitor lines 11b are formed, for example, by plasma CVD (Chemical Vapor Deposition) method. Form.
- an intrinsic amorphous silicon film (thickness of about 200 nm) and phosphorus-doped n + amorphous silicon film (thickness of about 20 nm) are formed on the entire substrate on which the gate insulating film 12 is formed, for example, by plasma CVD.
- the first and second gate electrodes 11aa and 11ab are removed by performing photolithography, etching, and resist pattern peeling cleaning on the intrinsic amorphous silicon film and the n + amorphous silicon film.
- An island-shaped first semiconductor layer forming layer (13a) and a second semiconductor layer forming layer (13b) are formed above.
- a titanium film (thickness of about 30 nm) and a copper film (thickness) are formed on the entire substrate on which the first semiconductor layer formation layer (13a) and the second semiconductor layer formation layer (13b) are formed, for example, by sputtering.
- a metal laminated film is formed, and then the metal laminated film is subjected to photolithography, etching, and resist pattern peeling cleaning, whereby the first source electrode 14aba and the first A first source line 14a having two source electrodes 14abb, a second source line 14b having first and second source electrodes 14abb, 14abb, a first drain electrode 14ca, and a second drain electrode 14cb are formed.
- the first semiconductor layer 13a and the first TFT 5a including the first semiconductor layer 13a, and the second semiconductor layer 13b and the second TFT 5b including the first semiconductor layer 13b are formed.
- a silicon nitride film (thickness of about 200 nm) or the like is formed on the entire substrate on which the first TFT 5a and the second TFT 5b are formed by, for example, a plasma CVD method to form an inorganic insulating film.
- an acrylic photosensitive resin film is applied to the entire substrate on which the inorganic insulating film has been formed, for example, by a spin coating method or a slit coating method, and the applied photosensitive resin film is exposed to light. Then, by performing development and baking, an organic insulating film (thickness of about 2500 nm) having an opening serving as a part of the contact hole 15a is formed above the first drain electrode 14ca and the second drain electrode 14cb.
- the inorganic insulating film exposed from the opening of the organic insulating film is removed by etching to form a contact hole 15a, thereby forming an interlayer insulating film 15 composed of a laminated film of the inorganic insulating film and the organic insulating film. To do.
- the first pixel electrode 16a and the second pixel electrode 16b are formed by performing photolithography, etching, and resist pattern peeling and cleaning.
- an alignment film material film is applied to the entire substrate on which the first pixel electrode 16a and the second pixel electrode 16b are formed by, for example, a spin coating method or a slit coating method, and the applied alignment film material is applied to the alignment film material. Then, an alignment film (having a thickness of about 100 nm) is formed by performing exposure, development, and baking.
- the alignment film material film is formed of, for example, a thin film of a polymer organic compound configured such that a side chain is inclined in the irradiation direction of UV light by irradiation with UV (ultraviolet) light for a certain period of time.
- the TFT substrate 20 can be manufactured as described above.
- an acrylic photosensitive resin colored in black is applied to the entire substrate of the transparent substrate 10b such as a glass substrate by, for example, a spin coating method or a slit coating method, and the applied photosensitive resin is applied to a photomask.
- the black matrix 21 (thickness of about 2 ⁇ m) is formed by developing after exposure through the film.
- an acrylic photosensitive resin colored in red, green or blue is applied to the substrate on which the black matrix 21 is formed by, for example, spin coating or slit coating, and the applied photosensitive property is applied.
- the resin is exposed through a photomask and then patterned by development to form a colored layer (for example, a red layer) of a selected color with a thickness of about 2 ⁇ m. Further, the same process is repeated for the other two colors to form other two colored layers (for example, a green layer and a blue layer) with a thickness of about 2 ⁇ m.
- an ITO film (thickness of about 100 nm) is formed on the substrate on which each of the colored layers is formed by, for example, a sputtering method to form the common electrode 22.
- a photo spacer (thickness of about 1 ⁇ m) is formed by performing exposure, development, and baking.
- an alignment film material film is applied to the entire substrate on which the photo spacer is formed, for example, by spin coating or slit coating, and the applied alignment film material is exposed, developed and baked. By doing so, an alignment film (thickness of about 100 nm) is formed.
- the counter substrate 30 can be manufactured as described above.
- ⁇ Bonded body production process First, for example, after a seal material made of a UV curing and thermosetting resin or the like is printed in a frame shape on the surface of the counter substrate 30 manufactured in the counter substrate manufacturing step, a liquid crystal material is placed inside the seal material. Is dripped.
- the counter substrate 30 onto which the liquid crystal material has been dropped and the TFT substrate 20 manufactured in the TFT substrate manufacturing process are bonded together under reduced pressure, and then the bonded bonded body is released to atmospheric pressure. By pressing, the surface and the back surface of the bonded body are pressurized.
- the sealing material is cured by heating the bonded body.
- the unnecessary part is removed by dividing the bonding body which hardened the above-mentioned sealing material, for example by dicing.
- the liquid crystal display panel 50 (bonding body) can be produced as described above.
- a predetermined inspection signal is applied to each gate line 11 a, each capacitance line 11 b, each first source line 14 a, each second source line 14 b, and the common electrode 22 for the liquid crystal display panel 50 manufactured in the bonded body manufacturing process.
- the defect Sa is detected.
- the short-circuit defect Sa is generated when the foreign matter F that causes the short-circuit defect Sb generated between the first source electrode 14 aba and the first drain electrode 14 ca transports the liquid crystal display panel. It is thought that this occurs due to movement due to vibration of the panel or pressure applied to the panel surface.
- the laser light L is applied to the Ra portion of the first source electrode 14aba in the first subpixel P in which the short-circuit defect Sa has been detected.
- the first TFT 5a is separated from the first source line 14a by irradiating and cutting the first source electrode 14aba at the cut portion C.
- the laser light L is output with a spot size of about 1 ⁇ m ⁇ 5 ⁇ m using, for example, a YAG (Yttrium Aluminum Garnet) laser.
- the capacitance line 11b and the first drain electrode 14ca are connected by laser light irradiation, thereby blackening the first subpixel Pa.
- the liquid crystal display panel 50 in which the short-circuit defect Sa of the present embodiment is corrected can be manufactured.
- each first source line 14a or each second source line 14a in the TFT substrate 20 manufactured in the TFT substrate manufacturing process, in each pixel P, each first source line 14a or each second source line 14a.
- each gate line 11a is opened at a branched portion of each first source line 14a or each second source line 14b, that is, a portion of the first source electrode 14aba and the second source electrode 14abb.
- the first source of the first TFT 5a on the TFT substrate 20 side in each pixel P of the liquid crystal display panel 50 in the bonded body manufactured in the bonded body manufacturing step When a short-circuit defect Sa in which the electrode 14aba or the second source electrode 14abb of the second TFT 5b and the common electrode 22 of the counter substrate 20 are short-circuited is detected, the short-circuit defect Sa is detected in the defect correction process.
- the first source electrode 14 aba or the second source electrode 14 abb that is short-circuited is cut by irradiating the laser beam L through the opened portion of each gate line 11 a, and the corresponding first TFT 5 a or second TFT 5 b is changed.
- the TFT is separated from the first source line 14a or the second source line 14b to which the TFT is connected. Thereby, in the pixel P in which the short-circuit defect Sa is detected, the signal input to the common electrode 22 is not input to the first source line 14a or the second source line 14b, so that each TFT ( The short-circuit defect Sa generated between the source electrode (first source electrode 14aba and second source electrode 14abb) of the first TFT 5a and the second TFT 5b) and the common electrode 22 of the counter substrate 30 can be corrected.
- the defect correction step the portion (first source electrode 14 aba or second source electrode 14 abb) irradiated with the laser beam L when correcting the short-circuit defect Sa is the first source line 14 a or the second source line.
- each first source line 14a or each second source line 14b by irradiation with the laser beam L and each The damage of the gate line 11a can be suppressed, and for example, the short-circuit defect can be corrected more easily than when the TFT is arranged in the vicinity of the portion where the source line and the gate line intersect. Therefore, a short circuit generated between the source electrode (first source electrode 14 aba and second source electrode 14 abb) of each TFT (first TFT 5 a and second TFT 5 b) provided on the TFT substrate 20 and the common electrode 22 of the counter substrate 30.
- the defect Sa can be corrected as easily as possible.
- each gate line 11a is opened at a single drawn portion of each first source line 14a or each second source line 14b. 11a and the area where each first source line 14a and each second source line 14b overlap can be suppressed and formed at the intersection of each gate line 11a and each first source line 14a and each second source line 14b. Parasitic capacitance can be reduced.
- the first source electrode 14aba has the cut portion C formed in a line shape of 3 ⁇ m or more so as not to overlap the first semiconductor layer 13a
- the second source Since the electrode 14abb has the cut portions C formed in a linear shape of 3 ⁇ m or more so as not to overlap the second semiconductor layer 13b, a laser is applied to each cut portion C when correcting the short-circuit defect Sa.
- the short-circuited first source electrode 14aba or second source electrode 14abb can be reliably cut.
- each first TFT 5a and each second TFT 5b are provided in an intermediate portion between the first source line 14a and the second source line 14b adjacent via the pixel P.
- a portion (first source electrode 14 aba or second source electrode 14 abb) irradiated with laser light L when correcting the short-circuit defect Sa intersects with each gate line 11 a of each first source line 14 a or each second source line 14 b. It can be specifically spaced from the portion extending in the direction of the movement.
- a + -shaped dark portion is centered on the center of each first subpixel Pa and each second subpixel Pb Therefore, using the dark portion, the first TFT 5a and the second TFT 5b, the capacitor line 11b, and the extended portions of the first drain electrode 14ca and the second drain electrode 14cb overlapping the capacitor line 11b are formed. By disposing, it is possible to suppress a decrease in the aperture ratio of each pixel P due to the disposition of the auxiliary capacitor.
- the liquid crystal display panel 50 of the present embodiment in the pixel P in which the short-circuit defect Sa is corrected, the first subpixel Pa becomes a black spot, but the second subpixel Pb is normally driven.
- the display quality can be improved as compared with the case where the whole is blackened.
- FIG. 8 is a plan view of the TFT substrate 20a showing the method for manufacturing the liquid crystal display panel 50 of the present embodiment.
- the same parts as those in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof is omitted.
- the manufacturing method of the liquid crystal display panel 50 in which the laser beam L for cutting is irradiated to one place with respect to the pixel P in which the short-circuit defect Sa is detected is illustrated.
- a method of manufacturing the liquid crystal display panel 50 in which the cutting laser beam L is irradiated to three locations on the pixels P where Sa is detected will be exemplified.
- the first source electrode in the first subpixel P in which the short circuit defect Sa is detected as shown in FIG.
- the first source electrode 14aba is cut at the cut portion C
- the gate line 11a is cut into the first gate electrode 11aa.
- the first TFT 5a is separated from the first source line 14a and the gate line 11a by cutting at the front side and the rear side.
- the capacitance line 11b and the first drain electrode 14ca are connected by laser light irradiation, thereby blackening the first subpixel Pa.
- the liquid crystal display panel 50 in which the short-circuit defect Sa of the present embodiment is corrected can be manufactured.
- each pixel P in the TFT substrate 20 manufactured in the TFT substrate manufacturing process, in each pixel P, as in the first embodiment.
- 1 source line 14a or each 2nd source line 14b is drawn out along each gate line 11a, and then branches to the 1st subpixel Pa side, and the 1st source electrode 14aba branched to the 2nd subpixel Pb side Second gate electrode 11abb, and each gate line 11a is opened at each first source line 14a or a branched portion of each second source line 14b, that is, at the first source electrode 14abb and the second source electrode 14abb.
- the source electrodes (first source electrode 14aba and second source electrode) of each TFT (first TFT 5a and second TFT 5b) provided on the TFT substrate 20 are provided. And 14abb), it can be as much as possible easily correct the short-circuit defect Sa generated between the common electrode 22 of the counter substrate 30.
- the first gate electrode 11aa corresponding to the shorted first source electrode 14aba is connected to the gate line to which the first gate electrode 11aa is connected. 11a, the electrical connection between the first TFT 5a of the first subpixel Pa in which the short-circuit defect Sa has occurred and the corresponding gate line 11a and first source line 14a is released, so that the first TFT 5a Problems caused by the short-circuit defect Sa can be reduced.
- a liquid crystal display panel including a TFT has been exemplified.
- the present invention can also be applied to a liquid crystal display panel including a three-terminal switching element other than a TFT.
- the manufacturing method for correcting the short-circuit defect after the lighting inspection is exemplified.
- the present invention is applied to the array inspection using the charge detection method for the TFT substrate manufactured in the TFT substrate manufacturing process. After detecting the short-circuit defect generated between the source electrode and the drain electrode of the TFT and correcting the short-circuit defect, the source electrode of each TFT which is concerned after being panelized and the common electrode of the counter substrate It can apply also to the manufacturing method which suppresses generation
- a liquid crystal display panel including a bottom gate TFT has been exemplified.
- the present invention can also be applied to a liquid crystal display panel including a top gate TFT.
- the liquid crystal display panel including the TFT substrate in which the two source lines of the first source line and the second source line are provided between the pixels is illustrated.
- the present invention can also be applied to a liquid crystal display panel including a TFT substrate in which one source line is provided between pixels.
- the liquid crystal display panel including the TFT substrate having the TFT electrode connected to the pixel electrode as the drain electrode has been exemplified.
- the TFT electrode connected to the pixel electrode is used as the source.
- the present invention can also be applied to a liquid crystal display panel including a TFT substrate called an electrode.
- the liquid crystal provided with the liquid crystal display panel is provided. Useful for TVs.
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Abstract
Each pixel, which is provided with a mutually adjacent first sub-pixel and second sub-pixel, of a TFT substrate (20) which configures a liquid-crystal display panel comprises a first source electrode (14aba) which splits toward the first sub-pixel side and configures a portion of each first TFT (5a), and a second source electrode (14abb) which splits toward the second sub-pixel side and configures a portion of each second TFT (5b), after each source line (14a), which extends between pixels, is integrally extracted along each gate line (11a) which extends between the first sub-pixel and the second sub-pixel of each pixel. Each gate line (11a) opens at the part where each source line (14a) splits.
Description
本発明は、液晶表示パネル及びその製造方法に関し、特に、薄膜トランジスタ基板を備えた液晶表示パネルにおいて、薄膜トランジスタ基板の各薄膜トランジスタのソース電極と、対向基板の共通電極との間に発生した短絡欠陥を修正する技術に関するものである。
The present invention relates to a liquid crystal display panel and a manufacturing method thereof, and in particular, in a liquid crystal display panel including a thin film transistor substrate, a short-circuit defect generated between the source electrode of each thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate is corrected. It is related to the technology.
アクティブマトリクス駆動方式の液晶表示パネルは、例えば、画像の最小単位である各画素毎に、薄膜トランジスタ（Thin Film Transistor、以下、「ＴＦＴ」とも称する）、及びＴＦＴに接続された画素電極を有するＴＦＴ基板と、ＴＦＴ基板に対向するように設けられ、共通電極を有する対向基板と、ＴＦＴ基板の各画素電極及び対向基板の共通電極の間に設けられた液晶層とを備えている。ここで、多くのＴＦＴ基板では、各画素の液晶層、すなわち、各画素の液晶容量に充電された電荷を安定に保持するために、各画素毎に補助容量が設けられている。
An active matrix liquid crystal display panel includes, for example, a TFT substrate having a thin film transistor (hereinafter referred to as “TFT”) and a pixel electrode connected to the TFT for each pixel which is the minimum unit of an image. And a counter substrate provided to face the TFT substrate and having a common electrode, and a liquid crystal layer provided between each pixel electrode of the TFT substrate and the common electrode of the counter substrate. Here, in many TFT substrates, an auxiliary capacitor is provided for each pixel in order to stably hold charges charged in the liquid crystal layer of each pixel, that is, the liquid crystal capacitor of each pixel.
例えば、特許文献１には、液晶表示パネルの色ずれを防止するために、マトリクス状に配列された（上記画素に相当する）各単位画素を複数の副画素領域に分割し、各副画素領域に（上記ＴＦＴに相当する）アクティブ素子、（上記液晶容量に相当する）液晶キャパシタ、及び（上記補助容量に相当する）蓄積キャパシタを配置し、同一単位画素内において、副画素領域における蓄積キャパシタと液晶キャパシタとの容量比を副画素領域毎に異ならせた液晶表示パネルが開示されている。
For example, in Patent Document 1, in order to prevent color misregistration of a liquid crystal display panel, each unit pixel arranged in a matrix (corresponding to the above-described pixel) is divided into a plurality of subpixel regions, and each subpixel region is divided. An active element (corresponding to the TFT), a liquid crystal capacitor (corresponding to the liquid crystal capacitor), and a storage capacitor (corresponding to the auxiliary capacitor) are arranged in the same unit pixel, There is disclosed a liquid crystal display panel in which a capacitance ratio with a liquid crystal capacitor is varied for each sub-pixel region.
ところで、ＴＦＴ基板を備えた液晶表示パネルでは、各画素のＴＦＴにおいて、ソース電極及びドレイン電極の間に導電性を有する異物が介在すると、ソース電極及びドレイン電極の間が短絡して、その画素が正常に動作しなくなるおそれがあるので、例えば、基板検査工程において、各画素のＴＦＴの何れかでソース電極及びドレイン電極の間が短絡した短絡欠陥が検出された場合には、修正工程において、レーザー光の照射により、短絡欠陥が検出された画素の画素電極と、短絡したドレイン電極とを切り離して黒点化することが多い。
By the way, in the liquid crystal display panel provided with the TFT substrate, when a foreign substance having conductivity is interposed between the source electrode and the drain electrode in the TFT of each pixel, the source electrode and the drain electrode are short-circuited, and the pixel is For example, in the substrate inspection process, when a short-circuit defect in which the source electrode and the drain electrode are short-circuited is detected in any of the TFTs of each pixel, the laser is corrected in the correction process. In many cases, the pixel electrode of the pixel in which the short-circuit defect is detected and the short-circuited drain electrode are separated from each other and become a black spot by light irradiation.
しかしながら、上記修正工程において、短絡欠陥が検出された画素の画素電極と、短絡したドレイン電極とを切り離しても、液晶表示パネルを運搬する際の振動やパネル表面に対する加圧などに起因して、ソース電極及びドレイン電極の間を短絡させていた異物を介して、ＴＦＴ基板側の短絡した又は短絡していたソース電極と、対向基板側の共通電極との間が短絡するおそれがある。また、上記基板検査工程において、短絡欠陥として検出されないレベルであっても、仮に、ソース電極及びドレイン電極の間に導電性を有する異物が潜在していれば、液晶表示パネルを運搬する際の振動やパネル表面に対する加圧などにより、ソース電極及びドレイン電極の間に潜在する異物が顕在化して、ＴＦＴ基板側のソース電極と、対向基板側の共通電極との間が短絡するおそれもある。なお、特許文献１に開示された液晶表示パネルのように、ゲート線及びソース線の交差する部分の近傍にＴＦＴが設けられた液晶表示パネルでは、上記修正工程において、レーザー光を照射する際に、ＴＦＴに接続されたゲート線及びソース線を損傷させるおそれがあるので、改善の余地がある。
However, in the above correction process, even if the pixel electrode of the pixel in which the short-circuit defect is detected and the drain electrode that is short-circuited are separated, due to vibration during transportation of the liquid crystal display panel or pressure on the panel surface, There is a risk of short circuit between the short-circuited source electrode on the TFT substrate side or the short-circuited source electrode and the common electrode on the counter substrate side through foreign matter that has short-circuited between the source electrode and the drain electrode. In addition, in the substrate inspection process, even when the level is not detected as a short-circuit defect, if there is a conductive foreign substance between the source electrode and the drain electrode, the vibration when transporting the liquid crystal display panel There is also a possibility that a foreign substance latent between the source electrode and the drain electrode becomes obvious due to pressure applied to the panel surface or the like, and the source electrode on the TFT substrate side and the common electrode on the counter substrate side are short-circuited. Note that, in the liquid crystal display panel in which the TFT is provided in the vicinity of the portion where the gate line and the source line intersect like the liquid crystal display panel disclosed in Patent Document 1, when the laser beam is irradiated in the correction step, Since there is a risk of damaging the gate line and the source line connected to the TFT, there is room for improvement.
本発明は、かかる点に鑑みてなされたものであり、その目的とするところは、薄膜トランジスタ基板の各薄膜トランジスタのソース電極と、対向基板の共通電極との間に発生した短絡欠陥を可及的に容易に修正することにある。
The present invention has been made in view of such a point, and an object of the present invention is to minimize a short-circuit defect generated between the source electrode of each thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate. It is easy to modify.
上記目的を達成するために、本発明は、各画素において、各ソース線が各ゲート線に沿って単一に引き出された後に第１副画素側に分岐した第１ソース電極と、第２副画素側に分岐した第２ソース電極とを備えるようにしたものである。
In order to achieve the above object, according to the present invention, in each pixel, a first source electrode branched to the first subpixel side after each source line is led out along each gate line, And a second source electrode branched to the pixel side.
具体的に本発明に係る液晶表示パネルは、互いに隣り合う第１副画素及び第２副画素を有する画素と、該第１副画素及び第２副画素の間に配置されたゲート線と、該ゲート線と交差する方向の上記画素の縁に沿って配置されたソース線と、上記第１副画素に設けられた第１薄膜トランジスタと、該第１薄膜トランジスタに設けられた第１ソース電極と、上記第２副画素に設けられた第２薄膜トランジスタと、該第２薄膜トランジスタに設けられた第２ソース電極とを備えた薄膜トランジスタ基板と、上記薄膜トランジスタ基板に対向して設けられ、共通電極を有する対向基板と、上記薄膜トランジスタ基板及び対向基板の間に設けられた液晶層とを備え、上記ソース線は、上記ゲート線に沿って延びる引き出し部、及び該引き出し部から上記第１ソース電極と上記第２ソース電極とに分岐する分岐部を有し、上記ゲート線は、上記分岐部で開口している。
Specifically, a liquid crystal display panel according to the present invention includes a pixel having a first subpixel and a second subpixel adjacent to each other, a gate line disposed between the first subpixel and the second subpixel, A source line disposed along an edge of the pixel in a direction intersecting with the gate line, a first thin film transistor provided in the first sub-pixel, a first source electrode provided in the first thin film transistor, and A thin film transistor substrate provided with a second thin film transistor provided in the second subpixel; a second source electrode provided in the second thin film transistor; and a counter substrate provided opposite to the thin film transistor substrate and having a common electrode; A liquid crystal layer provided between the thin film transistor substrate and the counter substrate, the source line extending along the gate line, and an upper side from the drawer It has a branching portion that branches to the first source electrode and the second source electrode, the gate line is open at the bifurcation.
上記の構成によれば、ソース線がゲート線に沿って延びる引き出し部、及び引き出し部から第１ソース電極と第２ソース電極とに分岐する分岐部を有し、ゲート線がソース線の分岐部で開口しているので、液晶表示パネルの各画素において、薄膜トランジスタ基板側の第１薄膜トランジスタの第１ソース電極、又は第２薄膜トランジスタの第２ソース電極と、対向基板の共通電極との間が短絡した短絡欠陥が検出された場合には、短絡欠陥が検出された画素において、ゲート線の開口した部分を介してレーザー光を照射することにより、短絡した第１ソース電極又は第２ソース電極を切断して、対応する第１薄膜トランジスタ又は第２薄膜トランジスタをその薄膜トランジスタが接続されたソース線から分離することになる。これにより、短絡欠陥が検出された画素において、共通電極に入力される信号がソース線に入力されなくなるので、薄膜トランジスタ基板に設けられた薄膜トランジスタのソース電極と、対向基板の共通電極との間に発生した短絡欠陥が修正される。ここで、短絡欠陥を修正する際にレーザー光を照射する箇所（第１ソース電極又は第２ソース電極に分岐する分岐部）は、各ソース線の各ゲート線と交差する方向に延びる部分から離間していると共に、ゲート線に重なっていないので、レーザー光の照射によるソース線及びゲート線の損傷が抑制され、例えば、薄膜トランジスタがソース線及びゲート線の交差する部分の近傍に配置された場合よりも短絡欠陥が容易に修正される。したがって、薄膜トランジスタ基板の薄膜トランジスタのソース電極と、対向基板の共通電極との間に発生した短絡欠陥を可及的に容易に修正することが可能になる。
According to the above configuration, the source line has a lead portion extending along the gate line, and a branch portion branching from the lead portion to the first source electrode and the second source electrode, and the gate line is a branch portion of the source line. In each pixel of the liquid crystal display panel, the first source electrode of the first thin film transistor on the thin film transistor substrate side or the second source electrode of the second thin film transistor and the common electrode of the counter substrate are short-circuited in each pixel of the liquid crystal display panel. When the short-circuit defect is detected, the first source electrode or the second source electrode that has been short-circuited is cut by irradiating a laser beam through the opening of the gate line in the pixel in which the short-circuit defect is detected. Thus, the corresponding first thin film transistor or second thin film transistor is separated from the source line to which the thin film transistor is connected. As a result, in the pixel in which the short-circuit defect is detected, the signal input to the common electrode is not input to the source line, so that the signal is generated between the source electrode of the thin film transistor provided on the thin film transistor substrate and the common electrode of the counter substrate. The short-circuit defect is corrected. Here, when the short-circuit defect is corrected, a portion irradiated with laser light (a branch portion branched to the first source electrode or the second source electrode) is separated from a portion extending in a direction intersecting with each gate line of each source line. In addition, since it does not overlap with the gate line, damage to the source line and the gate line due to laser light irradiation is suppressed. For example, a thin film transistor is disposed near the intersection of the source line and the gate line. Even short-circuit defects are easily corrected. Therefore, it is possible to correct as much as possible a short-circuit defect generated between the source electrode of the thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate.
また、本発明に係る液晶表示パネルは、各々、互いに隣り合うように配置された第１副画素及び第２副画素を有し、マトリクス状に設けられた複数の画素と、該各画素の第１副画素及び第２副画素の間に、互いに平行に延びるようにそれぞれ設けられた複数のゲート線と、該各ゲート線と交差する方向の該各画素の間に、互いに平行に延びるようにそれぞれ設けられた複数のソース線と、上記各画素の第１副画素毎にそれぞれ設けられた複数の第１薄膜トランジスタと、上記各画素の第２副画素毎にそれぞれ設けられた複数の第２薄膜トランジスタとを備えた薄膜トランジスタ基板と、上記薄膜トランジスタ基板に対向するように設けられ、共通電極を有する対向基板と、上記薄膜トランジスタ基板及び対向基板の間に設けられた液晶層とを備え、上記薄膜トランジスタ基板は、上記各画素において、上記各ソース線が上記各ゲート線に沿って単一に引き出された後に上記第１副画素側に分岐して上記各第１薄膜トランジスタの一部を構成する第１ソース電極と、上記第２副画素側に分岐して上記各第２薄膜トランジスタの一部を構成する第２ソース電極とを有し、上記各ゲート線は、上記各ソース線の分岐した部分で開口している。
In addition, the liquid crystal display panel according to the present invention includes a first subpixel and a second subpixel arranged so as to be adjacent to each other, a plurality of pixels provided in a matrix, and a first subpixel of each pixel. A plurality of gate lines provided between the first sub-pixel and the second sub-pixel so as to extend in parallel with each other, and each of the pixels in a direction intersecting with each gate line so as to extend in parallel with each other. A plurality of source lines provided respectively, a plurality of first thin film transistors provided for each first sub-pixel of each pixel, and a plurality of second thin film transistors provided for each second sub-pixel of each pixel A thin film transistor substrate, a counter substrate provided to face the thin film transistor substrate and having a common electrode, and a liquid crystal layer provided between the thin film transistor substrate and the counter substrate, The thin film transistor substrate includes a portion of each of the first thin film transistors branching to the first sub-pixel side after each source line is drawn out along the gate lines in each pixel. A first source electrode to be configured; and a second source electrode that is branched to the second sub-pixel side to form a part of each of the second thin film transistors. The gate lines are branched from the source lines. Opened at the part.
上記の構成によれば、各画素において、各ソース線が各ゲート線に沿って単一に引き出された後に第１副画素側に分岐した第１ソース電極と、第２副画素側に分岐した第２ソース電極とを備え、各ゲート線が各ソース線の分岐した部分、すなわち、第１ソース電極及び第２ソース電極の部分で開口しているので、液晶表示パネルの各画素において、薄膜トランジスタ基板側の第１薄膜トランジスタの第１ソース電極、又は第２薄膜トランジスタの第２ソース電極と、対向基板の共通電極との間が短絡した短絡欠陥が検出された場合には、短絡欠陥が検出された画素において、各ゲート線の開口した部分を介してレーザー光を照射することにより、短絡した第１ソース電極又は第２ソース電極を切断して、対応する第１薄膜トランジスタ又は第２薄膜トランジスタをその薄膜トランジスタが接続されたソース線から分離することになる。これにより、短絡欠陥が検出された画素において、共通電極に入力される信号がソース線に入力されなくなるので、薄膜トランジスタ基板に設けられた各薄膜トランジスタのソース電極と、対向基板の共通電極との間に発生した短絡欠陥が修正される。ここで、短絡欠陥を修正する際にレーザー光を照射する箇所（第１ソース電極又は第２ソース電極）は、各ソース線の各ゲート線と交差する方向に延びる部分から離間していると共に、ゲート線に重なっていないので、レーザー光の照射による各ソース線及び各ゲート線の損傷が抑制され、例えば、薄膜トランジスタがソース線及びゲート線の交差する部分の近傍に配置された場合よりも短絡欠陥が容易に修正される。したがって、薄膜トランジスタ基板の各薄膜トランジスタのソース電極と、対向基板の共通電極との間に発生した短絡欠陥を可及的に容易に修正することが可能になる。
According to the above configuration, in each pixel, each source line is led out along each gate line and then branched to the first subpixel side and branched to the second subpixel side. A thin film transistor substrate in each pixel of the liquid crystal display panel, since each gate line is opened at a portion where each source line branches, that is, a portion of the first source electrode and the second source electrode. When a short-circuit defect is detected in which the first source electrode of the first thin-film transistor on the side or the second source electrode of the second thin-film transistor and the common electrode of the counter substrate are short-circuited, the pixel in which the short-circuit defect is detected , The first source electrode or the second source electrode that has been short-circuited is cut by irradiating the laser beam through the opened portion of each gate line, and the corresponding first thin film transistor or The second thin film transistor is its thin-film transistor will be separated from the connected source line. Thereby, in the pixel in which the short-circuit defect is detected, the signal input to the common electrode is not input to the source line, so that the thin film transistor substrate provided between the source electrode of each thin film transistor and the common electrode of the counter substrate is interposed. Any short circuit defects that occur are corrected. Here, the portion (first source electrode or second source electrode) irradiated with laser light when correcting the short-circuit defect is separated from the portion extending in the direction intersecting with each gate line of each source line, and Since it does not overlap with the gate line, damage to each source line and each gate line due to laser light irradiation is suppressed, and, for example, a short-circuit defect than when a thin film transistor is arranged near the intersection of the source line and the gate line Is easily corrected. Therefore, a short-circuit defect that has occurred between the source electrode of each thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate can be corrected as easily as possible.
上記各ゲート線は、上記各ソース線の単一に引き出された部分で開口していてもよい。
The gate lines may be opened at a single lead-out portion of the source lines.
上記の構成によれば、各ゲート線が各ソース線の単一に引き出された部分で開口しているので、各ゲート線と各ソース線との重なる面積が抑制され、各ゲート線と各ソース線との交差部分に形成される寄生容量が小さくなる。
According to the above configuration, since each gate line is opened at a single drawn portion of each source line, the overlapping area between each gate line and each source line is suppressed, and each gate line and each source are suppressed. The parasitic capacitance formed at the intersection with the line is reduced.
上記各第１薄膜トランジスタは、島状に設けられた第１半導体層を有し、上記第１ソース電極は、上記第１半導体層に重ならないように３μｍ以上の線状に形成された被切断部を有し、上記各第２薄膜トランジスタは、島状に設けられた第２半導体層を有し、上記第２ソース電極は、上記第２半導体層に重ならないように３μｍ以上の線状に形成された被切断部を有していてもよい。
Each of the first thin film transistors includes a first semiconductor layer provided in an island shape, and the first source electrode is a portion to be cut formed in a linear shape of 3 μm or more so as not to overlap the first semiconductor layer. Each of the second thin film transistors has a second semiconductor layer provided in an island shape, and the second source electrode is formed in a linear shape of 3 μm or more so as not to overlap the second semiconductor layer. It may have a part to be cut.
上記の構成によれば、第１ソース電極が第１半導体層に重ならないように３μｍ以上の線状に形成された被切断部を有し、第２ソース電極が第２半導体層に重ならないように３μｍ以上の線状に形成された被切断部を有しているので、短絡欠陥を修正する際には、各被切断部にレーザー光を照射することにより、短絡した第１ソース電極又は第２ソース電極が確実に切断される。
According to said structure, it has the to-be-cut | disconnected part formed in the 3 micrometers or more line shape so that a 1st source electrode may not overlap with a 1st semiconductor layer, and a 2nd source electrode does not overlap with a 2nd semiconductor layer. In order to correct a short-circuit defect, each of the cut portions is irradiated with laser light to correct the short-circuited first source electrode or the first source electrode. 2 The source electrode is cut reliably.
上記各第１薄膜トランジスタ及び各第２薄膜トランジスタは、上記隣り合う一対のソース線の中間部分に設けられていてもよい。
The first thin film transistors and the second thin film transistors may be provided in an intermediate portion between the pair of adjacent source lines.
上記の構成によれば、各第１薄膜トランジスタ及び各第２薄膜トランジスタが隣り合う一対のソース線の中間部分に設けられているので、短絡欠陥を修正する際にレーザー光を照射する箇所（第１ソース電極又は第２ソース電極）が、各ソース線の各ゲート線と交差する方向に延びる部分から具体的に離間される。また、例えば、液晶分子の配向をピコメートルレベルで精密に制御する光配向技術を適用した液晶表示パネルでは、各副画素の中央を中心に＋字状の暗部が形成されるので、その暗部を利用して、各第１薄膜トランジスタ及び各第２薄膜トランジスタを始め、容量線、並びに容量線に重なるドレイン電極の延設部を配置することにより、補助容量の配置に起因する各画素の開口率の低下が抑制される。
According to said structure, since each 1st thin-film transistor and each 2nd thin-film transistor are provided in the intermediate part of a pair of adjacent source line, the location (1st source) irradiated with a laser beam when correcting a short circuit defect Electrode or second source electrode) is specifically separated from a portion of each source line extending in a direction intersecting with each gate line. In addition, for example, in a liquid crystal display panel to which a photo-alignment technology that precisely controls the alignment of liquid crystal molecules at a picometer level is applied, a + -shaped dark portion is formed around the center of each sub-pixel. Utilizing each first thin film transistor and each second thin film transistor, the capacitance line, and the extension of the drain electrode that overlaps the capacitance line are arranged to reduce the aperture ratio of each pixel due to the arrangement of the auxiliary capacitance. Is suppressed.
また、本発明に係る液晶表示パネルの製造方法は、各々、互いに隣り合うように配置された第１副画素及び第２副画素を有し、マトリクス状に設けられた複数の画素と、該各画素の第１副画素及び第２副画素の間に、互いに平行に延びるようにそれぞれ設けられた複数のゲート線と、該各ゲート線と交差する方向の該各画素の間に、互いに平行に延びるようにそれぞれ設けられた複数のソース線と、上記各画素の第１副画素毎にそれぞれ設けられた複数の第１薄膜トランジスタと、上記各画素の第２副画素毎にそれぞれ設けられた複数の第２薄膜トランジスタとを備え、上記各画素において、上記各ソース線が上記各ゲート線に沿って単一に引き出された後に上記第１副画素側に分岐して上記各第１薄膜トランジスタの一部を構成する第１ソース電極と、上記第２副画素側に分岐して上記各第２薄膜トランジスタの一部を構成する第２ソース電極とを有し、上記各ゲート線が上記各ソース線の分岐した部分で開口した薄膜トランジスタ基板を作製する薄膜トランジスタ基板作製工程と、共通電極を有する対向基板を作製する対向基板作製工程と、上記薄膜トランジスタ基板作製工程で作製された薄膜トランジスタ基板、及び上記対向基板作製工程で作製された対向基板を液晶層を介して貼り合わせることにより、貼合体を作製する貼合体作製工程と、上記貼合体作製工程で作製された貼合体の各画素において、上記第１ソース電極又は第２ソース電極と上記共通電極との間が短絡した短絡欠陥を検出する欠陥検出工程と、上記欠陥検出工程で短絡欠陥が検出された画素において、上記各ゲート線の開口した部分を介してレーザー光を照射することにより、上記短絡した第１ソース電極又は第２ソース電極を切断して、対応する上記第１薄膜トランジスタ又は第２薄膜トランジスタを該薄膜トランジスタが接続されたソース線から分離する欠陥修正工程とを備える。
In addition, the method for manufacturing a liquid crystal display panel according to the present invention includes a plurality of pixels each having a first subpixel and a second subpixel arranged adjacent to each other and arranged in a matrix, A plurality of gate lines provided between the first sub-pixel and the second sub-pixel of the pixel so as to extend in parallel with each other, and the respective pixels in a direction intersecting with each gate line, in parallel with each other. A plurality of source lines provided to extend, a plurality of first thin film transistors provided for each first sub-pixel of each pixel, and a plurality of first thin-film transistors provided for each second sub-pixel of each pixel A second thin film transistor, and in each of the pixels, the source lines are led out along the gate lines and then branched to the first sub-pixel side so that a part of the first thin film transistors is formed. Configure first A source electrode and a second source electrode that branches to the second sub-pixel side and constitutes a part of each second thin film transistor, and each gate line is opened at a branch portion of each source line. Thin film transistor substrate manufacturing process, a counter substrate manufacturing process for manufacturing a counter substrate having a common electrode, a thin film transistor substrate manufactured in the thin film transistor substrate manufacturing process, and a counter substrate manufactured in the counter substrate manufacturing process In each pixel of the bonded body manufacturing process which manufactures a bonded body by bonding a board | substrate through a liquid crystal layer, and the said bonded body manufacturing process, said 1st source electrode or 2nd source electrode, In the defect detection step of detecting a short-circuit defect short-circuited with the common electrode, and the pixel in which the short-circuit defect is detected in the defect detection step, By irradiating a laser beam through the opening of each gate line, the shorted first source electrode or second source electrode is cut and the corresponding first thin film transistor or second thin film transistor is converted into the thin film transistor. And a defect correcting step for separating from the connected source line.
上記の方法によれば、薄膜トランジスタ基板作製工程で作製された薄膜トランジスタ基板では、各画素において、各ソース線が各ゲート線に沿って単一に引き出された後に第１副画素側に分岐した第１ソース電極と、第２副画素側に分岐した第２ソース電極とを備え、各ゲート線が各ソース線の分岐した部分、すなわち、第１ソース電極及び第２ソース電極の部分で開口しているので、欠陥検出工程において、貼合体作製工程で作製された貼合体、すなわち、液晶表示パネルの各画素において、薄膜トランジスタ基板側の第１薄膜トランジスタの第１ソース電極、又は第２薄膜トランジスタの第２ソース電極と、対向基板の共通電極との間が短絡した短絡欠陥が検出された場合には、欠陥修正工程において、短絡欠陥が検出された画素において、各ゲート線の開口した部分を介してレーザー光を照射することにより、短絡した第１ソース電極又は第２ソース電極を切断して、対応する第１薄膜トランジスタ又は第２薄膜トランジスタをその薄膜トランジスタが接続されたソース線から分離することになる。これにより、短絡欠陥が検出された画素において、共通電極に入力される信号がソース線に入力されなくなるので、薄膜トランジスタ基板に設けられた各薄膜トランジスタのソース電極と、対向基板の共通電極との間に発生した短絡欠陥が修正される。ここで、欠陥修正工程において、短絡欠陥を修正する際にレーザー光を照射する箇所（第１ソース電極又は第２ソース電極）は、各ソース線の各ゲート線と交差する方向に延びる部分から離間していると共に、ゲート線に重なっていないので、レーザー光の照射による各ソース線及び各ゲート線の損傷が抑制され、例えば、薄膜トランジスタがソース線及びゲート線の交差する部分の近傍に配置された場合よりも短絡欠陥が容易に修正される。したがって、薄膜トランジスタ基板の各薄膜トランジスタのソース電極と、対向基板の共通電極との間に発生した短絡欠陥を可及的に容易に修正することが可能になる。
According to the above method, in the thin film transistor substrate manufactured in the thin film transistor substrate manufacturing process, in each pixel, each source line is drawn out along each gate line and then branched to the first subpixel side. A source electrode and a second source electrode branched to the second subpixel side are provided, and each gate line opens at a branched portion of each source line, that is, a portion of the first source electrode and the second source electrode. Therefore, in the defect detection step, the first source electrode of the first thin film transistor on the thin film transistor substrate side or the second source electrode of the second thin film transistor in each pixel of the liquid crystal display panel in the bonded body manufactured in the bonded body manufacturing step. And a common electrode on the counter substrate are detected, a short-circuit defect is detected. Then, the first source electrode or the second source electrode that is short-circuited is cut by irradiating the laser beam through the opened portion of each gate line, and the corresponding first thin film transistor or second thin film transistor is connected to the thin film transistor. The source line is separated. Thereby, in the pixel in which the short-circuit defect is detected, the signal input to the common electrode is not input to the source line, so that the thin film transistor substrate provided between the source electrode of each thin film transistor and the common electrode of the opposite substrate Any short circuit defects that occur are corrected. Here, in the defect correction step, a portion (first source electrode or second source electrode) irradiated with laser light when correcting a short-circuit defect is separated from a portion extending in a direction intersecting with each gate line of each source line. In addition, since it does not overlap with the gate line, damage to each source line and each gate line due to laser light irradiation is suppressed. For example, a thin film transistor is disposed in the vicinity of a portion where the source line and the gate line intersect. Short circuit defects are more easily corrected than in the case. Therefore, a short-circuit defect that has occurred between the source electrode of each thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate can be corrected as easily as possible.
上記薄膜トランジスタ基板は、上記各画素において、上記各ゲート線が上記各第１薄膜トランジスタの一部を構成する第１ゲート電極と、該第１ゲート電極から離間して上記各第２薄膜トランジスタの一部を構成する第２ゲート電極とを有し、上記欠陥修正工程では、上記短絡した第１ソース電極又は第２ソース電極に対応する上記第１ゲート電極又は第２ゲート電極を該ゲート電極が接続されたゲート線から分離してもよい。
The thin film transistor substrate includes a first gate electrode in which each gate line forms a part of each first thin film transistor in each pixel, and a part of each second thin film transistor separated from the first gate electrode. In the defect correction step, the gate electrode is connected to the first gate electrode or the second gate electrode corresponding to the shorted first source electrode or the second source electrode. It may be separated from the gate line.
上記の方法によれば、欠陥修正工程では、短絡した第１ソース電極又は第２ソース電極に対応する第１ゲート電極又は第２ゲート電極をそのゲート電極が接続されたゲート線から分離するので、短絡欠陥が発生した副画素の薄膜トランジスタと、それに対応するゲート線及びソース線との電気的な接続が解除されることにより、薄膜トランジスタの短絡欠陥に起因する不具合が低減される。
According to the above method, in the defect correction step, the first gate electrode or the second gate electrode corresponding to the shorted first source electrode or the second source electrode is separated from the gate line to which the gate electrode is connected. By disconnecting the electrical connection between the thin film transistor of the sub-pixel in which the short circuit defect has occurred and the corresponding gate line and source line, problems caused by the short circuit defect of the thin film transistor are reduced.
本発明によれば、各画素において、各ソース線が各ゲート線に沿って単一に引き出された後に第１副画素側に分岐した第１ソース電極と、第２副画素側に分岐した第２ソース電極とを備えているので、薄膜トランジスタ基板の各薄膜トランジスタのソース電極と、対向基板の共通電極との間に発生した短絡欠陥を可及的に容易に修正することができる。
According to the present invention, in each pixel, the first source electrode branched to the first subpixel side after each source line is led out along each gate line, and the first source electrode branched to the second subpixel side. Since two source electrodes are provided, a short-circuit defect generated between the source electrode of each thin film transistor of the thin film transistor substrate and the common electrode of the counter substrate can be corrected as easily as possible.
以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、本発明は、以下の各実施形態に限定されるものではない。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.
《発明の実施形態１》
図１～図７は、本発明に係る液晶表示パネル及びその製造方法の実施形態１を示している。具体的に、図１は、本実施形態の液晶表示パネル５０を構成するＴＦＴ基板２０の平面図であり、図２は、図１中の領域Ａを拡大したＴＦＴ基板２０の平面図である。また、図３は、図２中のIII－III線に沿ったＴＦＴ基板２０及びそれを備えた液晶表示パネル５０の断面図である。さらに、図４は、ＴＦＴ基板２０における第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂが形成された領域、すなわち、短絡欠陥を修正する際にレーザー光が照射される領域の近傍を拡大した平面図である。Embodiment 1 of the Invention
1 to 7show Embodiment 1 of a liquid crystal display panel and a method for manufacturing the same according to the present invention. Specifically, FIG. 1 is a plan view of the TFT substrate 20 constituting the liquid crystal display panel 50 of the present embodiment, and FIG. 2 is a plan view of the TFT substrate 20 in which a region A in FIG. 1 is enlarged. 3 is a cross-sectional view of the TFT substrate 20 and the liquid crystal display panel 50 including the same along the line III-III in FIG. Further, FIG. 4 is an enlarged plan view of a region of the TFT substrate 20 where the first TFT 5a and the second TFT 5b are formed, that is, the vicinity of a region irradiated with laser light when correcting a short-circuit defect.
図１～図７は、本発明に係る液晶表示パネル及びその製造方法の実施形態１を示している。具体的に、図１は、本実施形態の液晶表示パネル５０を構成するＴＦＴ基板２０の平面図であり、図２は、図１中の領域Ａを拡大したＴＦＴ基板２０の平面図である。また、図３は、図２中のIII－III線に沿ったＴＦＴ基板２０及びそれを備えた液晶表示パネル５０の断面図である。さらに、図４は、ＴＦＴ基板２０における第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂが形成された領域、すなわち、短絡欠陥を修正する際にレーザー光が照射される領域の近傍を拡大した平面図である。
1 to 7
液晶表示パネル５０は、図３に示すように、互いに対向するように設けられたＴＦＴ基板２０及び対向基板３０と、ＴＦＴ基板２０及び対向基板３０の間に設けられた液晶層４０と、ＴＦＴ基板２０及び対向基板３０を互いに接着すると共に、ＴＦＴ基板２０及び対向基板３０の間に液晶層４０を封入するためのシール材（不図示）とを備えている。ここで、ＴＦＴ基板２０、対向基板３０及びそれらを備えた液晶表示パネル５０では、図１に示すように、各々、図中の縦方向に互いに隣り合うように配置された第１副画素Ｐａ及び第２副画素Ｐｂを有する複数の画素Ｐがマトリクス状に設けられている。
As shown in FIG. 3, the liquid crystal display panel 50 includes a TFT substrate 20 and a counter substrate 30 provided so as to face each other, a liquid crystal layer 40 provided between the TFT substrate 20 and the counter substrate 30, and a TFT substrate. 20 and the counter substrate 30 are bonded to each other, and a sealing material (not shown) for sealing the liquid crystal layer 40 between the TFT substrate 20 and the counter substrate 30 is provided. Here, in the TFT substrate 20, the counter substrate 30, and the liquid crystal display panel 50 including them, as shown in FIG. 1, first sub-pixels Pa and A plurality of pixels P having the second sub-pixel Pb are provided in a matrix.
ＴＦＴ基板２０は、図１～図３に示すように、透明基板１０ａと、各画素Ｐの第１副画素Ｐａ及び第２副画素Ｐｂの間に互いに平行に延びるように透明基板１０ａ上にそれぞれ設けられた複数のゲート線１１ａと、各ゲート線１１ａの延びる方向（図１中の横方向）の各画素Ｐの間に互いに平行に延びるように透明基板１０ａ上にそれぞれ設けられた複数の容量線１１ｂと、各ゲート線１１ａ及び各容量線１１ｂと直交する方向（図１中の縦方向）の各画素Ｐの間に互いに平行に延びるようにそれぞれ設けられた複数の第１ソース線１４ａと、各ゲート線１１ａ及び各容量線１１ｂと直交する方向の各画素Ｐの間に互いに平行に延びると共に、各第１ソース線１４ａと隣り合うようにそれぞれ設けられた複数の第２ソース線１４ｂと、各第１副画素Ｐａ毎にそれぞれ設けられた複数の第１ＴＦＴ５ａと、各第２副画素Ｐｂ毎にそれぞれ設けられた複数の第２ＴＦＴ５ｂと、各第１ＴＦＴ５ａ及び各第２ＴＦＴ５ｂを覆うように設けられた層間絶縁膜１５と、各第１副画素Ｐａにおいて層間絶縁膜１５上にそれぞれ設けられ、各第１ＴＦＴ５ａに接続された複数の第１画素電極１６ａと、各第２副画素Ｐｂにおいて層間絶縁膜１５上にそれぞれ設けられ、各第２ＴＦＴ５ｂに接続された複数の第２画素電極１６ｂと、各第１画素電極１６ａ及び各第２画素電極１６ｂを覆うように設けられた配向膜（不図示）とを備えている。
1 to 3, the TFT substrate 20 is respectively formed on the transparent substrate 10a so as to extend in parallel between the transparent substrate 10a and the first subpixel Pa and the second subpixel Pb of each pixel P. A plurality of capacitors provided on the transparent substrate 10a so as to extend in parallel with each other between the provided gate lines 11a and the pixels P in the extending direction of the gate lines 11a (lateral direction in FIG. 1). A plurality of first source lines 14a provided so as to extend in parallel with each other between the pixels 11 in a direction (vertical direction in FIG. 1) perpendicular to the gate lines 11a and the capacitor lines 11b. A plurality of second source lines 14b that extend in parallel to each other between the pixels P in a direction orthogonal to the gate lines 11a and the capacitor lines 11b and are adjacent to the first source lines 14a, respectively. , Each A plurality of first TFTs 5a provided for each sub-pixel Pa, a plurality of second TFTs 5b provided for each second sub-pixel Pb, and an interlayer insulating film provided so as to cover each first TFT 5a and each second TFT 5b 15 and a plurality of first pixel electrodes 16a provided on the interlayer insulating film 15 in each first subpixel Pa and connected to each first TFT 5a, and on the interlayer insulating film 15 in each second subpixel Pb. A plurality of second pixel electrodes 16b connected to each second TFT 5b, and an alignment film (not shown) provided so as to cover each first pixel electrode 16a and each second pixel electrode 16b. .
容量線１１ｂは、図１に示すように、隣り合う一対のゲート１１ａの間で２列の格子状に設けられている。
As shown in FIG. 1, the capacitor line 11b is provided in a two-row lattice form between a pair of adjacent gates 11a.
第１ＴＦＴ５ａは、図１～図３に示すように、透明基板１０ａ上にゲート線１１ａの一部として設けられた第１ゲート電極１１ａａと、第１ゲート電極１１ａａを覆うように設けられたゲート絶縁膜１２と、ゲート絶縁膜１２上に第１ゲート電極１１ａａに重なるように島状に設けられた第１半導体層１３ａと、第１半導体層１３ａ上に第１ゲート電極１１ａａに重なると共に、互いに離間及び対峙するように設けられた第１ソース電極１４ａｂａ及び第１ドレイン電極１４ｃａとを備えている。
As shown in FIGS. 1 to 3, the first TFT 5a includes a first gate electrode 11aa provided as a part of the gate line 11a on the transparent substrate 10a and a gate insulation provided so as to cover the first gate electrode 11aa. The film 12, the first semiconductor layer 13a provided in an island shape so as to overlap the first gate electrode 11aa on the gate insulating film 12, and the first gate electrode 11aa on the first semiconductor layer 13a and spaced apart from each other And a first source electrode 14aba and a first drain electrode 14ca provided to face each other.
第１ソース電極１４ａｂａは、図１及び図２に示すように、第１ソース線１４ａ又は第２ソース線１４ｂからゲート線１１ａに沿って単一に引き出された後に、第１副画素Ｐａ側にＵ字状に分岐された部分である。ここで、第１ソース線１４ａ又は第２ソース線１４ｂからゲート線１１ａに沿って単一に引き出された部分は、図２に示すように、第１ソース線１４ａ又は第２ソース線１４ｂがゲート線１１ａに沿って延びる引き出し部１４ａｂになっている。
As shown in FIGS. 1 and 2, the first source electrode 14 ab is drawn out from the first source line 14 a or the second source line 14 b along the gate line 11 a, and then on the first subpixel Pa side. It is a portion branched in a U-shape. Here, as shown in FIG. 2, the portion of the first source line 14a or the second source line 14b that is led out along the gate line 11a is gated by the first source line 14a or the second source line 14b. The lead portion 14ab extends along the line 11a.
第１ドレイン電極１４ｃａは、図１に示すように、各第１副画素Ｐａにおいて、その中央を中心に＋字状に延設され、その＋字状に延設された部分の中央で層間絶縁膜１５に形成されたコンタクトホール１５ａを介して第１画素電極１６ａに接続されていると共に、ゲート絶縁膜１２を介して容量線１１ｂに重なることにより、各第１副画素Ｐａの補助容量を構成している。
As shown in FIG. 1, in each first subpixel Pa, the first drain electrode 14ca is extended in a + -shape around the center thereof, and an interlayer insulation is formed in the center of the portion extended in the + -shape. The auxiliary capacitor of each first subpixel Pa is configured by being connected to the first pixel electrode 16a through the contact hole 15a formed in the film 15 and overlapping the capacitor line 11b through the gate insulating film 12. is doing.
第２ＴＦＴ５ｂは、図１～図３に示すように、透明基板１０ａ上にゲート線１１ａの一部として設けられた第２ゲート電極１１ａｂと、第２ゲート電極１１ａｂを覆うように設けられたゲート絶縁膜１２と、ゲート絶縁膜１２上に第２ゲート電極１１ａｂに重なるように島状に設けられた第２半導体層１３ｂと、第２半導体層１３ｂ上に第２ゲート電極１１ａｂに重なると共に、互いに離間及び対峙するように設けられた第２ソース電極１４ａｂｂ及び第２ドレイン電極１４ｃｂとを備えている。
As shown in FIGS. 1 to 3, the second TFT 5b includes a second gate electrode 11ab provided as a part of the gate line 11a on the transparent substrate 10a and a gate insulation provided so as to cover the second gate electrode 11ab. The film 12, the second semiconductor layer 13b provided in an island shape so as to overlap the second gate electrode 11ab on the gate insulating film 12, and the second gate electrode 11ab overlapped on the second semiconductor layer 13b and separated from each other And a second source electrode 14abb and a second drain electrode 14cb provided to face each other.
第２ソース電極１４ａｂｂは、図１及び図２に示すように、第１ソース線１４ａ又は第２ソース線１４ｂからゲート線１１ａに沿って単一に引き出された後に、第２副画素Ｐａ側にＵ字状に分岐された部分である。ここで、第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂの間は、図２に示すように、引き出し部１４ａｂから第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂに分岐する分岐部１４ａｂｃとなっている。
As shown in FIGS. 1 and 2, the second source electrode 14abb is led out along the gate line 11a from the first source line 14a or the second source line 14b to the second subpixel Pa side. It is a portion branched in a U-shape. Here, between the first source electrode 14 aba and the second source electrode 14 abb, as shown in FIG. 2, there is a branch portion 14 abc that branches from the lead portion 14 ab to the first source electrode 14 aba and the second source electrode 14 abb. .
第２ドレイン電極１４ｃｂは、図１に示すように、各第２副画素Ｐｂにおいて、その中央を中心に＋字状に延設され、その＋字状に延設された部分の中央で層間絶縁膜１５に形成されたコンタクトホール１５ａを介して第２画素電極１６ｂに接続されていると共に、ゲート絶縁膜１２を介して容量線１１ｂに重なることにより、各第２副画素Ｐｂの補助容量を構成している。
As shown in FIG. 1, in each second subpixel Pb, the second drain electrode 14cb extends in a + -shape around the center thereof, and an interlayer insulation is formed in the center of the portion extended in the + -shape. The auxiliary capacitor of each second subpixel Pb is configured by being connected to the second pixel electrode 16b through the contact hole 15a formed in the film 15 and overlapping the capacitor line 11b through the gate insulating film 12. is doing.
第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂは、図１に示すように、ゲート線１１ａと直交する方向（図中の縦方向）に沿って隣り合うもの同士が互いに異なるソース線（第１ソース線１４ａ及び第２ソース線１４ｂ）に接続されており、第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂと第１ソース線１４ａ又は第２ソース線１４ｂとの接続構造が千鳥状に配置されている。すなわち、図１に示すように、図中の右下側の第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂは、図中の中央に延びる第１ソース線１４ａに接続され、それらに図中の縦方向に沿って隣り合う図中の右上側の第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂは、図中の右側に延びる第２ソース線１４ｂに接続され、図中の左下側の第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂは、図中の中央に延びる第２ソース線１４ｂに接続され、それらに図中の縦方向に沿って隣り合う図中の左上側の第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂは、図中の左側に延びる第１ソース線１４ａに接続されている。
As shown in FIG. 1, the first TFT 5a and the second TFT 5b have source lines (first source line 14a and second source different from each other) that are adjacent to each other along a direction orthogonal to the gate line 11a (vertical direction in the drawing). The connection structure of the first TFT 5a and the second TFT 5b and the first source line 14a or the second source line 14b is arranged in a staggered manner. That is, as shown in FIG. 1, the first TFT 5a and the second TFT 5b on the lower right side in the drawing are connected to the first source line 14a extending in the center in the drawing and are adjacent to each other along the vertical direction in the drawing. The first TFT 5a and the second TFT 5b on the upper right side in the drawing are connected to the second source line 14b extending on the right side in the drawing, and the first TFT 5a and the second TFT 5b on the lower left side in the drawing are the second source extending in the center in the drawing. A first TFT 5a and a second TFT 5b on the upper left side in the figure that are connected to the line 14b and are adjacent to each other along the vertical direction in the figure are connected to a first source line 14a that extends to the left side in the figure.
ゲート線１１ａは、図１及び図２に示すように、第１ソース線１４ａ及び第２ソース線１４ｂの分岐した部分（第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂの間の分岐部１４ａｂｃ）と、単一に引き出された部分（引き出し部１４ａｂ）とで開口している。ここで、第１ゲート電極１１ａａ及び第２ゲート電極１１ａｂは、図１及び図２に示すように、ゲート線１１ａの開口した領域を介して互いに離間している。
As shown in FIGS. 1 and 2, the gate line 11a includes a branched portion of the first source line 14a and the second source line 14b (a branched portion 14abc between the first source electrode 14aba and the second source electrode 14abb). , A single lead-out portion (drawing portion 14ab) opens. Here, as shown in FIGS. 1 and 2, the first gate electrode 11aa and the second gate electrode 11ab are separated from each other through the open region of the gate line 11a.
第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂは、図２に示すように、第１半導体層１３ａ及び第２半導体層１３ｂにそれぞれ重ならないように、３μｍ以上に線状に形成された被切断部Ｃをそれぞれ有している。ここで、第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂの近傍の具体的な寸法を例示すると、図４に示すように、Ｄａが１０μｍ程度であり、Ｄｂが１５μｍ程度であり、Ｄｃが６μｍ程度であり、Ｄｄが７μｍ程度であり、Ｄｅが４μｍ程度であり、Ｄｆが７μｍ程度であり、Ｄｇが１０μｍ程度であり、Ｄｈが４．５μｍ程度である。なお、第１副画素Ｐａ及び第２副画素Ｐｂの各大きさは、縦３７５μｍ程度×横２５０μｍ程度である。
As shown in FIG. 2, the first source electrode 14aba and the second source electrode 14abb are to be cut in a line shape of 3 μm or more so as not to overlap the first semiconductor layer 13a and the second semiconductor layer 13b, respectively. Each has C. Here, specific dimensions in the vicinity of the first TFT 5a and the second TFT 5b are illustrated. As shown in FIG. 4, Da is about 10 μm, Db is about 15 μm, Dc is about 6 μm, and Dd is 7 μm. De is about 4 μm, Df is about 7 μm, Dg is about 10 μm, and Dh is about 4.5 μm. Each size of the first subpixel Pa and the second subpixel Pb is about 375 μm long × about 250 μm wide.
対向基板３０は、図３に示すように、透明基板１０ｂと、透明基板１０ｂ上に枠状に且つその枠内に格子状に設けられたブラックマトリクス２１と、ブラックマトリクス２１の各格子間にそれぞれ設けられた赤色層、緑色層及び青色層などの複数の着色層（不図示）と、ブラックマトリクス２１及び各着色層を覆うように設けられた共通電極２２と、共通電極２２上に柱状に設けられた複数のフォトスペーサ（不図示）と、共通電極及び各フォトスペーサを覆うように設けられた配向膜（不図示）とを備えている。
As shown in FIG. 3, the counter substrate 30 includes a transparent substrate 10 b, a black matrix 21 provided in a frame shape on the transparent substrate 10 b and in a lattice shape in the frame, and between the lattices of the black matrix 21. A plurality of colored layers (not shown) such as a red layer, a green layer and a blue layer provided, a common electrode 22 provided so as to cover the black matrix 21 and each colored layer, and a columnar shape provided on the common electrode 22 And a plurality of photo spacers (not shown) and an alignment film (not shown) provided so as to cover the common electrode and each photo spacer.
液晶層４０は、電気光学特性を有するネマチックの液晶材料などにより構成され、負の誘電率異方性（Δε＜０）の液晶分子を含んでいる。
The liquid crystal layer 40 is made of a nematic liquid crystal material having electro-optical characteristics, and includes liquid crystal molecules having negative dielectric anisotropy (Δε <0).
上記構成の液晶表示パネル５０は、ＴＦＴ基板２０上の各第１画素電極１６ａ及び各第２画素電極１６ｂと対向基板３０上の共通電極２２との間に配置する液晶層４０に各画素Ｐ毎に所定の電圧を印加して、液晶層４０の配向状態を変えることにより、各画素Ｐ毎にパネル内を透過する光の透過率を調整して、画像を表示するように構成されている。ここで、液晶表示パネル５０では、各画素Ｐの第１副画素Ｐａ及び第２副画素Ｐｂを個別に駆動させることにより、各画素Ｐの第１副画素Ｐａ及び第２副画素Ｐｂにおける輝度を互いに異ならせるように制御されている。
The liquid crystal display panel 50 having the above-described configuration is provided for each pixel P in the liquid crystal layer 40 disposed between each first pixel electrode 16 a and each second pixel electrode 16 b on the TFT substrate 20 and the common electrode 22 on the counter substrate 30. By applying a predetermined voltage to the liquid crystal layer 40 and changing the alignment state of the liquid crystal layer 40, the transmittance of light transmitted through the panel is adjusted for each pixel P, and an image is displayed. Here, in the liquid crystal display panel 50, the first subpixel Pa and the second subpixel Pb of each pixel P are individually driven, so that the luminance of the first subpixel Pa and the second subpixel Pb of each pixel P is increased. It is controlled to be different from each other.
次に、本実施形態の液晶表示パネル５０を製造する方法について説明する。ここで、図５は、第１ソース電極１４ａｂａ及び共通電極２２の間に短絡欠陥Ｓａが発生した液晶表示パネル５０の断面図である。また、図６は、第１ソース電極１４ａｂａ及び第１ドレイン電極１４ｃａの間に短絡欠陥Ｓｂが発生した液晶表示パネル５０の断面図である。さらに、図７は、本実施形態の液晶表示パネル５０の製造方法を示すＴＦＴ基板２０の平面図である。なお、本実施形態の製造方法は、ＴＦＴ基板作製工程、対向基板作製工程、貼合体作製工程、欠陥検出工程及び欠陥修正工程を備える。
Next, a method for manufacturing the liquid crystal display panel 50 of the present embodiment will be described. Here, FIG. 5 is a cross-sectional view of the liquid crystal display panel 50 in which a short-circuit defect Sa has occurred between the first source electrode 14 aba and the common electrode 22. FIG. 6 is a cross-sectional view of the liquid crystal display panel 50 in which a short-circuit defect Sb has occurred between the first source electrode 14aba and the first drain electrode 14ca. Further, FIG. 7 is a plan view of the TFT substrate 20 showing a method for manufacturing the liquid crystal display panel 50 of the present embodiment. In addition, the manufacturing method of this embodiment includes a TFT substrate manufacturing process, a counter substrate manufacturing process, a bonded body manufacturing process, a defect detection process, and a defect correction process.
＜ＴＦＴ基板作製工程＞
まず、ガラス基板などの透明基板１０ａの基板全体に、例えば、スパッタリング法により、チタン膜（厚さ２５ｎｍ程度）及び銅膜（厚さ４００ｎｍ程度）などを順に成膜して、金属積層膜を形成した後に、その金属積層膜に対して、フォトリソグラフィ、エッチング及びレジストパターンの剥離洗浄を行うことにより、第１ゲート電極１１ａａ及び第２ゲート電極１１ａｂを有するゲート線１１ａ、並びに容量線１１ｂを形成する。 <TFT substrate manufacturing process>
First, a titanium film (thickness of about 25 nm) and a copper film (thickness of about 400 nm) are sequentially formed on the entire substrate of thetransparent substrate 10a such as a glass substrate by, for example, sputtering to form a metal laminated film. After that, the metal laminated film is subjected to photolithography, etching, and resist pattern peeling cleaning to form the gate line 11a having the first gate electrode 11aa and the second gate electrode 11ab, and the capacitor line 11b. .
まず、ガラス基板などの透明基板１０ａの基板全体に、例えば、スパッタリング法により、チタン膜（厚さ２５ｎｍ程度）及び銅膜（厚さ４００ｎｍ程度）などを順に成膜して、金属積層膜を形成した後に、その金属積層膜に対して、フォトリソグラフィ、エッチング及びレジストパターンの剥離洗浄を行うことにより、第１ゲート電極１１ａａ及び第２ゲート電極１１ａｂを有するゲート線１１ａ、並びに容量線１１ｂを形成する。 <TFT substrate manufacturing process>
First, a titanium film (thickness of about 25 nm) and a copper film (thickness of about 400 nm) are sequentially formed on the entire substrate of the
続いて、ゲート線１１ａ及び容量線１１ｂが形成された基板全体に、例えば、プラズマＣＶＤ（Chemical Vapor Deposition）法により、窒化シリコン膜（厚さ４００ｎｍ程度）などを成膜して、ゲート絶縁膜１２を形成する。
Subsequently, a silicon nitride film (having a thickness of about 400 nm) or the like is formed on the entire substrate on which the gate lines 11a and the capacitor lines 11b are formed, for example, by plasma CVD (Chemical Vapor Deposition) method. Form.
さらに、ゲート絶縁膜１２が形成された基板全体に、例えば、プラズマＣＶＤ法により、例えば、真性アモルファスシリコン膜（厚さ２００ｎｍ程度）、及びリンがドープされたｎ＋アモルファスシリコン膜（厚さ２０ｎｍ程度）を順に成膜した後に、真性アモルファスシリコン膜及びｎ＋アモルファスシリコン膜の積層膜に対して、フォトリソグラフィ、エッチング及びレジストパターンの剥離洗浄を行うことにより、第１ゲート電極１１ａａ及び第２ゲート電極１１ａｂの上方に島状の第１半導体層形成層（１３ａ）及び第２半導体層形成層（１３ｂ）をそれぞれ形成する。
Further, an intrinsic amorphous silicon film (thickness of about 200 nm) and phosphorus-doped n + amorphous silicon film (thickness of about 20 nm) are formed on the entire substrate on which the gate insulating film 12 is formed, for example, by plasma CVD. Are sequentially formed, and then the first and second gate electrodes 11aa and 11ab are removed by performing photolithography, etching, and resist pattern peeling cleaning on the intrinsic amorphous silicon film and the n + amorphous silicon film. An island-shaped first semiconductor layer forming layer (13a) and a second semiconductor layer forming layer (13b) are formed above.
続いて、上記第１半導体層形成層（１３ａ）及び第２半導体層形成層（１３ｂ）が形成された基板全体に、例えば、スパッタリング法により、チタン膜（厚さ３０ｎｍ程度）及び銅膜（厚さ４００ｎｍ程度）などを順に成膜して、金属積層膜を形成した後に、その金属積層膜に対して、フォトリソグラフィ、エッチング及びレジストパターンの剥離洗浄を行うことにより、第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂを有する第１ソース線１４ａ、第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂを有する第２ソース線１４ｂ、第１ドレイン電極１４ｃａ、並びに第２ドレイン電極１４ｃｂを形成する。
Subsequently, a titanium film (thickness of about 30 nm) and a copper film (thickness) are formed on the entire substrate on which the first semiconductor layer formation layer (13a) and the second semiconductor layer formation layer (13b) are formed, for example, by sputtering. Are formed in order, and a metal laminated film is formed, and then the metal laminated film is subjected to photolithography, etching, and resist pattern peeling cleaning, whereby the first source electrode 14aba and the first A first source line 14a having two source electrodes 14abb, a second source line 14b having first and second source electrodes 14abb, 14abb, a first drain electrode 14ca, and a second drain electrode 14cb are formed.
そして、第１ソース電極１４ａｂａ及び第１ドレイン電極１４ｃａ、並びに第２ソース電極１４ａｂｂ及び第２ドレイン電極１４ｃｂをマスクとして、上記第１半導体層形成層（１３ａ）及び第２半導体層形成層（１３ｂ）のｎ＋アモルファスシリコン層をエッチングで除去することにより、第１半導体層１３ａ及びそれを備えた第１ＴＦＴ５ａ、並びに第２半導体層１３ｂ及びそれを備えた第２ＴＦＴ５ｂを形成する。
Then, using the first source electrode 14aba and the first drain electrode 14ca, and the second source electrode 14abb and the second drain electrode 14cb as a mask, the first semiconductor layer formation layer (13a) and the second semiconductor layer formation layer (13b). By removing the n + amorphous silicon layer by etching, the first semiconductor layer 13a and the first TFT 5a including the first semiconductor layer 13a, and the second semiconductor layer 13b and the second TFT 5b including the first semiconductor layer 13b are formed.
さらに、第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂが形成された基板全体に、例えば、プラズマＣＶＤ法により、窒化シリコン膜（厚さ２００ｎｍ程度）などを成膜し、無機絶縁膜を形成する。
Furthermore, a silicon nitride film (thickness of about 200 nm) or the like is formed on the entire substrate on which the first TFT 5a and the second TFT 5b are formed by, for example, a plasma CVD method to form an inorganic insulating film.
続いて、上記無機絶縁膜が形成された基板全体に、例えば、スピンコート法又はスリットコート法により、アクリル系の感光性樹脂膜を塗布し、その塗布された感光性樹脂膜に対して、露光、現像及びベーキングを行うことにより、第１ドレイン電極１４ｃａ及び第２ドレイン電極１４ｃｂの上方にコンタクトホール１５ａの一部となる開口部を有する有機絶縁膜（厚さ２５００ｎｍ程度）を形成する。
Subsequently, an acrylic photosensitive resin film is applied to the entire substrate on which the inorganic insulating film has been formed, for example, by a spin coating method or a slit coating method, and the applied photosensitive resin film is exposed to light. Then, by performing development and baking, an organic insulating film (thickness of about 2500 nm) having an opening serving as a part of the contact hole 15a is formed above the first drain electrode 14ca and the second drain electrode 14cb.
さらに、上記有機絶縁膜の開口部から露出する上記無機絶縁膜をエッチングで除去して、コンタクトホール１５ａを形成することにより、無機絶縁膜及び有機絶縁膜の積層膜からなる層間絶縁膜１５を形成する。
Further, the inorganic insulating film exposed from the opening of the organic insulating film is removed by etching to form a contact hole 15a, thereby forming an interlayer insulating film 15 composed of a laminated film of the inorganic insulating film and the organic insulating film. To do.
そして、層間絶縁膜１５が形成された基板全体に、例えば、スパッタリング法により、ＩＴＯ（Indium Tin Oxide）膜（厚さ１００ｎｍ程度）などの透明導電膜を成膜した後に、その透明導電膜に対して、フォトリソグラフィ、エッチング及びレジストパターンの剥離洗浄を行うことにより、第１画素電極１６ａ及び第２画素電極１６ｂを形成する。
Then, after a transparent conductive film such as an ITO (Indium Tin Oxide) film (thickness of about 100 nm) is formed on the entire substrate on which the interlayer insulating film 15 has been formed, for example, by sputtering, Then, the first pixel electrode 16a and the second pixel electrode 16b are formed by performing photolithography, etching, and resist pattern peeling and cleaning.
最後に、第１画素電極１６ａ及び第２画素電極１６ｂが形成された基板全体に、例えば、スピンコート法又はスリットコート法により、配向膜材料膜を塗布し、その塗布された配向膜材料に対して、露光、現像及びベーキングを行うことにより、配向膜（厚さ１００ｎｍ程度）を形成する。ここで、配向膜材料膜は、例えば、一定時間のＵＶ（ultraviolet）光の照射により側鎖がＵＶ光の照射方向に傾くように構成された高分子有機化合物の薄膜により形成されている。
Finally, an alignment film material film is applied to the entire substrate on which the first pixel electrode 16a and the second pixel electrode 16b are formed by, for example, a spin coating method or a slit coating method, and the applied alignment film material is applied to the alignment film material. Then, an alignment film (having a thickness of about 100 nm) is formed by performing exposure, development, and baking. Here, the alignment film material film is formed of, for example, a thin film of a polymer organic compound configured such that a side chain is inclined in the irradiation direction of UV light by irradiation with UV (ultraviolet) light for a certain period of time.
以上のようにして、ＴＦＴ基板２０を作製することができる。
The TFT substrate 20 can be manufactured as described above.
＜対向基板作製工程＞
まず、ガラス基板などの透明基板１０ｂの基板全体に、例えば、スピンコート法又はスリットコート法により、黒に着色されたアクリル系の感光性樹脂を塗布し、その塗布された感光性樹脂をフォトマスクを介して露光した後に、現像することにより、ブラックマトリクス２１（厚さ２μｍ程度）を形成する。 <Opposite substrate manufacturing process>
First, an acrylic photosensitive resin colored in black is applied to the entire substrate of thetransparent substrate 10b such as a glass substrate by, for example, a spin coating method or a slit coating method, and the applied photosensitive resin is applied to a photomask. The black matrix 21 (thickness of about 2 μm) is formed by developing after exposure through the film.
まず、ガラス基板などの透明基板１０ｂの基板全体に、例えば、スピンコート法又はスリットコート法により、黒に着色されたアクリル系の感光性樹脂を塗布し、その塗布された感光性樹脂をフォトマスクを介して露光した後に、現像することにより、ブラックマトリクス２１（厚さ２μｍ程度）を形成する。 <Opposite substrate manufacturing process>
First, an acrylic photosensitive resin colored in black is applied to the entire substrate of the
続いて、ブラックマトリクス２１が形成された基板上に、例えば、スピンコート法又はスリットコート法により、赤、緑又は青に着色されたアクリル系の感光性樹脂を塗布し、その塗布された感光性樹脂をフォトマスクを介して露光した後に、現像することによりパターニングして、選択した色の着色層（例えば、赤色層）を厚さ２μｍ程度に形成する。さらに、他の２色についても同様な工程を繰り返して、他の２色の着色層（例えば、緑色層及び青色層）を厚さ２μｍ程度に形成する。
Subsequently, an acrylic photosensitive resin colored in red, green or blue is applied to the substrate on which the black matrix 21 is formed by, for example, spin coating or slit coating, and the applied photosensitive property is applied. The resin is exposed through a photomask and then patterned by development to form a colored layer (for example, a red layer) of a selected color with a thickness of about 2 μm. Further, the same process is repeated for the other two colors to form other two colored layers (for example, a green layer and a blue layer) with a thickness of about 2 μm.
その後、上記各着色層が形成された基板上に、例えば、スパッタリング法により、ＩＴＯ膜（厚さ１００ｎｍ程度）を成膜して、共通電極２２を形成する。
Thereafter, an ITO film (thickness of about 100 nm) is formed on the substrate on which each of the colored layers is formed by, for example, a sputtering method to form the common electrode 22.
さらに、共通電極２２が形成された基板全体に、例えば、スピンコート法又はスリットコート法により、感光性のアクリル樹脂などからなる感光性樹脂膜を塗布した後に、その感光性樹脂膜に対して、露光、現像及びベーキングを行うことにより、フォトスペーサ（厚さ１μｍ程度）を形成する。
Furthermore, after applying a photosensitive resin film made of photosensitive acrylic resin or the like to the entire substrate on which the common electrode 22 is formed, for example, by spin coating or slit coating, A photo spacer (thickness of about 1 μm) is formed by performing exposure, development, and baking.
最後に、上記フォトスペーサが形成された基板全体に、例えば、スピンコート法又はスリットコート法により、配向膜材料膜を塗布し、その塗布された配向膜材料に対して、露光、現像及びベーキングを行うことにより、配向膜（厚さ１００ｎｍ程度）を形成する。
Finally, an alignment film material film is applied to the entire substrate on which the photo spacer is formed, for example, by spin coating or slit coating, and the applied alignment film material is exposed, developed and baked. By doing so, an alignment film (thickness of about 100 nm) is formed.
以上のようにして、対向基板３０を作製することができる。
The counter substrate 30 can be manufactured as described above.
＜貼合体作製工程＞
まず、例えば、上記対向基板作製工程で作製された対向基板３０の表面に、ＵＶ硬化及び熱硬化の併用型樹脂などからなるシール材を枠状に印刷した後に、そのシール材の内側に液晶材料を滴下する。 <Bonded body production process>
First, for example, after a seal material made of a UV curing and thermosetting resin or the like is printed in a frame shape on the surface of thecounter substrate 30 manufactured in the counter substrate manufacturing step, a liquid crystal material is placed inside the seal material. Is dripped.
まず、例えば、上記対向基板作製工程で作製された対向基板３０の表面に、ＵＶ硬化及び熱硬化の併用型樹脂などからなるシール材を枠状に印刷した後に、そのシール材の内側に液晶材料を滴下する。 <Bonded body production process>
First, for example, after a seal material made of a UV curing and thermosetting resin or the like is printed in a frame shape on the surface of the
続いて、上記液晶材料が滴下された対向基板３０と、上記ＴＦＴ基板作製工程で作製されたＴＦＴ基板２０とを、減圧下で貼り合わせた後に、その貼り合わせた貼合体を大気圧に開放することにより、その貼合体の表面及び裏面を加圧する。
Subsequently, the counter substrate 30 onto which the liquid crystal material has been dropped and the TFT substrate 20 manufactured in the TFT substrate manufacturing process are bonded together under reduced pressure, and then the bonded bonded body is released to atmospheric pressure. By pressing, the surface and the back surface of the bonded body are pressurized.
さらに、上記貼合体に挟持されたシール材にＵＶ光を照射した後に、その貼合体を加熱することによりシール材を硬化させる。
Furthermore, after irradiating the sealing material sandwiched between the bonded bodies with UV light, the sealing material is cured by heating the bonded body.
最後に、上記シール材を硬化させた貼合体を、例えば、ダイシングにより分断することにより、その不要な部分を除去する。
Finally, the unnecessary part is removed by dividing the bonding body which hardened the above-mentioned sealing material, for example by dicing.
以上のようにして、液晶表示パネル５０（貼合体）を作製することができる。
The liquid crystal display panel 50 (bonding body) can be produced as described above.
＜欠陥検出工程＞
上記貼合体作製工程で作製された液晶表示パネル５０に対して、各ゲート線１１ａ、各容量線１１ｂ、各第１ソース線１４ａ、各第２ソース線１４ｂ及び共通電極２２に所定の検査信号を入力して、点灯検査を行うことにより、例えば、図５に示すように、膜残りなどの導電性を有する異物Ｆを介して、第１ソース電極１４ａｂａと共通電極２２との間が短絡した短絡欠陥Ｓａを検出する。ここで、短絡欠陥Ｓａは、例えば、図６に示すように、第１ソース電極１４ａｂａ及び第１ドレイン電極１４ｃａの間で発生した短絡欠陥Ｓｂを引き起こした異物Ｆが、液晶表示パネルを運搬する際の振動やパネル表面に対する加圧などに起因して移動することにより、発生するものと考えられる。 <Defect detection process>
A predetermined inspection signal is applied to eachgate line 11 a, each capacitance line 11 b, each first source line 14 a, each second source line 14 b, and the common electrode 22 for the liquid crystal display panel 50 manufactured in the bonded body manufacturing process. For example, as shown in FIG. 5, a short circuit in which the first source electrode 14aba and the common electrode 22 are short-circuited through a foreign substance F having conductivity, such as a film residue, by performing a lighting inspection by inputting. The defect Sa is detected. Here, for example, as illustrated in FIG. 6, the short-circuit defect Sa is generated when the foreign matter F that causes the short-circuit defect Sb generated between the first source electrode 14 aba and the first drain electrode 14 ca transports the liquid crystal display panel. It is thought that this occurs due to movement due to vibration of the panel or pressure applied to the panel surface.
上記貼合体作製工程で作製された液晶表示パネル５０に対して、各ゲート線１１ａ、各容量線１１ｂ、各第１ソース線１４ａ、各第２ソース線１４ｂ及び共通電極２２に所定の検査信号を入力して、点灯検査を行うことにより、例えば、図５に示すように、膜残りなどの導電性を有する異物Ｆを介して、第１ソース電極１４ａｂａと共通電極２２との間が短絡した短絡欠陥Ｓａを検出する。ここで、短絡欠陥Ｓａは、例えば、図６に示すように、第１ソース電極１４ａｂａ及び第１ドレイン電極１４ｃａの間で発生した短絡欠陥Ｓｂを引き起こした異物Ｆが、液晶表示パネルを運搬する際の振動やパネル表面に対する加圧などに起因して移動することにより、発生するものと考えられる。 <Defect detection process>
A predetermined inspection signal is applied to each
＜欠陥修正工程＞
上記欠陥検出工程で短絡欠陥Ｓａが検出された場合には、図７に示すように、短絡欠陥Ｓａが検出された第１副画素Ｐにおいて、第１ソース電極１４ａｂａのＲａ部にレーザー光Ｌを照射することにより、第１ソース電極１４ａｂａを被切断部Ｃで切断することにより、第１ソース線１４ａから第１ＴＦＴ５ａを分離する。ここで、レーザー光Ｌは、例えば、ＹＡＧ（Yttrium Aluminium Garnet）レーザーなどを用いて、１μｍ×５μｍ程度のスポットサイズで出力されたものである。その後、第１ＴＦＴ５ａが分離された第１副画素Ｐにおいて、レーザー光の照射により、容量線１１ｂと第１ドレイン電極１４ｃａとを接続することにより、当該第１副画素Ｐａを黒点化する。 <Defect correction process>
When the short-circuit defect Sa is detected in the defect detection step, as shown in FIG. 7, the laser light L is applied to the Ra portion of the first source electrode 14aba in the first subpixel P in which the short-circuit defect Sa has been detected. Thefirst TFT 5a is separated from the first source line 14a by irradiating and cutting the first source electrode 14aba at the cut portion C. Here, the laser light L is output with a spot size of about 1 μm × 5 μm using, for example, a YAG (Yttrium Aluminum Garnet) laser. After that, in the first subpixel P from which the first TFT 5a is separated, the capacitance line 11b and the first drain electrode 14ca are connected by laser light irradiation, thereby blackening the first subpixel Pa.
上記欠陥検出工程で短絡欠陥Ｓａが検出された場合には、図７に示すように、短絡欠陥Ｓａが検出された第１副画素Ｐにおいて、第１ソース電極１４ａｂａのＲａ部にレーザー光Ｌを照射することにより、第１ソース電極１４ａｂａを被切断部Ｃで切断することにより、第１ソース線１４ａから第１ＴＦＴ５ａを分離する。ここで、レーザー光Ｌは、例えば、ＹＡＧ（Yttrium Aluminium Garnet）レーザーなどを用いて、１μｍ×５μｍ程度のスポットサイズで出力されたものである。その後、第１ＴＦＴ５ａが分離された第１副画素Ｐにおいて、レーザー光の照射により、容量線１１ｂと第１ドレイン電極１４ｃａとを接続することにより、当該第１副画素Ｐａを黒点化する。 <Defect correction process>
When the short-circuit defect Sa is detected in the defect detection step, as shown in FIG. 7, the laser light L is applied to the Ra portion of the first source electrode 14aba in the first subpixel P in which the short-circuit defect Sa has been detected. The
以上のようにして、本実施形態の短絡欠陥Ｓａが修正された液晶表示パネル５０を製造することができる。
As described above, the liquid crystal display panel 50 in which the short-circuit defect Sa of the present embodiment is corrected can be manufactured.
以上説明したように、本実施形態の液晶表示パネル５０及びその製造方法によれば、ＴＦＴ基板作製工程で作製されたＴＦＴ基板２０では、各画素Ｐにおいて、各第１ソース線１４ａ又は各第２ソース線１４ｂが各ゲート線１１ａに沿って単一に引き出された後に第１副画素Ｐａ側に分岐した第１ソース電極１４ａｂａと、第２副画素Ｐｂ側に分岐した第２ソース電極１４ａｂｂとを備え、各ゲート線１１ａが各第１ソース線１４ａ又は各第２ソース線１４ｂの分岐した部分、すなわち、第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂの部分で開口しているので、欠陥検出工程において、貼合体作製工程で作製された貼合体、すなわち、液晶表示パネル５０の各画素Ｐにおいて、ＴＦＴ基板２０側の第１ＴＦＴ５ａの第１ソース電極１４ａｂａ、又は第２ＴＦＴ５ｂの第２ソース電極１４ａｂｂと、対向基板２０の共通電極２２との間が短絡した短絡欠陥Ｓａが検出された場合には、欠陥修正工程において、短絡欠陥Ｓａが検出された画素Ｐにおいて、各ゲート線１１ａの開口した部分を介してレーザー光Ｌを照射することにより、短絡した第１ソース電極１４ａｂａ又は第２ソース電極１４ａｂｂを切断して、対応する第１ＴＦＴ５ａ又は第２ＴＦＴ５ｂをそのＴＦＴが接続された第１ソース線１４ａ又は第２ソース線１４ｂから分離することになる。これにより、短絡欠陥Ｓａが検出された画素Ｐにおいて、共通電極２２に入力される信号が第１ソース線１４ａ又は第２ソース線１４ｂに入力されなくなるので、ＴＦＴ基板２０に設けられた各ＴＦＴ（第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂ）のソース電極（第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂ）と、対向基板３０の共通電極２２との間に発生した短絡欠陥Ｓａを修正することができる。ここで、欠陥修正工程において、短絡欠陥Ｓａを修正する際にレーザー光Ｌを照射する箇所（第１ソース電極１４ａｂａ又は第２ソース電極１４ａｂｂ）は、各第１ソース線１４ａ又は各第２ソース線１４ｂの各ゲート線１１ａと直交する方向に延びる部分から離間していると共に、ゲート線１１ａに重なっていないので、レーザー光Ｌの照射による各第１ソース線１４ａ又は各第２ソース線１４ｂ及び各ゲート線１１ａの損傷を抑制することができ、例えば、ＴＦＴがソース線及びゲート線の交差する部分の近傍に配置された場合よりも短絡欠陥を容易に修正することができる。したがって、ＴＦＴ基板２０に設けられた各ＴＦＴ（第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂ）のソース電極（第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂ）と、対向基板３０の共通電極２２との間に発生した短絡欠陥Ｓａを可及的に容易に修正することができる。
As described above, according to the liquid crystal display panel 50 of the present embodiment and the manufacturing method thereof, in the TFT substrate 20 manufactured in the TFT substrate manufacturing process, in each pixel P, each first source line 14a or each second source line 14a. A first source electrode 14ab branched to the first subpixel Pa side after the source line 14b is drawn out singly along each gate line 11a, and a second source electrode 14abb branched to the second subpixel Pb side. And each gate line 11a is opened at a branched portion of each first source line 14a or each second source line 14b, that is, a portion of the first source electrode 14aba and the second source electrode 14abb. The first source of the first TFT 5a on the TFT substrate 20 side in each pixel P of the liquid crystal display panel 50 in the bonded body manufactured in the bonded body manufacturing step When a short-circuit defect Sa in which the electrode 14aba or the second source electrode 14abb of the second TFT 5b and the common electrode 22 of the counter substrate 20 are short-circuited is detected, the short-circuit defect Sa is detected in the defect correction process. In the pixel P, the first source electrode 14 aba or the second source electrode 14 abb that is short-circuited is cut by irradiating the laser beam L through the opened portion of each gate line 11 a, and the corresponding first TFT 5 a or second TFT 5 b is changed. The TFT is separated from the first source line 14a or the second source line 14b to which the TFT is connected. Thereby, in the pixel P in which the short-circuit defect Sa is detected, the signal input to the common electrode 22 is not input to the first source line 14a or the second source line 14b, so that each TFT ( The short-circuit defect Sa generated between the source electrode (first source electrode 14aba and second source electrode 14abb) of the first TFT 5a and the second TFT 5b) and the common electrode 22 of the counter substrate 30 can be corrected. Here, in the defect correction step, the portion (first source electrode 14 aba or second source electrode 14 abb) irradiated with the laser beam L when correcting the short-circuit defect Sa is the first source line 14 a or the second source line. 14b is separated from the portion extending in the direction orthogonal to each gate line 11a and does not overlap with the gate line 11a. Therefore, each first source line 14a or each second source line 14b by irradiation with the laser beam L and each The damage of the gate line 11a can be suppressed, and for example, the short-circuit defect can be corrected more easily than when the TFT is arranged in the vicinity of the portion where the source line and the gate line intersect. Therefore, a short circuit generated between the source electrode (first source electrode 14 aba and second source electrode 14 abb) of each TFT (first TFT 5 a and second TFT 5 b) provided on the TFT substrate 20 and the common electrode 22 of the counter substrate 30. The defect Sa can be corrected as easily as possible.
また、本実施形態の液晶表示パネル５０によれば、各ゲート線１１ａが各第１ソース線１４ａ又は各第２ソース線１４ｂの単一に引き出された部分で開口しているので、各ゲート線１１ａと各第１ソース線１４ａ及び各第２ソース線１４ｂとの重なる面積を抑制することができ、各ゲート線１１ａと各第１ソース線１４ａ及び各第２ソース線１４ｂとの交差部分に形成される寄生容量を小さくすることができる。
In addition, according to the liquid crystal display panel 50 of the present embodiment, each gate line 11a is opened at a single drawn portion of each first source line 14a or each second source line 14b. 11a and the area where each first source line 14a and each second source line 14b overlap can be suppressed and formed at the intersection of each gate line 11a and each first source line 14a and each second source line 14b. Parasitic capacitance can be reduced.
また、本実施形態の液晶表示パネル５０によれば、第１ソース電極１４ａｂａが第１半導体層１３ａに重ならないように３μｍ以上の線状に形成された被切断部Ｃを有し、第２ソース電極１４ａｂｂが第２半導体層１３ｂに重ならないように３μｍ以上の線状に形成された被切断部Ｃを有しているので、短絡欠陥Ｓａを修正する際には、各被切断部Ｃにレーザー光Ｌを照射することにより、短絡した第１ソース電極１４ａｂａ又は第２ソース電極１４ａｂｂを確実に切断することができる。
Further, according to the liquid crystal display panel 50 of the present embodiment, the first source electrode 14aba has the cut portion C formed in a line shape of 3 μm or more so as not to overlap the first semiconductor layer 13a, and the second source Since the electrode 14abb has the cut portions C formed in a linear shape of 3 μm or more so as not to overlap the second semiconductor layer 13b, a laser is applied to each cut portion C when correcting the short-circuit defect Sa. By irradiating the light L, the short-circuited first source electrode 14aba or second source electrode 14abb can be reliably cut.
また、本実施形態の液晶表示パネル５０によれば、各第１ＴＦＴ５ａ及び各第２ＴＦＴ５ｂが画素Ｐを介して隣り合う第１ソース線１４ａ及び第２ソース線１４ｂの中間部分に設けられているので、短絡欠陥Ｓａを修正する際にレーザー光Ｌを照射する箇所（第１ソース電極１４ａｂａ又は第２ソース電極１４ａｂｂ）を、各第１ソース線１４ａ又は各第２ソース線１４ｂの各ゲート線１１ａと交差する方向に延びる部分から具体的に離間させることができる。また、液晶分子の配向をピコメートルレベルで精密に制御する光配向技術を適用した液晶表示パネル５０では、各第１副画素Ｐａ及び各第２副画素Ｐｂの中央を中心に＋字状の暗部が形成されるので、その暗部を利用して、各第１ＴＦＴ５ａ及び各第２ＴＦＴ５ｂを始め、容量線１１ｂ、並びに容量線１１ｂに重なる第１ドレイン電極１４ｃａ及び第２ドレイン電極１４ｃｂの各延設部を配置することにより、補助容量の配置に起因する各画素Ｐの開口率の低下を抑制することができる。
Further, according to the liquid crystal display panel 50 of the present embodiment, each first TFT 5a and each second TFT 5b are provided in an intermediate portion between the first source line 14a and the second source line 14b adjacent via the pixel P. A portion (first source electrode 14 aba or second source electrode 14 abb) irradiated with laser light L when correcting the short-circuit defect Sa intersects with each gate line 11 a of each first source line 14 a or each second source line 14 b. It can be specifically spaced from the portion extending in the direction of the movement. Further, in the liquid crystal display panel 50 to which a photo-alignment technique for precisely controlling the alignment of liquid crystal molecules at a picometer level is applied, a + -shaped dark portion is centered on the center of each first subpixel Pa and each second subpixel Pb Therefore, using the dark portion, the first TFT 5a and the second TFT 5b, the capacitor line 11b, and the extended portions of the first drain electrode 14ca and the second drain electrode 14cb overlapping the capacitor line 11b are formed. By disposing, it is possible to suppress a decrease in the aperture ratio of each pixel P due to the disposition of the auxiliary capacitor.
また、本実施形態の液晶表示パネル５０によれば、短絡欠陥Ｓａが修正された画素Ｐでは、第１副画素Ｐａが黒点化するものの、第２副画素Ｐｂが正常に駆動するので、画素Ｐ全体が黒点化する場合よりも表示品位を向上させることができる。
Further, according to the liquid crystal display panel 50 of the present embodiment, in the pixel P in which the short-circuit defect Sa is corrected, the first subpixel Pa becomes a black spot, but the second subpixel Pb is normally driven. The display quality can be improved as compared with the case where the whole is blackened.
《発明の実施形態２》
図８は、本実施形態の液晶表示パネル５０の製造方法を示すＴＦＴ基板２０ａの平面図である。なお、以下の実施形態において、図１～図７と同じ部分については同じ符号を付して、その詳細な説明を省略する。 << Embodiment 2 of the Invention >>
FIG. 8 is a plan view of the TFT substrate 20a showing the method for manufacturing the liquidcrystal display panel 50 of the present embodiment. In the following embodiments, the same parts as those in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof is omitted.
図８は、本実施形態の液晶表示パネル５０の製造方法を示すＴＦＴ基板２０ａの平面図である。なお、以下の実施形態において、図１～図７と同じ部分については同じ符号を付して、その詳細な説明を省略する。 << Embodiment 2 of the Invention >>
FIG. 8 is a plan view of the TFT substrate 20a showing the method for manufacturing the liquid
上記実施形態１では、短絡欠陥Ｓａが検出された画素Ｐに対して、切断用のレーザー光Ｌを１箇所に照射する液晶表示パネル５０の製造方法を例示したが、本実施形態では、短絡欠陥Ｓａが検出された画素Ｐに対して、切断用のレーザー光Ｌを３箇所に照射する液晶表示パネル５０の製造方法を例示する。
In the first embodiment, the manufacturing method of the liquid crystal display panel 50 in which the laser beam L for cutting is irradiated to one place with respect to the pixel P in which the short-circuit defect Sa is detected is illustrated. A method of manufacturing the liquid crystal display panel 50 in which the cutting laser beam L is irradiated to three locations on the pixels P where Sa is detected will be exemplified.
具体的には、欠陥修正工程において、欠陥検出工程で短絡欠陥Ｓａが検出された場合には、図８に示すように、短絡欠陥Ｓａが検出された第１副画素Ｐにおいて、第１ソース電極１４ａｂａのＲａ部、並びにゲート線１１ａのＲｂ部及びＲｃ部にレーザー光Ｌをそれぞれ照射することにより、第１ソース電極１４ａｂａを被切断部Ｃで切断すると共に、ゲート線１１ａを第１ゲート電極１１ａａの前側及び後側で切断することにより、第１ソース線１４ａ及びゲート線１１ａから第１ＴＦＴ５ａを分離する。その後、第１ＴＦＴ５ａが分離された第１副画素Ｐにおいて、レーザー光の照射により、容量線１１ｂと第１ドレイン電極１４ｃａとを接続することにより、当該第１副画素Ｐａを黒点化する。これにより、本実施形態の短絡欠陥Ｓａが修正された液晶表示パネル５０を製造することができる。
Specifically, in the defect correction process, when the short circuit defect Sa is detected in the defect detection process, the first source electrode in the first subpixel P in which the short circuit defect Sa is detected as shown in FIG. By irradiating the Ra portion of 14aba and the Rb portion and Rc portion of the gate line 11a with the laser light L, the first source electrode 14aba is cut at the cut portion C, and the gate line 11a is cut into the first gate electrode 11aa. The first TFT 5a is separated from the first source line 14a and the gate line 11a by cutting at the front side and the rear side. After that, in the first subpixel P from which the first TFT 5a is separated, the capacitance line 11b and the first drain electrode 14ca are connected by laser light irradiation, thereby blackening the first subpixel Pa. Thereby, the liquid crystal display panel 50 in which the short-circuit defect Sa of the present embodiment is corrected can be manufactured.
以上説明したように、本実施形態の液晶表示パネル５０及びその製造方法によれば、上記実施形態１と同様に、ＴＦＴ基板作製工程で作製されたＴＦＴ基板２０では、各画素Ｐにおいて、各第１ソース線１４ａ又は各第２ソース線１４ｂが各ゲート線１１ａに沿って単一に引き出された後に第１副画素Ｐａ側に分岐した第１ソース電極１４ａｂａと、第２副画素Ｐｂ側に分岐した第２ソース電極１４ａｂｂとを備え、各ゲート線１１ａが各第１ソース線１４ａ又は各第２ソース線１４ｂの分岐した部分、すなわち、第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂの部分で開口しているので、ＴＦＴ基板２０に設けられた各ＴＦＴ（第１ＴＦＴ５ａ及び第２ＴＦＴ５ｂ）のソース電極（第１ソース電極１４ａｂａ及び第２ソース電極１４ａｂｂ）と、対向基板３０の共通電極２２との間に発生した短絡欠陥Ｓａを可及的に容易に修正することができる。
As described above, according to the liquid crystal display panel 50 and the manufacturing method thereof according to the present embodiment, in the TFT substrate 20 manufactured in the TFT substrate manufacturing process, in each pixel P, as in the first embodiment. 1 source line 14a or each 2nd source line 14b is drawn out along each gate line 11a, and then branches to the 1st subpixel Pa side, and the 1st source electrode 14aba branched to the 2nd subpixel Pb side Second gate electrode 11abb, and each gate line 11a is opened at each first source line 14a or a branched portion of each second source line 14b, that is, at the first source electrode 14abb and the second source electrode 14abb. Therefore, the source electrodes (first source electrode 14aba and second source electrode) of each TFT (first TFT 5a and second TFT 5b) provided on the TFT substrate 20 are provided. And 14abb), it can be as much as possible easily correct the short-circuit defect Sa generated between the common electrode 22 of the counter substrate 30.
また、本実施形態の液晶表示パネル５０の製造方法によれば、欠陥修正工程では、短絡した第１ソース電極１４ａｂａに対応する第１ゲート電極１１ａａをその第１ゲート電極１１ａａが接続されたゲート線１１ａから分離するので、短絡欠陥Ｓａが発生した第１副画素Ｐａの第１ＴＦＴ５ａと、それに対応するゲート線１１ａ及び第１ソース線１４ａとの電気的な接続が解除されることにより、第１ＴＦＴ５ａの短絡欠陥Ｓａに起因する不具合を低減することができる。
Further, according to the method for manufacturing the liquid crystal display panel 50 of the present embodiment, in the defect correcting step, the first gate electrode 11aa corresponding to the shorted first source electrode 14aba is connected to the gate line to which the first gate electrode 11aa is connected. 11a, the electrical connection between the first TFT 5a of the first subpixel Pa in which the short-circuit defect Sa has occurred and the corresponding gate line 11a and first source line 14a is released, so that the first TFT 5a Problems caused by the short-circuit defect Sa can be reduced.
なお、上記各実施形態では、ＴＦＴを備えた液晶表示パネルを例示したが、本発明は、ＴＦＴ以外の３端子のスイッチング素子を備えた液晶表示パネルにも適用することができる。
In each of the above embodiments, a liquid crystal display panel including a TFT has been exemplified. However, the present invention can also be applied to a liquid crystal display panel including a three-terminal switching element other than a TFT.
また、上記各実施形態では、点灯検査後に短絡欠陥を修正する製造方法を例示したが、本発明は、ＴＦＴ基板作製工程で作製されたＴＦＴ基板に対して、電荷検出法などを用いたアレイ検査を行い、ＴＦＴのソース電極及びドレイン電極の間で発生した短絡欠陥を検出した後に、その短絡欠陥を修正することにより、パネル化した後に懸念される各ＴＦＴのソース電極と、対向基板の共通電極との間における短絡欠陥の発生を抑制する製造方法にも適用することができる。
In each of the above embodiments, the manufacturing method for correcting the short-circuit defect after the lighting inspection is exemplified. However, the present invention is applied to the array inspection using the charge detection method for the TFT substrate manufactured in the TFT substrate manufacturing process. After detecting the short-circuit defect generated between the source electrode and the drain electrode of the TFT and correcting the short-circuit defect, the source electrode of each TFT which is concerned after being panelized and the common electrode of the counter substrate It can apply also to the manufacturing method which suppresses generation | occurrence | production of the short circuit defect between.
また、上記各実施形態では、ボトムゲート構造のＴＦＴを備えた液晶表示パネルを例示したが、本発明は、トップゲート構造のＴＦＴを備えた液晶表示パネルにも適用することができる。
In each of the above embodiments, a liquid crystal display panel including a bottom gate TFT has been exemplified. However, the present invention can also be applied to a liquid crystal display panel including a top gate TFT.
また、上記各実施形態では、各画素の間に第１ソース線及び第２ソース線の２本のソース線が設けられたＴＦＴ基板を備えた液晶表示パネルを例示したが、本発明は、各画素の間に１本のソース線が設けられたＴＦＴ基板を備えた液晶表示パネルにも適用することができる。
Further, in each of the above embodiments, the liquid crystal display panel including the TFT substrate in which the two source lines of the first source line and the second source line are provided between the pixels is illustrated. The present invention can also be applied to a liquid crystal display panel including a TFT substrate in which one source line is provided between pixels.
また、上記各実施形態では、画素電極に接続されたＴＦＴの電極をドレイン電極としたＴＦＴ基板を備えた液晶表示パネルを例示したが、本発明は、画素電極に接続されたＴＦＴの電極をソース電極と呼ぶＴＦＴ基板を備えた液晶表示パネルにも適用することができる。
Further, in each of the above embodiments, the liquid crystal display panel including the TFT substrate having the TFT electrode connected to the pixel electrode as the drain electrode has been exemplified. However, in the present invention, the TFT electrode connected to the pixel electrode is used as the source. The present invention can also be applied to a liquid crystal display panel including a TFT substrate called an electrode.
以上説明したように、本発明は、ＴＦＴ基板の各ＴＦＴのソース電極と、対向基板の共通電極との間に発生した短絡欠陥を容易に修正することができるので、液晶表示パネルを備えた液晶テレビなどについて有用である。
As described above, according to the present invention, since a short-circuit defect generated between the source electrode of each TFT of the TFT substrate and the common electrode of the counter substrate can be easily corrected, the liquid crystal provided with the liquid crystal display panel is provided. Useful for TVs.
Ｃ 被切断部
Ｌ レーザー光
Ｐ 画素
Ｐａ 第１副画素
Ｐｂ 第２副画素
Ｓａ 短絡欠陥
５ａ 第１ＴＦＴ
５ｂ 第２ＴＦＴ
１１ａ ゲート線
１１ａａ 第１ゲート電極
１１ａｂ 第２ゲート電極
１３ａ 第１半導体層
１３ｂ 第２半導体層
１４ａ 第１ソース線
１４ａｂ 引き出し部
１４ｂ 第２ソース線
１４ａｂａ 第１ソース電極
１４ａｂｂ 第２ソース電極
１４ａｂｃ 分岐部
２０ ＴＦＴ基板
２２ 共通電極
３０ 対向基板
４０ 液晶層
５０ 液晶表示パネル（貼合体） C Cut-off portion L Laser light P Pixel Pa First sub-pixel Pb Second sub-pixel Sa Short-circuit defect 5a First TFT
5b 2nd TFT
11a gate line 11aa first gate electrode 11absecond gate electrode 13a first semiconductor layer 13b second semiconductor layer 14a first source line 14ab lead-out part 14b second source line 14aba first source electrode 14abb second source electrode 14abc branch part 20 TFT substrate 22 Common electrode 30 Counter substrate 40 Liquid crystal layer 50 Liquid crystal display panel (bonded body)
Ｌ レーザー光
Ｐ 画素
Ｐａ 第１副画素
Ｐｂ 第２副画素
Ｓａ 短絡欠陥
５ａ 第１ＴＦＴ
５ｂ 第２ＴＦＴ
１１ａ ゲート線
１１ａａ 第１ゲート電極
１１ａｂ 第２ゲート電極
１３ａ 第１半導体層
１３ｂ 第２半導体層
１４ａ 第１ソース線
１４ａｂ 引き出し部
１４ｂ 第２ソース線
１４ａｂａ 第１ソース電極
１４ａｂｂ 第２ソース電極
１４ａｂｃ 分岐部
２０ ＴＦＴ基板
２２ 共通電極
３０ 対向基板
４０ 液晶層
５０ 液晶表示パネル（貼合体） C Cut-off portion L Laser light P Pixel Pa First sub-pixel Pb Second sub-pixel Sa Short-
5b 2nd TFT
11a gate line 11aa first gate electrode 11ab
Claims (7)
- 互いに隣り合う第１副画素及び第２副画素を有する画素と、該第１副画素及び第２副画素の間に配置されたゲート線と、該ゲート線と交差する方向の上記画素の縁に沿って配置されたソース線と、上記第１副画素に設けられた第１薄膜トランジスタと、該第１薄膜トランジスタに設けられた第１ソース電極と、上記第２副画素に設けられた第２薄膜トランジスタと、該第２薄膜トランジスタに設けられた第２ソース電極とを備えた薄膜トランジスタ基板と、
上記薄膜トランジスタ基板に対向して設けられ、共通電極を有する対向基板と、
上記薄膜トランジスタ基板及び対向基板の間に設けられた液晶層とを備え、
上記ソース線は、上記ゲート線に沿って延びる引き出し部、及び該引き出し部から上記第１ソース電極と上記第２ソース電極とに分岐する分岐部を有し、
上記ゲート線は、上記分岐部で開口している、液晶表示パネル。 A pixel having a first subpixel and a second subpixel adjacent to each other; a gate line disposed between the first subpixel and the second subpixel; and an edge of the pixel in a direction intersecting the gateline A source line disposed along the first sub-pixel, a first thin film transistor provided in the first sub-pixel, a first source electrode provided in the first thin-film transistor, and a second thin-film transistor provided in the second sub-pixel A thin film transistor substrate comprising a second source electrode provided on the second thin film transistor;
A counter substrate provided facing the thin film transistor substrate and having a common electrode;
A liquid crystal layer provided between the thin film transistor substrate and the counter substrate,
The source line has a lead portion extending along the gate line, and a branch portion branching from the lead portion to the first source electrode and the second source electrode,
The liquid crystal display panel, wherein the gate line is opened at the branch portion. - 各々、互いに隣り合うように配置された第１副画素及び第２副画素を有し、マトリクス状に設けられた複数の画素と、該各画素の第１副画素及び第２副画素の間に、互いに平行に延びるようにそれぞれ設けられた複数のゲート線と、該各ゲート線と交差する方向の該各画素の間に、互いに平行に延びるようにそれぞれ設けられた複数のソース線と、上記各画素の第１副画素毎にそれぞれ設けられた複数の第１薄膜トランジスタと、上記各画素の第２副画素毎にそれぞれ設けられた複数の第２薄膜トランジスタとを備えた薄膜トランジスタ基板と、
上記薄膜トランジスタ基板に対向するように設けられ、共通電極を有する対向基板と、
上記薄膜トランジスタ基板及び対向基板の間に設けられた液晶層とを備え、
上記薄膜トランジスタ基板は、上記各画素において、上記各ソース線が上記各ゲート線に沿って単一に引き出された後に上記第１副画素側に分岐して上記各第１薄膜トランジスタの一部を構成する第１ソース電極と、上記第２副画素側に分岐して上記各第２薄膜トランジスタの一部を構成する第２ソース電極とを有し、
上記各ゲート線は、上記各ソース線の分岐した部分で開口している、液晶表示パネル。 Each has a first subpixel and a second subpixel arranged adjacent to each other, and is provided between a plurality of pixels provided in a matrix and the first subpixel and the second subpixel of each pixel. A plurality of gate lines respectively provided so as to extend in parallel with each other; a plurality of source lines provided so as to extend in parallel with each other between the respective pixels in a direction intersecting with each gate line; A thin film transistor substrate provided with a plurality of first thin film transistors provided for each first sub-pixel of each pixel and a plurality of second thin film transistors provided for each of the second sub-pixels of each pixel;
A counter substrate provided to face the thin film transistor substrate and having a common electrode;
A liquid crystal layer provided between the thin film transistor substrate and the counter substrate,
The thin film transistor substrate forms a part of the first thin film transistor by branching to the first sub-pixel side after the source lines are led out along the gate lines in each pixel. A first source electrode, and a second source electrode that branches to the second subpixel side and forms a part of each of the second thin film transistors,
Each of the gate lines is a liquid crystal display panel opened at a branched portion of each of the source lines. - 上記各ゲート線は、上記各ソース線の単一に引き出された部分で開口している、請求項２に記載の液晶表示パネル。 3. The liquid crystal display panel according to claim 2, wherein each of the gate lines is opened at a single drawn portion of each of the source lines.
- 上記各第１薄膜トランジスタは、島状に設けられた第１半導体層を有し、
上記第１ソース電極は、上記第１半導体層に重ならないように３μｍ以上の線状に形成された被切断部を有し、
上記各第２薄膜トランジスタは、島状に設けられた第２半導体層を有し、
上記第２ソース電極は、上記第２半導体層に重ならないように３μｍ以上の線状に形成された被切断部を有している、請求項２又は３に記載の液晶表示パネル。 Each of the first thin film transistors has a first semiconductor layer provided in an island shape,
The first source electrode has a portion to be cut formed in a linear shape of 3 μm or more so as not to overlap the first semiconductor layer,
Each of the second thin film transistors has a second semiconductor layer provided in an island shape,
4. The liquid crystal display panel according to claim 2, wherein the second source electrode has a portion to be cut formed in a linear shape of 3 μm or more so as not to overlap the second semiconductor layer. 5. - 上記各第１薄膜トランジスタ及び各第２薄膜トランジスタは、上記隣り合う一対のソース線の中間部分に設けられている、請求項２乃至４の何れか１つに記載の液晶表示パネル。 5. The liquid crystal display panel according to claim 2, wherein each of the first thin film transistors and each of the second thin film transistors is provided in an intermediate portion between the pair of adjacent source lines.
- 各々、互いに隣り合うように配置された第１副画素及び第２副画素を有し、マトリクス状に設けられた複数の画素と、該各画素の第１副画素及び第２副画素の間に、互いに平行に延びるようにそれぞれ設けられた複数のゲート線と、該各ゲート線と交差する方向の該各画素の間に、互いに平行に延びるようにそれぞれ設けられた複数のソース線と、上記各画素の第１副画素毎にそれぞれ設けられた複数の第１薄膜トランジスタと、上記各画素の第２副画素毎にそれぞれ設けられた複数の第２薄膜トランジスタとを備え、上記各画素において、上記各ソース線が上記各ゲート線に沿って単一に引き出された後に上記第１副画素側に分岐して上記各第１薄膜トランジスタの一部を構成する第１ソース電極と、上記第２副画素側に分岐して上記各第２薄膜トランジスタの一部を構成する第２ソース電極とを有し、上記各ゲート線が上記各ソース線の分岐した部分で開口した薄膜トランジスタ基板を作製する薄膜トランジスタ基板作製工程と、
共通電極を有する対向基板を作製する対向基板作製工程と、
上記薄膜トランジスタ基板作製工程で作製された薄膜トランジスタ基板、及び上記対向基板作製工程で作製された対向基板を液晶層を介して貼り合わせることにより、貼合体を作製する貼合体作製工程と、
上記貼合体作製工程で作製された貼合体の各画素において、上記第１ソース電極又は第２ソース電極と上記共通電極との間が短絡した短絡欠陥を検出する欠陥検出工程と、
上記欠陥検出工程で短絡欠陥が検出された画素において、上記各ゲート線の開口した部分を介してレーザー光を照射することにより、上記短絡した第１ソース電極又は第２ソース電極を切断して、対応する上記第１薄膜トランジスタ又は第２薄膜トランジスタを該薄膜トランジスタが接続されたソース線から分離する欠陥修正工程とを備える、液晶表示パネルの製造方法。 Each has a first subpixel and a second subpixel arranged adjacent to each other, and is provided between a plurality of pixels provided in a matrix and the first subpixel and the second subpixel of each pixel. A plurality of gate lines respectively provided so as to extend in parallel with each other; a plurality of source lines provided so as to extend in parallel with each other between the respective pixels in a direction intersecting with each gate line; A plurality of first thin film transistors provided for each first sub-pixel of each pixel; and a plurality of second thin film transistors provided for each second sub-pixel of each pixel. A first source electrode that is singly drawn along the gate lines and then branches to the first sub-pixel side to form a part of each first thin film transistor; and a second sub-pixel side Branch to each above And a second source electrode constituting a part of the thin film transistor and the thin film transistor substrate fabricating step of the respective gate lines and a thin film transistor substrate which is open at the branch portion of each source line,
A counter substrate manufacturing step of manufacturing a counter substrate having a common electrode;
A bonded body manufacturing step of manufacturing a bonded body by bonding the thin film transistor substrate manufactured in the thin film transistor substrate manufacturing step and the counter substrate manufactured in the counter substrate manufacturing step through a liquid crystal layer;
In each pixel of the bonded body manufactured in the bonded body manufacturing process, a defect detection process for detecting a short-circuit defect in which the first source electrode or the second source electrode and the common electrode are short-circuited;
In the pixel in which the short-circuit defect is detected in the defect detection step, the first source electrode or the second source electrode that has been short-circuited is cut by irradiating a laser beam through the opened portion of each gate line, And a defect correcting step of separating the corresponding first thin film transistor or second thin film transistor from the source line to which the thin film transistor is connected. - 上記薄膜トランジスタ基板は、上記各画素において、上記各ゲート線が上記各第１薄膜トランジスタの一部を構成する第１ゲート電極と、該第１ゲート電極から離間して上記各第２薄膜トランジスタの一部を構成する第２ゲート電極とを有し、
上記欠陥修正工程では、上記短絡した第１ソース電極又は第２ソース電極に対応する上記第１ゲート電極又は第２ゲート電極を該ゲート電極が接続されたゲート線から分離する、請求項６に記載の液晶表示パネルの製造方法。 The thin film transistor substrate includes a first gate electrode in which each gate line forms a part of each first thin film transistor in each pixel, and a part of each second thin film transistor separated from the first gate electrode. A second gate electrode to be configured;
The said defect correction process isolate | separates the said 1st gate electrode or 2nd gate electrode corresponding to the said shorted 1st source electrode or 2nd source electrode from the gate line to which this gate electrode was connected. Liquid crystal display panel manufacturing method.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004163943A (en) * | 2002-11-14 | 2004-06-10 | Samsung Electronics Co Ltd | Thin-film transistor substrate for liquid crystal display device |
| WO2006064789A1 (en) * | 2004-12-14 | 2006-06-22 | Sharp Kabushiki Kaisha | Liquid crystal display apparatus and defect correction method for liquid crystal display apparatus |
| JP2008089646A (en) * | 2006-09-29 | 2008-04-17 | Sharp Corp | Display device |
| WO2009001578A1 (en) * | 2007-06-28 | 2008-12-31 | Sharp Kabushiki Kaisha | Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device, television receiver, and method of manufacturing liquid crystal panel |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100289538B1 (en) * | 1998-05-20 | 2001-06-01 | 김순택 | Line layout of tft lcd |
| JP3645184B2 (en) * | 2000-05-31 | 2005-05-11 | シャープ株式会社 | Liquid crystal display device and defect correcting method thereof |
| US7206048B2 (en) * | 2003-08-13 | 2007-04-17 | Samsung Electronics Co., Ltd. | Liquid crystal display and panel therefor |
| US7733435B2 (en) * | 2005-05-23 | 2010-06-08 | Sharp Kabushiki Kaisha | Active matrix substrate, display apparatus, and pixel defect correction method |
| US7768604B2 (en) * | 2005-09-20 | 2010-08-03 | Au Optronics Corporation | Transflective liquid crystal display with partially shifted reflectivity curve |
| JP4932823B2 (en) * | 2006-03-06 | 2012-05-16 | シャープ株式会社 | Active matrix substrate, display device, and television receiver |
| TWI364734B (en) | 2006-06-30 | 2012-05-21 | Chimei Innolux Corp | Liquid crystal display panel, driving method and liquid crystal displayer |
| JP4851545B2 (en) * | 2007-02-09 | 2012-01-11 | シャープ株式会社 | Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device, television receiver, active matrix substrate manufacturing method, liquid crystal panel manufacturing method |
| JP2009288462A (en) * | 2008-05-28 | 2009-12-10 | Ips Alpha Technology Ltd | Display device and manufacturing method thereof |
| US8587754B2 (en) * | 2009-06-30 | 2013-11-19 | Samsung Display Co., Ltd. | Liquid crystal display and method of manufacturing the same |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004163943A (en) * | 2002-11-14 | 2004-06-10 | Samsung Electronics Co Ltd | Thin-film transistor substrate for liquid crystal display device |
| WO2006064789A1 (en) * | 2004-12-14 | 2006-06-22 | Sharp Kabushiki Kaisha | Liquid crystal display apparatus and defect correction method for liquid crystal display apparatus |
| JP2008089646A (en) * | 2006-09-29 | 2008-04-17 | Sharp Corp | Display device |
| WO2009001578A1 (en) * | 2007-06-28 | 2008-12-31 | Sharp Kabushiki Kaisha | Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device, television receiver, and method of manufacturing liquid crystal panel |
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