WO2013032280A2

WO2013032280A2 - Substrate for chip packages and method of manufacturing substrate for chip packages

Info

Publication number: WO2013032280A2
Application number: PCT/KR2012/007003
Authority: WO
Inventors: Tea Hyuk Kang; Hong Il Kim
Original assignee: Lg Innotek Co., Ltd.
Priority date: 2011-09-02
Filing date: 2012-08-31
Publication date: 2013-03-07
Also published as: TWI482249B; TW201316467A; WO2013032280A3

Abstract

Provided are a substrate for chip packages and a method of manufacturing the same, the substrate for chip packages, including: a circuit pattern layer which has a bonding area on its one surface and a contact area on its another surface, and is formed of brass; and an insulation layer which is adhered to one surface of the circuit pattern layer. In accordance with the present invention, the circuit pattern layer of the substrate for chip packages is formed of brass, and thus unlike a conventional substrate, in the contact area of the substrate for chip packages, it would be unnecessary to form the plated layer on the circuit pattern layer. Thus, it is advantageous that the production cost for a product of the substrate for chip packages can be reduced.

Description

SUBSTRATE FOR CHIP PACKAGES AND METHOD OF MANUFACTURING SUBSTRATE FOR CHIP PACKAGES

The present invention relates to the technical field of a chip package, more specifically, a technology of manufacturing a substrate for chip packages.

The technologies relating to a semiconductor or an optical device have been steadily developed to meet the requirements for high densification, miniaturization, and high performance. However, because the technologies have relatively fallen behind technologies for manufacturing a semiconductor, attempts have been recently made to settle the requirements for high performance, miniaturization and high densification by the development of technologies relating to packages.

In connection with semiconductor/optical device packages, a silicon chip or an LED (light emitting diode) chip, a smart IC chip and the like are bonded onto a substrate using a wire bonding method or an LOC (lead on chip) bonding method.

FIG. 1 is a view showing a conventional method of manufacturing a substrate for chip packages.

An insulation layer 110 is first prepared (S1). The insulation layer 110 may be formed of an insulation film, for example, a polyimide film. After preparing the insulation layer 110, via holes 112 are formed in the insulation layer 110 (S2).

Subsequently, a metal layer 120 is laminated on the insulation layer 120 (S3). The metal layer 120 may be composed of Cu. Then, a surface of the metal layer is activated through various chemical treatments, a photoresist is then applied thereto, and exposure and development processes are performed. After completing the development process, a necessary circuit is formed by an etching process, and a circuit pattern layer 120 is formed by peeling off the photoresist (S4).

Here, one surface of the circuit pattern layer 120, namely, an upper surface becomes a contact area. Another surface of the circuit pattern layer 120, namely, a lower surface is bonded to a wire for an electrical connection with a chip. Therefore, the surface bonded to the wire of the circuit pattern layer 120 becomes a bonding area.

Accordingly, the substrate for chip packages including the circuit pattern layer having the bonding area on its one surface and the contact area on its another surface, and the insulation layer adhered to the bonding area of the circuit pattern layer may be formed.

Subsequently, the substrate for chip packages may be plated using a predetermined metal material. Specifically, the substrate for chip packages is plated using Ni to form a first plated layer 130 on both surfaces of the substrate for chip package, namely, the bonding area and the contact area (S5). After forming the first plated layer 130 on both surfaces of the substrate for chip packages, a second plated layer 140 is formed on the first plated layer 130 using Au (S6).

Like this, the substrate for chip packages has the first plated layer 130 and the second plated layer 140 on the both surfaces thereof. The lower surface of the substrate for chip packages, namely, the bonding area is not exposed to the outside. However, the upper surface of the substrate for chip packages, namely, the contact area is exposed to the outside, thereby suffering stress such as friction. For this reason, the first and second plated

players

130 and 140 formed on the contact area can be easily peel off.

Furthermore, the first plated layer 130 is formed by Ni plating, and the second plated player 140 is formed by Au plating. Ni and Au have been used as a protective barrier metal against erosion or other chemical attacks as well as a closing material for securing a functional property in semiconductor and chip carrier business circles. That is, the first plated layer 130 and the second plated layer 140 are formed by an electrolytic Ni-Au plating method.

The electrolytic Ni-Au plating has the property of quality which requires erosion resistance, but the cost thereof amounts to more than 30% of the production cost of a product due to an increase in price of Au.

The present invention has been made keeping in mind the above problems, and an aspect of the present invention provides a substrate for smart IC chip packages and a method of manufacturing the same, which reduces a production cost.

According to an aspect of the present invention, there is provided a substrate for chip packages including: a circuit pattern layer which has a bonding area on its one surface and a contact area on its another surface, and is composed of brass; and an insulation layer which is adhered to one surface of the circuit pattern layer.

The brass may be any one of 7-3 brass containing 70% Cu and 30% Zn, and 6-4 brass containing 60% Cu and 40% Zn.

The substrate for chip packages may further include a plated layer formed on the bonding area of the circuit pattern layer.

The plated layer may include: a first plated layer formed on one surface of the circuit pattern layer using Ni; and a second plated layer formed on the first plated layer using Au.

The insulation layer may be formed of polyimide, polyethylene naphthalate, or polyethyleneterephthalate.

The substrate for chip packages may further include a lower adhesive layer which is located between the insulation layer and the circuit pattern layer, and bonds the circuit pattern layer to the insulation layer.

The substrate for chip packages may be configured such that the lower adhesive layer is composed of an adhesive or a bonding sheet.

The substrate for chip packages may further include: a third plated layer formed on another surface of the circuit pattern layer using Ni; and a fourth plated layer formed on the third plated layer using an alloy of Ni and Au.

In the alloy of Ni and Au, a ratio of Au content may be 98%, and a ratio of Co content may be 2%.

In accordance with the present invention, a metal layer which forms the circuit pattern layer of the substrate for chip packages is formed of brass, and thus unlike a conventional substrate, in the contact area of the substrate for chip packages, it would be unnecessary to form the plated layer on the circuit pattern layer. Thus, it is advantageous that the production cost for a product of the substrate for chip packages can be reduced.

Furthermore, in accordance with the present invention, it is advantageous that because adhesive strength between the insulation film and a molding resin at the time of manufacturing the chip package can be improved, reliability and durability of the chip package can be improved.

The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings:

FIG. 1 is a view showing a conventional process of manufacturing a substrate for chip packages.

FIG. 2 and FIG. 3 are process exemplification views roughly illustrating processes for a manufacturing method of a substrate for chip packages according to an exemplary embodiment of the present invention.

FIG. 4 is a view showing a contact surface of a smart IC chip package according to a conventional technology, and a contact surface of a smart IC chip package according to the present invention.

FIG. 5 is a view showing the results of a hardness test concerning a plated layer according to the conventional technology, and a metal layer formed of bass according to the present invention.

Exemplary embodiments according to the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The exemplary embodiments of the present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, when it is determined that specific descriptions regarding publicly known relevant functions or configurations may unnecessarily be beside main points of the present invention, corresponding descriptions are omitted. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification. With regard to the elements which perform similar functions and operations, like numbers refer to like elements through the specification.

Referring to FIG. 2 and FIG. 3, in step S1, a flexible cooper clad laminate (FCCL) film composed of a structure in which an insulation layer, an adhesive layer, and a copper foil layer are sequentially laminated is manufactured.

A detailed explanation about step S1 is as follows. First, an insulation film is prepared. At this time, the insulation film may be formed of a polyimide resin film material or a polyethylene naphthalate resin film material, and preferably a polyimide resin film material, but the materials are not limited to this.

Then, the insulation film becomes an insulation layer 210. An adhesive layer 130 is formed on one surface of the insulation layer 210. At this time, as for a material which forms the adhesive layer 230, the adhesive layer 230 may be formed of a material including at least one of epoxy resin, acrylic resin, and polyimide resin. In particular, the epoxy resin or the polyimide resin may be used. With intent to have flexibility, various natural rubbers, a plasticizer, a hardener, phosphorous flame retardant, and other various additives may be added to the material of forming the adhesive layer. Furthermore, the polyimide resin mainly uses thermal polyimide, but thermal curable polyimide resin may be also used. However, this is only one example. The adhesive layer of the present invention may be formed of all resins having adhesive properties which have been developed and commercialized, or can be implemented according to future technical development.

Then, a copper foil layer 150 is formed by laminating an electrolytic copper foil on the adhesive layer. Thus, the flexible copper foil laminate film 200 is manufactured. At this time, roughness formed on a surface of the electrolytic copper foil is reflected in the adhesive layer 130. Consequently, surface roughness is formed on the adhesive layer 230. At this time, the surface roughness Rz formed on the adhesive layer 230 may be adjusted by adjusting conditions such as a thickness of the electrolytic copper foil, laminating conditions (for example, temperature or pressure), and the like. The surface roughness Rz formed on the adhesive layer may be within a range of 3 to 10 ㎛, but the range is not limited to this. In a case where the roughness Rz is less than 3㎛, it would be difficult to improve adhesive strength with a molding part which will be formed later at the time of manufacturing a complete product. When the roughness Rz is more than 10㎛, it is problematic that grains which form the surface roughness are separated in a powder shape, thereby causing pollution during a manufacturing process relating to the substrate for chip packages.

After manufacturing the flexible copper foil laminate film, as illustrated in FIG. 2-(C), the copper foil layer 150 is removed through an etching process (S2). Like this, when the copper foil layer is removed, constructions composed of the insulation layer, and the adhesive layer, which is formed on the insulation layer, and on which surface roughness 231 is formed, may be obtained. Thus, in the case of applying a molding resin to the insulation layer, thanks to the surface roughness formed on the insulation layer, adhesive strength between the insulation layer and the molding resin can be improved, and reliability and durability can be improved.

After removing the copper foil layer (S2), a lower adhesive layer 210 is formed in a lower part of the insulation layer 210 among the constructions obtained in step S3. Hereinafter, the construction in which the lower adhesive layer, the insulation layer, and the adhesive layer are sequentially laminated is defined as a base substrate 300.

The lower adhesive layer 310 may be formed by a method of performing a laminating process after applying an adhesive or a method of performing the laminating process after attaching a bonding sheet to a lower part of the insulation layer.

In a case where the lower adhesive layer is formed by applying the adhesive to it, like the adhesive layer in step S1, the adhesive layer may be formed of a material including at least one of epoxy resin, acrylic resin, polyimide resin. In particular, it would be preferable to use the epoxy resin or the polyimide resin. With intent to have flexibility, various natural rubbers, a plasticizer, a hardener, phosphorous flame retardant, and other various additives may be added to the material of forming the adhesive layer. Furthermore, as the polyimide resin, thermal polyimide may be mainly used, but thermal curable polyimide resin may be also used.

Then, as illustrated in FIG. 2-(e), one or more via holes are formed in the base substrate 300 (S4). The via holes may include a via hole on which a chip is mounted, a via hole for electrically connecting each layer, a thermal via hole for easily diffusing heat, and a via hole which becomes a basis for aligning each layer. At this time, as for a method of forming the via holes, a punching processing method, a method of carrying out a drill process using a laser, and the like may be used. In addition to this, all methods of forming the via holes, which have been developed and commercialized, or will be implemented according to future technical development may be used.

After the via holes 330 are formed on the base substrate 300, a circuit pattern layer 330 is formed in a lower part of the base substrate 300. At this time, the formation of the circuit pattern layer may be performed as follows.

As illustrated in FIG. 3-(f), a metal layer 410 is first formed in a lower part of the base substrate 300. At this time, the metal layer 410 is formed of brass. The brass is called an alloy which is made by applying Zn to Cu and has golden yellow. The alloy which has been practically used contains 30 to 40% Zn. The alloy containing 30% Zn is called 7-3 brass, and the alloy containing 40% Zn is called 6-4 brass. In other words, 7-3 brass is called brass containing 70% Cu and 30% Zn. 6-4 brass is called brass containing 60% Cu and 40% Zn and has yellow which is near to golden yellow. As the ratio of Zn increases, a color tone becomes light, and as the ratio of Zn reduces, the color tone has red. Generally, as the ratio of Zn increases, hardness also increases, but at the same time, brittleness which is called a fragile property also increases, so more than 45% Zn is not used.

Then, a circuit pattern layer 430 is formed by etching a metal layer 410. More specifically, after a surface of the metal layer is activated through various chemical treatments, a photo resist is then applied thereto, and exposure and development processes are carried out. After completing the development process, a necessary circuit is formed through the etching process, and the circuit pattern layer 430 is formed by peeling off the photoresist.

Here, the circuit pattern layer 430 includes one surface (i.e. a bonding surface or a bonding area) to which a wire for an electrical connection with a chip is bonded, and another surface (i.e. a contact surface or a contact area) opposite to one surface bonded to the insulation layer 210. Here, because the circuit pattern layer 430 is formed by patterning the metal layer 410 composed of brass, the circuit pattern layer 430 shows brightness which is similar to Au. That is, the circuit pattern layer 430 is composed of brass, thereby being capable of omitting a plated layer which is plated on the contact surface of a conventional smart chip package, namely, Ni-Au plated layer.

In addition, the bonding surface of the circuit pattern layer 430 may be plated. Hereinafter, a plating process according to an exemplary embodiment of the present invention will be explained. As previously described, the contact surface of the circuit pattern layer 430 may not be plated. Thus, a mask layer 370 is formed on the contact surface of the circuit pattern layer 430 (S6), and the plated layer 460 may be formed on the bonding surface of the circuit pattern layer 430 by plating the substrate for chip packages(S7). That is, plating is not made on the circuit pattern layer 430 which is masked, but is made only on the bonding surface of the circuit pattern layer 430. The plated layer 460 is configured such that a first plated layer 464 is formed using Ni, and a second plated layer 462 is formed by plating the first plated layer 464 using Au. After the first and second plated

layers

464 and 462 are formed, the mask layer 370 is separated or peeled off from the contact surface of the circuit pattern layer 430.

Alternatively, the plated layer may be formed on the contact surface of the circuit pattern layer 430. Specifically, a third plated layer (not shown) is formed on the contact surface of the circuit pattern layer 430 using Ni. The third plated layer is plated with an alloy of Au and Co to form a fourth plated layer (not shown). Here, because the fourth plated layer is formed using the alloy of Au and Co, hardness of the fourth plated layer is improved. For example, when the fourth plated layer is formed using Au according to a conventional prior, the fourth plated layer shows hardness of 180 to 200 HV. In the alloy of Au and Co, it would be preferable that the Au content shows 98%, and the Co content shows2%. However, the present invention is not limited to this, all contents which would be obvious to those having ordinary skill in the art may be used. FIG. 4 is a view showing a contact surface of a smart IC chip package according to a conventional technology, and a contact surface of a smart IC chip package according to the present invention. As illustrated in FIG. 3, in the conventional smart IC chip package, in the contact area, the circuit pattern layer 120 formed of Cu is formed on the insulation layer 110, and thereafter the plated layer including an Ni layer 130 and an Au layer 140 is formed on the circuit pattern layer 120. On the contrary, in the smart IC chip package according to the present invention, in the contact area, the circuit pattern layer 430 is composed of brass, so even if a separate plated layer is not formed, a gloss which is similar to the Au layer of the existing plated layer shows. Accordingly, it is advantageous that the smart IC chip package according to the present invention is not required to form a separate plated layer on the circuit pattern layer 430 in the contact area.

In addition, to bond a wire for electrically connecting an IC chip which will be mounted later and the circuit pattern layer 430 to the bonding surface of the circuit pattern layer 430, the plated layer 460 is formed to be identical with the existing smart IC chip package. The plated layer 460 includes the Ni layer 462 formed on the bonding surface of the circuit pattern layer 430 to be similar to the existing plated layer, and the Au layer formed on the Ni layer 462. In other words, the wire is not directly bonded to the surface of the circuit pattern layer 430 made of brass. Accordingly, to bond the wire, the plated layer 460 is formed on the bonding surface of the circuit pattern layer 430 to be similar to the existing smart IC chip package.

The metal layer or circuit pattern layer 430 according to the present invention shows surface resistivity as shown in the following Table 1.

Table 1

Material of Plated Layer	Ni/Au (Conventional Art)	Brass (the Present Invention)
Unit [ohm/sq]	0.00077	0.00134

As shown in Table 1 above, the plated layer according to the conventional art shows surface resistivity of 0.00077 ohm/sq. The metal player made of brass according to the present invention shows surface resistivity of 0.00134 ohm/sq. As shown in Table 1 above, as for the brass, there are 7-3 brass containing 70% Cu and 30% Zn, and 6-4 brass containing 60% Cu and 40% Zn. As a result of measuring their surface resistivity, it was measured in the same level as the existing Ni and Au plating.

Furthermore, the brass layer according to the present invention shows the results of a scratch test as shown in FIG.4. FIG. 5 is a view showing the results of a hardness test concerning a plated layer according to the conventional technology, and a metal layer formed of bass according to the present invention. In FIG. 5, (a) shows the results of a hardness test concerning the plated layer according to the conventional technology. Furthermore, in FIG. 5, (b) shows the results of a hardness test concerning the metal layer formed of bass according to the present invention.

The hardness was measured using a thin film scratch tester (i.e. Multi- Scratch Test & Friction Coefficient Tester under Model No. UNMT-2M manufactured by Center for Tribology) at a velocity of 0.05mm/sec, by giving three changes in load in a range of 40g, 60g, and 70g. Here, the surface hardness of the metal layer formed of brass was measured to be excellent up to more than 80% compared to the existing Ni/Au layer.

Furthermore, the substrate for chip packages forms surface roughness on one surface of the insulation layer coated with the molding resin and has improved roughness. Thus, it is advantageous that adhesive strength between the insulation film and the molding resin can be improved, and reliability and durability of the chip package (e.g. a COB type and the like) can be improved. Moreover, in spite of the use of polyimide as the insulation layer, adhesive strength between the insulation film and the molding resin can be improved, and the heat resistance, mechanical properties, electrical characteristics, and flame resistance of a product based on the use of the polyimide can be also improved. Furthermore, as the chip package is manufactured using the flexible copper foil laminate film, the effects such as the light weight, small size, and simplified thin thickness of a product can be additionally achieved.

As previously described, in the detailed description of the invention, having described the detailed exemplary embodiments of the invention, it should be apparent that modifications and variations can be made by persons skilled without deviating from the spirit or scope of the invention. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims and their equivalents.

Claims

A substrate for chip packages, comprising:

a circuit pattern layer which has a bonding area on its one surface and a contact area on its another surface, and is formed of brass; and

an insulation layer which is adhered to one surface of the circuit pattern layer.
The substrate for chip packages of claim 1, wherein the brass is one of 7-3 brass containing 70% Cu and 30% Zn, and 6-4 brass containing 60% Cu and 40% Zn.
The substrate for chip packages of claim 1, further comprising a plated layer formed on the bonding area of the circuit pattern layer.
The substrate for chip packages of claim 3, wherein the plated layer comprises a first plated layer which is formed on one surface of the circuit pattern layer using Ni; and a second plated layer which is formed on the first plated layer using Au.
The substrate for chip packages of claim 1, wherein the insulation layer is formed of polyimide, polyethylene naphthalate, or polyethyleneterephthalate.
The substrate for chip packages of claim 1, further comprising a lower adhesive layer which is located between the insulation layer and the circuit pattern layer, and bonds the circuit pattern layer to the insulation layer.
The substrate for chip packages of claim 1, wherein the lower adhesive layer is composed of an adhesive or a bonding sheet.
The substrate for chip packages of claim 4, further comprising: a third plated layer which is formed on another surface of the circuit pattern layer using Ni; and a fourth plated layer which is formed on the third plated layer using an alloy of Ni and Au.
The substrate for chip packages of claim 8, wherein the alloy of Ni and Au has a ratio of Au content of 98% and a ratio of Co content of 2%.
A method of manufacturing a substrate for chip packages, comprising:

forming via holes in an insulation layer;

forming a metal layer on one surface of the insulation layer using brass;

forming a circuit pattern layer having a bonding area on its one surface and a contact area on its another surface by patterning the metal layer; and

forming a plated layer on one surface of the circuit pattern layer.
The method of claim 10, wherein the brass is one of 7-3 brass containing 70% Cu and 30% Zn, and 6-4 brass containing 60% Cu and 40% Zn.
The method of claim 10, wherein the forming of the plated layer further comprises forming a mask layer on another surface of the circuit pattern layer, and removing the mask layer after the formation of the plated layer.
The method of claim 12, wherein the forming of the plated layer comprises forming a fist plated layer on the one surface of the circuit pattern layer using Ni, and forming a second plated layer on the first plated layer using Au.
The method of claim 10,further comprising forming a lower adhesive layer for bonding the circuit pattern layer to the insulation layer on one surface of the insulation layer before forming the circuit pattern layer.
The method of claim 10, further comprising forming a third plated layer on another surface of the circuit pattern layer using Ni, and forming a fourth plated layer on the third plated layer using an alloy of Ni and Au.