WO2013020269A1 - 移相全桥电路及其控制方法 - Google Patents

移相全桥电路及其控制方法 Download PDF

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Publication number
WO2013020269A1
WO2013020269A1 PCT/CN2011/078150 CN2011078150W WO2013020269A1 WO 2013020269 A1 WO2013020269 A1 WO 2013020269A1 CN 2011078150 W CN2011078150 W CN 2011078150W WO 2013020269 A1 WO2013020269 A1 WO 2013020269A1
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Prior art keywords
mos transistor
mos
transformer
phase
drain
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PCT/CN2011/078150
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English (en)
French (fr)
Inventor
付登萌
韩卫军
孙辉
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联合汽车电子有限公司
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Priority to PCT/CN2011/078150 priority Critical patent/WO2013020269A1/zh
Publication of WO2013020269A1 publication Critical patent/WO2013020269A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/337—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
    • H02M3/3372—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration of the parallel type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a DC/DC (DC-DC converter), and more particularly to a soft switching Phase shift full bridge circuit.
  • the vehicle DC/DC In electric vehicles and hybrid vehicles, the vehicle DC/DC is used to convert the voltage of the high-voltage battery into a low voltage, thereby supplying power to the low-voltage load while charging the low-voltage battery.
  • soft switching technology In order to improve the efficiency of DC/DC, reduce the volume, and reduce the cost, soft switching technology is widely used. Automotive DC/DC usually uses a phase-shifted full-bridge circuit to achieve soft switching.
  • FIG. 1 is an existing phase shift full bridge circuit, including:
  • a leading bridge arm which is composed of MOS tubes Q1 and Q2 connected in series;
  • a lag bridge arm which is composed of MOS tubes Q3 and Q4 connected in series, and the connection node D of the two MOS tubes is connected to one end of the primary side of the transformer TX;
  • the two clamp diodes D1 and D2 are connected in reverse between the connection node A of the MOS transistors Q1 and Q3 and the connection node B of the MOS transistors Q2 and Q4.
  • the connection nodes E and the transformer of the two clamp diodes D1 and D2 are connected.
  • the other end of the TX primary side is connected;
  • a resonant inductor L1 is connected in series between the connection node C of the two MOS transistors Q1 and Q2 and the connection node E;
  • An output circuit is mainly composed of two rectifying MOS tubes Q5, Q6, an output inductor L2 and an output capacitor C; one end of the secondary side of the transformer TX is connected to the rectifying MOS tube Q5 and grounded; the other end of the secondary side of the transformer TX is connected to the rectifying MOS tube Grounding after Q6; the middle tap of the secondary side of the transformer TX (dividing the secondary side of the transformer TX into two coils) is connected in series with the output inductor L2 and the output capacitor C.
  • the input DC voltage Vin is applied between the connection node A and the connection node B, and the output DC voltage Vo is the two ends of the output capacitor C, that is, the load not shown is Parallel to the output capacitor C.
  • phase-shifted full-bridge circuit shown in FIG. 1 The control method of the phase-shifted full-bridge circuit shown in FIG. 1 is as shown in FIG. 2, wherein OA, OB, OC, OD, OE, and OF are the applied gate voltages of the MOS transistors Q1 to Q6, respectively, and V_TX is the transformer TX once. Voltage (primary voltage), I_TX is the primary current of the transformer TX (primary current).
  • the entire phase shift control can be divided into the following stages in one work cycle:
  • Phase 1 OA, OD, and OF are high level, OB, OC, and OE are low level, MOS transistors Q1, Q4, and Q6 are turned on, V_TX is positive, and I_TX is increased;
  • Phase 2 OD goes low, MOS transistor Q4 turns off, the parasitic capacitance between the resonant inductor L1 and the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate.
  • the drain and source of the MOS transistor Q4 The voltage between the two starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q3 starts to drop.
  • V_TX drops and I_TX continues to increase.
  • Phase 3 OC becomes a high level.
  • the MOS transistors Q1 and Q3 are turned on, and the full bridge structure composed of the MOS transistors Q1 to Q4 enters the freewheel mode, and V_TX is zero, and I_TX is decreased.
  • OE becomes a high level, that is, MOS tubes Q5 and Q6 are simultaneously turned on.
  • the time interval between the turn-off of the MOS transistor Q4 and the turn-on of the MOS transistor Q3 is the dead time of the MOS transistors Q3, Q4 (lag bridge arm), which should be carefully selected to make the MOS transistor When Q3 is turned on, its drain-source voltage is zero, thereby achieving zero-voltage turn-on of MOS transistor Q3.
  • This process can be described by the equivalent circuit of phase 2 shown in FIG.
  • capacitors C3 and C4 represent the parasitic capacitance between the drain and source of MOS transistors Q3 and Q4, respectively.
  • the initial values are Vin and 0, respectively;
  • IL1 is the current of resonant inductor L1, and its initial value is greater than zero. Since the input power source Vin will supply energy during the resonance process, the drain-source voltage of the MOS transistor Q4 can reach the input voltage (ie, the drain-source voltage of the MOS transistor Q3 is zero), so the zero voltage of the MOS transistor Q3 is turned on. Always feasible.
  • Phase 4 OA goes low, MOS transistor Q1 turns off, the parasitic capacitance between the resonant inductor L1 and the drain and source of the MOS transistor Q1, and the parasitic capacitance between the drain and source of the Q2 resonate.
  • the drain and source of the MOS transistor Q1 The voltage between the two starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q2 starts to drop.
  • V_TX rises in the opposite direction, and I_TX decreases and reverses.
  • Phase 5 OB goes high. At this time, MOS transistors Q2 and Q3 are turned on, V_TX is negative, and I_TX is increased in reverse. At the same time, OF becomes a low level, and MOS transistor Q6 is turned off.
  • the time interval between the turn-off of the MOS transistor Q1 and the turn-on of the MOS transistor Q2 is the dead time of the MOS transistors Q1, Q2 (leading bridge arm), which should be carefully selected to make the MOS transistor When Q2 is turned on, its drain-source voltage is zero, thereby achieving zero voltage turn-on of MOS transistor Q2.
  • This process can be described by the equivalent circuit of stage 4 shown in FIG.
  • capacitors C1 and C2 represent the parasitic capacitance between the drain and source of MOS transistors Q1 and Q2, respectively.
  • the initial values are 0 and Vin respectively;
  • IL1 is the current of resonant inductor L1, and its initial value is greater than zero.
  • the input power source Vin will absorb energy, so in order to make the drain-source voltage of the MOS transistor Q2 reach zero, the following conditions must be satisfied: L1*(I 0 ) 2 >2*Vin*Q c .
  • Phase 6 OC goes low, MOS transistor Q3 turns off, the parasitic capacitance between the resonant inductor L1 and the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate.
  • the drain and source of the MOS transistor Q3 The voltage between the two starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q4 starts to drop.
  • V_TX drops and I_TX continues to increase. This phase is similar to Phase 2, and the analysis process is no longer exhaustive.
  • Phase 7 OD becomes high level. At this time, MOS transistors Q2 and Q4 are turned on, and the full bridge structure composed of MOS transistors Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is decreased. At the same time, OF becomes a high level, that is, MOS tubes Q5 and Q6 are simultaneously turned on. This phase is similar to Phase 3, and the analysis process is no longer exhaustive.
  • Stage 8 OB becomes low level, MOS transistor Q2 is turned off, the parasitic capacitance between the resonant inductor L1 and the drain and source of the MOS transistor Q1, and the parasitic capacitance between the drain and source of the Q2 resonate, and the drain and source of the MOS transistor Q2
  • the voltage between the two starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q1 starts to drop.
  • V_TX rises in the opposite direction, and I_TX decreases and reverses. This phase is similar to Phase 4, and the analysis process is no longer exhaustive.
  • the resonant inductor L1 in order to make the drain-source voltage zero before the MOS transistors Q1 and Q2 are turned on, the resonant inductor L1 must store sufficient energy before the resonance occurs. This can be achieved by increasing the inductance of the resonant inductor L1 or by increasing the current flowing through the resonant inductor L1.
  • the current flowing through the resonant inductor L1 is determined by the load, which determines that the commonly used phase-shifted full-bridge circuit cannot achieve soft switching within the full load range, that is, phase shifting under light load (small load) conditions.
  • the bridge circuit cannot implement soft switching.
  • the technical problem to be solved by the present invention is to provide a phase shift full bridge circuit control method, which can be Soft switching under light load conditions.
  • the present invention also provides a phase shift full bridge circuit to which the control method is applicable, which can improve the efficiency of the system.
  • the control method of the phase shift full bridge circuit of the present invention divides a duty cycle of the phase shift full bridge circuit into the following 10 stages; Wherein OA, OB, OC, OD, OE, and OF are the applied gate voltages of the MOS transistors Q1 to Q6, respectively, V_TX is the primary voltage of the transformer TX, and I_TX is the primary current of the transformer TX;
  • Phase 1 OA, OD, and OF are high level, OB, OC, and OE are low level, MOS transistors Q1, Q4, and Q6 are turned on, V_TX is positive, and I_TX is increased;
  • Phase 2 OD becomes low level, MOS transistor Q4 is turned off, the leakage inductance between the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate, the MOS transistor Q4
  • the voltage between the drain and the source begins to rise, that is, the voltage between the drain and the source of the MOS transistor Q3 begins to decrease;
  • V_TX decreases, and I_TX continues to increase;
  • Stage 3 OE becomes high level, and MOS tubes Q5 and Q6 are turned on at the same time; at this time, the secondary side (secondary side) of the transformer TX is short-circuited, and I_TX rises rapidly;
  • Phase 4 OC becomes high level. At this time, the MOS transistors Q1 and Q3 are turned on, and the full bridge structure composed of the MOS transistors Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is slowly decreased;
  • Phase 5 OA becomes low level, MOS transistor Q1 is turned off, the leakage inductance of the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q1 and the parasitic capacitance between the drain and source of the Q2 resonate, the MOS transistor
  • the voltage between the drain and source of Q1 begins to rise, that is, the voltage between the drain and source of MOS transistor Q2 begins to decrease;
  • V_TX rises in the reverse direction, and I_TX decreases and reverses;
  • Stage 6 OB becomes high level. At this time, MOS transistors Q2 and Q3 are turned on, V_T is negative, and I_TX is increased in reverse; at the same time OF becomes low level, and MOS transistor Q6 is turned off;
  • Phase 7 OC goes low, MOS transistor Q3 turns off, the leakage inductance between the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate.
  • MOS transistor Q3 The voltage between the drain and the source begins to rise, that is, the voltage between the drain and the source of the MOS transistor Q4 begins to decrease; V_TX decreases, and I_TX continues to increase;
  • Stage 8 OF becomes high level, and MOS tubes Q5 and Q6 are turned on at the same time; at this time, the secondary side of the transformer TX is short-circuited, and I_TX rises rapidly;
  • Stage 9 OD becomes high level. At this time, MOS tubes Q2 and Q4 are turned on, and the full bridge structure composed of MOS tubes Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is slowly decreased;
  • Stage 10 OB becomes low level, MOS transistor Q2 is turned off, the leakage inductance of the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q1 and the parasitic capacitance between the drain and source of the Q2 resonate, the MOS transistor
  • the voltage between the drain and source of Q2 begins to rise, that is, the voltage between the drain and source of MOS transistor Q1 begins to decrease; V_TX rises in the reverse direction, and I_TX decreases and reverses.
  • the MOS transistor may be replaced in whole or in part with an insulated gate bipolar transistor.
  • phase-shifted full-bridge circuit to which the above-described phase-shifting full-bridge circuit control method is applied must satisfy the following two conditions: First, the primary side of the transformer is a full-bridge structure, and the full-bridge structure is composed of 4n MOS tubes, where n For the natural number; second, the secondary side of the transformer is a synchronous rectification structure, that is, both ends of the secondary winding of the transformer are grounded through a MOS tube.
  • the MOS transistor in the circuit may be replaced in whole or in part by an insulated gate bipolar transistor.
  • the control method of the phase shift full bridge circuit of the invention can realize soft switching under light load conditions, and the applicable phase shift full bridge circuit can omit the resonant inductor L1 of the primary side of the transformer TX and the two clamp diodes D1 and D2, thereby reducing System cost, reducing system size.
  • the removed device is also a loss, and can be deleted after deletion. Further improve the efficiency of the system.
  • FIG. 2 is a timing chart of a control method of a conventional phase shift full bridge circuit
  • Figure 3 is an equivalent circuit diagram of stage 2 in Figure 2;
  • Figure 4 is an equivalent circuit diagram of stage 4 of Figure 2;
  • Figure 5 is a phase shift full bridge circuit in which the method of the present invention is particularly applicable
  • FIG. 6 is a timing chart of a phase shift full bridge circuit control method of the present invention.
  • Figure 7 is an equivalent circuit diagram of stage 3 in Figure 6;
  • Figure 8 is an equivalent circuit diagram of stage 5 in Figure 6;
  • FIG. 9 is a schematic diagram showing an implementation environment of a method for controlling a phase-shifted full-bridge circuit of the present invention.
  • Figure 10 is a waveform of the control method of the phase shift full bridge circuit of the present invention in a test environment.
  • Q1 ⁇ Q4 are MOS tubes; Q5 and Q6 are rectifier MOS tubes; L1 is resonant inductors; D1 and D2 are clamp diodes; TX is transformers; L2 is output inductors; C is output capacitors; Vin is DC input voltage; Vo DC output voltage; OA, OB, OC, OD, OE, OF are the applied gate voltages of MOS transistors Q1 ⁇ Q6 respectively; V_TX is the transformer primary voltage; I_TX is the transformer primary current; C1 ⁇ C4 are MOS tube Q1 ⁇ The parasitic capacitance between the source and the drain of Q4; Vc1 to Vc4 are the voltages across the parasitic capacitances C1 to C4; IL1 is the current flowing through the resonant inductor L1; Llk is the leakage inductance of the primary side of the transformer TX; IL is the leakage current The current of Llk is sensed.
  • the control method of the phase-shifted full-bridge circuit provided by the present invention is as shown in FIG. 6.
  • the control method divides one duty cycle of the phase-shifted full-bridge circuit into the following ten stages.
  • OA, OB, OC, OD, OE, and OF are the applied gate voltages of the MOS transistors Q1 to Q6, respectively,
  • V_TX is the primary voltage of the transformer TX, and
  • I_TX is the primary current of the transformer TX.
  • Phase 1 OA, OD, and OF are high level, OB, OC, and OE are low level, MOS transistors Q1, Q4, and Q6 are turned on, V_TX is positive, and I_TX is increased.
  • Phase 2 OD becomes low level, MOS transistor Q4 is turned off, the leakage inductance between the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate, the MOS transistor Q4
  • the voltage between the drain and the source starts to rise, that is, the voltage between the drain and the source of the MOS transistor Q3 starts to drop.
  • V_TX drops and I_TX continues to increase.
  • Phase 3 OE goes high, and MOS transistors Q5 and Q6 are turned on at the same time. This process can be described by the equivalent circuit of stage 3 shown in FIG.
  • capacitors C3 and C4 represent the parasitic capacitance between the drain and source of MOS transistors Q3 and Q4, respectively; Llk represents the leakage inductance of the primary side (primary side) of transformer TX. At this time, the voltage across the capacitor C4 is greater than zero and less than the input voltage Vin, and the secondary side (secondary side) of the transformer TX is short-circuited by the MOS transistors Q5 and Q6, so the leakage current flowing through the primary side of the transformer increases sharply, and at the same time, the capacitor C4 The voltage at the terminal rises rapidly.
  • Phase 4 OC becomes a high level. At this time, the MOS transistors Q1 and Q3 are turned on, and the full bridge structure composed of the MOS transistors Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is slowly decreased.
  • the time interval between the turn-off of the transistor Q4 and the turn-on of the MOS transistor Q3 is the dead time of the MOS transistors Q3, Q4 (lag bridge arm), and the dead time should be carefully
  • the MOS transistor Q3 is turned on, its source-drain voltage is zero, thereby achieving zero voltage turn-on of the MOS transistor Q3.
  • the selection method of the dead time is prior art and will not be described again.
  • Phase 5 OA becomes low level, MOS transistor Q1 is turned off, the leakage inductance of the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q1 and the parasitic capacitance between the drain and source of the Q2 resonate, the MOS transistor
  • the voltage between the drain and source of Q1 begins to rise, that is, the voltage between the drain and source of MOS transistor Q2 begins to decrease.
  • V_TX rises in the opposite direction, and I_TX decreases and reverses.
  • Phase 6 OB becomes high. At this time, MOS transistors Q2 and Q3 are turned on, V_T is negative, and I_TX is inversely increased. At the same time, OF becomes a low level, and MOS transistor Q6 is turned off.
  • the time interval between the turn-off of MOS transistor Q1 and the turn-on of MOS transistor Q2 is the dead time of MOS transistors Q1, Q2 (leading bridge arm), which should be carefully selected to make MOS
  • MOS transistors Q1, Q2 leading bridge arm
  • capacitors C1 and C2 represent the parasitic capacitance of the drain and source of MOS transistors Q1 and Q2, respectively;
  • Llk represents the leakage inductance of the primary side of transformer TX.
  • E lk is the energy stored in the primary leakage inductance Llk of the transformer TX
  • Vin is the input supply voltage
  • Q C is the initial charge of the parasitic capacitance C2 between the drain and source of the MOS transistor Q2.
  • Phase 7 OC goes low, MOS transistor Q3 turns off, the leakage inductance between the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q3, and the parasitic capacitance between the drain and source of the Q4 resonate.
  • MOS transistor Q3 The voltage between the drain and the source begins to rise, that is, the voltage between the drain and the source of the MOS transistor Q4 begins to drop.
  • V_TX drops and I_TX continues to increase. This phase is similar to Phase 2, and the analysis process is no longer exhaustive.
  • Stage 8 OF becomes high level, and MOS transistors Q5 and Q6 are turned on at the same time. This phase is similar to Phase 3, and the analysis process is no longer exhaustive.
  • Stage 9 OD becomes high level. At this time, MOS transistors Q2 and Q4 are turned on, and the full bridge structure composed of MOS tubes Q1 to Q4 enters the freewheel mode, V_TX is zero, and I_TX is slowly decreased. This phase is similar to Phase 4, and the analysis process is no longer exhaustive.
  • Stage 10 OB becomes low level, MOS transistor Q2 is turned off, the leakage inductance of the primary side of the transformer TX and the parasitic capacitance between the drain and source of the MOS transistor Q1 and the parasitic capacitance between the drain and source of the Q2 resonate, the MOS transistor The voltage between the drain and source of Q2 begins to rise, that is, the voltage between the drain and source of MOS transistor Q1 begins to decrease. V_TX rises in the opposite direction, and I_TX decreases and reverses. This phase is similar to Phase 5, and the analysis process is no longer exhaustive.
  • the control method of the phase-shifted full-bridge circuit of the present invention switches the secondary side of the transformer TX through the synchronous rectification control during the process of switching from the energy transfer phase to the freewheeling phase, so that the primary side leakage inductance of the transformer TX is stored.
  • the energy is used to solve the problem that the traditional phase-shifted full-bridge circuit control method cannot realize zero voltage switching due to insufficient resonance energy at light load.
  • phase 2 and phase 3 corresponds to phase 2 of the prior art method shown in FIG. 2; the sum of phase 7 and phase 8 corresponds to FIG. Stage 6 of the existing method shown.
  • the control method of the present invention can be applied to all phase-shifted full-bridge circuits that simultaneously satisfy the following two conditions: First, the primary side of the transformer TX is a full-bridge structure, and the full-bridge structure is composed of 4n MOS tubes, where n is Natural number; (when n ⁇ 2, n MOS transistors are connected in parallel to one primary MOS tube in Fig. 1) Second, the secondary side of the transformer TX is a synchronous rectification structure, that is, both ends of the secondary side winding of the transformer TX Grounded through a MOS tube.
  • phase shift full bridge circuit shown in FIG. 5
  • the most simplified phase-shifted full-bridge circuit corresponding to the control method of the present invention is as shown in FIG. 5, and includes:
  • a lead bridge arm which is composed of a MOS tube Q1 and Q2 connected in series, and a connection node C of the two MOS tubes Q1 and Q2 is connected to one end of the primary side of the transformer TX;
  • a hysteresis bridge arm which is composed of MOS tubes Q3 and Q4 connected in series, and the connection node D of the two MOS tubes Q3 and Q4 is connected to the other end of the primary side of the transformer TX;
  • the input DC voltage Vin is applied between the connection node A of the MOS transistors Q1 and Q3 and the connection node B of the MOS transistors Q2 and Q4;
  • An output circuit is mainly composed of two rectifying MOS tubes Q5, Q6, an output inductor L2 and an output capacitor C; one end of the secondary side of the transformer TX is connected to the rectifying MOS tube Q5 and grounded; the other end of the secondary side of the transformer TX is connected to the rectifying MOS tube Grounding after Q6; the middle tap of the secondary side of the transformer TX (dividing the secondary side of the transformer TX into two coils equally) is connected to the series connected output inductor L2 and the output capacitor C and grounded;
  • the MOS transistors Q1 to Q6 can also be changed to other Switching device, such as IGBT (Insulated Gate Bipolar Transistor), the emitter of the IGBT is equivalent to the source of the MOS transistor, and the collector of the IGBT is equivalent to the drain of the MOS transistor .
  • IGBT Insulated Gate Bipolar Transistor
  • the MOS transistors Q1 to Q6 are both NMOS as an example.
  • the source of the MOS transistor Q1 is connected to the drain of the MOS transistor Q2 as a connection node C.
  • the source of the MOS transistor Q3 is connected to the drain of the MOS transistor Q4 as a connection node D.
  • the drain of the MOS transistor Q1 is connected to the drain of the MOS transistor Q3 as the connection node A.
  • the source of the MOS transistor Q2 is connected to the source of the MOS transistor Q4, and is connected to the node B and grounded.
  • the positive pole of the input DC voltage Vin is connected to the connection node A, and the negative pole is connected to the connection node B.
  • the transformer TX has only one winding on the primary side, and the secondary side of the transformer TX has an intermediate tap that evenly distributes the secondary winding.
  • One end of the secondary side of the transformer TX is connected to the drain of the rectifying MOS transistor Q5, and the other end of the secondary side of the transformer TX is connected to the drain of the rectifying MOS transistor Q6, and the sources of the rectifying MOS transistors Q5 and Q6 are grounded.
  • the tap of the secondary side of the transformer TX is connected to the series output inductor L2 and the output capacitor C and grounded. A load not shown is applied across the output capacitor C, that is, the load is connected in parallel with the output capacitor C.
  • FIG. 9 shows a specific implementation environment of the control method of the present invention, wherein the phase shift control circuit and FIG. 5 It's exactly the same, no longer telling.
  • AUIRS2191 is the driving chip of the primary MOSFET, and provides the external gate voltage for the MOS transistors Q1 ⁇ Q4, thereby controlling the turn-on or turn-off of these MOS transistors
  • UCC27322 is the driving chip of the secondary MOSFET, which is the MOS transistor Q5, Q6 provides an additional gate voltage to control the turn-on or turn-off of these MOS transistors
  • ISO7240 is an isolation chip for isolation of the primary and secondary sides of the transformer
  • UCC28950 is the control chip.
  • Figure 10 is a signal output waveform of the phase shift full bridge circuit of the present invention in the test environment shown in Figure 9.
  • Test conditions DC input voltage is 420V; DC output voltage is 10V; output current is 10A.
  • CH1 represents the primary voltage of the transformer and CH4 represents the primary current of the transformer.
  • CH1 obtained by the test is consistent with the V_TX obtained by the theoretical analysis in Fig. 6.
  • the CH4 obtained by the test is also consistent with the I_TX obtained by the theoretical analysis in Fig. 6.
  • the control method of the phase-shifted full-bridge circuit of the present invention controls the transformer TX through synchronous rectification (ie, both ends of the secondary winding of the transformer are grounded through a MOS tube or IGBT) during the process of switching from the energy transfer phase to the freewheeling phase.
  • the secondary side is short-circuited, so that the transformer TX has a certain amount of energy stored on the primary side leakage, which is used to solve the problem that the zero-voltage switching cannot be realized due to insufficient resonance energy at the light load in the control method of the conventional phase-shifted full-bridge circuit.
  • phase-shifted full-bridge circuit can omit the resonant inductor L1 on the primary side of the transformer TX and the two clamp diodes D1 and D2, thereby reducing system cost and reducing system volume.
  • the removed device is also inherently lossy, so the phase-shifted full-bridge circuit of the present invention can Improve the efficiency of the system.

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Abstract

一种移相全桥电路及其控制方法。该方法将移相全桥电路的一个工作周期分为10个阶段。OA、OB、OC、OD、OE、OF分别为MOS管一至六（Q1〜Q6）的外加栅极电压。该方法将OE、OC同时上升改为先后上升，将OF、OD同时上升改为先后上升，从而使得轻载条件下移相全桥电路实现软开关。在该方法适用的移相全桥电路中，变压器一次侧为全桥结构并且变压器二次侧为同步整流结构。该电路省略变压器一次侧的谐振电感和箝位二极管，从而降低***成本，减小***体积，提高***的效率。

Description

移相全桥电路及其控制方法 Technical Field
本发明涉及一种 DC/DC （直流-直流变换器），特别是涉及一种软开关（soft switching）的 移相全桥电路。
Background Art
在电动汽车、混合动力汽车中，车用DC/DC用于将高压电池的电压转换成低压，从而给低压负载供电，同时给低压电池充电。为了提高DC/DC的效率，减小体积，降低成本，软开关技术被广泛应用。车用DC/DC通常采用移相全桥电路来实现软开关。
请参阅图1，这是一种现有的移相全桥电路，包括：
一变压器TX；
一超前桥臂，由MOS管Q1和Q2串接组成；
一滞后桥臂，由MOS管Q3和Q4串接组成，这两个MOS管的连接节点D与变压器TX一次侧的一端连接；
两箝位二极管D1、D2，反相串接于MOS管Q1和Q3的连接节点A和MOS管Q2和Q4的连接节点B之间，这两个箝位二极管D1和D2的连接节点E与变压器TX一次侧的另一端连接；
一谐振电感L1，串接于两个MOS管Q1和Q2的连接节点C与连接节点E之间；
一输出电路，主要由两整流MOS管Q5、Q6、输出电感L2和输出电容C组成；变压器TX二次侧的一端连接整流MOS管Q5后接地；变压器TX二次侧的另一端连接整流MOS管Q6后接地；变压器TX二次侧的中间抽头（将变压器TX二次侧平均分为两个线圈）串接输出电感L2和输出电容C后接地。
图1所示的移相全桥电路中，输入的直流电压Vin加在连接节点A和连接节点B之间，输出的直流电压Vo为输出电容C的两端，即，未画出的负载是与输出电容C并联的。
图1所示的移相全桥电路的控制方法如图2所示，其中OA、OB、OC、OD、OE、OF分别为MOS管Q1～Q6的外加栅极电压，V_TX为变压器TX的一次电压（原边电压），I_TX为变压器TX的一次电流（原边电流）。在一个工作周期内整个移相控制可以分为如下几个阶段：
阶段1：OA、OD、OF为高电平，OB、OC、OE为低电平，MOS管Q1、Q4、Q6导通，V_TX为正，I_TX增加；
阶段2：OD变为低电平，MOS管Q4关断，谐振电感L1与MOS管Q3漏源极之间的寄生电容、Q4漏源极之间的寄生电容产生谐振，MOS管Q4漏源极之间的电压开始上升，即，MOS管Q3漏源极之间的电压开始下降。V_TX下降，I_TX继续增加。
阶段3：OC变为高电平，此时，MOS管Q1、Q3导通，由MOS管Q1～Q4组成的全桥结构进入续流模式，V_TX为零，I_TX减小。与此同时OE变为高电平，即MOS管Q5、Q6同时导通。
MOS管Q4关断与MOS管Q3导通之间的时间间隔（即阶段2的时间长度）为MOS管Q3、Q4（滞后桥臂）的死区时间，该死区时间应仔细选择以使得MOS管Q3导通时其漏源极电压为零，从而实现MOS管Q3的零电压开通。该过程可通过图3所示的阶段2的等效电路来描述。
图3中电容C3、C4分别代表MOS管Q3、Q4漏源极之间的寄生电容，其初始值分别为Vin和0；IL1为谐振电感L1的电流，其初始值大于0。由于在该谐振过程中输入电源Vin将会提供能量，所以MOS管Q4的漏源极电压一定能达到输入电压（即MOS管Q3的漏源极电压为零），因此MOS管Q3的零电压开通总是可行的。
阶段4：OA变为低电平，MOS管Q1关断，谐振电感L1与MOS管Q1漏源极之间的寄生电容、Q2漏源极之间的寄生电容产生谐振，MOS管Q1漏源极之间的电压开始上升，即，MOS管Q2漏源极之间的电压开始下降。V_TX反向上升，I_TX减小并反向。
阶段5：OB变为高电平，此时，MOS管Q2、Q3导通，V_TX为负，I_TX反向增加。与此同时OF变为低电平，MOS管Q6关断。
MOS管Q1关断与MOS管Q2导通之间的时间间隔（即阶段4的时间长度）为MOS管Q1、Q2（超前桥臂）的死区时间，该死区时间应仔细选择以使得MOS管Q2导通时其漏源极电压为零，从而实现MOS管Q2的零电压开通。该过程可通过图4所示的阶段4的等效电路来描述。
图4中电容C1、C2分别代表MOS管Q1、Q2漏源极之间的寄生电容，其初始值分别为0和Vin；IL1为谐振电感L1的电流，其初始值大于0。在该谐振过程中输入电源Vin将会吸收能量，所以为了使MOS管Q2的漏源极电压能达到零， 以下条件必须满足：L1*(I0)2>2*Vin*Qc。 式中，L1为谐振电感L1的电感量；I0为谐振电感L1的初始电流，Vin为输入电源电压，QC为MOS管Q2漏源极之间的寄生电容C2的初始电荷。
阶段6：OC变为低电平，MOS管Q3关断，谐振电感L1与MOS管Q3漏源极之间的寄生电容、Q4漏源极之间的寄生电容产生谐振，MOS管Q3漏源极之间的电压开始上升，即，MOS管Q4漏源极之间的电压开始下降。V_TX下降，I_TX继续增加。此阶段与阶段2类似，分析过程不再累述。
阶段7：OD变为高电平，此时，MOS管Q2、Q4导通，由MOS管Q1～Q4组成的全桥结构进入续流模式，V_TX为零，I_TX减小。与此同时OF变为高电平，即MOS管Q5、Q6同时导通。此阶段与阶段3类似，分析过程不再累述。
阶段8：OB变为低电平，MOS管Q2关断，谐振电感L1与MOS管Q1漏源极之间的寄生电容、Q2漏源极之间的寄生电容产生谐振，MOS管Q2漏源极之间的电压开始上升，即，MOS管Q1漏源极之间的电压开始下降。V_TX反向上升，I_TX减小并反向。此阶段与阶段4类似，分析过程不再累述。
根据以上分析，为了使MOS管Q1、Q2在导通之前漏源极电压为零，谐振电感L1必须在谐振发生前储存足够的能量。这可以通过增大谐振电感L1的电感量、或增大流过谐振电感L1的电流来实现。然而，流过谐振电感L1的电流是由负载决定的，这就决定了常用的移相全桥电路无法实现全负载范围内的软开关，即，在轻载（小负载）条件下移相全桥电路无法实现软开关。
 Technical Problem
本发明所要解决的技术问题是提供一种移相全桥电路的控制方法，该方法可以在 轻载条件下实现软开关。为此，本发明还要提供所述控制方法适用的移相全桥电路，其能提高***的效率。
Technical Solution
为解决上述技术问题，本发明移相全桥电路的控制方法将移相全桥电路的一个工作周期分为如下10个阶段； 其中OA、OB、OC、OD、OE、OF分别为MOS管Q1～Q6的外加栅极电压，V_TX为变压器TX的一次电压，I_TX为变压器TX的一次电流；
阶段1：OA、OD、OF为高电平，OB、OC、OE为低电平，MOS管Q1、Q4、Q6导通，V_TX为正，I_TX增加；
阶段2：OD变为低电平，MOS管Q4关断，变压器TX原边漏感与MOS管Q3漏源极之间的寄生电容、Q4漏源极之间的寄生电容产生谐振，MOS管Q4漏源极之间的电压开始上升，即，MOS管Q3漏源极之间的电压开始下降；V_TX下降，I_TX继续增加；
阶段3：OE变为高电平，MOS管Q5、Q6同时导通；此时，变压器TX副边（二次侧）短路，I_TX迅速上升；
阶段4：OC变为高电平，此时，MOS管Q1、Q3导通，由MOS管Q1～Q4组成的全桥结构进入续流模式，V_TX为零，I_TX缓慢减小；
阶段5：OA变为低电平，MOS管Q1关断，变压器TX原边的漏感与MOS管Q1漏源极之间的寄生电容、Q2漏源极之间的寄生电容产生谐振，MOS管Q1漏源极之间的电压开始上升，即，MOS管Q2漏源极之间的电压开始下降；V_TX反向上升，I_TX减小并反向；
阶段6：OB变为高电平，此时，MOS管Q2、Q3导通，V_T为负，I_TX反向增加；与此同时OF变为低电平，MOS管Q6关断；
阶段7：OC变为低电平，MOS管Q3关断，变压器TX原边漏感与MOS管Q3漏源极之间的寄生电容、Q4漏源极之间的寄生电容产生谐振，MOS管Q3漏源极之间的电压开始上升，即，MOS管Q4漏源极之间的电压开始下降；V_TX下降，I_TX继续增加；
阶段8：OF变为高电平，MOS管Q5、Q6同时导通；此时，变压器TX副边短路，I_TX迅速上升；
阶段9：OD变为高电平，此时，MOS管Q2、Q4导通，由MOS管Q1～Q4组成的全桥结构进入续流模式，V_TX为零，I_TX缓慢减小；
阶段10：OB变为低电平，MOS管Q2关断，变压器TX原边的漏感与MOS管Q1漏源极之间的寄生电容、Q2漏源极之间的寄生电容产生谐振，MOS管Q2漏源极之间的电压开始上升，即，MOS管Q1漏源极之间的电压开始下降；V_TX反向上升，I_TX减小并反向。
所述控制方法中，MOS管可全部或部分替换为绝缘栅双极型晶体管。
上述移相全桥电路的控制方法适用的移相全桥电路，必须同时满足以下两个条件：其一，变压器的一次侧为全桥结构，该全桥结构为4n个MOS管组成，其中n为自然数；其二，变压器的二次侧为同步整流结构，即变压器的二次侧绕组的两端各通过一个MOS管接地。
所述电路中MOS管可全部或部分替换为绝缘栅双极型晶体管。
 Advantageous Effects
本发明移相全桥电路的控制方法可以在轻载情况下实现软开关，其适用的移相全桥电路可以省略变压器TX一次侧的谐振电感L1及两个箝位二极管D1、D2，从而降低***成本，减小***体积。去除掉的器件原本也是会产生损耗的，删除后可以 进一步提高***的效率。
Description of Drawings
图1是现有的一种移相全桥电路；
图2是现有的移相全桥电路的控制方法的时序图；
图3是图2中阶段2的等效电路图；
图4是图2中阶段4的等效电路图；
图5是本发明所述方法特别适用的一种移相全桥电路；
图6是本发明的移相全桥电路控制方法的时序图；
图7是图6中阶段3的等效电路图；
图8是图6中阶段5的等效电路图；
图9是本发明的移相全桥电路的控制方法的实施环境示意图；
图10是本发明的移相全桥电路的控制方法在测试环境下的波形。
图中附图标记说明：
Q1～Q4均为MOS管；Q5、Q6为整流MOS管；L1为谐振电感；D1、D2为箝位二极管；TX为变压器；L2为输出电感；C为输出电容；Vin为直流输入电压；Vo为直流输出电压；OA、OB、OC、OD、OE、OF分别为MOS管Q1～Q6的外加栅极电压；V_TX为变压器一次电压；I_TX为变压器一次电流；C1～C4分别是MOS管Q1～Q4的源漏极之间的寄生电容；Vc1～Vc4分别是寄生电容C1～C4两端的电压；IL1是流过谐振电感L1的电流；Llk是变压器TX一次侧的漏电感；IL是流过漏电感Llk的电流。
 Best Mode
Mode for Invention
本发明提供的移相全桥电路的控制方法如图6所示，该控制方法将移相全桥电路的一个工作周期分为如下10个阶段。 其中OA、OB、OC、OD、OE、OF分别为MOS管Q1～Q6的外加栅极电压，V_TX为变压器TX的一次电压，I_TX为变压器TX的一次电流。
阶段1：OA、OD、OF为高电平，OB、OC、OE为低电平，MOS管Q1、Q4、Q6导通，V_TX为正，I_TX增加。
阶段2：OD变为低电平，MOS管Q4关断，变压器TX原边漏感与MOS管Q3漏源极之间的寄生电容、Q4漏源极之间的寄生电容产生谐振，MOS管Q4漏源极之间的电压开始上升，即，MOS管Q3漏源极之间的电压开始下降。V_TX下降，I_TX继续增加。
阶段3：OE变为高电平，MOS管Q5、Q6同时导通。该过程可通过图7所示的阶段3的等效电路来描述。
图7中电容C3、C4分别代表MOS管Q3、Q4漏源极之间的寄生电容；Llk代表变压器TX原边（一次侧）的漏电感。此时电容C4两端的电压大于零而小于输入电压Vin，变压器TX副边（二次侧）被MOS管Q5、Q6短路，所以流过变压器原边的漏感的电流急剧增加，同时电容C4两端的电压快速上升。当电容C4两端的电压到达输入电压Vin时，MOS管Q3的体二极管被导通，由MOS管Q1～Q4组成的全桥结构进入续流模式。假设MOS管Q5导通与MOS管Q4关断同时发生，变压器TX原边漏电感在此阶段可吸收的最大能量为：ΔE=Vin*Qc，式中，Vin为输入电源电压，QC为MOS管Q4漏源极之间的寄生电容C4两端电压到达Vin所需电荷。
阶段4：OC变为高电平，此时，MOS管Q1、Q3导通，由MOS管Q1～Q4组成的全桥结构进入续流模式，V_TX为零，I_TX缓慢减小。
MOS 管Q4关断与MOS管Q3导通之间的时间间隔（即，阶段2和阶段3的时间长度之和）为MOS管Q3、Q4（滞后桥臂）的死区时间，该死区时间应仔细选择以使得MOS管Q3导通时其源漏极电压为零，从而实现MOS管Q3的零电压开通。该死区时间的选择方法为现有技术，不再累述。
阶段5：OA变为低电平，MOS管Q1关断，变压器TX原边的漏感与MOS管Q1漏源极之间的寄生电容、Q2漏源极之间的寄生电容产生谐振，MOS管Q1漏源极之间的电压开始上升，即，MOS管Q2漏源极之间的电压开始下降。V_TX反向上升，I_TX减小并反向。
阶段6：OB变为高电平，此时，MOS管Q2、Q3导通，V_T为负，I_TX反向增加。与此同时OF变为低电平，MOS管Q6关断。
MOS管Q1关断与MOS管Q2导通之间的时间间隔（即，阶段5的时间长度）为MOS管Q1、Q2（超前桥臂）的死区时间，该死区时间应仔细选择以使得MOS管Q2导通时其漏源极电压为零，从而实现MOS管Q2的零电压开通。该过程可通过图8所示的阶段5的等效电路来描述。该死区时间的选择方法为现有技术，不再累述。
图8中电容C1、C2分别代表MOS管Q1、Q2漏源极的寄生电容；Llk代表变压器TX原边的漏电感。在该谐振过程中输入电源Vin将会吸收能量，所以为了使MOS管Q2的源极电压能达到零，以下条件必须满足：Elk>Vin*Qc。式中，Elk为变压器TX原边漏电感Llk储存的能量，Vin为输入电源电压，QC为MOS管Q2漏源极之间寄生电容C2的初始电荷。由于该漏电感在续流阶段初始时已经获得了能量ΔE=Vin*Qc，再加上由于变压器励磁电流所产生的能量，关系式Elk>Vin*Qc总是能满足的，即，MOS管Q2的零电压开通总是可行的。
阶段7：OC变为低电平，MOS管Q3关断，变压器TX原边漏感与MOS管Q3漏源极之间的寄生电容、Q4漏源极之间的寄生电容产生谐振，MOS管Q3漏源极之间的电压开始上升，即，MOS管Q4漏源极之间的电压开始下降。V_TX下降，I_TX继续增加。此阶段与阶段2类似，分析过程不再累述。
阶段8：OF变为高电平，MOS管Q5、Q6同时导通。此阶段与阶段3类似，分析过程不再累述。
阶段9：OD变为高电平，此时，MOS管Q2、Q4导通，由MOS管Q1～Q4组成的全桥结构进入续流模式，V_TX为零，I_TX缓慢减小。此阶段与阶段4类似，分析过程不再累述。
阶段10：OB变为低电平，MOS管Q2关断，变压器TX原边的漏感与MOS管Q1漏源极之间的寄生电容、Q2漏源极之间的寄生电容产生谐振，MOS管Q2漏源极之间的电压开始上升，即，MOS管Q1漏源极之间的电压开始下降。V_TX反向上升，I_TX减小并反向。此阶段与阶段5类似，分析过程不再累述。
根据以上分析，本发明移相全桥电路的控制方法从传递能量阶段切换到续流阶段的过程中，通过同步整流控制将变压器TX二次侧短路，从而使得变压器TX一次侧漏感储存一定的能量，用以解决传统移相全桥电路控制方法中由于轻载时谐振能量不足而无法实现零电压开关的问题。
图6所示的本发明移相全桥电路的控制方法中，阶段2与阶段3的总和相当于图2所示的现有方法的阶段2；阶段7与阶段8的总和相当于图2所示的现有方法的阶段6。
本发明所述的控制方法可以适用于所有同时满足以下两个条件的移相全桥电路：其一，变压器TX一次侧为全桥结构，该全桥结构为4n个MOS管组成，其中n为自然数；（当n≥2时，n个MOS管并联相当于图1中的一个原边MOS管）其二，变压器TX二次侧为同步整流结构，即变压器TX二次侧绕组的两端各通过一个MOS管接地。
显然，本发明所述的控制方法适用于图1所示的移相全桥电路。但是与本发明所述的控制方法相对应的最简化的移相全桥电路如图5所示， 包括：
一变压器TX；
一超前桥臂，由MOS管Q1和Q2串接组成，这两个MOS管Q1和Q2的连接节点C与变压器TX一次侧的一端连接；
一滞后桥臂，由MOS管Q3和Q4串接组成，这两个MOS管Q3和Q4的连接节点D与变压器TX一次侧的另一端连接；
输入的直流电压Vin加在MOS管Q1和Q3的连接节点A和MOS管Q2和Q4的连接节点B之间；
一输出电路，主要由两整流MOS管Q5、Q6、输出电感L2和输出电容C组成；变压器TX二次侧的一端连接整流MOS管Q5后接地；变压器TX二次侧的另一端连接整流MOS管Q6后接地；变压器TX二次侧的中间抽头（将变压器TX二次侧平均分为两个线圈）连接串接的输出电感L2和输出电容C后接地；
输出电容C的两端为输出的直流电压Vo。
更具体地，所述MOS管Q1～Q6也可以改为其他 开关器件，比如IGBT（绝缘栅双极型晶体管），IGBT的发射极相当于MOS管的源极，IGBT的集电极相当于MOS管的漏极 。下面以MOS管Q1～Q6均为NMOS为例说明，MOS管Q1的源极与MOS管Q2的漏极相连接，作为连接节点C。MOS管Q3的源极与MOS管Q4的漏极相连接，作为连接节点D。MOS管Q1的漏极与MOS管Q3的漏极相连接，作为连接节点A。MOS管Q2的源极与MOS管Q4的源极相连接，作为连接节点B并接地。输入的直流电压Vin的正极接在连接节点A，负极接在连接节点B。变压器TX一次侧只有一个绕组，变压器TX二次侧具有一个平均分配二次侧绕组的中间抽头。变压器TX二次侧的一端接整流MOS管Q5的漏极，变压器TX二次侧的另一端接整流MOS管Q6的漏极，整流MOS管Q5、Q6的源极都接地。变压器TX二次侧的抽头接串联的输出电感L2和输出电容C后接地。未画出的负载加在输出电容C的两端，即负载与输出电容C并联。
图9显示了本发明所述控制方法的具体实施环境，其中的移相控制电路与图5 完全一样，不再累述。其中，AUIRS2191为原边MOSFET的驱动芯片，为MOS管Q1～Q4提供外加的栅极电压，从而控制这些MOS管的导通或关断；UCC27322为副边MOSFET的驱动芯片，为MOS管Q5、Q6提供外加的栅极电压，从而控制这些MOS管的导通或关断；ISO7240为隔离芯片，用于变压器一次侧和二次侧的隔离；UCC28950为控制芯片。
图10是本发明移相全桥电路在图9所示的测试环境下的信号输出波形。 测试条件：直流输入电压为420V；直流输出电压为10V；输出电流为10A。其中CH1表示变压器一次电压，CH4表示变压器一次电流。显然测试得到的CH1与图6中理论分析得到的V_TX相一致，测试得到的CH4也与图6中理论分析得到的I_TX相一致。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
 Industrial Applicability
本发明移相全桥电路的控制方法从传递能量阶段切换到续流阶段的过程中，通过同步整流（即变压器的二次侧绕组的两端各通过一个MOS管或IGBT接地）控制将变压器TX二次侧短路，从而使得变压器TX一次侧漏感储存一定的能量，用以解决传统移相全桥电路的控制方法中由于轻载时谐振能量不足而无法实现零电压开关的问题。
与现有的移相全桥电路相比，本发明 的移相全桥电路可以省略变压器TX一次侧的谐振电感L1及两个箝位二极管D1、D2，从而降低***成本，减小***体积。去除掉的器件原本也是会产生损耗的，因而本发明的移相全桥电路可以 提高***的效率。
 Sequence List Text

Claims (6)

  1. 一种移相全路电路的控制方法，其特征是，将移相全桥电路的一个工作周期分为如下10个阶段； 其中OA、OB、OC、OD、OE、OF分别为MOS管一到MOS管六（Q1～Q6）的外加栅极电压，V_TX为变压器（TX）的一次电压，I_TX为变压器（TX）的一次电流；
    阶段1：OA、OD、OF为高电平，OB、OC、OE为低电平，MOS管一（Q1）、MOS管四（Q4）、MOS管六（Q6）导通，V_TX为正，I_TX增加；
    阶段2：OD变为低电平，MOS管四（Q4）关断，变压器（TX）原边漏感与MOS管三（Q3）漏源极之间的寄生电容、MOS管四（Q4）漏源极之间的寄生电容产生谐振，MOS管四（Q4）漏源极之间的电压开始上升，即，MOS管三（Q3）漏源极之间的电压开始下降；V_TX下降，I_TX继续增加；
    阶段3：OE变为高电平，MOS管五（Q5）、MOS管六（Q6）同时导通；此时，变压器（TX）副边短路，I_TX迅速上升；
    阶段4：OC变为高电平，此时，MOS管一（Q1）、MOS管三（Q3）导通，由MOS管一到MOS管四（Q1～Q4）组成的全桥结构进入续流模式，V_TX为零，I_TX缓慢减小；
    阶段5：OA变为低电平，MOS管一（Q1）关断，变压器（TX）原边的漏感与MOS管一Q1漏源极之间的寄生电容、MOS管二（Q2）漏源极之间的寄生电容产生谐振，MOS管一（Q1）漏源极之间的电压开始上升，即，MOS管二（Q2）漏源极之间的电压开始下降；V_TX反向上升，I_TX减小并反向；
    阶段6：OB变为高电平，此时，MOS管二（Q2）、MOS管三（Q3）导通，V_T为负，I_TX反向增加；与此同时OF变为低电平，MOS管六（Q6）关断；
    阶段7：OC变为低电平，MOS管三（Q3）关断，变压器（TX）原边漏感与MOS管三（Q3）漏源极之间的寄生电容、MOS管四（Q4）漏源极之间的寄生电容产生谐振，MOS管三（Q3）漏源极之间的电压开始上升，即，MOS管四（Q4）漏源极之间的电压开始下降；V_TX下降，I_TX继续增加；
    阶段8：OF变为高电平，MOS管五（Q5）、MOS管六（Q6）同时导通；此时，变压器（TX）副边短路，I_TX迅速上升；
    阶段9：OD变为高电平，此时，MOS管二（Q2）、MOS管四（Q4）导通，由MOS管一到MOS管四（Q1～Q4）组成的全桥结构进入续流模式，V_TX为零，I_TX缓慢减小；
    阶段10：OB变为低电平，MOS管二（Q2）关断，变压器（TX）原边的漏感与MOS管一（Q1）漏源极之间的寄生电容、MOS管二（Q2）漏源极之间的寄生电容产生谐振，MOS管二（Q2）漏源极之间的电压开始上升，即，MOS管一（Q1）漏源极之间的电压开始下降；V_TX反向上升，I_TX减小并反向。
  2. 根据权利要求1所述的移相全路电路的控制方法，其特征是，所述MOS管全部或部分替换为绝缘栅双极型晶体管。
  3. 权利要求1所述的控制方法适用的移相全桥电路，其特征是， 必须同时满足以下两个条件：
    其一，变压器的一次侧为全桥结构，该全桥结构为4n个MOS管组成，其中n为自然数；
    其二，变压器的二次侧为同步整流结构，即变压器的二次侧绕组的两端各通过一个MOS管接地。
  4. 根据权利要求3所述的移相全桥电路，其特征是，包括：
    一变压器（TX）；
    一超前桥臂，由MOS管一（Q1）和MOS管二（Q2）串接组成，这两个MOS管的连接节点三（C）与变压器（TX）一次侧的一端连接；
    一滞后桥臂，由MOS管三（Q3）和MOS管四（Q4）串接组成，这两个MOS管的连接节点四（D）与变压器（TX）一次侧的另一端连接；
    输入的直流电压（Vin）加在MOS管一（Q1）和MOS管三（Q3）的连接节点一（A）和MOS管二（Q2）和MOS管四（Q4）的连接节点二（B）之间；
    一输出电路，主要由两整流MOS管（Q5、Q6）、输出电感（L2）和输出电容（C）组成；
    输出电容（C）的两端为输出的直流电压（Vo）。
  5. 根据权利要求4所述的移相全桥电路，其特征是，所述输出电路中，变压器（TX）二次侧的一端接整流MOS管五（Q5）后接地，变压器（TX）二次侧的另一端接整流MOS管六（Q6）后接地；变压器（TX）二次侧的中间抽头接串联的输出电感（L2）和输出电容（C）后接地。
  6. 根据权利要求3、4或5所述的移相全桥电路，其特征是，所述MOS管全部或部分替换为绝缘栅双极型晶体管。
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