WO2013004090A1 - 一种用于数据传输的方法及装置 - Google Patents
一种用于数据传输的方法及装置 Download PDFInfo
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- WO2013004090A1 WO2013004090A1 PCT/CN2012/072413 CN2012072413W WO2013004090A1 WO 2013004090 A1 WO2013004090 A1 WO 2013004090A1 CN 2012072413 W CN2012072413 W CN 2012072413W WO 2013004090 A1 WO2013004090 A1 WO 2013004090A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6552—DVB-T2
Definitions
- the application date for this application is September 5, 2011, and the application number is 201110260661.4.
- the invention name is
- the invention belongs to communication technology, and in particular relates to a method and device for data transmission. Background technique
- LDPC low density parity check
- the LDPC code is a linear error correction code based on the sparse parity check matrix H, and the elements in H are 1 except 0. If N indicates the code length of the LDPC code, K indicates the information bit length, M indicates the check bit length, 7 indicates the column weight, indicates the line weight, and R indicates the code rate, the LDPC code can be expressed as (N, K) LDPC. code. If the sum is constant, the LDPC code is a regular LDPC code (regular LDPC;); otherwise, it is an irregular LDPC code (Irregular LDPC).
- the LDPC code code word is the zero space of its check matrix H, and the encoding process is described as follows. First, the parity check matrix construction unit constructs a parity check matrix H according to a preset LDPC coding parameter; then, a generator matrix G is obtained from the parity matrix construction unit according to the check matrix H, where the matrix G and the corresponding checksum are generated. The matrix H is a dual matrix; finally, the coding unit encodes the input data s with the generator matrix G to obtain the codeword c of the output LDPC code.
- the technical problem to be solved by the present invention is to provide a method for data transmission to reduce the storage space required for storing a parity check matrix.
- Generating a parity check matrix according to a generated sequence corresponding to the pre-stored row generator The input data is encoded using a generator matrix obtained from the parity check matrix to obtain output data including parity information.
- An object of the present invention is to provide an apparatus for data transmission, the apparatus comprising: a storage module, a check matrix generation module, and a codeword generation module;
- the storage module is configured to save a generation sequence corresponding to the row generator, and provide the generation sequence to the verification matrix generation module;
- the check matrix generating module is configured to generate a parity check matrix according to the generated sequence provided by the storage module, and send the parity check matrix to the codeword generating module;
- the codeword generating module is configured to receive the parity check matrix from the check matrix generating module, and encode the input data by using a generating matrix obtained by the parity check matrix.
- a method and apparatus for data transmission uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts the row generator or directly addresses the parity. The way the matrix is checked minimizes the storage space required to store the parity matrix.
- FIG. 1 is a schematic flowchart of a method for data transmission according to an embodiment of the present invention
- FIG. 2 is a schematic diagram of performance of a (1344, 672) LDPC code according to Embodiment 1 of the present invention
- FIG. 3 is a schematic diagram of (1344, 840) LDPC code performance provided by Embodiment 2 of the present invention.
- FIG. 4 is a schematic diagram of performance of (1344, 1008) LDPC code according to Embodiment 3 of the present invention
- FIG. 5 is a schematic diagram of performance of (1344, 1176) LDPC code according to Embodiment 4 of the present invention
- Figure 2 is a schematic diagram showing the performance of the (2688, 1680) LDPC code provided in Embodiment 6 of the present invention
- Figure 8 is a (2688, 2016) LDPC provided in Embodiment 7 of the present invention
- Figure 9 is a schematic diagram showing the performance of (2688, 2240) LDPC code provided in Embodiment 8 of the present invention
- Figure 10 is a schematic diagram showing the performance of (5376, 2688) LDPC code provided in Embodiment 9 of the present invention
- FIG. 12 is a schematic diagram showing the performance of (5376, 4032) LDPC code according to Embodiment 11 of the present invention
- FIG. 13 is a schematic diagram of Embodiment 12 of the present invention.
- FIG. 14 is a schematic structural diagram of an apparatus for data transmission according to Embodiment 13 of the present invention;
- FIG. 15 is a schematic diagram of Embodiment 14 of the present invention. Another schematic structure of an apparatus for data transmission. detailed description
- An object of the present invention is to generate a parity check matrix by generating a sequence corresponding to a row generator saved in advance; and encoding the input data by using a generator matrix obtained by the parity check matrix, so that only a very small amount of storage space is needed
- the generation sequence corresponding to the row generator By storing the generation sequence corresponding to the row generator, the problem that the parity check matrix is excessively stored can be solved.
- FIG. 1 is an exemplary flowchart of a method for data transmission provided by the present invention. Referring to FIG. 1, the method includes the following steps:
- Step 101 Generate a parity check matrix H according to a generation sequence corresponding to the pre-stored row generator.
- the number of rows and the number of columns of the parity check matrix to be constructed in this example are determined according to a preset code length, a code rate, and a dimension of the submatrix, and the parity check matrix is divided into sub An array of matrices.
- the number of columns is the code length of the LDPC code, denoted as N;
- ⁇ denotes a column weight, denotes a row weight, R denotes a code rate, ⁇ denotes a number of row generators, and the LDPC code can be represented as an (N, K) LDPC code, and assuming that the constructed LDPC code of the embodiment of the present invention
- the parity check matrix H can be expressed as follows:
- H is a full rank matrix of ⁇ ⁇ ⁇ .
- the first line of OA ⁇ p - l is called the ith row generator of H, then H has a total of P row generators.
- the i-th row sub-matrix of the parity check matrix (where 0 ⁇ ⁇ P ) can be generated by the first row of the first row sub-matrix, so that the i-th row generator of the first behavior matrix H of the i-th row sub-matrix , then H has a total of P line generators.
- the first '', G ⁇ ⁇ P row generators, the number of columns in which element 1 is located (range: 0 ⁇ N-1) is called the matrix H
- the row generators of the matrix ⁇ correspond to one generation sequence.
- the row generation sequence consists of X numbers, and the required storage space is greatly reduced relative to ⁇ ;
- the elements of other rows in the entire sub-matrix are obtained by cyclic shift or direct addressing, thereby generating the entire parity check matrix H.
- Each row of the submatrix is obtained by shifting one line of its previous line to the right by one, where the first line is the right shift of the last line.
- the value of the other row elements in the loop submatrix is obtained by cyclically shifting its first row of elements. For example, you can rotate the w bit to the right of the first row of elements to get the second row of elements; shift the w bit to the right of the second row of elements to get the third row of elements, and so on, you can get the second row to the The value of all elements of the t line.
- the direct addressing method is specifically as follows:
- the code length is N
- the code rate is a sequence of R generation.
- a total of P generation sequences correspond to P row sub-matrices, and the number of sub-matrices in each sub-matrix is N/t.
- a parity check matrix with a code length of N and a code rate of R includes a P* ⁇ ) submatrix whose dimension is txt.
- Each nonzero element in the generated sequence corresponds to a non-zero matrix, and the remaining submatrices , are all zero matrices with dimensions ⁇ ⁇ .
- the above calculation method can be understood as: according to the code length, the code rate and the row weight, confirm the dimension of the sub-matrix, and take any element in the generated sequence to generate a sub-matrix, and only the first row element in the generated sub-matrix One position is 1, and the remaining positions are 0; the position of the element is 1 according to the number in the generated sequence according to the following rules Determine: The number obtains the position information of the element according to the divisibility principle, so the first line information of the sub-matrix can be determined, and the position of the element of the sub-matrix other than the first line is 1 according to the first line element.
- Direct addressing is obtained, that is, the position of the element other than the first row in the sub-matrix is 1 can correspond to the first row, and the corresponding relationship is: except the column value of any row of the first row minus the row After the value, the result of modulo the dimension is equal to the value of the column in the first row.
- Each non-zero element in the generated sequence corresponds to a non-zero matrix, and the remaining sub-matrices are all zero matrices.
- a parity check matrix is obtained. It is assumed that the generated sequence corresponding to the row generator for generating the parity check matrix contains y numbers, and the obtained check matrix contains y sub-matrices containing element 1, which are known by the properties of the matrix.
- the submatrix of 1 is a permutation unit matrix.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- Step 102 Encode the input data by using a generation matrix obtained by a parity check matrix.
- a corresponding generation matrix G can be obtained from the parity check matrix H in the same manner as in the prior art, wherein the generation matrix G and the corresponding parity risk matrix H are dual matrices.
- the generation matrix G and the corresponding parity check matrix H are dual matrices.
- the generator matrix G can be obtained in the following manner:
- the generator matrix G corresponding to the check matrix H can be expressed as:
- each column of the matrix is obtained by shifting one column of the previous column down one bit, wherein the first column is the cyclic down of the last column.
- ⁇ w ⁇ f '' ⁇ ' 1 ''' The first column of ⁇ 1 is called the j+1th column generator of the generator matrix G, then G has a total of p column generators.
- This embodiment only exemplifies the above-described representation of the generation matrix G.
- the present invention is not limited to the above-described representation, and the manner of the G matrix obtained by the H matrix and the G matrix are also within the scope of the present invention.
- the input data is encoded, and the input data is converted into an LDPC codeword to obtain output data including parity information.
- the LDPC code is a linear block code, and the encoding process can be expressed as:
- ⁇ K coded information bits
- ⁇ ( ⁇ .' ⁇ ⁇ ' ⁇ ' ⁇ - ⁇ ' ⁇ .' ⁇ ⁇ ' ⁇ 1) is ⁇
- ⁇ ( ⁇ ⁇ ''"' ⁇ TM) is ⁇ - ⁇ check bits
- the input data can be encoded in the same manner as in the prior art.
- the above method determines that the generation sequence corresponding to the line generator matching the code length, the code rate, and the dimension of the sub-matrix is stored in advance in the case where the LDPC code length, the code rate, and the dimension of the sub-matrix have been selected.
- the selection of the code length and code rate of the multi-rate LDPC code includes many methods, and a feasible method can determine the length of the code used according to the principle of the highest spectrum efficiency according to the upper layer indicating the length of the transmission packet.
- the code length is determined by first using the codeword with the highest code rate under the code length, and determining whether the code rate is applicable according to the metric of the PER.
- the code rate is lowered to be adjacent thereto. Lower code rate until the lowest bit rate is reached.
- the above is only an example of a selection method.
- the present invention is not limited to the above selection method, and the selection of the LDPC code length, the code rate, and the dimension of the sub-matrix by other methods are all within the scope of the present invention.
- the data after the data transmission method of the present invention is interleaved and modulated, and then transmitted outward.
- the modulation method may include: quadrature amplitude modulation (QAM), phase shift keying (PSK), amplitude phase shift keying (APSK), differential phase shift keying (DPSK), absolute phase shift keying (BPSK), Differential amplitude phase shift keying (DAPSK) and orthogonal frequency division multiplexing (OFDM).
- the modulated signal can be transmitted through various communication systems, including terrestrial links supporting mobile multimedia broadcasting, etc., for example: It can be transmitted through a terrestrial mobile multimedia broadcasting system (T-MMB: Terrestrial Mobile Multimedia Broadcasting).
- T-MMB Terrestrial Mobile Multimedia Broadcasting
- the LDPC code length, code rate, information bit length, and size of the cyclic submatrix are shown in Table 1.
- the present invention can be applied to a regular LDPC code and an irregular LDPC code.
- the technical solutions of the present invention are described in detail below through twelve embodiments. [Embodiment 1]
- This embodiment uses (1344, 672) an irregular LDPC code as an example for description.
- the code length N of the irregular LDPC code to be implemented in this embodiment is 1344
- the information bit length K is 672
- the line weight is ⁇ 2
- the sub-matrix of 42 rows and 42 columns is taken as the most 'J, and the unit is taken as an example to describe the implementation process of the LDPC code.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generator of the LDPC code is as shown in Table 2, and the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 16) of the (i+1)th row generator.
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 1344 and a code rate of 1/2, a total of 16 row generators, each row generator corresponding to a row of sub-matrices, and the number of sub-matrices in each row of sub-matrices is 32.
- a parity check matrix with a code length of 1344 and a code rate of 1/2 includes 16 x 32 sub-matrices with a dimension of 42x 42.
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 7, therefore, there are 7 elements 1 in the first row of each row of sub-matrices, that is, there are 7 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 2 includes a number of generated sequences containing rows of numbers, and the number of sequences generated by each row in Table 2
- the word is the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 2 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 2 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 2 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- Table 2 is evenly divided into a plurality of generated sequences including 7 numbers, and a number in the sequence is generated according to each obtained line, that is, a number in each row as shown in Table 2, and a parity check matrix is obtained.
- the first row generation sequence is 156, 326, 342, 444, 575, 898, and 1005, indicating the first row of the first row of sub-matrices in the parity check matrix, that is, the parity check matrix.
- the first row of the first row of the 157th column, the 327th column, the 343th column, the 445th column, the 576th column, the 899th column, and the 1006th column have a value of 1 in the first row of the first row of the submatrix The remaining columns are 0;
- the second row generation sequence is 55, 85, 167, 486, 617, 1047, and 1307, indicating the first row of the second row sub-matrix of the parity check matrix, that is, the 56th row in the 43rd row of the parity check matrix.
- Columns, 86th column, 168th column, 487th column, 618th column, 1048th column, and 1308th column have a value of 1, and the remaining columns in the first row of the second row of the submatrix are 0, for other rows.
- the value of the first row of the sub-matrix can be obtained by reference to an example, and is not described here.
- the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- FIG. 2 is a schematic diagram showing the BER/BLER performance of the (1344,672) LDPC code in the AWGN channel and its performance comparison with Shannon Limit and uncoded BPSK in the first embodiment.
- the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- line 201 represents Shannon limit
- AWGN additive white Gaussian noise
- BER Bit error rate
- Curve 204 represents the BER performance curve of the signal transmitted without the use of BPSK modulation and then transmitted over the AWGN channel.
- This embodiment uses (1344, 840) an irregular LDPC code as an example for description.
- the code length N of the non-regular LDPC code to be implemented in this embodiment is 1344
- the information bit length K is 672
- the line weight is 10
- the sub-matrix of 42 rows x 42 columns is taken as the most 'J, the unit is taken as an example to describe the implementation process of the LDPC code.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generator of the LDPC code is as shown in Table 3.
- the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 12) of the (i+1)th row generator.
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 1344 and a code rate of 5/8, a total of 12 row generators, each row generator corresponding to 12 rows of sub-matrices, and the number of sub-matrices in each row of sub-matrices is 32.
- a parity check matrix having a code length of 1344 and a code rate of 5/8 includes a total of 1 2 ⁇ 32 sub-matrices having a dimension of 42 ⁇ 42.
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 10, there are 10 elements 1 in the first row of each row of sub-matrices, that is, there are 10 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 3 includes a plurality of generated sequences including row-repeated numbers, and the number of sequences generated in each of the rows in Table 3 is taken as the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the sequence of the first row in Table 3 is used as the number of columns in which the element 1 in the first row of the first row of sub-matrix is located, in the second row in Table 3.
- Table 3 is evenly divided into a plurality of generated sequences including 10 numbers, and a number in the sequence is generated according to each obtained line, that is, a number in each row as shown in Table 3, and a parity check matrix is obtained.
- the first row generation sequence is 265, 295, 377, 408, 422, 544, 578, 696, 722, 1176, representing the first row of the first row of sub-matrices in the parity check matrix.
- 266, 296, 378, 409, 423, 545, 579, 697, 723, and 1177 in the first row of the parity check matrix The value of the column is 1 and the remaining columns in the first row of the sub-matrix of the first row are 0.
- the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- FIG. 3 is a schematic diagram showing the BER/BLER performance of the (1344,840) LDPC code in the AWGN channel and its performance comparison with Shannon Limit and uncoded BPSK in the second embodiment.
- the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- a straight line 301 represents Shannon limit; , ' ⁇ modulation, then transmitted in an additive white Gaussian noise (AWGN) channel, and decoded by a SPA (Sum-Product Arithmetic) algorithm.
- Bit error rate (BER) curve of the signal a frame error rate (BLER) curve of the signal modulated and then transmitted in the AWGN channel and decoded using the SPA algorithm;
- BLER frame error rate
- Curve 304 represents the BER performance curve of the signal transmitted without the use of BPSK modulation and then transmitted over the AWGN channel.
- This embodiment uses (1344, 1008) an irregular LDPC code as an example for description.
- the code length N of the irregular LDPC code to be implemented in this embodiment is 1344
- the information bit length K is 1008
- the line weight is 15
- the implementation process of the LDPC code will be described by taking the sub-matrix of 42 rows and 42 columns as the minimum unit as an example.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generator of the LDPC code is as shown in Table 4, and the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 8) of the (i+1)th row generator.
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 1344 and a code rate of 3/4, a total of 8 row generators, each row generator corresponding to 8 rows of sub-matrices, and the number of sub-matrices in each row of sub-matrices is 32.
- the parity check matrix with a code length of 1344 and a code rate of 5/8 contains 8 X 32 sub-matrices with a dimension of 42 X 42.
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 15, therefore, there are 15 elements 1 in the first row of each row of sub-matrices, that is, there are 15 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 4 includes a plurality of generated sequences including row-repeated numbers, and the number of sequences generated in each of the rows in Table 4 is taken as the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 4 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 4 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 4 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- Table 4 is evenly divided into a plurality of generated sequences including 15 numbers, and a parity check matrix is obtained according to the numbers in each generated sequence, that is, the numbers in each row as shown in Table 4.
- the first generation sequence is 3, 91, 140, 223, 253, 335, 366, 502, 536, 680, 718, 785, 1089, 1103, and 1253, indicating the parity check matrix.
- the first row of the first row of sub-matrices that is, the fourth ⁇ ij, the 92 ⁇ ij, the 141 ⁇ ij, the 224th in the first row of the parity check matrix
- Columns, columns 254, 336, 367, 503, 537, 681, 719, 786, 1090, 1104, and 1254 are 1
- the remaining columns in the first row of the first row of the sub-matrix are 0.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- Embodiment 3 of the present invention The performance of the (1344, 1008) irregular LDPC code provided in Embodiment 3 of the present invention will be described below by comparison with the prior art simulation.
- 4 is a schematic diagram showing the BER/BLER performance of the (1344,1008) LDPC code modulated by BPSK in the third embodiment and its performance comparison with Shannon Limit and uncoded BPSK. In this simulation, the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- Curve 402 represents the encoding using the inventive (1344, 1008) irregular LDPC code, BPSK modulation, and then in the additive white Gaussian noise (AWGN) channel, and using the sum product decoding algorithm (SPA: Sum) -Product Arithmetic ) a bit error rate (BER ) curve of the decoded signal;
- Curve 403 represents a frame error rate (BLER) curve of a signal encoded by the inventive (1344, 1008) irregular LDPC code, BPMS modulated, then transmitted in the AWGN channel, and decoded using the SPA algorithm;
- BLER frame error rate
- Curve 404 represents the BER performance curve of the signal transmitted without the encoding, directly using BPSK modulation, and then transmitted over the AWGN channel.
- This embodiment uses (1344, 1176) an irregular LDPC code as an example for description.
- the code length N of the irregular LDPC code to be implemented in this embodiment is 1344
- the information bit length K is 1176
- the line weight is 28
- the sub-matrix of 42 rows x 42 columns is taken as a minimum unit as an example to illustrate the implementation process of the LDPC code.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- a parity check matrix is generated based on a generation sequence corresponding to the row generator stored in advance.
- the row generator of the LDPC code is as shown in Table 5, and the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 4 ) of the (i+1)th row generator.
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 1344 and a code rate of 7/8, a total of 4 row generators, each row generator corresponding to 4 rows of sub-matrices, and the number of sub-matrices in each row of sub-matrices is 32.
- the parity check matrix with a code length of 1344 and a code rate of 7/8 contains 4 X 28 sub-matrices with a dimension of 42 X 42.
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 28, there are 28 elements 1 in the first row of each row of sub-matrices, that is, there are 28 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 5 includes a plurality of generated sequences including row-repeated numbers, and the number of sequences generated in each of the rows in Table 5 is taken as the number of columns in which the element 1 of the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 5 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 5 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence is generated from the last row in Table 5 as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- Table 5 is evenly divided into a plurality of generated sequences of 28 numbers, and a number in the sequence is generated according to each obtained line, that is, a number in each row as shown in Table 5, to obtain a parity check matrix.
- the first line generation sequence is 55, 85, 167, 198, 212, 274, 334, 368, 384, 429, 486, 512, 550, 617, 666, 689, 752, 779. , 874, 885, 940, 973, 1047, 1064, 1103, 1149, 1253, and 1265, indicating the first row of the first row of sub-matrices in the parity check matrix, that is, the 56th row in the first row of the parity check matrix Columns, 86, 168, 199, 213, 275, 335, 369, 385, 430, 487, 513, 551, Columns 618, 667, 690, 753, 780, 875, 886, 941, 974, 1048, 1065, 1104, 1150
- the value of the 1254, 1266 column is 1, and the remaining columns in the first row of the first row of the sub-matrix are 0.
- the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- FIG. 5 is a schematic diagram showing the BER/BLER performance of the (1344, 1176) LDPC code in the AWGN channel and its performance comparison with the Shannon Limit and the uncoded BPSK in the fourth embodiment.
- the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- Curve 502 represents the encoding using the inventive (1344, 1176) irregular LDPC code, BPSK modulation, and then in the additive white Gaussian noise (AWGN) channel, and using the sum product decoding algorithm (SPA: Sum) -Product Arithmetic ) a bit error rate (BER ) curve of the decoded signal;
- Curve 503 represents a frame error rate (BLER) curve of a signal encoded by the inventive (1344, 1176) irregular LDPC code, BPSK modulated, then transmitted in the AWGN channel, and decoded using the SPA algorithm;
- BLER frame error rate
- Curve 504 represents the BER performance curve of the signal transmitted without the use of BPSK modulation and then transmitted over the AWGN channel.
- This embodiment uses the (2688, 1344) irregular LDPC code as an example for description.
- the code length N of the non-regular LDPC code to be implemented in this embodiment is 2688
- the information bit length K is 1344
- the line weight is 7
- the sub-matrix of 112 rows x 11 column is taken as the most, and the unit is taken as an example to describe the implementation process of the LDPC code.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generator of the LDPC code is as shown in Table 6, in which the (i+1 row) corresponds to the generation sequence (0 ⁇ ⁇ 12) of the (i+1)th row generator.
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 2688 and a code rate of 1/2, a total of 12 row generators, each row generator corresponding to 12 rows of sub-matrices, and the number of sub-matrices in each row of sub-matrices is twenty four.
- a parity check matrix with a code length of 2688 and a code rate of 1/2 includes 12 X 24 sub-matrices with a dimension of 112 X 112.
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 7, therefore, there are 7 elements 1 in the first row of each row of sub-matrices, that is, there are 7 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 6 includes a plurality of generated sequences including row-repeated numbers, and the number of sequences generated in each of the rows in Table 6 is taken as the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 6 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 6 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 6 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- the table 6 is evenly divided into a plurality of generation sequences including 7 numbers, and the numbers in the sequence are generated according to each of the obtained lines, that is, the numbers in each row as shown in Table 6, to obtain a parity check matrix.
- the first generation sequence is 417, 582, 1113, 1518, 2328, 2388, and 2544, indicating the first row of the first row of sub-matrices in the parity check matrix, that is, the parity check matrix.
- the first row of the first row of the 418th column, the 583th column, the 1114th column, the 15th column, the 2329th column, the 2389th column, and the 2545th column have a value of 1 in the first row of the first row of the submatrix
- the remaining columns are 0;
- the second row generation sequence is 112, 343, 529, 607, 844, 1405 and 1861, indicating the first row of the second row sub-matrix of the parity check matrix, that is, the 113th in the 113th row of the parity check matrix.
- the 344th column, the 530th column, the 608th column, the 845th column, the 1406th column, and the 1862th column have a value of 1, and the remaining columns in the first row of the second row of the submatrix are 0, for other rows.
- the value of the first row of the sub-matrix can be obtained by reference to an example, and is not described here.
- the values of the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- step 102 The specific implementation is the same as that in step 102, and will not be described again.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- Embodiment 5 of the present invention The performance of the (2688, 1344) irregular LDPC code provided in Embodiment 5 of the present invention will be described below by comparison with the prior art simulation.
- 6 is a schematic diagram showing the BER/BLER performance of the (2688, 1344) LDPC code in the AWGN channel and its performance comparison with Shannon Limit and uncoded BPSK in the fifth embodiment. In this simulation, the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- line 601 represents the Shannon limit
- Curve 602 represents an encoding using the inventive (2688, 1344) irregular LDPC code, BPSK modulation, and then in an additive white Gaussian noise (AWGN) channel, and using a sum product decoding algorithm (SPA: Sum) -Product Arithmetic ) a bit error rate (BER ) curve of the decoded signal;
- SPA Sum
- SPA sum product decoding algorithm
- BER bit error rate
- Curve 603 represents a frame error rate (BLER) curve of a signal encoded by the non-regular LDPC code of the present invention (2688, 1344), modulated by the BPSK method, then transmitted in the AWGN channel, and decoded using the SPA algorithm;
- BLER frame error rate
- Curve 604 represents the BER performance curve of the signal transmitted without the encoding, directly using BPSK modulation, and then transmitted over the AWGN channel.
- This embodiment uses (2688, 1680) an irregular LDPC code as an example for description.
- the code length N of the irregular LDPC code to be implemented in this embodiment is 2688
- the information bit length K is 1680
- the line weight is 10
- the implementation process of the LDPC code is described by using the sub-matrix of 112 rows and x11 columns as the most, and the unit as an example.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 2688 and a code rate of 5/8, a total of 9 row generators, each row generator corresponding to 9 rows of sub-matrices, and the number of sub-matrices in each row of sub-matrices is twenty four.
- a parity check matrix having a code length of 2688 and a code rate of 5/8 includes a total of 9 X 24 sub-matrices having a dimension of 11 2 X 11 2 .
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 10, there are 10 elements 1 in the first row of each row of sub-matrices, that is, there are 10 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 7 includes a plurality of generated sequences including row-repeated numbers, and the number of sequences generated in each of the rows in Table 7 is taken as the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 7 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 7 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 7 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- the table 7 is evenly divided into a plurality of generated sequences including 10 numbers, and the numbers in the sequence are generated according to each of the obtained lines, that is, the numbers in each row as shown in Table 7, and the parity check matrix is obtained.
- the first row generation sequence is 7, 193, 271, 358, 508, 941, 1069, 1232, 1830, 2544, representing the first row of the first row of sub-matrices in the parity check matrix.
- the eighth column the 194th column, the 272th column, the 359th column, the 509th column, the 942th column, the 1070th column, the 1233th column, the 1831th column, the 2545th in the first row of the parity check matrix
- the value of the column is 1 and the remaining columns in the first row of the sub-matrix of the first row are 0.
- the values of other row elements in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated, row-replaced, and replaced at various angles. Column permutation or any transformation that changes the position of the submatrix.
- step 102 the input data is encoded using a generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- Embodiment 6 of the present invention The performance of the (2688, 1680) irregular LDPC code provided in Embodiment 6 of the present invention will be described below by comparison with the prior art simulation.
- 7 is a schematic diagram showing the BER/BLER performance of the (2688, 1680) LDPC code in the AWGN channel and its performance comparison with Shannon Limit and uncoded BPSK in the sixth embodiment. In this simulation, the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- Curve 702 represents an encoding using the inventive (2688, 1680) irregular LDPC code, BPSK modulation, and then in an additive white Gaussian noise (AWGN) channel, and using a sum product decoding algorithm (SPA: Sum) -Product Arithmetic ) a bit error rate (BER ) curve of the decoded signal;
- SPA sum product decoding algorithm
- BER bit error rate
- Curve 703 represents a frame error rate (BLER) curve of a signal encoded by the non-regular LDPC code of the present invention (2688, 1680), modulated by the BPSK method, then transmitted in the AWGN channel, and decoded using the SPA algorithm;
- BLER frame error rate
- Curve 704 represents the BER performance curve of the signal transmitted without the encoding, directly using BPSK modulation, and then transmitted over the AWGN channel.
- This embodiment uses (2688, 2016) an irregular LDPC code as an example for description.
- the code length N of the non-regular LDPC code to be implemented in this embodiment is 2688
- the information bit length K is 2016, the line weight is 15
- the sub-matrix of 112 rows x 11 column is taken as the most, and the unit is taken as an example to describe the implementation process of the LDPC code.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generator of the LDPC code is as shown in Table 8, and the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 6) of the (i+1)th row generator.
- a parity check matrix with a code length of 2688 and a code rate of 3/4 includes a total of 6 X 24 sub-matrices with a dimension of 112 X 112.
- the row weight of the LDPC code in this embodiment is 15, therefore, there are 15 elements 1 in the first row of each row of sub-matrices, that is, there are 15 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 8 includes a plurality of generated sequences including row-repeated numbers, and the number of sequences generated in each of the rows in Table 8 is taken as the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 8 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 8 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 8 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- the table 8 is evenly divided into a plurality of generated sequences of 15 numbers, and the numbers in the sequence are generated according to each of the obtained lines, that is, the numbers in each row as shown in Table 8, to obtain a parity check matrix.
- the first row generation sequence is 62, 293, 374, 514, 679, 865, 943, 1030, 1180, 1257, 1435, 1613, 1904, 2203, and 2388, indicating the parity check matrix.
- the first row of the first row of sub-matrices that is, the 63rd column, the 294th column, the 375th column, the 515th column, the 680th column, the 866th column, the 944th column in the first row of the parity check matrix
- Columns 1031, 1181, 1258, 1436, 1614, 1905, 2204, 2389 are 1 and the remaining columns in the first row of the first row of sub-matrix
- the values of the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using the generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- Figure 8 is a comparison of the BER/BLER performance of the (2688,2016) LDPC code in the AWGN channel and its performance with Shannon Limit and uncoded BPSK in the seventh embodiment. Schematic diagram. In this simulation, the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- line 801 represents the Shannon limit
- Curve 802 represents an encoding using the inventive (2688, 2016) irregular LDPC code, BPSK modulation, and then in an additive white Gaussian noise (AWGN) channel, and using a sum product decoding algorithm (SPA: Sum) -Product Arithmetic ) a bit error rate (BER ) curve of the decoded signal;
- SPA sum product decoding algorithm
- BER bit error rate
- Curve 803 represents a frame error rate (BLER) curve of a signal encoded by the non-regular LDPC code of the present invention (2688, 2016), modulated by the BPSK method, then transmitted in the AWGN channel, and decoded using the SPA algorithm;
- BLER frame error rate
- Curve 804 represents the BER performance curve of the signal transmitted without the encoding, directly using BPSK modulation, and then transmitted over the AWGN channel.
- This embodiment uses the (2688, 2240) irregular LDPC code as an example for description.
- the code length N of the non-regular LDPC code to be implemented in this embodiment is 2688
- the information bit length K is 2240
- the implementation process of the LDPC code is described by using the sub-matrix of 112 rows x l l2 columns as the most and unit.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generator of the LDPC code is as shown in Table 9, and the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 4 ) of the (i+1)th row generator.
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 2688 and a code rate of 7/8, a total of 4 row generators, each row generator corresponding to 4 rows of sub-matrices, and the number of sub-matrices in each row of sub-matrices is twenty four.
- a parity check matrix having a code length of 2688 and a code rate of 7/8 includes a total of 4 X 24 sub-matrices having a dimension of 11 2 X 112.
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 21, there are 21 elements 1 in the first row of each row of sub-matrices, that is, 21 columns having a value of 1; and, in addition, the parity in this embodiment
- Table 9 includes a plurality of generated sequences including row-repeated numbers, and the number of sequences generated in each of the rows in Table 9 is taken as the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 9 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 9 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 9 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- the table 9 is evenly divided into a plurality of generation sequences including 21 numbers, and the numbers in the sequence are generated according to each of the obtained lines, that is, the numbers in each row as shown in Table 9, and the parity check matrix is obtained.
- the first line generation sequence is 7, 193, 271, 358, 508, 585, 763, 889, 941, 1069, 1184, 1232, 1370, 1518, 1598, 1749, 1830, 1970.
- 2086 , 2203 and 2544 indicating the first row of the first row of sub-matrices in the parity check matrix, that is, the eighth column, the 194th column, the 272th column, the 359th column in the first row of the parity check matrix
- Column, column 1971, column 2087, column 2204, column 2545 have a value of 1, the remaining columns in the first row of the first row of submatrix are 0; for the first row of other row submatrices Values can be obtained by reference to the examples, and will not be described here.
- the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- Embodiment 8 of the present invention The performance of the (2688, 2240) irregular LDPC code provided in Embodiment 8 of the present invention will be described below by comparison with the prior art simulation.
- 9 is a schematic diagram showing the BER/BLER performance of the (2688, 2240) LDPC code in the AWGN channel and its performance comparison with Shannon Limit and uncoded BPSK in the eighth embodiment. In this simulation, the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- line 901 represents the Shannon limit
- Curve 902 represents an encoding using the inventive (2688, 2240) irregular LDPC code, BPSK modulation, and then in an additive white Gaussian noise (AWGN) channel, and using a sum decoding algorithm (SPA: Sum) -Product Arithmetic ) a bit error rate (BER ) curve of the decoded signal;
- SPA Sum
- SPA Sum
- SPA sum
- BER bit error rate
- a curve 903 indicates a frame error rate of a signal encoded by the non-regular LDPC code of the present invention (2688, 2240), modulated by the BPSK method, then transmitted in the AWGN channel, and decoded by the SPA algorithm. (BLER) curve;
- Curve 904 represents the BER performance curve of the signal transmitted without the use of BPSK modulation and then transmitted over the AWGN channel.
- an irregular LDPC code with different line weights (5376, 2688) is taken as an example for description.
- the code length N of the irregular LDPC code to be implemented in this embodiment is 5376
- the information bit length K is 2688
- the implementation process of the LDPC code will be described by taking the sub-matrix of 112 rows and 112 columns as the minimum unit as an example.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generator of the LDPC code is as shown in Table 10, and the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 24) of the (i+1)th row generator.
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 5376 and a code rate of 1/2, a total of 24 row generators, each row generator corresponding to 24 rows of sub-matrices, and the number of sub-matrices in each sub-matrix still For 48.
- a parity check matrix having a code length of 5376 and a code rate of 1/2 includes a total of 24 X 48 sub-matrices having a dimension of 112 X 112.
- the first row element in each sub-matrix is then determined according to the generation sequence corresponding to the row generator and the row weight.
- Table 10 includes a plurality of generated sequences including row-repeated numbers, and the number of sequences generated in each of the rows in Table 10 is taken as the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 10 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 10 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 10 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- the table 10 is evenly divided into a plurality of generation sequences including 7 numbers, and the numbers in the sequence are generated according to each of the obtained lines, that is, the numbers in each row as shown in Table 10, and the parity check matrix is obtained.
- the first row generation sequence is 147, 281, 1109, 1381, 2089, 4658, 5232, indicating the first row of the first row of sub-matrices in the parity check matrix, that is, the parity check matrix.
- the first row of the first row of the 148th column, the 282th column, the 11th column, the 1382th column, the 2090th column, the 4659th column, and the 5233th column have a value of 1 in the first row of the first row of the submatrix The rest of the columns are 0.
- the values of the first row of other row sub-matrices reference may be made to the analogy of the example, and details are not described herein again.
- the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by a parity check matrix ,, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- Embodiment 9 of the present invention The performance of the (5376, 2688) irregular LDPC code provided in Embodiment 9 of the present invention will be described below by comparison with the prior art simulation.
- 10 is a BER/BLER performance of a (5376, 2688) LDPC code modulated by BPSK in the ninth embodiment and its performance ratio with Shannon Limit, uncoded BPSK.
- line 1001 represents the Shannon limit
- AWGN additive white Gaussian noise
- SPA sum-product decoding algorithm
- BER bit error rate
- BLER bit error rate
- Curve 1004 represents the BER performance curve of the signal transmitted without the encoding, directly using BPSK modulation, and then transmitted over the AWGN channel.
- an irregular LDPC code with different line weights (5376, 3360) is taken as an example for description.
- the code length N of the irregular LDPC code to be implemented is 5376
- the information bit length K is 3360
- the line weight is 10
- the sub-matrix of 112 rows xl l2 columns is taken as a minimum unit as an example to illustrate the implementation process of the LDPC code.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generation of the LDPC code is as shown in Table 11, and the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 18) of the (i+1)th row generator.
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 5376 and a code rate of 5/8, a total of 18 row generators, each row generator corresponding to 24 rows of sub-matrices, and the number of sub-matrices per 24 rows of sub-matrices Still 48.
- the code length is 5376
- the code rate is
- the 5/8 parity check matrix contains a total of 18 X 48 sub-matrices with a dimension of 112 X 112.
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 10, there are 10 elements 1 in the first row of each row of sub-matrices, that is, there are 10 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 11 includes a plurality of generated sequences containing the row-repeated numbers, and the number of the sequence generated in each of the rows in Table 11 is taken as the number of columns in which the element 1 of the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 11 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 11 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 11 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- the table 11 is evenly divided into a plurality of generation sequences including 10 numbers, and the numbers in the sequence are generated according to the obtained each line, that is, the numbers in each row as shown in Table 11, and the parity check matrix is obtained.
- the first row generation sequence is 60, 773, 981, 1045, 1226, 1234, 1576, 1846, 2969, 4437, indicating the first row of the first row of sub-matrices in the parity check matrix.
- the value of the column is 1 and the remaining columns in the first row of the sub-matrix of the first row are 0.
- the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- FIG. 11 is a schematic diagram showing the BER/BLER performance of the (5376, 3360) LDPC code in the AWGN channel and its performance comparison with the Shannon Limit, uncoded BPSK in the tenth embodiment. In this simulation, the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- line 1101 represents the Shannon limit
- AWGN additive white Gaussian noise
- SPA sum-Product Arithmetic
- BER bit error rate
- BLER bit error rate
- Curve 1104 represents the BER performance curve of the signal transmitted without the encoding, directly using BPSK modulation, and then transmitted over the AWGN channel.
- This embodiment uses (5376, 4032) an irregular LDPC code as an example for description.
- the code length N of the non-regular LDPC code to be implemented in this embodiment is 5376
- the information bit length K is 4032
- the line weight is 15
- the sub-matrix of 112 rows and 112 columns is taken as the most, and the unit is taken as an example to describe the implementation process of the LDPC code.
- the flowchart of the method in this embodiment is similar to the flowchart of the exemplary method of the present invention shown in FIG. 1.
- the implementation method of the LDPC code in this embodiment includes the following steps:
- step 101 a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generator of the LDPC code is as shown in Table 12, and the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 12) of the (i+1)th row generator.
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 15, therefore, there are 15 elements 1 in the first row of each row of sub-matrices, that is, there are 15 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 12 includes a plurality of generated sequences including the row-repeated numbers, and the number of the sequence generated in each of the rows in Table 12 is taken as the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 12 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 12 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 12 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- the table 12 is evenly divided into a plurality of generation sequences including 15 numbers, and the numbers in the sequence are generated according to each of the obtained lines, that is, the numbers in each row as shown in Table 12, and the parity check matrix is obtained.
- the first line generation sequence is 0, 181, 342, 661, 686, 869, 933, 1963, 2919, 3105, 3183, 3270, 4398, 4518, 5076, indicating the parity check matrix.
- the first row of the first row of sub-matrices that is, the first column, the 182th column, the 343th column, the 662th column, the 687th column, the 870th column, the 934th column in the first row of the parity check matrix
- Columns 1964, 2920, 3106, 3184, 3271, 4399, 4519, and 5077 have a value of 1, and the remaining columns in the first row of the first row of the submatrix
- the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by a parity check matrix ,, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- Fig. 12 is a diagram showing the BER/BLER performance of the (5376, 4032) LDPC code modulated by BPSK in the eleventh embodiment and its performance comparison with the Shannon Limit, uncoded BPSK. In this simulation, the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- line 1201 represents the Shannon limit; Line modulation, then force.
- Curve 1204 represents the BER performance curve of the signal transmitted without the encoding, directly using BPSK modulation, and then transmitted over the AWGN channel.
- an irregular LDPC code having a different row weight (5376, 4704) is taken as an example for description.
- the code length N of the irregular LDPC code to be implemented is 5376
- the information bit length K is 4704
- the sub-matrix of 112 rows xl l2 columns is taken as a minimum unit as an example to illustrate the implementation process of the LDPC code.
- a parity check matrix is generated based on a generation sequence corresponding to the pre-stored row generator.
- the row generator of the LDPC code is as shown in Table 13, and the (i+1 row) in the table corresponds to the generation sequence (0 ⁇ ⁇ 6) of the (i+1)th row generator, as shown below. :
- determining the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and code rate and a dimension of the sub-matrix, and dividing the parity check matrix into sub-matrices An array of units; a parity check matrix with a code length of 5376 and a code rate of 7/8, a total of 6 row generators, each row generator corresponding to 6 rows of sub-matrices, and the number of sub-matrices in each row of sub-matrices is 48.
- the parity check matrix with a code length of 5376 and a code rate of 7/8 contains a total of 6 X 48 sub-matrices with a dimension of 112 X 112.
- the first row element in each sub-matrix is then determined based on the generation sequence corresponding to the row generator and the row weight.
- the row weight of the LDPC code in this embodiment is 28, there are 28 elements 1 in the first row of each row of sub-matrices, that is, there are 28 columns with a value of 1; in addition, due to the parity in this embodiment
- Table 13 includes a plurality of generated sequences including row-repeated numbers, and the number of sequences generated in each of the rows in Table 13 is taken as the number of columns in which the element 1 in the first row of the corresponding sub-matrix is located. That is, the number in the first row generation sequence in Table 13 is taken as the number of columns in which the element 1 in the first row of the first row submatrix is located, and the number in the second row generation sequence in Table 13 is taken as the second. The number of columns in which the element 1 is in the first row of the row submatrix, and so on, until the number in the sequence of the last row in Table 13 is used as the column in which the element 1 in the first row of the last row of the submatrix is located number.
- the table 13 is evenly divided into a plurality of generation sequences including 28 numbers, and the numbers in the sequence are generated according to each of the obtained lines, that is, the numbers in each row as shown in Table 13, and the parity check matrix is obtained.
- the first line generation sequence is 55, 85, 167, 198, 212, 274, 334, 368, 384, 429, 486, 512, 550, 617, 666, 689, 752, 779 , 874, 885, 940, 973, 1047, 1064, 1103, 1149, 1253, and 1265, indicating the first row of the first row of sub-matrices in the parity check matrix, that is, the 56th row in the first row of the parity check matrix Columns, 86, 168, 199, 213, 275, 335, 369, 385, 430, 487, 513, 551, Columns 618, 667, 690, 753, 780, 875, 886, 941, 974, 1048, 1065, 1104, 1150
- the value of the 1254, 1266 column is 1, and the remaining columns in the first row of the first row of the sub-matrix are 0.
- the elements of other rows in the sub-matrix can be obtained by using two implementations of cyclic shift or direct addressing.
- the parity check matrix after the parity check matrix is obtained, it can be rotated at various angles, row permutation, column permutation, or any transformation of the submatrix position.
- step 102 the input data is encoded using a generator matrix G obtained by the parity check matrix H, and converted into an LDPC codeword to obtain output data including parity information.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts or directly addresses the row generator to obtain a parity check matrix, so that the parity is stored.
- the storage space required for the matrix is minimized.
- Figure 13 is a schematic diagram showing the BER/BLER performance of the (5376, 4704) LDPC code modulated by BPSK in the AWGN channel and its performance compared with the Shannon Limit, uncoded BPSK. In this simulation, the sum-product algorithm is used for decoding, and the maximum number of iterations is 50.
- line 1301 represents the Shannon limit
- AWGN additive white Gaussian noise
- SPA sum-product decoding algorithm
- BER bit error rate
- BLER frame error rate
- Curve 1304 represents the BER performance curve of the signal transmitted without the encoding, directly using BPSK modulation, and then transmitted over the AWGN channel.
- FIG. 14 is a schematic structural diagram of an apparatus for data transmission according to Embodiment 13 of the present invention.
- the device includes: a storage module 1410, a check matrix generation module 1420, and a codeword generation module 1430.
- the check matrix generation module 1420 further includes: a sequence analysis unit 1421 and a cyclic shift unit 1422.
- the storage module 1410 is configured to store the generated sequence, and provide the generated sequence analyzing unit 1421 in the check matrix generating module 1420 with the generated generating sequence thereof.
- the generating sequence analyzing unit 1421 in the check matrix generating module 1420 is configured to determine the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and a code rate and a dimension of the sub-matrix. And dividing the parity check matrix into an array in units of sub-matrices: determining a first row element in each sub-matrix according to a generation sequence corresponding to the row generator and a row weight; according to each of the sub-matrices a row of elements, the elements of each of the other rows of the sub-matrix are obtained, and the obtained sub-matrix of each row of the determined first row of elements is sent to the cyclic shifting unit 1422;
- the cyclic shift unit 1422 in the check matrix generation module 1420 is configured to obtain each sub-matrix according to the first row element of each sub-matrix and to use a cyclic shift, where each sub-matrix constitutes the sub-matrix
- the parity check matrix in the embodiment, the parity check matrix is sent to the codeword generation module 1430;
- the codeword generation module 1430 is configured to receive the parity check matrix from the cyclic shift unit 1422 in the check matrix generation module 1420, and encode the input data by using the generator matrix obtained by the parity check matrix.
- the device shown in FIG. 14 may further include: a check matrix transform unit, which may be used to perform rotation, row replacement, and various angle rotations on the parity check matrix obtained by the cyclic shift unit 1422.
- the column replaces or changes various sub-matrix positions and the like, and then transmits the transformed parity risk matrix to the codeword generation module 1430.
- the check matrix conversion unit may be separately provided in the implementation device of the embodiment, or may be provided in the verification matrix generation module 1420, or may be disposed in other modules.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and cyclically shifts the generated sequence to obtain a parity check matrix, so that the storage required for storing the parity check matrix is used. The space is minimized.
- FIG. 15 is a schematic structural diagram of an apparatus for data transmission according to Embodiment 13 of the present invention.
- the device includes: a storage module 1510, a check matrix generation module 1520, and a codeword generation module 1530.
- the check matrix generation module 1520 further includes: a sequence analysis unit 1521 and a direct addressing unit 1522.
- a storage module 1510 is configured to store a generated sequence and provide the generated sequence analysis unit 1521 in the check matrix generation module 1520 with the generated sequence stored therein;
- the generated sequence analyzing unit 1521 in the check matrix generating module 1520 is configured to determine the number of rows and the number of columns of the parity check matrix to be constructed according to a preset code length and a code rate and a dimension of the sub-matrix. And dividing the parity check matrix into an array in units of sub-matrices: determining a first row element in each sub-matrix according to a generation sequence corresponding to the row generator and a row weight; according to each of the sub-matrices One line element, Obtaining elements of other rows in each sub-matrix, and sending each row sub-matrix of the determined first row element to the direct addressing unit 422;
- the direct addressing unit 1522 in the check matrix generation module 1520 is configured to obtain each sub-matrix according to the first row element of each sub-matrix and directly address it.
- each sub-matrix constitutes the sub-matrix
- the parity check matrix in the embodiment, the parity check matrix is sent to the codeword generation module 1530;
- the codeword generation module 1530 is configured to receive a parity check matrix from the direct addressing 1522 in the check matrix generation module 1520, and use the parity check matrix to convert the input data into an LDPC codeword.
- the method further includes: a check matrix transform unit, where the check matrix transform unit can be used to perform various angle rotations and row replacements on the parity check matrix obtained by the direct addressing unit 1522.
- the column replaces or changes various sub-matrix positions and the like, and then transmits the transformed parity risk matrix to the codeword generation module 1530.
- the check matrix conversion unit may be separately provided in the implementation device of the embodiment, or may be provided in the verification matrix generation module 1520, or may be disposed in other modules.
- the apparatus for data transmission provided in the thirteenth and fourteenth embodiments of the present invention, the working principle and the related operation procedure are basically the same as those in the foregoing method for implementing data transmission, and details are not described herein again.
- the present invention uses a generation sequence corresponding to a row generator to represent a parity check matrix, and directly addresses the generated sequence to obtain a parity check matrix, so that the storage required for storing the parity check matrix is used. The space is minimized.
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DK12808016.5T DK2755340T3 (da) | 2011-07-06 | 2012-03-16 | Fremgangsmåde og indretning til at transmittere data |
EP12808016.5A EP2755340B1 (en) | 2011-07-06 | 2012-03-16 | Method and device for transmitting data |
US14/130,965 US9411676B2 (en) | 2011-07-06 | 2012-03-16 | Method and device for transmitting data |
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