WO2012169037A1 - プログラマブルコントローラシステム - Google Patents
プログラマブルコントローラシステム Download PDFInfo
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- WO2012169037A1 WO2012169037A1 PCT/JP2011/063229 JP2011063229W WO2012169037A1 WO 2012169037 A1 WO2012169037 A1 WO 2012169037A1 JP 2011063229 W JP2011063229 W JP 2011063229W WO 2012169037 A1 WO2012169037 A1 WO 2012169037A1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/15—Plc structure of the system
- G05B2219/15081—Period length ratio between application and communication task is settable
Definitions
- the present invention relates to a programmable controller system for controlling industrial equipment.
- Temporal reliability is required for communication of control data between controller units in a programmable controller system. That is, it is required to reliably deliver data of a predetermined size to the other party in a predetermined time.
- the divided data since the divided data is transmitted using the socket, when there are a plurality of transmission sources, the divided data is sent to the transmission destination at the timing when the divided data is intended due to a collision of communication data. The case where it does not arrive is considered. That is, the technique disclosed in Patent Document 1 has a problem that reliable data communication cannot be performed.
- the present invention has been made in view of the above, and an object of the present invention is to obtain a programmable controller system that guarantees temporal reliability of communication data even when the calculation cycle is longer than the communication cycle.
- the present invention connects a plurality of controller units each including a bus interface including a buffer memory, and the plurality of controller systems via the bus interface.
- the inter-unit transfer process for transferring the storage contents of the buffer memory provided in the bus interface of the transmitting controller unit to the buffer memory provided in the bus interface of the receiving controller unit is executed at a first time interval.
- a programmable controller system comprising: a bus, wherein the transmission-side controller unit generates communication data at a second time interval that is larger than the first time interval; and Generated communication data A data dividing unit that generates a number of transfer unit data equal to or less than a value obtained by dividing and dividing the second time interval by the first time interval, and a plurality of transfer unit data generated by the data dividing unit And a data storage unit that sequentially stores each of the above in a buffer memory included in the bus interface of the own controller unit at the first time interval, and the controller unit on the receiving side performs a transfer process between the units of the own controller unit.
- a data reading unit sequentially reading a plurality of transfer unit data sequentially transferred to the buffer memory at the first time interval at the first time interval and a plurality of transfer unit data read by the data reading unit are combined.
- a data combination unit for reconstructing the communication data generated by the data generation unit.
- the programmable controller system transfers communication data generated at each calculation cycle (second time interval) via a bus that transfers data at a communication cycle (first time interval) smaller than the calculation cycle. Since the arrival time can be ensured, the temporal reliability of the communication data can be ensured even when the calculation cycle is longer than the communication cycle.
- FIG. 1 is a diagram illustrating a configuration of a programmable controller system according to the first embodiment.
- FIG. 2 is a diagram for explaining how data is exchanged between the controller units of the first embodiment.
- FIG. 3 is a diagram illustrating the configuration of the controller unit according to the first embodiment.
- FIG. 4 is a timing chart illustrating data transmission / reception timings according to the first embodiment.
- FIG. 5 is a diagram for explaining the flow of data between the components of the first embodiment.
- FIG. 6 is a diagram illustrating a configuration of the programmable controller system according to the second embodiment.
- FIG. 7 is a diagram illustrating the configuration of the controller unit according to the second embodiment.
- FIG. 8 is a diagram illustrating a state in which data communication is performed between the controller units according to the second embodiment.
- FIG. 9 is a timing chart illustrating data transmission / reception timings according to the second embodiment.
- FIG. 10 is a diagram for explaining the flow of data between the components according to the second embodiment.
- FIG. 11 is a diagram illustrating a configuration of a programmable controller system according to the third embodiment.
- FIG. 12 is a diagram illustrating the configuration of the controller unit according to the third embodiment.
- FIG. 13 is a timing chart illustrating data transmission / reception timings according to the third embodiment.
- FIG. 14 is a diagram illustrating a configuration of a programmable controller system according to the fourth embodiment.
- FIG. 15 is a diagram illustrating the configuration of the controller unit according to the fourth embodiment.
- FIG. 16 is a timing chart illustrating data transmission / reception timings according to the fourth embodiment.
- FIG. 17 is a diagram illustrating a configuration of a programmable controller system according to the fifth embodiment.
- FIG. 18 is a diagram illustrating the configuration of the controller unit according to the fifth embodiment.
- FIG. 19 is a timing chart illustrating data transmission / reception timings according to the fifth embodiment.
- FIG. 1 is a diagram showing the configuration of the programmable controller system according to the first embodiment of the present invention. As shown in FIG. 1, the programmable controller system 1 includes controller units 10A to 10C and a base unit 20.
- the controller units 10A to 10C each have a CPU (a CPU 11 to be described later), and control the programmable controller system 1 by using the CPU 11 included in each of the controller units 10A to 10C. Cooperation between the controller units 10A to 10C is performed by transmitting / receiving control data to / from each other. Specifically, each of the controller units 10A to 10C performs a predetermined calculation by the CPU 11 included in the controller unit 10A to 10C using the control data transmitted from the other controller unit among the controller units 10A to 10C, and the result thereof. To the other controller unit as control data.
- the controller units 10A to 10C correspond to, for example, a PLC unit, a motion controller unit, a robot controller unit, and a CNC unit. Hereinafter, the controller units 10A to 10C may be collectively referred to as the controller unit 10.
- the base unit 20 includes a fixed cycle bus 30.
- the periodic bus 30 assigns time slots capable of data transmission to each of the controller units 10A to 10C in a time-sharing manner.
- Each of the controller units 10A to 10C receives data of a size smaller than the size of the buffer memory for transmission / reception (transmission communication memories 15a and 15b and reception communication memories 16a and 16b described later) via the fixed-cycle bus 30. Can be reliably transferred to the transmission destination within the time slot assigned to the controller unit 10 itself.
- FIG. 2 is a diagram for explaining how data is exchanged between the controller units 10.
- the three time slots constituting the communication cycle are exclusively assigned to the controller units 10A to 10C, respectively. That is, in each time slot, only one of the controller units 10A to 10C can be the controller unit 10 on the transmission side, and communication data does not collide on the fixed-cycle bus 30.
- the controller unit 10 serving as the transmission source transfers data within the time slot allocated to the controller unit 10 with the other two controller units 10 as transmission destinations.
- the product life cycle of the programmable controller system 1 is longer than that of household appliances. Therefore, in order to enable connection of the controller unit 10 even if the period (calculation period) in which the controller unit 10 prepares control data to be transmitted is improved due to future technological advances, the fixed-cycle bus 30 is often used. In some cases, data can be exchanged at a faster communication cycle than the controller unit 10 released on the market at the same time.
- the buffer memory for transmission / reception is configured with a high-speed memory such as SRAM (Static Random Access Memory) incorporated in an interface circuit for transmission / reception (the fixed-cycle bus I / F 14 described later), so the size can be flexibly changed.
- the size of control data to be transmitted generated by the controller unit 10 varies relatively easily depending on user settings and the like. That is, the user can increase the calculation cycle of the controller unit 10 and generate control data of a larger size. As a result, the size of the control data may be larger than the size of the transmission / reception buffer memory.
- control data in order to ensure the temporal reliability of data communication even when the calculation cycle is longer than the communication cycle, the control data is divided into a predetermined number of times. Transmission is made to the transmission destination in the communication cycle. That is, in FIG. 2, data transferred in one time slot (transfer unit data) includes a header part 100 and a data part 101. One control data is divided into a plurality of pieces so as to be transmitted in a plurality of time slots, and each piece of divided data (divided data) is stored in the data unit 101 included in the transfer unit data.
- the header part 100 includes a block number indicating the position of the divided data stored in the data part 101 from the head in the control data before division (hereinafter referred to as communication data).
- various units having different functions such as an A / D conversion unit and a temperature control unit are prepared as units connectable to the base unit 20. .
- the user can select a desired functional unit according to the purpose of use of the programmable controller system 1 and connect it to the base unit 20.
- the controller unit 10 is described as being connected by a fixed cycle bus 30 as an internal bus of the base unit 20, but if data communication can be performed at a fixed cycle, an external bus is used. (Or a network).
- FIG. 3 is a diagram for explaining the configuration of the controller unit 10.
- the controller unit 10 includes a CPU 11, a DRAM 12, a DMA controller 13, and a fixed-cycle bus interface (I / F) 14.
- the CPU 11, DRAM 12, DMA controller 13, and fixed-cycle bus I / F 14 are each connected to the bus.
- the CPU 11 generates communication data for each calculation cycle. Then, the generated communication data is divided, transfer unit data is generated from each divided data, and stored in the DRAM 12. In addition, in order to receive all the communication data sequentially generated, the CPU 11 can divide the communication data up to the number obtained by dividing the calculation cycle by the communication cycle at the maximum. If you want to increase the size of the communication data, the time (calculation cycle) required to generate the communication data increases according to the size of the communication data, so the size of the communication data can be increased by increasing the number of divisions of the communication data. Can handle the increase.
- the CPU 11 combines the transferred divided data and reconstructs the communication data before the division.
- the DRAM 12 stores communication data generated by the CPU 11 and communication data sent from another controller unit 10.
- the fixed-cycle bus I / F 14 is a connection interface for connecting to the fixed-cycle bus 30.
- the buffer memory for data transmission and the buffer memory for data reception each have a double buffer configuration. That is, the fixed-cycle bus I / F 14 includes a transmission communication memory 15a and a transmission communication memory 15b as buffer memories for data transmission, and a reception communication memory 16a and a reception communication memory as buffer memories for data reception. 16b.
- the controller unit 10 can efficiently transmit data by executing the set of the divided data to be transmitted to the buffer memory for data transmission and the transmission of the divided data in parallel at the time of data transmission. Can be executed.
- the transmission communication memories 15 a and 15 b may be collectively referred to as the transmission communication memory 15.
- the reception communication memories 16a and 16b may be collectively referred to as the reception communication memory 16.
- the DMA controller 13 executes data transfer (DMA transfer) between the DRAM 12 and the transmission communication memory 15 or the reception communication memory 16 based on a command from the CPU 11.
- DMA transfer data transfer
- FIG. 4 is a timing chart for explaining the timing of data transmission / reception
- FIG. 5 is a diagram for explaining the flow of data between components.
- the controller unit 10A is a transmission source and the controller unit 10B and the controller unit 10C are transmission destinations
- the description will be made assuming that the calculation cycle is twice as large as the communication cycle and the number of divisions of the communication data is two.
- the operations of the controller unit 10B and the controller unit 10C, which are transmission destinations, are the same, and therefore the operation of the controller unit 10B will be described as a representative here.
- each communication cycle shown in FIG. 4 each of the first to sixth communication cycles
- the notation of the time slot is omitted for the sake of simplicity.
- the data communication from the controller unit 10A to the controller units 10B and 10C is executed using one of the time slots.
- the CPU 11 of the controller unit 10A In the first calculation cycle, the CPU 11 of the controller unit 10A generates communication data. Then, the CPU 11 of the controller unit 10A divides the generated communication data, generates transfer unit data from the respective divided data (divided data D0, divided data D1), and stores the generated respective transfer unit data in the DRAM 12. (Step S1). The CPU 11 of the controller unit 10A writes a block number in each header portion 100 when generating transfer unit data.
- transfer unit data including the divided data D0 in the data portion 101 is referred to as transfer unit data D0
- transfer unit data including the divided data D1 in the data portion 101 is referred to as transfer unit data D1.
- the CPU 11 of the controller unit 10A instructs the DMA controller 13 to transfer the transfer unit data D0 stored in the DRAM 12 from the DRAM 12 to the transmission communication memory 15a (step S2).
- the fixed-cycle bus I / F 14 of the controller unit 10A transmits the transfer unit data D0 stored in the transmission communication memory 15a to the reception communication memory 16a of the controller unit 10B (step S3).
- the CPU 11 of the controller unit 10A instructs the DMA controller 13 to transfer the transfer unit data D1 stored in the DRAM 12 from the DRAM 12 to the transmission communication memory 15b (step S4).
- the CPU 11 of the controller unit 10B refers to the block number described in the header part 100 of the transfer unit data D0 stored in the reception communication memory 16a and instructs the DMA controller 13 to send a command. Then, the divided data D0 stored in the data portion 101 is transferred from the reception communication memory 16a to the DRAM 12 (step S5). In the fifth communication cycle, the fixed-cycle bus I / F 14 of the controller unit 10A transmits the transfer unit data D1 stored in the transmission communication memory 15b to the reception communication memory 16b of the controller unit 10B (step) S6).
- the CPU 11 of the controller unit 10B refers to the block number described in the header unit 100 of the transfer unit data D1 stored in the reception communication memory 16b and instructs the DMA controller 13 to send a command. Then, the divided data D1 stored in the data part 101 is transferred from the reception communication memory 16b to the DRAM 12 (step S7).
- the CPU 11 of the controller unit 10B completes storing the divided data D0 and the divided data D1 in the DRAM 12 of the controller unit 10B by storing the divided data D0 and the divided data D1 in the DRAM 12 so that the addresses are consecutive in the order of the respective block numbers.
- the divided data D1 and D2 may be automatically combined, and as a result, the communication data before the division may be reconstructed.
- the CPU 11 of the controller unit 10B temporarily stores the divided data D0 and the divided data D1 in the DRAM 12 at different positions, and reads the divided data D0 and the divided data D1 that are temporarily stored separately in the DRAM 12, respectively.
- the communication data before the division may be reconstructed by combining them into one.
- the programmable controller system 1 can reliably reach the transmission destination by the end of the third calculation cycle by the communication data generated by the transmission source controller unit 10 in the first calculation cycle.
- the data transfer operation has been described by focusing on one piece of communication data.
- the controller unit 10 generates communication data for each calculation cycle, and the generated communication data is processed in a pipeline process. Transfer sequentially. That is, the programmable controller system 1 causes the communication data generated by the transmission source controller unit 10 to arrive at the transmission destination by the end of the (i + 2) th calculation cycle in the i th calculation cycle, and the transmission destination controller unit 10 i + 3)
- the communication data can be used from the calculation cycle.
- the number of connections of the controller unit 10 to the fixed cycle bus 30 is three, but the number of connections of the controller unit is not limited to three. Even if the number of connections of the controller unit 10 is increased or decreased from 3, only the time slot time for the own controller unit 10 allocated within the communication cycle changes, and the controller unit 10 of the transmission source creates communication data. The timing of a series of processing until the transmission destination controller unit 10 can use the communication data does not change.
- the CPU 11 has been described as performing communication data division, transfer unit data generation, and communication data reconstruction.
- the controller unit 10 executes part or all of these processes.
- a dedicated circuit or processor may be provided separately from the CPU 11.
- the CPU 11 in the controller unit 10 on the transmission side, the CPU 11 generates communication data with a calculation cycle larger than the communication interval of the fixed-cycle bus 30, and generates the generated data.
- the DMA controller 13 stores each of the plurality of transfer unit data in the transmission communication memories 15a and 15b.
- the DMA controller 13 sequentially reads out a plurality of transfer unit data sequentially transferred to the receiving communication memories 16a and 16b at the communication interval. Since the DMA controller 13 combines a plurality of transfer unit data read out to reconstruct the communication data.
- the communication data that is generated for each calculation period may be allowed to surely arrive via the periodic bus 30 for data transfer with a smaller communication period than the calculation period. That is, even when the calculation cycle is longer than the communication cycle, the temporal reliability of the communication data is guaranteed.
- the transmission communication memory 15 and the reception communication memory 16 constitute a double buffer, respectively, for data transfer between the DRAM 12 and the transmission communication memory 15, and between the transmission communication memory 15 and the reception communication memory 16. Since the data transfer (inter-unit transfer process) and the data transfer between the receiving communication memory 16 and the DRAM 12 are executed in pipeline processing, the transfer unit data can be transferred at every communication cycle. it can.
- the communication cycle is time-divided into a plurality of time slots that are exclusively assigned to each of the plurality of controller units 10, and data transfer between the DRAM 12 and the transmission communication memory 15 in the controller unit 10 on the transmission side.
- the CPU 11 included in the transmission-side controller unit 10 generates transfer unit data by attaching a block number for specifying a position in the generated communication data to each divided data, and the receiving-side controller unit 10
- the CPU 11 provided is configured to reconstruct the communication data before the division based on the identification number assigned to the received transfer data.
- FIG. FIG. 6 is a diagram showing the configuration of the programmable controller system according to the second embodiment of the present invention.
- the same components as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.
- the programmable controller system 2 includes controller units 40A to 40C and a base unit 20.
- the controller units 40A to 40C may be collectively referred to as the controller unit 40.
- FIG. 7 is a diagram for explaining the configuration of the controller unit 40.
- the controller unit 40 includes a CPU 41, a DRAM 12, a DMA controller 13, and a fixed-cycle bus I / F 42.
- the CPU 41, DRAM 12, DMA controller 13, and fixed-cycle bus I / F 42 are each connected to the bus.
- the fixed-cycle bus I / F 42 is a connection interface for connecting to the fixed-cycle bus 30.
- the fixed-cycle bus I / F 42 according to the second embodiment includes a transmission communication memory 43 and a reception communication memory 44.
- FIG. 8 is a diagram for explaining how data is exchanged between the controller units 40.
- the communication cycle is composed of four time slots, and the first one of the four time slots is assigned to the DMA transfer. The remaining three are assigned to the controller units 40A to 40C, respectively. That is, according to the second embodiment of the present invention, the data transfer between the DRAM 12 and the transmission / reception buffer memory (the transmission communication memory 43 or the reception communication memory 44), and the transmission communication memory 43 and the reception communication are performed. Data transfer to and from the memory 44 can be continuously executed within a time corresponding to one communication cycle.
- FIG. 9 is a timing chart for explaining the timing of data transmission / reception
- FIG. 10 is a diagram for explaining the flow of data between components.
- the controller unit 40A is a transmission source and the controller unit 40B and the controller unit 40C are transmission destinations
- the notation of the time slot assigned to the controller unit 40 is omitted for the sake of simplicity.
- each time slot is composed of four time slots.
- the CPU 41 of the controller unit 40A In the first calculation cycle, the CPU 41 of the controller unit 40A generates communication data. Then, the CPU 41 of the controller unit 40A divides the generated communication data, generates transfer unit data from the respective divided data (divided data D0, divided data D1), and stores the generated respective transfer unit data in the DRAM 12. (Step S11). The CPU 41 of the controller unit 40A writes a block number in each header portion 100 when generating transfer unit data.
- the CPU 41 of the controller unit 40A instructs the DMA controller 13 to transfer the transfer unit data D0 stored in the DRAM 12 from the DRAM 12 to the transmission communication memory 43 (Ste S12). Thereafter, in the time slot assigned to the controller unit 40A in the third communication cycle, the fixed-cycle bus I / F 42 of the controller unit 40A transfers the transfer unit data D0 stored in the transmission communication memory 43 to the controller unit 40B. The data is transferred to the reception communication memory 44 (step S13).
- the CPU 41 of the controller unit 40B refers to the block number described in the header portion 100 of the transfer unit data D0 stored in the reception communication memory 44, and The DMA controller 13 is instructed to transfer the divided data D0 stored in the data portion 101 from the reception communication memory 44 to the DRAM 12 (step S14).
- the CPU 41 of the controller unit 40A instructs the DMA controller 13 to transfer the transfer unit data D1 stored in the DRAM 12 from the DRAM 12 to the transmission communication memory 43 (step S15). .
- the fixed-cycle bus I / F 42 of the controller unit 40A transfers the transfer unit data D1 stored in the transmission communication memory 43 to the controller unit 40B.
- the data is transferred to the reception communication memory 44 (step S16).
- the CPU 41 of the controller unit 40B refers to the block number described in the header portion 100 of the transfer unit data D1 stored in the reception communication memory 44.
- the DMA controller 13 is instructed to transfer the divided data D1 stored in the data portion 101 from the reception communication memory 44 to the DRAM 12 (step S17). Note that the CPU 41 of the controller unit 40B reconstructs the communication data before the division from the divided data D0 and the divided data D1, similarly to the CPU 11 of the first embodiment.
- the communication cycle is time-divided into a plurality of time slots, and each time slot is assigned to each of the plurality of controller units 40 and the DMA transfer. Since the inter-unit transfer process is executed in the time slot assigned to the unit 40, the inter-unit transfer process and the DMA transfer are performed as one step as shown in Step S12 and Step S13 or Step S13 and Step S14. It can be executed in the time required for the communication cycle. As a result, as shown in FIG. 9, the communication data generated in the first calculation cycle can be used from the middle of the third calculation cycle (beginning of the sixth communication cycle). That is, according to the second embodiment, the time from when the transmission-side controller unit 40 generates communication data until the reception-side controller unit 40 can use the communication data is compared with the first embodiment. And can be shortened.
- Embodiment 3 In the second embodiment, the first time slot of each communication cycle is assigned for DMA transfer. In the third embodiment, the last time slot of each communication cycle is allocated for DMA transfer.
- FIG. 11 is a diagram showing a configuration of the programmable controller system according to the third embodiment of the present invention.
- the same components as those in the first embodiment or the second embodiment are denoted by the same reference numerals, and redundant description is omitted.
- the programmable controller system 3 includes controller units 50A to 50C and a base unit 20.
- the controller units 50A to 50C may be collectively referred to as the controller unit 50.
- FIG. 12 is a diagram for explaining the configuration of the controller unit 50.
- the controller unit 50 includes a CPU 51, a DRAM 12, a DMA controller 13, and a fixed-cycle bus I / F 42.
- the CPU 51, DRAM 12, DMA controller 13, and fixed-cycle bus I / F 42 are each connected to the bus.
- the fixed-cycle bus I / F 42 is a connection interface for connecting to the fixed-cycle bus 30.
- the fixed-cycle bus I / F 42 according to the third embodiment includes a transmission communication memory 43 and a reception communication memory 44.
- FIG. 13 is a timing chart illustrating data transmission / reception timing.
- the controller unit 50A is a transmission source and the controller unit 50B and the controller unit 50C are transmission destinations will be described.
- the time slots assigned to the controller unit 50 are omitted in each communication cycle shown in FIG. 13 (each of the first to sixth communication cycles) for the sake of simplicity.
- each time slot is composed of four time slots.
- processes related to data communication from the controller unit 50A to the controller units 50B and 50C processes other than the DMA transfer use one time slot. Executed.
- the CPU 51 of the controller unit 50A when the CPU 51 of the controller unit 50A generates the first half of the communication data, the CPU 51 generates transfer unit data D0 from the communication data (divided data D0) of the first half, and generates the generated transfer unit. Data D0 is stored in DRAM 12 (step S21). Thereafter, in the second communication cycle, when the CPU 51 of the controller unit 50A generates the latter half of the communication data, it generates transfer unit data D1 from the latter half of the communication data (divided data D1), and generates the generated transfer unit. Data D1 is stored in DRAM 12 (step S22). The CPU 51 of the controller unit 50A writes a block number in each header portion 100 when generating transfer unit data.
- the CPU 51 of the controller unit 50A instructs the DMA controller 13 to transfer the transfer unit data D0 stored in the DRAM 12 from the DRAM 12 to the transmission communication memory 43. Transfer (step S23).
- the fixed-cycle bus I / F 42 of the controller unit 50A transfers the transfer unit data D0 stored in the transmission communication memory 43 to the reception communication memory 44 of the controller unit 50B (step S24).
- the CPU 51 of the controller unit 50B refers to the block number described in the header part 100 of the transfer unit data D0 stored in the reception communication memory 44.
- the DMA controller 13 is instructed to transfer the divided data D0 stored in the data part 101 from the reception communication memory 44 to the DRAM 12 (step S25).
- the CPU 51 of the controller unit 50A instructs the DMA controller 13 to transfer the transfer unit data D1 stored in the DRAM 12 from the DRAM 12 to the transmission communication memory 43 (step). S26).
- the fixed-cycle bus I / F 42 of the controller unit 50A transfers the transfer unit data D1 stored in the transmission communication memory 43 to the reception communication memory 44 of the controller unit 50B (step S27).
- the CPU 51 of the controller unit 50B refers to the block number described in the header portion 100 of the transfer unit data D1 stored in the reception communication memory 44.
- the DMA controller 13 is instructed to transfer the divided data D1 stored in the data section 101 from the reception communication memory 44 to the DRAM 12 (step S28). Note that the CPU 51 of the controller unit 50B reconstructs the communication data before the division from the divided data D0 and the divided data D1, similarly to the CPU 11 of the first embodiment.
- the time slot for DMA transfer is secured at the end of the communication cycle, and the CPU 51 stores the communication data without waiting for the completion of the communication data every communication cycle. Since the transfer unit data is generated from a part of the generated data, as shown in step S23 of FIG. 13, the DMA transfer for the communication data can be started before the communication data is completed. become. That is, the time from when the transmission-side controller unit 50 generates communication data to when the reception-side controller unit 50 becomes able to use the communication data can be further reduced as compared with the second embodiment.
- FIG. 14 is a diagram showing a configuration of a programmable controller system according to the fourth embodiment of the present invention.
- the same components as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.
- the programmable controller system 4 includes controller units 60A to 60C and a base unit 20.
- the controller units 60A to 60C may be collectively referred to as the controller unit 60.
- FIG. 15 is a diagram for explaining the configuration of the controller unit 60.
- the controller unit 60 includes a CPU 61, a DRAM 12, a DMA controller 13, and a fixed-cycle bus I / F 14.
- the CPU 61, DRAM 12, DMA controller 13, and fixed-cycle bus I / F 14 are each connected to the bus.
- the fixed-cycle bus I / F 14 is a connection interface for connecting to the fixed-cycle bus 30.
- the fixed-cycle bus I / F 14 according to the fourth embodiment includes a transmission communication memory 15a, a transmission communication memory 15b, a reception communication memory 16a, and a reception communication memory 16b.
- FIG. 16 is a timing chart illustrating data transmission / reception timing.
- the controller unit 60A is a transmission source and the controller unit 60B and the controller unit 60C are transmission destinations will be described. Note that, in the respective communication cycles shown in FIG. 16 (each of the first to sixth communication cycles), the notation of the time slot assigned to the controller unit 60 is omitted for the sake of simplicity.
- the process is composed of three time slots, and the processing related to data communication from the controller unit 60A to the controller units 60B and 60C is executed using one of the time slots.
- the CPU 61 of the controller unit 60A when the CPU 61 of the controller unit 60A generates the first half of the communication data, the CPU 61 generates transfer unit data D0 from the communication data (divided data D0) of the first half, and generates the generated transfer unit. Data D0 is stored in transmission communication memory 15a (step S31).
- the fixed-cycle bus I / F 14 of the controller unit 60A transfers the transfer unit data D0 stored in the transmission communication memory 15a to the reception communication memory 16a of the controller unit 60B (step S32).
- the CPU 61 of the controller unit 60A instructs the DMA controller 13 to transfer the transfer unit data D0 stored in the transmission communication memory 15a from the transmission communication memory 15a to the DRAM 12.
- Step S33 when the CPU 61 of the controller unit 60A generates the latter half of the communication data, it generates the transfer unit data D1 from the communication data (divided data D1) of the latter half, and generates the generated transfer unit.
- Data D1 is stored in transmission communication memory 15b (step S34).
- the CPU 61 of the controller unit 60A writes a block number in each header section 100 when generating transfer unit data.
- the CPU 61 of the controller unit 60A instructs the DMA controller 13 to transfer the transfer unit data D1 stored in the transmission communication memory 15b from the transmission communication memory 15b to the DRAM 12 (step S35).
- the fixed-cycle bus I / F 14 of the controller unit 60A transfers the transfer unit data D1 stored in the transmission communication memory 15b to the reception communication memory 16b of the controller unit 60B (step S36).
- the CPU 61 of the controller unit 60B instructs the DMA controller 13 to transfer the transfer unit data D0 stored in the reception communication memory 16a from the reception communication memory 16a to the DRAM 12 (step S37).
- the process of step S36 and step S37 is performed simultaneously with the process of step S35.
- the CPU 61 of the controller unit 60B instructs the DMA controller 13 to transfer the transfer unit data D1 stored in the reception communication memory 16b from the reception communication memory 16b to the DRAM 12 (step S38).
- the CPU 61 of the controller unit 60B reconstructs the communication data before the division from the divided data D0 and the divided data D1, similarly to the CPU 11 of the first embodiment.
- the CPU 61 in the controller unit 60 on the transmission side, the CPU 61 generates communication data that is completed in a calculation cycle that is larger than the communication cycle, for each communication cycle, Each of the generated divided data is directly stored in the transmission communication memory 15 without going through the DRAM 12, and in the controller unit 60 on the reception side, the DMA controller 13 has been transferred to the reception communication memory 16 by inter-unit transfer processing. Since the CPU 61 is configured to sequentially read out the plurality of divided data for each communication cycle and combine the plurality of divided data read out by the DMA controller 13 to construct the communication data, the transmission communication memory via the DRAM 12 is configured. 15 compared with the case where the divided data is stored in 15, the controller unit 60 on the transmission side transmits the communication data. It forms the controller unit 60 of the receiving side after it is possible to reduce the time to be able to utilize the communication data.
- the DMA controller 13 sequentially reads a plurality of divided data stored in the transmission communication memory 15 every communication cycle, and the CPU 61 reads a plurality of divided data read by the DMA controller 13.
- the controller unit 60 on the transmission side is also constructed. Can use the communication data transmitted to the controller unit 60 on the receiving side.
- the transmission communication memory 15 and the reception communication memory 16 each constitute a double buffer, and data transfer between the DRAM 12 and the transmission communication memory 15, inter-unit transfer processing, and between the reception communication memory 16 and the DRAM 12. Since the data transfer between them is executed by pipeline processing, transfer unit data can be transferred at every communication cycle.
- the communication cycle is time-divided into a plurality of time slots that are exclusively assigned to each of the plurality of controller units 60, and processing for storing the divided data in the transmission-side controller unit 60 in the transmission communication memory 15,
- the inter-unit transfer process between the transmission-side controller unit 60 and the reception-side controller unit 60 and the data transfer between the reception communication memory 16 and the DRAM 12 in the reception-side controller unit 60 are performed by the transmission-side controller unit. Since it is configured to be executed in the time slot assigned to 60, collision of communication data among a plurality of controller units 60 can be prevented.
- FIG. 17 is a diagram showing a configuration of a programmable controller system according to the fifth embodiment of the present invention.
- the same components as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.
- the programmable controller system 5 includes controller units 70A to 70C and a base unit 20.
- the controller units 70A to 70C may be collectively referred to as the controller unit 70.
- FIG. 18 is a diagram for explaining the configuration of the controller unit 70.
- the controller unit 70 includes a CPU 71, a DRAM 12, a DMA controller 13, and a fixed cycle bus I / F 72.
- the CPU 71, DRAM 12, DMA controller 13, and fixed-cycle bus I / F 72 are each connected to the bus.
- the fixed-cycle bus I / F 72 is a connection interface for connecting to the fixed-cycle bus 30.
- the fixed-cycle bus I / F 72 according to the fifth embodiment includes a transmission communication memory 73a, a transmission communication memory 73b, and a reception communication memory 74.
- FIG. 19 is a timing chart illustrating data transmission / reception timing.
- the controller unit 70A is a transmission source and the controller unit 70B and the controller unit 70C are transmission destinations will be described.
- Each communication cycle shown in FIG. 19 (each of the first to sixth communication cycles) is omitted from the description of the time slot assigned to the controller unit 70 for the sake of simplicity.
- the process is composed of four time slots, and the process related to data communication from the controller unit 70A to the controller units 70B and 70C is executed using one of the time slots except for the process related to DMA transfer.
- the CPU 71 of the controller unit 70A when the CPU 71 of the controller unit 70A generates the first half of the communication data, the CPU 71 generates transfer unit data D0 from the communication data (division data D0) of the first half, and generates the generated transfer unit. Data D0 is stored in transmission communication memory 73a (step S41). Thereafter, in the time slot for DNA transfer in the first communication cycle, the CPU 71 of the controller unit 70A instructs the DMA controller 13 to transfer the transfer unit data D0 stored in the transmission communication memory 73a to the transmission communication memory. The data is transferred from 73a to the DRAM 12 (step S42).
- the fixed-cycle bus I / F 72 of the controller unit 70A transfers the transfer unit data D0 stored in the transmission communication memory 73a to the reception communication memory 74 of the controller unit 70B (step S43).
- the CPU 71 of the controller unit 70A when the CPU 71 of the controller unit 70A generates the latter half of the communication data, the CPU 71 generates the transfer unit data D1 from the communication data (divided data D1) of the latter half.
- the transfer unit data D1 is stored in the transmission communication memory 73b (step S44).
- the CPU 71 of the controller unit 70A writes the block number in each header portion 100 when generating the transfer unit data.
- step S43 and step S44 the CPU 71 of the controller unit 70A instructs the DMA controller 13 to transfer data stored in the transmission communication memory 73b.
- the unit data D1 is transferred from the transmission communication memory 73b to the DRAM 12 (step S45).
- step S45 the CPU 71 of the controller unit 70B instructs the DMA controller 13 to transfer the transfer unit data D0 stored in the reception communication memory 74 from the reception communication memory 74 to the DRAM 12 (step S45). S46).
- the fixed-cycle bus I / F 72 of the controller unit 70A transfers the transfer unit data D1 stored in the transmission communication memory 73b to the reception communication memory 74 of the controller unit 70B (step S47).
- the CPU 71 of the controller unit 70B instructs the DMA controller 13 to transfer the transfer unit data D1 stored in the reception communication memory 74 to the reception communication memory.
- the data is transferred from 74 to the DRAM 12 (step S48). Note that the CPU 71 of the controller unit 70B reconstructs the communication data before the division from the divided data D0 and the divided data D1, similarly to the CPU 11 of the first embodiment.
- the time slot for DMA transfer is secured at the end of the communication cycle, and the CPU 71 does not wait for the completion of the communication data for each communication cycle. Since the divided data that is already generated is stored in the transmission communication memory 73, as shown in step S42 in FIG. 19, before the communication data is completed, the DMA transfer related to the communication data is performed. Will be able to start. That is, the time from when the transmission-side controller unit 70 generates the communication data until the reception-side controller unit 70 can use the communication data can be further reduced as compared with the fourth embodiment.
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Abstract
Description
図1は、本発明にかかる実施の形態1のプログラマブルコントローラシステムの構成を示す図である。図1に示すように、プログラマブルコントローラシステム1は、コントローラユニット10A~10Cとベースユニット20とを備えて構成されている。
図6は、本発明にかかる実施の形態2のプログラマブルコントローラシステムの構成を示す図である。なお、ここでは、実施の形態1と同じ構成要素には同一の符号を付して、重複する説明を省略する。図6に示すように、プログラマブルコントローラシステム2は、コントローラユニット40A~40Cとベースユニット20とを備えて構成されている。以降、コントローラユニット40A~40Cをコントローラユニット40と総称する場合がある。
実施の形態2では、各交信周期の先頭のタイムスロットがDMA転送用に割り当てられていた。実施の形態3においては、各交信周期の末尾のタイムスロットがDMA転送用に割り当てられる。
図14は、本発明にかかる実施の形態4のプログラマブルコントローラシステムの構成を示す図である。なお、ここでは、実施の形態1と同じ構成要素には同一の符号を付して、重複する説明を省略する。図14に示すように、プログラマブルコントローラシステム4は、コントローラユニット60A~60Cとベースユニット20とを備えて構成されている。以降、コントローラユニット60A~60Cをコントローラユニット60と総称する場合がある。
図17は、本発明にかかる実施の形態5のプログラマブルコントローラシステムの構成を示す図である。なお、ここでは、実施の形態1と同じ構成要素には同一の符号を付して、重複する説明を省略する。図17に示すように、プログラマブルコントローラシステム5は、コントローラユニット70A~70Cとベースユニット20とを備えて構成されている。以降、コントローラユニット70A~70Cをコントローラユニット70と総称する場合がある。
10、40、50、60、70、10A~10C、40A~40C、50A~50C、60A~60C、70A~70C コントローラユニット
11、41、51、61、71 CPU
12 DRAM
13 DMAコントローラ
14、42、72 定周期バスI/F
15、15a、15b、43、73a、73b 送信用交信メモリ
16、16a、16b、44、74 受信用交信メモリ
20 ベースユニット
30 定周期バス
100 ヘッダ部
101 データ部
Claims (12)
- バッファメモリを備えるバスインタフェースを夫々備える複数のコントローラユニットと、前記バスインタフェースを介して前記複数のコントローラシステムを接続し、前記複数のコントローラユニットのうちの送信側のコントローラユニットのバスインタフェースが備えるバッファメモリの記憶内容を受信側のコントローラユニットのバスインタフェースが備えるバッファメモリに転送するユニット間転送処理を第1の時間間隔で実行するバスと、を備えるプログラマブルコントローラシステムであって、
前記送信側のコントローラユニットは、
前記第1の時間間隔よりも大きい第2の時間間隔で交信データを生成するデータ生成部と、
前記データ生成部が生成した交信データを分割して前記第2の時間間隔を前記第1の時間間隔で除して得られる値以下の数の転送単位データを生成するデータ分割部と、
前記データ分割部が生成した複数の転送単位データの夫々を自コントローラユニットのバスインタフェースが備えるバッファメモリに前記第1の時間間隔で順次格納するデータ格納部と、
を備え、
前記受信側のコントローラユニットは、
前記ユニット間転送処理により自コントローラユニットのバッファメモリに前記第1の時間間隔で順次転送されてくる複数の転送単位データを前記第1の時間間隔で順次読み出すデータ読み出し部と、
前記データ読み出し部が読み出した複数の転送単位データを結合して前記データ生成部が生成した交信データを再構築するデータ結合部と、
を備える、
ことを特徴とするプログラマブルコントローラシステム。 - 前記バッファメモリはダブルバッファ構成を備え、
前記データ格納部が転送単位データを格納する処理と、前記ユニット間転送処理と、前記データ読み出し部が転送単位データを読み出す処理と、を前記ダブルバッファ構成のバッファメモリを使用してパイプライン処理的に実行する、
ことを特徴とする請求項1に記載のプログラマブルコントローラシステム。 - 前記第1の時間間隔は、前記複数のコントローラユニットの夫々に排他的に割り当てられる複数のタイムスロットに時分割されており、
前記データ格納部が転送単位データを格納する処理と、前記ユニット間転送処理と、前記データ読み出し部が転送単位データを読み出す処理とは、前記送信側のコントローラユニットに割り当てられたタイムスロットにおいて実行される、
ことを特徴とする請求項2に記載のプログラマブルコントローラシステム。 - 前記第1の時間間隔は、前記複数のコントローラユニットの夫々に排他的に割り当てられる第1のタイムスロットであって前記ユニット間転送処理が実行される第1のタイムスロットと、前記データ格納部が転送単位データを格納する処理と前記データ読み出し部が転送単位データを読み出す処理とが実行される第2のタイムスロットとを含む複数のタイムスロットに分割されている、
ことを特徴とする請求項1に記載のプログラマブルコントローラシステム。 - 前記第2のタイムスロットは、前記第1の時間間隔の末尾に位置し、
前記データ分割部は、前記第1の時間間隔毎に、交信データの完成を待つことなく当該交信データの生成済みの一部から転送単位データを生成する、
ことを特徴とする請求項4に記載のプログラマブルコントローラシステム。 - 前記データ分割部は、前記データ生成部が生成した交信データにおける位置を特定するための識別番号を夫々の分割データに付して前記複数の転送単位データを生成し、
前記データ結合部は、前記複数の転送データに付されている識別番号に基づいて前記データ生成部が生成した交信データを再構築する、
ことを特徴とする請求項1乃至請求項5のうちの何れか一項に記載のプログラマブルコントローラシステム。 - バッファメモリを備えるバスインタフェースを夫々備える複数のコントローラユニットと、前記バスインタフェースを介して前記複数のコントローラシステムを接続し、前記複数のコントローラユニットのうちの送信側のコントローラユニットが備えるバッファメモリの記憶内容を受信側のコントローラユニットが備えるバッファメモリに第1の時間間隔で転送するユニット間転送処理を実行するバスと、を備えるプログラマブルコントローラシステムであって、
前記送信側のコントローラユニットは、前記第1の時間間隔よりも大きい第2の時間間隔毎に完成する交信データを、前記第1の時間間隔毎に分割して生成し、前記生成した分割データの夫々を自コントローラユニットのバスインタフェースが備えるバッファメモリに前記第1の時間間隔で順次格納するデータ生成部を備え、
前記受信側のコントローラユニットは、
前記ユニット間転送処理により自コントローラユニットのバスインタフェースが備えるバッファメモリに前記第1の時間間隔で順次転送されてくる複数の分割データを前記第1の時間間隔で順次読み出す第1データ読み出し部と、
前記第1データ読み出し部が読み出した複数の分割データを結合して前記データ生成部が完成する交信データを構築する第1データ結合部と、
を備える、
ことを特徴とするプログラマブルコントローラシステム。 - 前記送信側のコントローラユニットは、
前記データ生成部が自コントローラユニットのバスインタフェースが備えるバッファメモリに順次格納した複数の分割データを前記第1の時間間隔で順次読み出す第2データ読み出し部と、
前記第2データ読み出し部が読み出した複数の分割データを結合して前記データ生成部が完成する交信データを構築する第2データ結合部と、
を備える、
ことを特徴とする請求項7に記載のプログラマブルコントローラシステム。 - 前記第2データ読み出し部が分割データを読み出す処理と、当該分割データにかかる前記ユニット間転送処理と、を同時並行的に実行する、
ことを特徴とする請求項7に記載のプログラマブルコントローラシステム。 - 前記バッファメモリはダブルバッファ構成を備え、
前記データ生成部が分割データを格納する処理と、前記ユニット間転送処理と、前記第1データ読み出し部が分割データを読み出す処理と、を前記ダブルバッファ構成のバッファメモリを使用してパイプライン処理的に実行する、
ことを特徴とする請求項7または請求項8に記載のプログラマブルコントローラシステム。 - 前記第1の時間間隔は、前記複数のコントローラユニットの夫々に排他的に割り当てられる複数のタイムスロットに時分割されており、
前記データ生成部が分割データを格納する処理と、前記ユニット間転送処理と、前記第1データ読み出し部が分割データを読み出す処理とは、前記送信側のコントローラユニットに割り当てられたタイムスロットにおいて実行される、
ことを特徴とする請求項9に記載のプログラマブルコントローラシステム。 - 前記第1の時間間隔は、前記複数のコントローラユニットの夫々に排他的に割り当てられる第1のタイムスロットであって前記データ生成部が分割データを生成して格納する処理と前記ユニット間転送処理とが同時並行的に実行される第1のタイムスロットと、前記第1の時間間隔の末尾に位置し、前記第1データ読み出し部が分割データを読み出す処理に割り当てられてられる第2のタイムスロットと、を含む複数のタイムスロットに分割されている、
ことを特徴とする請求項7または請求項8に記載のプログラマブルコントローラシステム。
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Also Published As
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JPWO2012169037A1 (ja) | 2015-02-23 |
CN103597416A (zh) | 2014-02-19 |
DE112011105318T5 (de) | 2014-03-06 |
JP5523630B2 (ja) | 2014-06-18 |
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