WO2012164926A1 - 抵抗変化型不揮発性記憶装置 - Google Patents
抵抗変化型不揮発性記憶装置 Download PDFInfo
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- WO2012164926A1 WO2012164926A1 PCT/JP2012/003543 JP2012003543W WO2012164926A1 WO 2012164926 A1 WO2012164926 A1 WO 2012164926A1 JP 2012003543 W JP2012003543 W JP 2012003543W WO 2012164926 A1 WO2012164926 A1 WO 2012164926A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/32—Material having simple binary metal oxide structure
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
Definitions
- a so-called 1D1R type cross-point memory which is a non-volatile memory device in which memory cells are arranged in a matrix form.
- a memory cell is arranged at the intersection of a bit line and a word line arranged orthogonally.
- This memory cell includes a bidirectional diode element that functions as a current control element, and a resistance change element connected in series to the bidirectional diode element.
- a nonvolatile memory device in which memory cells of a 1D1R type cross-point memory are stacked in multiple layers is also known. Conventionally, various methods have been proposed for writing a memory cell of a nonvolatile memory device using such a resistance change element.
- Patent Document 1 proposes a method of applying a voltage to a word line and a bit line in an initial break operation, which is an operation for initializing a memory cell, for a memory cell of a 1D1R type cross-point memory.
- FIG. 20 is a diagram showing a configuration of a memory cell array of the nonvolatile memory device shown therein.
- FIG. 21 also shows voltage waveforms applied to the selected word line, the non-selected word line, the selected bit line, and the non-selected bit line when the memory cell array is initially broken.
- the nonvolatile memory device of Patent Document 1 applies a selection potential (VSS in this figure) to a selected word line, and simultaneously sets a plurality of selected bit lines in a floating state.
- a selection potential VSS in this figure
- the voltages of the bit lines connected to the memory cells for which the initial break has ended are individually lowered. Therefore, even if the initial break time varies depending on the bits, the initial break is performed stably.
- variable resistance nonvolatile memory device is required to perform an initial break operation more stably.
- a resistance change element that changes to a high resistance state having a resistance value belonging to a second range higher than the first range is connected in series to the resistance change element Two-terminal current control element, and the variable resistance nonvolatile element
- the memory device applies the low-resistance voltage having the first polarity whose absolute value is equal to or higher than the first voltage to the memory cell via the corresponding first signal line and second signal line. Accordingly, the resistance change element that changes the resistance change element to the low resistance state, and the absolute value of the second voltage is applied to the memory cell via the first signal line and the second signal line corresponding thereto.
- FIG. 10 is a diagram showing a configuration of a variable resistance nonvolatile memory device according to a modification of the first embodiment of the present invention.
- FIG. 11A is a circuit diagram of a current limiting circuit, a first HR drive circuit, and a second LR drive circuit according to a modification of the first embodiment of the present invention.
- FIG. 11B is a circuit diagram of the first LR drive circuit and the second HR drive circuit according to a modification of the first embodiment of the present invention.
- FIG. 12 is a circuit diagram of a current limiting circuit and a control circuit according to a modification of the first embodiment of the present invention.
- FIG. 13A is a timing chart showing an operation of the variable resistance nonvolatile memory device according to Embodiment 1 of the present invention.
- FIG. 13A is a timing chart showing an operation of the variable resistance nonvolatile memory device according to Embodiment 1 of the present invention.
- FIG. 13B is a timing chart showing an operation of the variable resistance nonvolatile memory device according to Embodiment 1 of the present invention.
- FIG. 14 is a diagram showing a configuration of a memory cell array according to the second embodiment of the present invention.
- FIG. 15 is a diagram showing a block selection order according to the second embodiment of the present invention.
- FIG. 16 is a diagram showing a block selection order according to the second embodiment of the present invention.
- FIG. 17 is a diagram showing a block selection order according to the second embodiment of the present invention.
- FIG. 18 is a diagram showing a block selection order according to the second embodiment of the present invention.
- FIG. 19 is a diagram showing a configuration of a memory cell array according to a modification of the second embodiment of the present invention.
- FIG. 19 is a diagram showing a configuration of a memory cell array according to a modification of the second embodiment of the present invention.
- the inventors of the present application examined a method of initial break operation in a 1D1R type cross-point memory array using a memory cell including a current control element and a resistance change element as one of resistance change type nonvolatile memory devices.
- the resistance value of the memory cell is usually smaller than the resistance value immediately after manufacture.
- the present embodiment is a 1D1R type cross-point memory array using a resistance change type nonvolatile memory element, and the resistance change element is stably set to the initial break regardless of the position in the memory cell array.
- a possible nonvolatile memory device will be described.
- variable resistance nonvolatile memory device further includes a plurality of inter-block switches provided between the blocks of the first signal line, and the write circuit is connected to the selected first block. After the initial break of a plurality of included memory cells, between the block provided between the first block and a second block adjacent to the one circuit side with respect to the first block The initial break may be performed on the second block after the switch is turned off.
- variable resistance nonvolatile memory device can eliminate the leakage current to the memory cell that has been subjected to the initial break.
- the variable resistance nonvolatile memory device can perform the initial break of the selected cell without being affected by the leakage current, so that the variable resistance element can be initialized more stably.
- variable resistance nonvolatile memory device is further inserted in a path of current flowing from the write circuit to the plurality of memory cells, and a current in a first direction that changes the plurality of memory cells to a high resistance state.
- a current limiting circuit that limits only the current in the first direction among the current in the second direction that changes the plurality of memory cells to the low resistance state, and the write circuit includes the memory in the initial break.
- the initial break voltage having the second polarity may be applied to the cell, and the current limiting circuit may limit the current in the first direction flowing through the path in the initial break.
- Each of the memory cells has the first polarity with a voltage of the first signal line higher than the voltage of the second signal line via the connected first signal line and second signal line. It changes to the low resistance state when a first voltage is applied, and changes to the high resistance state when a second voltage having the second polarity opposite to the first polarity is applied.
- the write circuit includes a first drive circuit that generates a first drive voltage that is greater than or equal to the first voltage, a second drive circuit that generates a second drive voltage that is greater than or equal to the second voltage, and the first drive.
- variable resistance nonvolatile memory device further switches conduction and non-conduction between the capacitive load element, a node between the current limiting circuit and the first selection circuit, and the capacitive load element.
- a selection switch, and the selection switch may connect the node and the capacitive load element during the initial break.
- variable resistance nonvolatile memory device can suppress fluctuations in the voltage of the first signal line during the initial break. Therefore, the variable resistance nonvolatile memory device can perform an initial break more stably.
- the present invention can be realized not only as such a resistance variable nonvolatile device, but also as an initial break method of the variable resistance nonvolatile device having the characteristic means included in the variable resistance nonvolatile device as a step. it can. Further, the present invention can be realized as a method of manufacturing a variable resistance nonvolatile device for manufacturing such a variable resistance nonvolatile device.
- the present invention can be realized as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a variable resistance nonvolatile device, or a memory device including such a variable resistance nonvolatile device. I can do it.
- LSI semiconductor integrated circuit
- the resistance change element 1 can be in at least a low resistance state and a high resistance state, and stores information by reversibly changing a resistance value (resistance state) based on an applied electrical signal. Can do. That is, when the resistance change element 1 is in the high resistance state, the resistance change element 1 changes to the low resistance state when the absolute value of the voltage applied to the resistance change element 1 exceeds the predetermined first voltage, and when the resistance change element 1 is in the low resistance state When the absolute value of the voltage applied to the resistance change element 1 in the opposite direction (reverse polarity) to the first voltage application direction (application polarity) exceeds a predetermined second voltage, the first voltage changes to the high resistance state. Has characteristics.
- FIG. 2 shows an example of voltage-current characteristics of the current control element 2. It (> 0) is a predetermined current value for determining a threshold voltage, V1 is a first threshold voltage (positive threshold voltage), and V2 is a second threshold voltage (negative threshold voltage). As shown in FIG. 2, this characteristic is non-linear, and in the region where the voltage V satisfies V2 ⁇ V ⁇ V1, the resistance is large and no current flows substantially. At this time, if the current flowing through the current control element 2 is I, I satisfies the relationship ⁇ It ⁇ I ⁇ It. On the other hand, in the region where the voltage V satisfies V ⁇ V2 or V1 ⁇ V, the resistance value decreases rapidly and a large current flows. At this time, It ⁇ I in the region satisfying V1 ⁇ V, and I ⁇ ⁇ It in the region satisfying V ⁇ V2.
- the threshold voltage means a voltage when a predetermined current flows.
- the predetermined current here is a value that can be arbitrarily determined in order to determine the threshold voltage, and is determined by the characteristics of the element controlled by the current control element 2 or the characteristics of the current control element 2.
- the threshold current is determined as the current at the time of switching from a state in which no current substantially flows to a state in which a large current flows.
- the magnitude of the current at the positive voltage and the magnitude of the current at the negative voltage are described symmetrically at the origin, but these are not necessarily symmetrical.
- it may be
- a 1-bit storage element is realized by the bidirectional memory cell 10 provided between the bit line 11 and the word line 12.
- one end of the resistance change element 1 is connected to the bit line 11, the other end of the resistance change element 1 and one end of the current control element 2 are connected, and the other end of the current control element 2 is Although the word line 12 is connected, one end of the resistance change element 1 is connected to the word line 12, the other end of the resistance change element 1 and one end of the current control element 2 are connected, and the current control element 2 The other end may be connected to the bit line 11.
- FIG. 3A and 3B are conceptual diagrams showing a three-dimensional structure including the memory cell 10.
- FIG. 3A shows a three-dimensional structure of a so-called single-layer cross-point memory cell.
- the memory cell 10 is arranged between the bit line 11 and the word line 12 at the intersection of the bit line 11 and the word line 12 arranged so as to be orthogonal to each other.
- the oxygen deficiency of the second tantalum oxide layer is less than the oxygen deficiency of the first tantalum oxide layer.
- the oxygen content of the second tantalum oxide layer is higher than the oxygen content of the first tantalum oxide layer.
- the degree of oxygen deficiency refers to the proportion of oxygen that is deficient with respect to the amount of oxygen constituting the oxide of the stoichiometric composition in each transition metal.
- the transition metal is tantalum (Ta)
- the stoichiometric oxide composition is Ta 2 O 5 , and thus can be expressed as TaO 2.5 .
- the degree of oxygen deficiency of TaO 2.5 is 0%.
- the metal constituting the resistance change layer 16 may be a transition metal other than tantalum.
- the transition metal tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), or the like can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions. For example, when hafnium oxide is used to form a variable resistance layer having a laminated structure, x is 0.9 when the composition of the first hafnium oxide layer that is the first transition metal oxide layer 16a is HfO x.
- the thickness of the second zirconium oxide layer is preferably 1 to 5 nm.
- the 1st transition metal oxide layer 16a comprised by the 1st transition metal, and the 2nd transition metal comprised by the 2nd transition metal different from a 1st transition metal A stacked structure including the oxide layer 16b may be used as the resistance change layer 16, the 1st transition metal oxide layer 16a comprised by the 1st transition metal, and the 2nd transition metal comprised by the 2nd transition metal different from a 1st transition metal A stacked structure including the oxide layer 16b may be used.
- the oxygen deficiency of the second transition metal oxide layer 16b is smaller than the oxygen deficiency of the first transition metal oxide layer 16a.
- the resistance value of the second transition metal oxide layer 16b is higher than the resistance value of the first transition metal oxide layer 16a.
- the resistance change phenomenon in the resistance change film having the laminated structure of each material described above is caused by a redox reaction occurring in a minute filament formed in the second transition metal oxide layer 16b having a high resistance. It is considered that the resistance value changes, and as a result, occurs. That is, when a positive voltage is applied to the upper electrode 17 on the second transition metal oxide layer 16b side with respect to the internal electrode 15, oxygen ions in the resistance change layer 16 are converted into the second transition metal oxide layer. By being drawn toward the 16b side, an oxidation reaction occurs in a minute filament formed in the second transition metal oxide layer 16b. This is thought to increase the resistance of the microfilament.
- the current control element 2 includes, for example, a lower electrode 13 made of tantalum nitride and a semiconductor layer 14 made of a nitrogen-deficient silicon nitride film having a nitrogen content smaller than that of Si 3 N 4. And an internal electrode 15 made of tantalum nitride.
- the thickness of the semiconductor layer 14 can be 3 to 20 nm, for example.
- the silicon nitride film can be formed to have semiconductor characteristics by reducing the nitrogen content, and the current control element 2 configured as an MSM diode can be manufactured by a simple manufacturing process.
- a nitrogen-deficient silicon nitride film (SiN z : 0 ⁇ z ⁇ 1.33) can be formed by reactive sputtering in a nitrogen gas atmosphere using a Si target, for example.
- the chamber pressure may be 0.1 Pa to 1 Pa and the Ar / N 2 flow rate may be 18 sccm / 2 sccm at room temperature.
- the initial break voltage varies for each resistance change element 1 constituting the memory cell array, or the resistance change element 1 is initially set to change to a state in which the resistance change starts.
- the initial break voltage to be applied is increased.
- the data input / output circuit 107 reduces the resistance or increases the resistance change element Rij in the selected memory cell Mij in accordance with the write instruction of the data “0” or the data “1” of the data input signal Din.
- Write resistance In the present embodiment, data “0” writing corresponds to low resistance writing, and data “1” writing corresponds to high resistance writing.
- the write circuit 105 is connected to the data input / output circuit 107.
- the write circuit 105 includes a first LR drive circuit 105a1 that drives a high level and a second LR drive circuit 105c2 that drives a low level when performing data “0” write, that is, low resistance write. Yes.
- the write circuit 105 includes a first HR drive circuit 105c1 that drives a high level when data “1” is written, that is, high resistance write, and an output terminal of the first HR drive circuit 105c1 connected to an input terminal.
- Current limiting circuit 105b, and a second HR driving circuit 105a2 for driving the low level.
- the output voltage of the inverter circuit becomes the ground potential. Therefore, since the gate of the current limiting circuit 105b rises to the voltage VCLH via the PMOS transistor MP5, the current flowing through the current limiting circuit 105b decreases.
- the threshold voltage of the inverter circuit is set to a voltage required when the resistance change element Rij breaks initially and VCLH is applied to the gate input of the current limiting circuit 105b, the PMOS transistor MP3 is connected to the current control element 2. If the current value is set so as not to decrease the reliability, an appropriate current limit value can be obtained at the time when the variable resistance element initially breaks.
- the selection switch 111b switches between conduction and non-conduction between a node between the current limiting circuit 105b and the row selection circuit 103 and the capacitive load element 111a.
- the write circuit 105 first applies an initial break voltage to the word line WL1 and the bit line BLn in order to perform an initial break on the memory cells in the block 120-x, and then the memory cell located at this intersection. The initial break.
- the write circuit 105 applies initial break voltages in the order of WL2 and BLn, WL1 and BLn-1, WL2 and BLn-1, and initially breaks the memory cells located at the respective intersections. That is, the write circuit 105 is arranged at a position closest to the row selection circuit 103 from a memory cell arranged at a position farthest from the row selection circuit 103 among a plurality of memory cells included in each selected block.
- the memory cells are sequentially selected in the order of going to the memory cell, and the initial break is performed on the selected memory cells.
- the order of block selection as shown in FIG. 15 can be considered.
- the write circuit 105 includes the uppermost word line (the word line farthest from the column selection circuit 104) among the plurality of existing word lines and the rightmost bit line (row) among the plurality of existing bit lines. From the block (the upper right corner block in the memory cell array 102 in FIG. 15) including the memory cell intersected by the bit line farthest from the selection circuit 103, the lowermost word line and the plurality of word lines.
- the blocks may be sequentially selected in a zigzag order in the order of the block including the memory cell intersected by the leftmost bit line (the block in the lower left corner of FIG. 15).
- the write circuit 105 selects in units of blocks, but may select in units of memory cells.
- the write circuit 105 sets the switch selection signal VAS-x to the ground potential and NVAS-x to the power supply potential.
- the inter-block switch 112 between the block 120-x and the block 120-x-1 is turned off.
- the write circuit 105 performs an initial break of the memory cells in the block 120-x-1.
- the write circuit 105 sequentially turns off the inter-block switch 112 adjacent to the side close to the row selection circuit 103 for the block for which the initial break has been completed.
- the write circuit 105 performs an initial break on a block adjacent to the side closer to the row selection circuit 103.
- the write circuit 105 finally performs an initial break on a plurality of memory cells included in the block 120-1.
- variable resistance nonvolatile memory device according to Embodiments 1 and 2 and the modifications thereof may be combined.
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Abstract
Description
本願発明者らは、抵抗変化型不揮発性記憶装置の1つとして、電流制御素子と抵抗変化素子とを含むメモリセルを用いた1D1R型クロスポイントメモリアレイにおける、初期ブレイク動作の方法を検討した。初期ブレイクを行うと、通常、メモリセルの抵抗値は、製造直後の抵抗値より小さくなる。
本発明の実施の形態1に係る抵抗変化型不揮発性記憶装置は、初期ブレイクの際に、書き込み回路からメモリセルへの経路に流れる電流を制限する。これにより、当該抵抗変化型不揮発性記憶装置は、1D1R型クロスポイントメモリアレイにおいて、電流制御素子の信頼性を損なうことなく抵抗変化素子の初期ブレイクを行うことが可能となる。
ここで、メモリセルの初期ブレイクが進むに従って、抵抗変化素子Rijの抵抗値が減少するため、非選択セルへの漏れ電流が増加する。これにより、ワード線WLi上の電圧降下、及びビット線BLj上の電圧上昇により、初期ブレイクが困難になるという課題が生じることを本発明者は見出した。この課題は、メモリセルアレイ102内のメモリセルを初期ブレイクする順番を工夫することにより、解決可能である。
2、Dij 電流制御素子
10、Mij メモリセル
11、BLj ビット線
12、WLi ワード線
13 下部電極
14 ダイオード層
15 内部電極
16 抵抗変化層
16a 第1の遷移金属酸化物層
16b 第2の遷移金属酸化物層
17 上部電極
100 抵抗変化型不揮発性記憶装置
101 メモリ本体部
102 メモリセルアレイ
103 行選択回路
104 列選択回路
105 書き込み回路
105a1 第1LR化駆動回路
105a2 第2HR化駆動回路
105b 電流制限回路
105c1 第1HR化駆動回路
105c2 第2LR化駆動回路
106 読み出し回路
107 データ入出力回路
108 アドレス入力回路
109 制御回路
110 制御回路
111 容量負荷回路
111a 容量負荷素子
111b 選択スイッチ
112 ブロック間スイッチ
120 ブロック
Claims (13)
- 複数の第1信号線と、前記複数の第1信号線に交差する複数の第2信号線と、前記複数の第1信号線と前記複数の第2信号線との交差点に配置されているメモリセルを複数有するメモリセルアレイとを備える抵抗変化型不揮発性記憶装置であって、
前記複数のメモリセルの各々は、予め定められた第1の極性の第1の電圧が印加されると第1範囲に属する抵抗値の低抵抗状態に変化し、かつ前記第1の極性とは逆の極性である第2の極性の第2の電圧が印加されると前記第1範囲よりも高い第2範囲に属する抵抗値の高抵抗状態に変化する抵抗変化素子と、前記抵抗変化素子に直列に接続されている2端子の電流制御素子とを含み、
前記抵抗変化型不揮発性記憶装置は、
前記メモリセルに、対応する前記第1信号線及び前記第2信号線を介して、絶対値が前記第1の電圧以上の前記第1の極性の低抵抗化電圧を印加することにより、前記抵抗変化素子を前記低抵抗状態に変化させる低抵抗化書き込みと、前記メモリセルに、対応する前記第1信号線及び前記第2信号線を介して、絶対値が前記第2の電圧以上の前記第2の極性の高抵抗化電圧を印加することにより、前記抵抗変化素子を前記高抵抗状態に変化させる高抵抗化書き込みとを行う書き込み回路と、
前記複数の第1信号線のいずれかを選択する第1選択回路と、
前記複数の第2信号線のいずれかを選択する第2選択回路とを備え、
前記複数のメモリセルは、複数のブロックに分割されており、
前記複数のブロックの各々は、複数のメモリセルを含み、
前記書き込み回路は、さらに、
前記抵抗変化型不揮発性記憶装置が製造された後の初期状態の前記抵抗変化素子に対し、対応する前記第1信号線及び前記第2信号線を介して、前記低抵抗化電圧及び前記高抵抗化電圧の絶対値より絶対値が大きい初期ブレイク電圧を印加することにより、前記抵抗変化素子を、前記低抵抗化書き込み及び前記高抵抗化書き込みにより抵抗変化が可能な状態に遷移させる初期ブレイクを行い、
前記初期ブレイクにおいて、前記第1選択回路により選択された第1信号線及び前記第2選択回路により選択された第2信号線に、前記第1選択回路及び前記第2選択回路を介して前記初期ブレイク電圧を印加し、
前記複数のブロックのうち、前記第1選択回路及び前記第2選択回路の少なくとも一方の回路から最も遠い位置に配置されているブロックから、前記いずれか一方の回路に最も近い位置に配置されているブロックへ向かう順に、順次ブロックを選択し、選択したブロックに含まれる複数のメモリセルに前記初期ブレイクを行う
抵抗変化型不揮発性記憶装置。 - 前記書き込み回路は、選択した各ブロックに含まれる複数のメモリセルのうち、前記第1選択回路及び前記第2選択回路の少なくとも一方の回路から最も遠い位置に配置されているメモリセルから、前記いずれか一方の回路に最も近い位置に配置されているメモリセルへ向かう順に、順次メモリセルを選択し、選択したメモリセルに前記初期ブレイクを行う
請求項1記載の抵抗変化型不揮発性記憶装置。 - 前記書き込み回路は、前記第1選択回路から最も遠い位置に配置されており、かつ前記第2選択回路から最も遠い位置に配置されているブロックから、前記第1選択回路に最も近い位置に配置されており、かつ前記第2選択回路に最も近い位置に配置されているブロックへ向かう順に、ジグザグに順次ブロックを選択し、選択したブロックに含まれる複数のメモリセルに前記初期ブレイクを行う
請求項1記載の抵抗変化型不揮発性記憶装置。 - 前記複数のブロックは、行列状に配置されており、
前記書き込み回路は、
ブロック単位の行及び列の一方であり、前記第1信号線に沿う方向の複数のラインのうち、前記第2選択回路から最も遠い位置に配置されているラインから、前記第2選択回路に最も近い位置に配置されているラインへ向かう順に、順次ラインを選択し、
選択したラインに配置されている複数のブロックのうち、前記第1選択回路から最も遠い位置に配置されているブロックから、前記第1選択回路に最も近い位置に配置されているブロックへ向かう順に、順次ブロックを選択する
請求項1記載の抵抗変化型不揮発性記憶装置。 - 前記抵抗変化型不揮発性記憶装置は、さらに、
前記第1信号線の前記ブロックの間の各々に設けられている複数のブロック間スイッチを含み、
前記書き込み回路は、選択した第1ブロックに含まれる複数のメモリセルの前記初期ブレイクを行ったのち、当該第1ブロックと、当該第1ブロックに対して前記一方の回路側に隣接する第2ブロックとの間に設けられている前記ブロック間スイッチをオフしたうえで、前記第2ブロックに前記初期ブレイクを行う
請求項1記載の抵抗変化型不揮発性記憶装置。 - 前記抵抗変化型不揮発性記憶装置は、さらに、
前記書き込み回路から前記複数のメモリセルへ流れる電流の経路に挿入され、前記複数のメモリセルを高抵抗状態に変化させる第1方向の電流と、前記複数のメモリセルを低抵抗状態に変化させる第2方向の電流とのうち、前記第1方向の電流のみを制限する電流制限回路を備え、
前記書き込み回路は、前記初期ブレイクにおいて、前記メモリセルに、前記第2の極性の前記初期ブレイク電圧を印加し、
前記電流制限回路は、前記初期ブレイクにおいて、前記経路に流れる前記第1方向の電流を制限する
請求項1~5のいずれか1項に記載の抵抗変化型不揮発性記憶装置。 - 前記各メモリセルは、接続されている第1信号線と第2信号線とを介して、前記第1信号線の電圧が前記第2信号線の電圧よりも高い前記第1の極性の第1の電圧が印加されたときに前記低抵抗状態に変化し、前記第1の極性とは逆の前記第2の極性の第2の電圧が印加されたときに前記高抵抗状態に変化し、
前記書き込み回路は、前記第1の電圧以上の第1駆動電圧を発生する第1駆動回路と、前記第2の電圧以上の第2駆動電圧を発生する第2駆動回路と、前記第1駆動電圧の基準となる電圧を発生する第3駆動回路と、前記第2駆動電圧の基準となる電圧を発生する第4駆動回路とを有し、
前記第1選択回路は、前記複数の第1信号線の中から1つの第1信号線を選択し、選択した1つの第1信号線と、前記第1駆動回路及び前記第4駆動回路とを接続し、
前記第2選択回路は、前記複数の第2信号線の中から1つの第2信号線を選択し、選択した1つの第2信号線と、前記第2駆動回路及び前記第3駆動回路とを接続し、
前記電流制限回路は、前記第4駆動回路と前記第1選択回路との間に挿入されている
請求項6記載の抵抗変化型不揮発性記憶装置。 - 前記各メモリセルは、接続されている第1信号線と第2信号線とを介して、前記第1信号線の電圧が前記第2信号線の電圧よりも高い前記第1の極性の第1の電圧が印加されたときに前記低抵抗状態に変化し、前記第1の極性とは逆の前記第2の極性の第2の電圧が印加されたときに前記高抵抗状態に変化し、
前記書き込み回路は、前記第1の電圧以上の第1駆動電圧を発生する第1駆動回路と、前記第2の電圧以上の第2駆動電圧を発生する第2駆動回路と、前記第1駆動電圧の基準となる電圧を発生する第3駆動回路と、前記第2駆動電圧の基準となる電圧を発生する第4駆動回路とを有し、
前記第1選択回路は、前記複数の第1信号線の中から1つの第1信号線を選択し、選択した1つの第1信号線と、前記第1駆動回路及び前記第4駆動回路とを接続し、
前記第2選択回路は、前記複数の第2信号線の中から1つの第2信号線を選択し、選択した1つの第2信号線と、前記第2駆動回路及び前記第3駆動回路とを接続し、
前記電流制限回路は、前記第2駆動回路と前記第2選択回路との間に挿入されている
請求項6記載の抵抗変化型不揮発性記憶装置。 - 前記電流制限回路は、前記初期ブレイク電圧の前記メモリセルへの供給を開始した後、かつ、前記メモリセルが前記初期ブレイクされる前である第1期間において、第1電流値まで前記経路に流れる前記第1方向の電流を制限し、前記第1期間の後であり、かつ、前記メモリセルが前記初期ブレイクされる時点を含む第2期間において、第1電流値より小さい第2電流値まで前記経路に流れる前記第1方向の電流を制限する
請求項6~8のいずれか1項に記載の抵抗変化型不揮発性記憶装置。 - 前記電流制限回路は、前記第1信号線又は前記第2信号線の電圧が予め定められた電圧に達したか否かを検出し、前記第1信号線又は前記第2信号線の電圧が前記予め定められた電圧に達した場合に、制限する電流を前記第1電流値から前記第2電流値に変更する
請求項9記載の抵抗変化型不揮発性記憶装置。 - 前記抵抗変化型不揮発性記憶装置は、さらに、
容量負荷素子と、
前記電流制限回路と前記第1選択回路との間のノードと、前記容量負荷素子との間の導通及び非導通を切り替える選択スイッチとを備え、
前記選択スイッチは、前記初期ブレイク時に前記ノードと前記容量負荷素子とを導通させる
請求項7記載の抵抗変化型不揮発性記憶装置。 - 前記抵抗変化型不揮発性記憶装置は、さらに、
容量負荷素子と、
前記電流制限回路と前記第2選択回路との間のノードと、前記容量負荷素子との間の導通及び非導通を切り替える選択スイッチとを備え、
前記選択スイッチは、前記初期ブレイク時に前記ノードと前記容量負荷素子とを導通させる
請求項8記載の抵抗変化型不揮発性記憶装置。 - 前記抵抗変化素子は、第1電極と、第2電極と、前記第1電極及び前記第2電極に挟まれた遷移金属酸化物層とを有し、
前記遷移金属酸化物層は、前記第1電極と接する酸素不足型の第1の遷移金属酸化物層と、前記第2電極と接し前記第1の遷移金属酸化物層よりも酸素不足度が少ない第2の遷移金属酸化物層とを含む
請求項1~12のいずれか1項に記載の抵抗変化型不揮発性記憶装置。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014049175A (ja) * | 2012-08-31 | 2014-03-17 | Toshiba Corp | 不揮発性半導体記憶装置、及びそのフォーミング方法 |
JP2014216046A (ja) * | 2013-04-23 | 2014-11-17 | 株式会社東芝 | 半導体記憶装置 |
JP2016021272A (ja) * | 2014-06-16 | 2016-02-04 | パナソニックIpマネジメント株式会社 | 抵抗変化型不揮発性記憶装置 |
JP2017168173A (ja) * | 2016-03-17 | 2017-09-21 | 株式会社東芝 | 集積回路 |
US11756616B2 (en) | 2021-02-19 | 2023-09-12 | Fujitsu Limited | Computer and calculation method using memristor array |
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US9401201B1 (en) * | 2015-05-22 | 2016-07-26 | Qualcomm Incorporated | Write driver for memory |
FR3042304B1 (fr) | 2015-10-09 | 2017-11-24 | Commissariat Energie Atomique | Procede et circuit pour controler le courant de programmation dans une matrice de memoire non volatile |
KR102645776B1 (ko) * | 2016-11-18 | 2024-03-11 | 에스케이하이닉스 주식회사 | 저항성 메모리 장치, 이를 위한 리드 회로 및 방법 |
JP6899024B1 (ja) * | 2020-06-11 | 2021-07-07 | ウィンボンド エレクトロニクス コーポレーション | 抵抗変化型シナプスアレイ装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007226884A (ja) * | 2006-02-23 | 2007-09-06 | Sharp Corp | 不揮発性半導体記憶装置及びデータ書き換え方法 |
WO2007141865A1 (ja) * | 2006-06-08 | 2007-12-13 | Renesas Technology Corp. | 半導体装置及びその製造方法 |
JP2011065737A (ja) * | 2009-09-18 | 2011-03-31 | Toshiba Corp | 抵抗変化型メモリ |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10144086A (ja) | 1996-11-14 | 1998-05-29 | Sharp Corp | 不揮発性半導体記憶装置 |
CN102017145B (zh) * | 2008-12-04 | 2012-08-01 | 松下电器产业株式会社 | 非易失性存储元件以及非易失性存储装置 |
JP4607256B2 (ja) | 2008-12-18 | 2011-01-05 | パナソニック株式会社 | 不揮発性記憶装置及びその書き込み方法 |
JP4861444B2 (ja) | 2009-03-16 | 2012-01-25 | 株式会社東芝 | 可変抵抗素子のフォーミング方法 |
WO2010125805A1 (ja) * | 2009-04-27 | 2010-11-04 | パナソニック株式会社 | 抵抗変化型不揮発性記憶素子の書き込み方法及び抵抗変化型不揮発性記憶装置 |
CN102473457B (zh) * | 2010-06-29 | 2014-07-23 | 松下电器产业株式会社 | 非易失性存储装置以及其驱动方法 |
JP2012069216A (ja) * | 2010-09-24 | 2012-04-05 | Toshiba Corp | 不揮発性半導体記憶装置 |
WO2013051267A1 (ja) * | 2011-10-06 | 2013-04-11 | パナソニック株式会社 | 不揮発性記憶素子および不揮発性記憶装置 |
-
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007226884A (ja) * | 2006-02-23 | 2007-09-06 | Sharp Corp | 不揮発性半導体記憶装置及びデータ書き換え方法 |
WO2007141865A1 (ja) * | 2006-06-08 | 2007-12-13 | Renesas Technology Corp. | 半導体装置及びその製造方法 |
JP2011065737A (ja) * | 2009-09-18 | 2011-03-31 | Toshiba Corp | 抵抗変化型メモリ |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014049175A (ja) * | 2012-08-31 | 2014-03-17 | Toshiba Corp | 不揮発性半導体記憶装置、及びそのフォーミング方法 |
JP2014216046A (ja) * | 2013-04-23 | 2014-11-17 | 株式会社東芝 | 半導体記憶装置 |
JP2016021272A (ja) * | 2014-06-16 | 2016-02-04 | パナソニックIpマネジメント株式会社 | 抵抗変化型不揮発性記憶装置 |
JP2017168173A (ja) * | 2016-03-17 | 2017-09-21 | 株式会社東芝 | 集積回路 |
US11756616B2 (en) | 2021-02-19 | 2023-09-12 | Fujitsu Limited | Computer and calculation method using memristor array |
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