WO2012164865A1 - 接合構造体 - Google Patents

接合構造体 Download PDF

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Publication number
WO2012164865A1
WO2012164865A1 PCT/JP2012/003318 JP2012003318W WO2012164865A1 WO 2012164865 A1 WO2012164865 A1 WO 2012164865A1 JP 2012003318 W JP2012003318 W JP 2012003318W WO 2012164865 A1 WO2012164865 A1 WO 2012164865A1
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WIPO (PCT)
Prior art keywords
layer
electrode
young
modulus
semiconductor element
Prior art date
Application number
PCT/JP2012/003318
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English (en)
French (fr)
Inventor
太一 中村
秀敏 北浦
章央 吉澤
Original Assignee
パナソニック株式会社
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Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to US14/123,657 priority Critical patent/US20140103531A1/en
Priority to CN201280025481.0A priority patent/CN103563062A/zh
Priority to EP12793525.2A priority patent/EP2717303A4/en
Publication of WO2012164865A1 publication Critical patent/WO2012164865A1/ja

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/264—Bi as the principal constituent
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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    • B32—LAYERED PRODUCTS
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Definitions

  • the present invention relates to internal bonding of semiconductor components, and particularly to a bonded structure in which a semiconductor element and an electrode of a power semiconductor module that require excellent mechanical properties and heat resistance are bonded via Bi solder.
  • Sn-Pb eutectic solder has been used extensively in the electronics packaging field. However, in recent years, joints that do not use lead have been desired due to concerns about the harmfulness of lead and increased environmental concerns. .
  • the candidates for this alternative solder material include Au-based, Zn-based, Sn-based, and Bi-based ones.
  • Au-based solder materials for example, Au-20 wt% Sn having a melting point of 280 ° C. is partially put into practical use, but since the main component is Au, the material physical properties are hard and the material It is not versatile due to its high cost and limited use for small parts.
  • Zn-based solder materials are highly corrosive and have an excessively high elastic modulus, so improvement in mechanical properties is a problem in application to internal joining of semiconductor components.
  • Sn-based solder materials have excellent mechanical properties, their melting points are as low as less than 250 ° C. and poor heat resistance. Therefore, for the purpose of improving the heat resistance of Sn-based materials, for example, a bonding material whose melting point has been raised by forming an intermetallic compound by forming an SnCu compound has been studied. Since voids are sometimes generated, improvement of mechanical characteristics and heat dissipation characteristics is a problem.
  • Patent Document 1 is an example in which this Bi-based solder material is used as a bonding material.
  • FIG. 8 is a cross-sectional view of a conventional joint structure described in Patent Document 1.
  • the power semiconductor module 401 includes a joint 404 between the power semiconductor element 402 and the electrode 403, and the joint 404 Bi—Ag based solder material is used for 15 to 60% by weight of Ag.
  • the Bi—Ag solder material described in Patent Document 1 has bonding reliability, but the operating temperature of the power semiconductor element 402 is GaN, In an environment of 175 ° C. or 200 ° C., which has a higher operating temperature than Si, such as SiC, the Bi-Ag solder material described in Patent Document 1 may cause cracks and peeling at the joint 404.
  • the Bi-Ag solder material is resistant to thermal stress based on the difference between the thermal expansion coefficient of the power semiconductor element 402 ( ⁇ 3 ppm / K) and the linear expansion coefficient of the Cu electrode 403 ( ⁇ 18 ppm / K). Since stress cannot be relaxed, it is considered that cracks, peeling, and the like occur at the joint 404.
  • Patent Document 2 which has a problem of preventing cracking and peeling of the bonded structure.
  • the protective resin coated on the semiconductor element is also formed on the outer peripheral surface area between the intermediate bonding layer and the solder bonding layer of the semiconductor element, thereby improving the crack resistance inside the semiconductor element. It is shown that the thermal stress applied to the interface between the semiconductor element and the solder material and the interface between the solder material and the electrode is reduced.
  • the protective resin is coated and filled in a predetermined region to improve the stress relaxation property of the bonded structure composed of the semiconductor element and the electrode via the solder material.
  • the stress relaxation property is improved and cracks and peeling are prevented from occurring in the bonded structure of the power semiconductor module by means different from the invention described in Patent Document 2 characterized by filling with a protective resin. Doing this is a technical issue.
  • the present inventors have formed a laminated structure in which a strain with respect to an external stress is changed in a gradient from a bonding material toward a material to be bonded (semiconductor element, Cu electrode), so that the material to be bonded (semiconductor element)
  • the present invention was completed with the idea of effectively relieving and absorbing thermal stress based on the difference in thermal expansion coefficient of the Cu electrode).
  • the present invention 1 is a bonded structure in which a semiconductor element is bonded to a Cu electrode with a bonding material containing Bi as a main component, and a laminated body is formed from the bonding material and an intermediate layer formed on the surface of the bonding material.
  • each Young's modulus E1 to E4 is either or both of the following conditions (p1) and (q1): E3 ⁇ E2 ⁇ E1 (p1) E3 ⁇ E2 ⁇ E4 (q1)
  • the laminated body is configured with respect to the semiconductor element and the Cu electrode so as to satisfy the above.
  • Invention 2 is the invention 1, wherein the laminate is a three-layer laminate comprising the bonding material and two intermediate layers formed on the upper and lower surfaces of the bonding material, the semiconductor element side
  • the Young's modulus of the first intermediate layer is E21
  • the Young's modulus of the second intermediate layer on the Cu electrode side is E24
  • the Young's modulus E1, E21, E24, E3, and E4 are as follows: And (q2) E3 ⁇ E21 ⁇ E1 (p2) E3 ⁇ E24 ⁇ E4 (q2)
  • a three-layer stack is formed with respect to the semiconductor element and the Cu electrode so as to satisfy the above.
  • Invention 3 is the invention 1, wherein the laminate is a two-layer laminate comprising the joining material and an intermediate layer formed on the joining element side of the joining material, on the semiconductor element side.
  • the Young's modulus of the intermediate layer is E21
  • the Young's moduli E1, E21, E3 satisfy the following conditions (p2) E3 ⁇ E21 ⁇ E1 (p2)
  • p2 E3 ⁇ E21 ⁇ E1
  • a two-layer laminate is formed with respect to the semiconductor element and the Cu electrode so as to satisfy the above.
  • Invention 4 is the invention 1, wherein the laminate is a two-layer laminate comprising the joining material and an intermediate layer formed on the Cu electrode side of the joining material, wherein the Young's modulus of the intermediate layer Where E24 is the Young's modulus E24, E3, E4, the following condition (q2) E3 ⁇ E24 ⁇ E4 (q2)
  • the laminate is a two-layer laminate comprising the joining material and an intermediate layer formed on the Cu electrode side of the joining material, wherein the Young's modulus of the intermediate layer
  • E24 is the Young's modulus E24, E3, E4, the following condition (q2) E3 ⁇ E24 ⁇ E4 (q2)
  • a two-layer laminate is formed with respect to the semiconductor element and the Cu electrode so as to satisfy the above.
  • Invention 5 is the bonding according to any one of Inventions 1 to 4, wherein the intermediate layer is at least one metal selected from the group consisting of AuSn compounds, AgSn compounds, CuSn compounds, Au, and Ag. It is a structure.
  • the present invention 6 is the bonded structure according to any one of the above inventions 1 to 5, wherein the intermediate layer is a CuSn compound.
  • the present invention provides a temperature cycle during use of a power semiconductor module by bonding a semiconductor element and a Cu electrode through a laminated structure in which the Young's modulus increases in a gradient from the bonding material to the material to be bonded. Since a so-called spring effect is exerted on the generated thermal stress to develop an excellent stress relaxation function, the semiconductor element and the electrode can be bonded with high quality, thereby improving the bonding reliability.
  • FIG. 6 is a table summarizing the configurations and thicknesses of the electrode surface treatment layer and the Bi underlayer before bonding and the compositions and thicknesses of the second intermediate layer and the first intermediate layer after bonding in Examples 1 to 15 in the embodiment of the present invention. Chart showing yield test results for bonded structures Enlarged sectional view of a mounting structure showing the prior art
  • the invention described in Embodiment 1 is a bonded structure in which a semiconductor element is bonded to a Cu electrode with a bonding material containing Bi as a main component, and a laminate is formed from the bonding material and an intermediate layer formed on the surface of the bonding material. Constructing and bonding Cu on the surface of the semiconductor element and the Cu electrode through the laminated body, the bonding material, the intermediate layer, toward one direction of the semiconductor element, or the bonding material, Each Young's modulus is sequentially increased toward one direction of the intermediate layer and the Cu electrode, or further, each Young's modulus is sequentially increased from the bonding material to both the semiconductor element and the Cu electrode via the intermediate layer. Increased bonded structure.
  • the Young's modulus of Cu on the surface of the semiconductor element is E1
  • the Young's modulus of the intermediate layer is E2
  • the Young's modulus of the bonding material is E3
  • the Young's modulus of the Cu electrode is
  • E4 is set, the Young's moduli E1 to E4 satisfy the following conditions (p1) and (q1) E3 ⁇ E2 ⁇ E1 (p1) E3 ⁇ E2 ⁇ E4 (q1)
  • the stacked body is configured with respect to the semiconductor element and the Cu electrode so as to satisfy both or either of the above.
  • the inventions described in the second to fourth embodiments described below are subordinate conceptual inventions of the invention described in the first embodiment, and the invention described in the second embodiment is based on the above-mentioned bonding material.
  • An intermediate layer is formed on both lower surfaces, and this three-layer laminate (intermediate layer, bonding material, intermediate layer) is interposed between the semiconductive element and the Cu electrode, and from the bonding material to the intermediate layer. Then, the Young's modulus is sequentially increased toward both surfaces of the semiconductor element and the Cu electrode to reduce stress.
  • an intermediate layer is formed on the surface of the bonding material facing the semiconductor element to form a two-layer laminate (intermediate layer, bonding material), and the bonding material,
  • the Young's modulus is sequentially increased toward the intermediate layer and the semiconductor element to relieve stress.
  • an intermediate layer is formed on the surface of the bonding material on the Cu electrode side to form a two-layer laminate (intermediate layer, bonding material). Similar to the invention, each of the Young's moduli is sequentially increased to relieve stress, thereby joining.
  • copper as a material of the lowermost layer of an electrode or a barrier metal layer described later is a concept including copper and a copper alloy.
  • FIG. 1 is a cross-sectional view of a mounting structure including the joint structure of the invention described in the embodiment as a constituent element.
  • the semiconductor element 102 and the Cu electrode 103 are bonded by the bonding material 104 to form the bonded structure 106, and then the bonded structure 106 is sealed with the sealing resin 105 to form the power semiconductor module 100. Further, the power semiconductor module 100 is mounted on the substrate 101 using the solder material 109 to form the mounting structure 110.
  • junction structure 106 will be described in detail.
  • FIG. 2A, 2B, and 2C are manufacturing process diagrams of the joint structure 106.
  • FIG. 2C when the second intermediate layer 206 is formed on the lower surface of the bonding material 104 and the first intermediate layer 207 is formed on the upper surface of the bonding material 104, that is, a three-layer laminate 209a is interposed. The case where it was made to explain is demonstrated.
  • FIG. 2A is a process diagram for supplying the Cu electrode 103.
  • the Cu electrode 103 When supplying the Cu electrode 103, the Cu electrode 103 is supplied in a nitrogen atmosphere (room temperature) containing 5% hydrogen. On the Cu electrode 103 made of a Cu alloy, an Ag layer 201 and an electrode surface treatment layer 202 are formed in advance as a surface treatment layer by electrolytic plating.
  • FIG. 2B is a process diagram for mounting the semiconductor element 102 having the Bi layer 203 on the Ag layer 201 which is a surface treatment layer of the Cu electrode 103.
  • the Cu electrode 103 is heated to 320 ° C. in a nitrogen atmosphere containing 5% hydrogen.
  • a semiconductor element 102 made of GaN and having a thickness of 0.3 mm, 4 mm ⁇ 5 mm has a barrier metal layer 204 composed of a multilayer of Cr 0.1 ⁇ m / Ni 1 ⁇ m / Cu 3 ⁇ m from the GaN side and a Bi underlayer 205 by vapor deposition.
  • the Bi layer 203 made of Bi having a thickness of 10 ⁇ m is formed on the Bi underlayer 205 by electroplating.
  • the Cr on the semiconductor element 102 side is formed in order to ensure conduction by Si and ohmic contact.
  • Ni in the barrier metal layer 204 is formed to prevent deterioration of the function of the device due to diffusion of the Cu component into the device of the semiconductor element, that is, to prevent diffusion of Cu.
  • Cu in the barrier metal layer 204 is a layer in contact with the Bi base layer 205.
  • the reason for providing this Cu layer is that Bi and Ni of the Bi layer 203 form an intermetallic compound Bi 3 Ni at the interface, and this brittle metal compound layer is deformed by thermal stress, for example, when a power semiconductor module is used. This is because Cu may be formed between Bi and Ni of the barrier metal layer to prevent diffusion of Bi into Ni because there is a possibility of becoming a starting point of cracks.
  • Cu was selected because it is a metal with a small amount of dissolution in Bi (about 0.4 at%), and thus a barrier effect for preventing the diffusion of Bi is developed.
  • the thickness of Cu Bi diffusion can be prevented if it is 1 ⁇ m or more, but it is set to 3 ⁇ m in consideration of 2 ⁇ m of variation in film thickness by electroplating.
  • the semiconductor element 102 is placed on the Cu electrode 103 with a load of about 50 gf to 150 gf so that the Bi layer 203 is in contact with the Ag layer 201 which is the surface treatment layer of the Cu electrode 103.
  • the semiconductor element 102 is placed on the Cu electrode 103 with a load of 60 gf.
  • FIG. 2C is a process diagram for solidifying the bonding material 104 in a state where a part of the Ag layer 201 is diffused into the melted Bi layer 203 by natural cooling.
  • natural bonding is performed in a nitrogen atmosphere containing 5% hydrogen, and the bonding material 104 is solidified to bond the Cu electrode 103 and the semiconductor element 102, thereby manufacturing the bonded structure 106.
  • the bonding material 104 will be described.
  • the Ag layer 201 which is the surface treatment layer of the Cu electrode 103 is diffused into Bi until the Bi layer 203 of FIGS. 2B to 2C is melted and solidified.
  • the melting point of the bonding material 104 after Ag diffuses into Bi is 262 ° C.
  • the purpose of forming the Ag layer 201 as the surface treatment layer of the Cu electrode 103 is to ensure the wettability of the molten Bi to the entire lower surface of the semiconductor element 102.
  • the second intermediate layer 206 and the first intermediate layer 207 will be described.
  • the second intermediate layer 206 is a layer formed by a diffusion reaction in the electrode surface treatment layer 202 in a heated state at 320 ° C. or by a diffusion reaction between the electrode surface treatment layer 202 and the Cu electrode 103.
  • the first intermediate layer 207 is also formed by a diffusion reaction in the Bi underlayer 205 in a heated state at 320 ° C. or by a diffusion reaction between Cu, which is the lowermost layer of the barrier metal layer 204, and the Bi underlayer 205. Is a layer.
  • the above-described bonding structure 106 is obtained by bonding the Cu electrode 103 and Cu on the surface of the semiconductor element 102 via a three-layer laminate 209a of the second intermediate layer 206, the bonding material 104, and the first intermediate layer 207. It is. In order to relieve the stress of the bonding portion 208, the Young's modulus is sequentially increased toward the bonding material 104, the second intermediate layer 206, and the Cu electrode 103, and toward the bonding material 104, the first intermediate layer 207, and the semiconductor element 102. It is necessary to increase, i.e., increase in a slope.
  • the Young's modulus of the first intermediate layer 207 is between the Young's modulus of the bonding material 104 and the Young's modulus of the surface of the semiconductor element 102, that is, takes an intermediate value and the Young's modulus of the second intermediate layer 206.
  • the rate is achieved by taking a value between the Young's modulus of the bonding material 104 and the Young's modulus of the Cu electrode 103, that is, an intermediate value.
  • the three-layer laminate 209a will be described in more detail.
  • the Young's modulus of the first intermediate layer 207 facing the semiconductor element 102 is E21 and the Young's modulus of the second intermediate layer 206 facing the Cu electrode 103 is E24
  • the Young's modulus of Cu on the surface of the semiconductor element 102 is
  • E1 the Young's modulus of the bonding material 104 is E3
  • E4 the Young's modulus of the Cu electrode 103 is E4
  • the stacked body 209 a is configured with respect to the semiconductor element 102 and the Cu electrode 103 so as to satisfy the above.
  • the Young's modulus of the intermediate layer takes an intermediate value, for example, in the case of the first intermediate layer 207 close to the semiconductor element 102 side, the Young's modulus E3 of the bonding material 104 and the barrier metal layer 204 of the semiconductor element 102 Is not only a numerical value close to the center with the Young's modulus of the lower layer (Cu), but a numerical value close to the Young's modulus of the lower layer (Cu) of the barrier metal layer 204 or the Young's modulus of the bonding material, that is, the median value.
  • the numerical value may be biased toward one Young's modulus.
  • Example 1 described later is an example of the former, and Example 3 is an example of the latter.
  • stress relaxation can be achieved by interposing a two-layer laminate between a semiconductor element and an electrode.
  • FIG. 3 shows the joint structure of the invention described in Embodiment 3 in the case where the laminate has two layers.
  • An intermediate layer of the laminated body is formed on the semiconductor element 102 side of the bonding material 104.
  • an intermediate layer is not formed on the Cu electrode 103 side of the bonding material 104.
  • the Young's modulus of the first intermediate layer 207 is set to be the Young of the bonding material 104.
  • the ratio between the Young's modulus of the lower layer (Cu) of the barrier metal layer 204 of the semiconductor element 102 each Young's modulus of the two-layer laminate 209b of the bonding material 104 and the first intermediate layer 207 is bonded.
  • the material 104, the first intermediate layer 207, and the lower layer (Cu) of the barrier metal layer of the semiconductor element 102 are sequentially increased.
  • FIG. 4 shows the joint structure of the invention described in Embodiment 4 in the case where the laminate has another two-layer structure.
  • the intermediate layer of the laminate is formed on the Cu electrode 103 side of the bonding material 104.
  • the intermediate layer is not formed on the semiconductor element 102 of the bonding material 104.
  • each Young's modulus of the two-layer laminate 209c of the bonding material 104 and the second intermediate layer 206 is changed to the bonding material 104, the second intermediate layer 206, It is configured to increase sequentially toward the Cu electrode 103.
  • the 2-layer laminate 209c will be described in more detail.
  • an intermediate layer is formed only on one surface of the bonding material 104 as shown in FIG. 3 or FIG. 4, and the spring effect is exerted also as the two-layer laminates 209b and 209c.
  • the intermediate layer is formed on the upper and lower surfaces of the bonding material 104 as shown in FIG. 2C to form a three-layer laminate 209a, the spring effect works better.
  • the material of the intermediate layer is preferably selected from the group consisting of AuSn compounds, AgSn compounds, CuSn compounds, Au, and Ag, and more preferably CuSn compounds.
  • the thickness of the intermediate layer will be described taking the Au / Sn configuration as an example.
  • Example 1 in consideration of the film formation variation of plating, a thickness of 0.3 ⁇ m, which is considerably thinner than 0.6 ⁇ m, was aimed at so that only an intermetallic compound was surely generated.
  • the Sn thickness before bonding may be set appropriately so as not to leave a single layer of Sn after bonding based on the above design concept.
  • a phase of 232 ° C. which is the melting point of Sn, is formed in the bonding portion 208 and may be remelted when the power semiconductor 100 is mounted on the substrate 101.
  • the single layer is not left behind.
  • the bonding structure 106 As described above, when the formation of the bonding structure 106 is completed, the power semiconductor module 100 is formed using the bonding structure 106 as shown in FIG. Thus, the mounting structure 110 is created (see FIG. 5).
  • Sn-3 wt% Ag-0.5 wt% Cu (melting point: 217 ° C.) is used as the solder material 109 for mounting, but not limited to this as long as it is a lead-free Sn-based solder.
  • Sn-0.7 wt% Cu (melting point 227 ° C.)
  • Sn-3.5 wt% Ag-0.5 wt% Bi-6.0 wt% In (melting point 220 ° C.), etc. may be used. .
  • Example - an example of a bonded structure which is the invention described in the embodiment, an example of manufacturing a mounted structure in which a power semiconductor module obtained from the bonded structure is mounted on a substrate, and an evaluation test example of yield by the mounted structure explain.
  • Examples 1 to 5 are examples in which the first and second intermediate layers 207 and 206 are formed on the upper and lower surfaces of the bonding material 104 as described above.
  • Examples 6 to 10 are Examples in which only the first intermediate layer 207 is formed on the side of the semiconductor element 102 in the bonding material 104, Examples 11 to 15 have only the second intermediate layer 206 on the side of the Cu electrode 103 in the bonding material 104. This is an example of formation.
  • Comparative Example 1 the case where the electrode surface treatment layer 202 and the Bi underlayer 205 were not provided and the first and second intermediate layers 207 and 206 were not formed by heating / diffusion was defined as Comparative Example 1.
  • FIG. 6 shows the configurations and thicknesses of the electrode surface treatment layer 202 and the Bi underlayer 205 before bonding and the compositions and thicknesses of the second intermediate layer 206 and the first intermediate layer 207 after bonding in Examples 1 to 15. Summarized.
  • Example 1 As shown in FIG. 6, two layers of Au 0.1 ⁇ m / Sn 0.3 ⁇ m were formed as an electrode surface treatment layer 202 in a laminated form. In this case, the side far from the Bi layer 203 is Au, and the side near the Bi layer 203 is Sn.
  • the second intermediate layer 206 made of AuSn compound 2 ⁇ m was formed by heating to 320 ° C. to generate an intermetallic compound by a diffusion reaction in the electrode surface treatment layer 202.
  • an intermetallic compound was generated by a diffusion reaction in the Bi underlayer 205 to form a first intermediate layer 207 made of 2 ⁇ m of AuSn compound.
  • the above AuSn compound was confirmed to be AuSn4 (Au and Sn are in an atomic weight ratio of 1: 4) by energy dispersive X-ray spectroscopy (Energy Dispersive X-ray Spectroscopy).
  • Example 2 As shown in FIG. 6, two layers of Ag 0.5 ⁇ m / Sn 0.1 ⁇ m are formed as a laminate as the electrode surface treatment layer 202, and two layers of Ag 0.5 ⁇ m / Sn 0.1 ⁇ m are formed as a Bi underlayer 205. did. In this case, the side far from the Bi layer 203 is Ag, and the side near the Bi layer 203 is Sn.
  • the second intermediate layer 206 made of AgSn compound 2 ⁇ m was formed by diffusion reaction of the electrode surface treatment layer 202 by heating to 320 ° C.
  • the first intermediate layer 207 made of 2 ⁇ m of AgSn compound was formed by the diffusion reaction of the Bi underlayer 205.
  • the above AgSn compound was confirmed to be Ag3Sn (Ag and Sn are 3 to 1 in terms of atomic weight ratio) by energy dispersive X-ray spectroscopy.
  • Example 3 As shown in FIG. 6, a single layer of Sn 0.5 ⁇ m was formed as the electrode surface treatment layer 202, and a single layer of Sn 0.5 ⁇ m was formed as the Bi underlayer 205.
  • the second intermediate layer 206 made of CuSn compound 2 ⁇ m was formed by diffusion reaction between the electrode surface treatment layer 202 and Cu of the Cu electrode 103 by heating to 320 ° C.
  • a first intermediate layer 207 made of CuSn compound 2 ⁇ m was formed by a diffusion reaction between the Bi underlayer 205 and Cu which is the lowermost layer of the barrier metal layer 204.
  • the CuSn compound was confirmed to be Cu6Sn5 (Cu and Sn at an atomic weight ratio of 6 to 5) by energy dispersive X-ray spectroscopy.
  • Example 4 As shown in FIG. 6, a single layer of Au 2 ⁇ m was formed as the electrode surface treatment layer 202, and a single layer of Au 2 ⁇ m was formed as the Bi underlayer 205.
  • the second intermediate layer 206 made of Au 0.5 ⁇ m is formed by diffusion of the electrode surface treatment layer 202 by heating to 320 ° C.
  • the first intermediate layer made of 0.5 ⁇ m Au is formed by diffusion of the Bi underlayer 205.
  • An intermediate layer 207 was formed.
  • Au does not form an intermetallic compound with the electrode or the lowermost layer Cu of the barrier metal layer 204.
  • Example 5 As shown in FIG. 6, a single layer of Ag 2 ⁇ m was formed as the electrode surface treatment layer 202, and a single layer of Ag 2 ⁇ m was formed as the Bi underlayer 205.
  • the second intermediate layer 206 made of Ag 0.5 ⁇ m is formed by diffusion of the electrode surface treatment layer 202 by heating to 320 ° C.
  • the first intermediate layer made of Ag 0.5 ⁇ m is formed by diffusion of the Bi underlayer 205.
  • An intermediate layer 207 was formed.
  • Ag does not form an intermetallic compound with Cu as the lowermost layer of the electrode or barrier metal layer 204.
  • Examples 6 to 10 A bi- or single-layer Bi underlayer 205 having the configuration and thickness shown in FIG. 6 was formed, and then heated to 320 ° C. to form a first intermediate layer 207 having the composition and thickness shown in FIG. The second intermediate layer 206 was not formed.
  • Examples 11 to 15 A two-layer or single-layer electrode surface treatment layer 202 having the configuration and thickness shown in FIG. 6 was formed and then heated to 320 ° C. to form a second intermediate layer 206 having the composition and thickness shown in FIG. The first intermediate layer 207 was not formed.
  • the bonding structure 106 completed according to the above embodiment is used, wire bonding (or ribbon bonding) is performed using the wire 107, sealing is performed, and the power semiconductor module 100 is mounted. After the formation, the power semiconductor module 100 was mounted on the substrate 101 with a solder material to form a mounting structure 110.
  • solder material 109 As described above, Sn-3 wt% Ag-0.5 wt% Cu (melting point: 217 ° C.), which is a general solder material, was used as the solder material 109.
  • FIG. 7 shows the result of the yield test.
  • Comparative Example 1 when the high temperature side of the temperature cycle test condition was 150 ° C., the yield was 95%, but when the high temperature side was heated to 175 ° C. and 200, the yield was 65% and 50%. %, It was judged as a defective product (x).
  • Example 1 As a representative example, the reason for the superiority of the Example over Comparative Example 1 will be considered.
  • the configuration of Comparative Example 1 is the Cu electrode 103, the Bi layer 203 (bonding material) in which the Ag layer is diffused, and the Cu that is the lowermost layer of the barrier metal layer 204.
  • Example 1 since the first and second intermediate layers 207 and 206 are laminated on the upper and lower surfaces of the Bi layer 203 (bonding material) in which the Ag layer is diffused, Cu (110 ⁇ 10 9 N / m 2 ) / AuSn4 (55.6 ⁇ 10 9 N / m 2 )) / Bi-3.5 wt% Ag (32 ⁇ 10 9 N / m 2 ) / AuSn4 (55.6 ⁇ 10 9 N / m 2 )) / Cu (110 ⁇ 10 9 N / m 2 ).
  • E Young's modulus
  • ⁇ stress
  • ⁇ strain
  • Comparative Example 1 and Example 1 the difference between Comparative Example 1 and Example 1 is whether or not the AuSn compound (AuSn4) in the intermediate layer is interposed between the Cu layer and the Bi-3.5 wt% Ag layer.
  • AuSn4 the AuSn compound
  • the Young's modulus increases in a gradient due to the presence of an intermediate layer from the bonding material of Bi-3.5 wt% Ag toward Cu, and the spring effect works and the stress relaxation function is expressed. Conceivable.
  • the intermediate layer is only on the semiconductor element 102 or the Cu electrode 103 side of the bonding material 104, the stress relaxation function is effectively expressed.
  • it is desirable to provide an intermediate layer on both the semiconductor element 102 side and the Cu electrode 103 side.
  • Example 4 to 5 Example 9 to 10, and Examples 14 to 15 the thickness of the intermediate layer after bonding was greatly reduced to 0.5 ⁇ m compared to the thickness of the Au and Ag layers before bonding. Yes. This is because the electrode surface treatment layer before bonding and the Bi-3.5 wt% Ag diffused in the portion close to the Bi underlayer, but even with this configuration, the desired spring effect works. Thus, the yield test confirms that the stress relaxation function is effectively exhibited.
  • the present invention is characterized in that the Young's modulus is gradually increased from the stacked body toward the semiconductor element or the electrode.
  • the Young's modulus of the first intermediate layer 207 (AuSn4) of Example 1 is 55. .6 ⁇ 10 9 N / m 2
  • Young's modulus of (32 ⁇ 10 9 N / m 2) of is a numerical value substantially inboard in example 3
  • the Young's modulus of the first intermediate layer 207 (Cu6Sn5) is 93.5 ⁇ 10 9 N / m 2 It is a numerical value close to the Young's modulus (110 ⁇ 10 9 N / m 2 ) of the Cu layer of the barrier metal layer 204.
  • the Young's modulus of the first and second intermediate layers 207 and 206 is close to that of the surface of the semiconductor element, that is, Cu or the electrode Cu under the barrier metal layer, the spring effect works in light of the above test results. If the Young's modulus of the first and second intermediate layers 207 and 206 is between that of Cu on the surface of the semiconductor element and that of the Cu electrode, it can be said that the numerical values in the vicinity of the center need not be designed.
  • the mounting structure having the bonding structure of the present invention includes a semiconductor element and a Cu electrode through a laminated structure in which the Young's modulus increases in a gradient from the bonding material to the material to be bonded (semiconductor element, Cu electrode). Can be applied to a semiconductor package such as a power semiconductor module and a small power transistor.

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Abstract

　半導体素子１０２をＣｕ電極１０３にＢｉを主成分とする接合材料１０４を介して接合した接合構造体１０６において、接合材料１０４から被接合材料（半導体素子１０２、Ｃｕ電極１０３）に向けて、ヤング率が傾斜的に増大するような積層体２０９ａを介して半導体素子１０２とＣｕ電極１０３とを接合することにより、パワー半導体モジュールの使用時における温度サイクルで生じる熱応力に対する応力緩和性を確保する。

Description

接合構造体
　本発明は半導体部品の内部接合に関して、特に、優れた機械特性と耐熱性が要求されるパワー半導体モジュールの半導体素子と電極とをＢｉ系はんだを介して接合した接合構造体に関する。
　エレクトロニクス実装分野においては、従来から、Ｓｎ－Ｐｂ共晶はんだが多用されて来たが、鉛の有害性の懸念や環境への関心の高まりから、近年、鉛を用いない接合が望まれている。
　このため、一般的なはんだ材であるＳｎ－Ｐｂ共晶はんだについては、代替材料が開発、実用化されている。
　一方、半導体部品の内部接合については、高温鉛はんだの代替材料が各種検討されている。
　この代替はんだ材料の候補には、Ａｕ系、Ｚｎ系、Ｓｎ系、Ｂｉ系のものが挙げられる。このうち、Ａｕ系のはんだ材料に関しては、例えば、融点が２８０℃のＡｕ－２０重量％Ｓｎなどが一部実用化されているが、主成分がＡｕであるため、材料物性が硬いうえ、材料コストが高く、小型部品に使用が限定されるなどの理由から汎用性がない。
　Ｚｎ系のはんだ材料は腐食性が強いうえ、弾性率が高すぎるため、半導体部品の内部接合への適用においては機械特性の向上が課題である。
　Ｓｎ系のはんだ材料は優れた機械特性を有するが、融点が２５０℃未満と低く耐熱性に乏しい。そこで、Ｓｎ系の耐熱性向上を目的として、例えばＳｎＣｕ化合物を形成することで、金属間化合物化により融点を上げた接合材料が検討されているが、金属間化合物化の際の凝固収縮により接合時に空隙が発生するため、機械特性、放熱特性の改善が課題である。
　このような理由により、融点が２７０℃付近のＢｉ系が、高温鉛はんだ代替材料の有力候補として検討されている。
　例えば、特許文献１はこのＢｉ系のはんだ材料を接合材料に用いた例である。
　図８は、特許文献１に記載された従来の接合構造体の断面図であり、パワー半導体モジュール４０１は、パワー半導体素子４０２と電極４０３との間に接合部４０４を有し、この接合部４０４には、Ｂｉ－Ａｇ系はんだ材料が用いられており、１５～６０重量％のＡｇを含ませている。
　しかしながら、パワー半導体素子４０２の動作温度がＳｉの場合の１５０℃であれば、特許文献１に記載のＢｉ－Ａｇ系はんだ材料は接合信頼性を有するが、パワー半導体素子４０２の動作温度がＧａＮ、ＳｉＣといったＳｉよりも動作温度が高い１７５℃、或いは２００℃の環境下では、特許文献１に記載のＢｉ－Ａｇ系はんだ材料では接合部４０４にクラック、剥離などが生じてしまう恐れがある。
　これは、パワー半導体素子４０２の熱膨張係数（α≒３ｐｐｍ／Ｋ）、Ｃｕ電極４０３の線膨張係数（α≒１８ｐｐｍ／Ｋ）の差に基づく熱応力に対して、Ｂｉ－Ａｇ系はんだ材料が応力緩和しきれないため、接合部４０４にクラック、剥離などが生じることに因ると考えられる。
　従って、前記特許文献１に記載のＢｉ－Ａｇ系はんだ材料による接合構造体では、パワー半導体素子４０２の動作温度が１５０℃より高い場合、この高温域に対する応力緩和性の向上が課題となる。
　一方、接合構造体のクラックや剥離の防止を課題とするものに特許文献２がある。
　特許文献２には、半導体素子上に被覆形成される保護樹脂を、半導体素子の中間接合層とはんだ接合層の間の外周面域にも被覆形成させることにより、半導体素子内部の耐クラック性を向上して、半導体素子とはんだ材料の界面や、はんだ材料と電極の界面に加わる熱的応力を軽減することが示される。
特開２００６－３１０５０７号公報 特開２０１１－０２３６３１号公報
　特許文献２に記載の発明では、保護樹脂を所定領域に被覆充填することにより、はんだ材料を介した半導体素子と電極からなる接合構造体の応力緩和性の向上を図っているが、本発明は、保護樹脂の充填を特徴とする特許文献２に記載の発明とは異なる手段で、パワー半導体モジュールの接合構造体において、応力緩和性を改善して、接合部でのクラックや剥離の発生を防止することを技術的課題とする。
　本発明者らは、接合材料から被接合材料（半導体素子、Ｃｕ電極）に向けて、外部応力に対する歪みが傾斜的に変化するような積層構造体を形成することにより、被接合材料（半導体素子、Ｃｕ電極）の熱膨張係数差に基づく熱応力を有効に緩和・吸収することを着想し、本発明を完成した。
　本発明１は、半導体素子をＣｕ電極にＢｉを主成分とする接合材料により接合した接合構造体において、前記接合材料とこの接合材料の表面に形成した中間層とから積層体を構成し、この積層体を介して前記半導体素子の表面のＣｕと前記Ｃｕ電極とを接合して、前記半導体素子の表面のＣｕのヤング率をＥ１、前記中間層のヤング率をＥ２、前記接合材料のヤング率をＥ３、前記Ｃｕ電極のヤング率をＥ４とした場合に、各ヤング率Ｅ１～Ｅ４が、次の条件（ｐ１），（ｑ１）の両方またはどちらか
　　　Ｅ３ ＜ Ｅ２ ＜ Ｅ１　　…（ｐ１）
　　　Ｅ３ ＜ Ｅ２ ＜ Ｅ４　　…（ｑ１）
を満たすように、前記積層体を前記半導体素子及び前記Ｃｕ電極に対して構成したことを特徴とする接合構造体である。
　本発明２は上記発明１において、前記積層体が、前記接合材料と、この接合材料の上・下両面に形成した２つの中間層からなる３層の積層体であって、前記半導体素子の側の第１中間層のヤング率をＥ２１とし、前記Ｃｕ電極の側の第２中間層のヤング率をＥ２４とすると、各ヤング率Ｅ１、Ｅ２１、Ｅ２４、Ｅ３、Ｅ４が、次の条件（ｐ２）及び（ｑ２）
　　　Ｅ３ ＜ Ｅ２１ ＜ Ｅ１　　…（ｐ２）
　　　Ｅ３ ＜ Ｅ２４ ＜ Ｅ４　　…（ｑ２）
を満たすように、３層の積層体を前記半導体素子及び前記Ｃｕ電極に対して構成したことを特徴とする接合構造体である。
　本発明３は上記発明１において、前記積層体が、前記接合材料と、この接合材料の前記半導体素子の側に形成した中間層からなる２層の積層体であって、前記半導体素子の側の中間層のヤング率をＥ２１とした場合に、各ヤング率Ｅ１、Ｅ２１、Ｅ３が、次の条件（ｐ２）
　　　Ｅ３ ＜ Ｅ２１ ＜ Ｅ１　　…（ｐ２）
を満たすように、２層の積層体を前記半導体素子及び前記Ｃｕ電極に対して構成したことを特徴とする接合構造体である。
　本発明４は上記発明１において、前記積層体が、前記接合材料と、この接合材料の前記Ｃｕ電極の側に形成した中間層からなる２層の積層体であって、前記中間層のヤング率をＥ２４とした場合に、各ヤング率Ｅ２４、Ｅ３、Ｅ４が、次の条件（ｑ２）
　　　Ｅ３ ＜ Ｅ２４ ＜ Ｅ４　　…（ｑ２）
を満たすように、２層の積層体を前記半導体素子及び前記Ｃｕ電極に対して構成したことを特徴とする接合構造体である。
　本発明５は上記発明１～４のいずれかにおいて、前記中間層が、ＡｕＳｎ化合物、ＡｇＳｎ化合物、ＣｕＳｎ化合物、Ａｕ、Ａｇよりなる群から選ばれた金属の少なくとも一種であることを特徴とする接合構造体である。
　本発明６は上記発明１～５のいずれかにおいて、前記中間層がＣｕＳｎ化合物であることを特徴とする接合構造体である。
　本発明は、接合材料から被接合材料に向けて、ヤング率が傾斜的に増大するような積層構造を介して半導体素子とＣｕ電極を接合することにより、パワー半導体モジュールの使用時における温度サイクルで生じる熱応力に対して、いわゆるバネ効果を働かせて優れた応力緩和機能を発現させるため、半導体素子と電極とを品質良く接合し、もって接合信頼性を向上できる。
接合構造体を構成要素とする実装構造体の断面図 本発明の実施の形態２における接合構造体の製造工程図 本発明の実施の形態２における接合構造体の製造工程図 本発明の実施の形態２における接合構造体の製造工程図 本発明の実施の形態３における接合構造体の構成図 本発明の実施の形態４における接合構造体の構成図 実装構造体の拡大断面図 本発明の実施の形態における実施例１～１５について、接合前の電極表面処理層及びＢｉ下地層の構成と厚み、接合後の第２中間層，第１中間層の組成と厚みをまとめた図表 接合構造体の歩留まり試験結果を示す図表 従来技術を示す実装構造体の拡大断面図
　実施の形態１に記載の発明は、半導体素子をＣｕ電極にＢｉを主成分とする接合材料により接合した接合構造体において、接合材料とこの接合材料の表面に形成した中間層とから積層体を構成し、この積層体を介して半導体素子の表面のＣｕと前記Ｃｕ電極とを接合して、前記接合材料、前記中間層、前記半導体素子の一方向に向けて、或いは、前記接合材料、前記中間層、前記Ｃｕ電極の一方向に向けて各ヤング率を順次増大させるか、又はさらに、前記接合材料から中間層経由で前記半導体素子と前記Ｃｕ電極との両方向に向けて各ヤング率を順次増大させた接合構造体である。
　これを分かり易く説明すると、接合構造体においては、半導体素子の表面のＣｕのヤング率をＥ１、前記中間層のヤング率をＥ２、前記接合材料のヤング率をＥ３、前記Ｃｕ電極のヤング率をＥ４とした場合に、各ヤング率Ｅ１～Ｅ４が、次の条件（ｐ１），（ｑ１）
　　　Ｅ３ ＜ Ｅ２ ＜ Ｅ１　　…（ｐ１）
　　　Ｅ３ ＜ Ｅ２ ＜ Ｅ４　　…（ｑ１）
の両方またはどちらかを満たすように、前記積層体を前記半導体素子と前記Ｃｕ電極に対して構成する。
　また、以下に説明する実施の形態２～４に記載の発明は、実施の形態１に記載の発明の下位概念的発明であり、実施の形態２に記載の発明は、前記接合材料の上・下両面に中間層を形成して、この３層の積層体（中間層、接合材料、中間層）を半前記導体素子と前記Ｃｕ電極の間に介在させて、前記接合材料から前記中間層経由で前記半導体素子と前記Ｃｕ電極との両面に向けて各ヤング率を順次増大させて、応力緩和を図るものである。
　次いで、実施の形態３に記載の発明は、前記接合材料の前記半導体素子に臨む面に中間層を形成して２層の積層体（中間層、接合材料）を構成し、前記接合材料、前記中間層、前記半導体素子に向けて各ヤング率を順次増大させて、応力を緩和するものである。
　実施の形態４に記載の発明は前記接合材料の前記Ｃｕ電極の側の面に中間層を形成して２層の積層体（中間層、接合材料）を構成し、実施の形態３に記載の発明と同様に各ヤング率を順次増大させて、応力緩和を図るようにした接合構造体である。
　尚、実施の形態に記載の発明では、電極、或いは後述するバリアメタル層の最下層の材質としての銅は、銅並びに銅合金を包含する概念である。
　以下、実施の形態に記載の発明を図面に基づいて説明する。
　図１は、実施の形態に記載の発明の接合構造体を構成要素とする実装構造体の断面図である。
　先ず、接合材料１０４により半導体素子１０２とＣｕ電極１０３を接合して接合構造体１０６を形成し、次いで、接合構造体１０６を封止樹脂１０５で封止してパワー半導体モジュール１００を形成し、最後に、パワー半導体モジュール１００をはんだ材料１０９を用いて基板１０１に実装して、実装構造体１１０を形成している。
　接合構造体１０６について詳述する。
　図２Ａ，図２Ｂ，図２Ｃは接合構造体１０６の製造工程図である。ここでは図２Ｃに示すように、接合材料１０４の下面に第２中間層２０６を形成し、接合材料１０４の上面に第１中間層２０７を形成した場合、つまり、３層の積層体２０９ａを介在させた場合を説明する。
　先ず、図２Ａは、Ｃｕ電極１０３を供給する工程図である。
　Ｃｕ電極１０３の供給に際しては、水素５％を含んだ窒素雰囲気中（室温）にＣｕ電極１０３を供給する。Ｃｕ合金で構成されたＣｕ電極１０３には、表面処理層として電解めっき法によりＡｇ層２０１、及び電極表面処理層２０２を、予め成膜させている。
　図２Ｂは、Ｂｉ層２０３を具備した半導体素子１０２を、Ｃｕ電極１０３の表面処理層であるＡｇ層２０１の上に載置する工程図である。
　半導体素子１０２を載置するに際しては、水素５％を含んだ窒素雰囲気中で、Ｃｕ電極１０３を３２０℃に加熱している。
　ＧａＮで構成され、厚み０．３ｍｍ、４ｍｍ×５ｍｍの大きさの半導体素子１０２には、蒸着法により、ＧａＮ側からＣｒ０．１μｍ／Ｎｉ１μｍ／Ｃｕ３μｍの多層よりなるバリアメタル層２０４、Ｂｉ下地層２０５を予め成膜し、また、電気めっき法によりＢｉ下地層２０５上に厚み１０μｍのＢｉよりなるＢｉ層２０３を成膜している。
　上記バリアメタル層２０４について述べると、半導体素子１０２側のＣｒは、Ｓｉとオーミック接合により導通を確保するために成膜される。
　また、バリアメタル層２０４のＮｉは、半導体素子のデバイスにＣｕ成分が拡散することによるデバイスの機能低下を防ぐため、つまりＣｕの拡散防止用に成膜される。
　バリアメタル層２０４のＣｕは、前記Ｂｉ下地層２０５に接する層である。このＣｕ層を設ける理由については、前記Ｂｉ層２０３のＢｉとＮｉは界面に金属間化合物Ｂｉ３Ｎｉを形成し、この脆い金属化合物層が例えばパワー半導体モジュールの使用時に熱応力により変形する際に亀裂の起点となる恐れがあることから、Ｂｉとバリアメタル層のＮｉとの間にＣｕを成膜してＢｉのＮｉへの拡散を防止するためである。
　Ｃｕを選定したのは、Ｂｉに対する溶解量が少ない（０．４ａｔ％程度）金属であることから、Ｂｉの拡散を防ぐバリア効果を発現させるためである。また、Ｃｕの厚みに関しては、１μｍ以上あればＢｉの拡散を防ぐことが可能であるが、電気めっき法での成膜厚みのバラつき２μｍを考慮し、３μｍとしている。
　上記Ｂｉ層２０３はＣｕ電極１０３の表面処理層であるＡｇ層２０１に接するように、半導体素子１０２を５０ｇｆ～１５０ｇｆ程度の荷重で、Ｃｕ電極１０３の上に載置している。
　ちなみに、後述する本発明の実施例では６０ｇｆの荷重で、半導体素子１０２をＣｕ電極１０３の上に載置している。
　図２Ｃでは、溶融したＢｉ層２０３にＡｇ層２０１の一部が拡散した状態の接合材料１０４を自然冷却により凝固させる工程図である。この図２Ｃの工程では、水素５％を含んだ窒素雰囲気中で自然冷却させ、接合材料１０４が凝固することによりＣｕ電極１０３と半導体素子１０２とを接合させ、接合構造体１０６を製造する。
　接合材料１０４について説明する。
　前述したように、図２Ｂ～図２ＣのＢｉ層２０３が溶融して凝固するまでの間、ＢｉにはＣｕ電極１０３の表面処理層であるＡｇ層２０１が拡散する。
　上記Ｂｉ層２０３のＢｉはＡｇと〈Ｂｉ－３．５重量％Ａｇ〉の２元共晶を形成するため、Ｂｉに対してＡｇが拡散した後の接合材料１０４の融点は２６２℃となる。
　Ｃｕ電極１０３の表面処理層としてＡｇ層２０１を形成する目的は、半導体素子１０２の下部全面に対する溶融Ｂｉの濡れ性を確保するためである。
　第２中間層２０６、第１中間層２０７について説明する。
　先ず、第２中間層２０６は、３２０℃の加熱状態で電極表面処理層２０２中の拡散反応により、或いは電極表面処理層２０２とＣｕ電極１０３のＣｕとの拡散反応により形成された層である。
　同様に、第１中間層２０７も、３２０℃の加熱状態でＢｉ下地層２０５中の拡散反応により、或いはバリアメタル層２０４の最下層であるＣｕとＢｉ下地層２０５との拡散反応により形成された層である。
　上述の接合構造体１０６は、Ｃｕ電極１０３と半導体素子１０２の表面のＣｕを、第２中間層２０６と接合材料１０４と第１中間層２０７との３層の積層体２０９ａを介して接合したものである。接合部２０８の応力緩和には、接合材料１０４、第２中間層２０６、Ｃｕ電極１０３に向けて、また、接合材料１０４、第１中間層２０７、半導体素子１０２に向けて、各ヤング率が順次増大、つまり傾斜的に増大する必要がある。
　これは、上記第１中間層２０７のヤング率が接合材料１０４のヤング率と半導体素子１０２の表面のヤング率との間にあり、つまり中間の値をとり、且つ、第２中間層２０６のヤング率が接合材料１０４のヤング率とＣｕ電極１０３のヤング率との間、つまり中間の値をとることにより達成される。
　３層の積層体２０９ａをさらに詳しく説明する。
　半導体素子１０２に臨む側の第１中間層２０７のヤング率をＥ２１とし、Ｃｕ電極１０３に臨む側の第２中間層２０６のヤング率をＥ２４とすると、半導体素子１０２の表面のＣｕのヤング率をＥ１、接合材料１０４のヤング率をＥ３、Ｃｕ電極１０３のヤング率をＥ４とした場合に、次の条件（ｐ）及び（ｑ）
　　　Ｅ３ ＜ Ｅ２１ ＜ Ｅ１　　…（ｐ）
　　　Ｅ３ ＜ Ｅ２４ ＜ Ｅ４　　…（ｑ）
を満たすように、上記積層体２０９ａを半導体素子１０２及びＣｕ電極１０３に対して構成する。
　この場合、中間層のヤング率が中間の値をとるとは、例えば、半導体素子１０２側に近い第１中間層２０７で説明すると、接合材料１０４のヤング率Ｅ３と半導体素子１０２のバリアメタル層２０４の下層（Ｃｕ）のヤング率とのほぼ中央寄りの数値だけを意味するのではなく、バリアメタル層２０４の下層（Ｃｕ）のヤング率、又は接合材料のヤング率に近い数値、つまり、中央値から一方のヤング率の方に偏った数値であっても差し支えない。後述の実施例１は前者の例、実施例３は後者の例である。
　一方、実施の形態３，４に記載の発明に示す通り、２層の積層体を半導体素子と電極の間に介在させて応力緩和を図ることができる。
　図３は積層体が２層の場合の実施の形態３に記載の発明の接合構造体を示す。
　積層体の中間層が接合材料１０４の前記半導体素子１０２の側に形成されている。この積層体２０９ｂには接合材料１０４の前記Ｃｕ電極１０３の側に中間層は形成されていない。
　Ｃｕ電極１０３と半導体素子１０２の表面のＣｕを、接合材料１０４と第１中間層２０７との２層の積層体２０９ｂを介して接合し、第１中間層２０７のヤング率を接合材料１０４のヤング率と半導体素子１０２のバリアメタル層２０４の下層（Ｃｕ）のヤング率との間に設定することにより、接合材料１０４と第１中間層２０７の２層の積層体２０９ｂの各ヤング率が、接合材料１０４、第１中間層２０７、半導体素子１０２のバリアメタル層の下層（Ｃｕ）に向けて順次増大するように構成する。
　そこで、この点を接合材料１０４の半導体素子側に中間層を形成した２層積層体に関する実施の形態３に記載の発明に基づいて説明すると、２層の積層体２０９ｂをさらに詳しく説明する。
　半導体素子１０２の側の第１中間層２０７のヤング率をＥ２１とし、半導体素子１０２の表面のＣｕのヤング率をＥ１、接合材料１０４のヤング率をＥ３とした場合に、次の条件（ｐ）
　　　Ｅ３ ＜ Ｅ２１ ＜ Ｅ１　　…（ｐ）
を満たすように、２層の積層体２０９ｂを半導体素子１０２とＣｕ電極１０３の間に構成する。
　次に、図４は積層体が別の２層構造の場合の実施の形態４に記載の発明の接合構造体を示す。
　この図４では、積層体の中間層が接合材料１０４の前記Ｃｕ電極１０３側に形成されている。この積層体２０９ｃには接合材料１０４の半導体素子１０２前記に中間層は形成されていない。
　Ｃｕ電極１０３と半導体素子１０２の表面のＣｕを、接合材料１０４と第２中間層２０６との２層の積層体２０９ｃを介して接合して、第２中間層２０６のヤング率を接合材料１０４のヤング率とＣｕ電極１０３のヤング率との間に設定することにより、接合材料１０４と第２中間層２０６の２層の積層体２０９ｃの各ヤング率が、接合材料１０４、第２中間層２０６、Ｃｕ電極１０３に向けて順次増大するように構成する。
　２層の積層体２０９ｃをさらに詳しく説明する。
　電極に臨む第２中間層２０６のヤング率をＥ２４とした場合に、接合材料１０４のヤング率をＥ３、Ｃｕ電極１０３のヤング率をＥ４とした場合に、次の条件（ｑ）
　　　Ｅ３ ＜ Ｅ２４ ＜ Ｅ４　　…（ｑ）
を満たすように、２層の積層体２０９ｃを半導体素子１０２とＣｕ電極１０３の間に構成する。
　接合構造体１０６を作成する際には、図３または図４に示すように中間層を接合材料１０４の一方の面にだけ形成して２層の積層体２０９ｂ，２０９ｃとしてもバネ効果を働かせることができるが、図２Ｃに示したように中間層を接合材料１０４の上・下面に形成して３層の積層体２０９ａにすると、バネ効果の働きはより良好になる。
　また、中間層の材質は、ＡｕＳｎ化合物、ＡｇＳｎ化合物、ＣｕＳｎ化合物、Ａｕ、Ａｇよりなる群から選定するのが好ましく、より好ましくはＣｕＳｎ化合物である。
　さらに、中間層の厚みについて、Ａｕ／Ｓｎの構成を例にとって説明する。
　接合前のＡｕ／Ｓｎの構成が接合後にＡｕＳｎ化合物になる反応は、下式（ａ）で表される。
　　　　　　　Ａｕ ＋ ４Ｓｎ → ＡｕＳｎ４　　　　　　…（ａ）
　ここで、接合前のＡｕの厚みをＬＡｕ、Ｓｎの厚みをＬＳｎとすると、化学量論的に両者の関係は下式（ｂ）のようになる。
　　　　ＬＳｎ ＝ ４×ＬＡｕ×ρＡｕ×ＭＳｎ／ρＳｎ×ＭＡｕ　　…（ｂ）
式（ｂ）中、ρは密度、Ｍは原子量、添え字は各元素を夫々表す。
　そこで、例えば、後述の実施例１に基づいて述べると、Ａｕを０．１μｍ成膜する場合、（ｂ）式に各物性値を代入すると、相当する接合前のＳｎの厚みは０．６μｍ強となるため、接合前のＳｎの厚みが０．６μｍ未満であれば、接合後には、上式（ａ）の金属間化合物のみが生成し、接合前のＳｎ成膜のうち、全てのＳｎが消失することがわかる。
　そこで、実施例１ではめっきの成膜ばらつきを考慮して、金属間化合物のみが確実に生成するように、Ｓｎの厚みは０．６μｍよりかなり薄い０．３μｍの成膜を狙った。
　従って、Ａｕの成膜厚みは０．１μｍ以外の場合でも、適宜、上記設計思想に基づき、接合後にＳｎの単層を残さないように、接合前のＳｎの厚みを設定すればよい。
　接合後にＳｎの単層が残ると、接合部２０８中でＳｎの融点である２３２℃の相が形成されてしまい、パワー半導体１００の基板１０１に対する実装時に再溶融する恐れがあるため、接合後にＳｎの単層を残さないようにしている。
　以上が、Ａｕ／Ｓｎの構成に関する説明であるが、他のＡｇ／Ｓｎ、Ｓｎ、Ａｕ、Ａｇの各水準に対する厚みに関する厚みの考え方も、上記に倣えばよい。
　以上のように、接合構造体１０６の作成が完了したならば、前記図１に示す通り、接合構造体１０６を用いてパワー半導体モジュール１００を作成し、これをはんだ材料１０９で基板１０１に実装して、実装構造体１１０を作成する（図５参照）。
　実装の際のはんだ材料１０９は、一般的には、Ｓｎ－３重量％Ａｇ－０．５重量％Ｃｕ（融点２１７℃）を用いるが、鉛フリーのＳｎ系はんだであれば、これに限らず、例えば、Ｓｎ－０．７重量％Ｃｕ（融点２２７℃）、Ｓｎ－３．５重量％Ａｇ－０．５重量％Ｂｉ－６．０重量％Ｉｎ（融点２２０℃）等を用いても良い。
　　　　　　　　　　　　　　－　実施例　－
　以下、実施の形態に記載の発明である接合構造体の実施例、接合構造体より得られたパワー半導体モジュールを基板に実装した実装構造体の製造例、実装構造体による歩留まりの評価試験例を説明する。
　　　　　　　　　　　《　接合構造体の実施例　》
　下記の実施例１～１５のうち、実施例１～５は前述した通り、接合材料１０４の上・下面に第１，第２中間層２０７，２０６を夫々形成した例、実施例６～１０は接合材料１０４のうちの前記半導体素子１０２の側に第１中間層２０７のみを形成した例、実施例１１～１５は接合材料１０４のうちの前記Ｃｕ電極１０３の側に第２中間層２０６のみを形成した例である。
　また、従来技術に準拠して、電極表面処理層２０２及びＢｉ下地層２０５を設けず、加熱・拡散による第１，第２中間層２０７，２０６を形成しない場合を比較例１とした。
　尚、図６には、実施例１～１５について、接合前の電極表面処理層２０２、Ｂｉ下地層２０５の構成と厚み、接合後の第２中間層２０６，第１中間層２０７の組成と厚みをまとめた。
　（１）実施例１
　図６に示すように、電極表面処理層２０２としてＡｕ０．１μｍ／Ｓｎ０．３μｍの２層を積層状に形成した。この場合、Ｂｉ層２０３から遠い側がＡｕであり、Ｂｉ層２０３に近い側がＳｎである。
　同様に、Ｂｉ下地層２０５としてＡｕ０．１μｍ／Ｓｎ０．３μｍの２層を積層状に形成した。この場合、Ｂｉ層２０３から遠い側がＡｕであり、Ｂｉ層２０３に近い側がＳｎである。
　次いで、３２０℃に加熱して、電極表面処理層２０２中の拡散反応により金属間化合物を生成させて、ＡｕＳｎ化合物２μｍよりなる第２中間層２０６を形成した。同様に、Ｂｉ下地層２０５中の拡散反応により金属間化合物を生成させて、ＡｕＳｎ化合物２μｍよりなる第１中間層２０７を形成した。
　上記ＡｕＳｎ化合物については、エネルギー分散型X線分光法（Energy Dispersive X-ray Spectroscopy）により、ＡｕＳｎ４（ＡｕとＳｎが原子量比で１対４）であることを確認した。
　（２）実施例２
　図６に示すように、電極表面処理層２０２としてＡｇ０．５μｍ／Ｓｎ０．１μｍの２層を積層状に形成し、Ｂｉ下地層２０５としてＡｇ０．５μｍ／Ｓｎ０．１μｍの２層を積層状に形成した。この場合、Ｂｉ層２０３から遠い側がＡｇであり、Ｂｉ層２０３に近い側がＳｎである。
　次いで、３２０℃に加熱して、電極表面処理層２０２の拡散反応により、ＡｇＳｎ化合物２μｍよりなる第２中間層２０６を形成した。同様に、Ｂｉ下地層２０５の拡散反応により、ＡｇＳｎ化合物２μｍよりなる第１中間層２０７を形成した。
　上記ＡｇＳｎ化合物については、エネルギー分散型X線分光法により、Ａｇ３Ｓｎ（ＡｇとＳｎが原子量比で３対１）であることを確認した。
　（３）実施例３
　図６に示すように、電極表面処理層２０２としてＳｎ０．５μｍの単層を形成し、Ｂｉ下地層２０５としてＳｎ０．５μｍの単層を形成した。
　次いで、３２０℃に加熱して、電極表面処理層２０２とＣｕ電極１０３のＣｕとの拡散反応により、ＣｕＳｎ化合物２μｍよりなる第２中間層２０６を形成した。同様に、Ｂｉ下地層２０５とバリアメタル層２０４の最下層であるＣｕとの拡散反応により、ＣｕＳｎ化合物２μｍよりなる第１中間層２０７を形成した。
　上記ＣｕＳｎ化合物については、エネルギー分散型X線分光法により、Ｃｕ６Ｓｎ５（ＣｕとＳｎが原子量比で６対５）であることを確認した。
　（４）実施例４
　図６に示すように、電極表面処理層２０２としてＡｕ２μｍの単層を形成し、Ｂｉ下地層２０５としてＡｕ２μｍの単層を形成した。
　次いで、３２０℃に加熱して、電極表面処理層２０２の拡散により、Ａｕ０．５μｍよりなる第２中間層２０６を形成し、同様に、Ｂｉ下地層２０５の拡散により、Ａｕ０．５μｍよりなる第１中間層２０７を形成した。ちなみに、Ａｕは電極、或いはバリアメタル層２０４の最下層のＣｕとは金属間化合物を形成しない。
　（５）実施例５
　図６に示すように、電極表面処理層２０２としてＡｇ２μｍの単層を形成し、Ｂｉ下地層２０５としてＡｇ２μｍの単層を形成した。
　次いで、３２０℃に加熱して、電極表面処理層２０２の拡散により、Ａｇ０．５μｍよりなる第２中間層２０６を形成し、同様に、Ｂｉ下地層２０５の拡散により、Ａｇ０．５μｍよりなる第１中間層２０７を形成した。ちなみに、Ａｇは電極、或いはバリアメタル層２０４の最下層のＣｕとは金属間化合物を形成しない。
　（６）実施例６～１０
　図６に示す構成と厚みで２層又は単層のＢｉ下地層２０５を形成した後、３２０℃に加熱して、図６に示す組成と厚みの第１中間層２０７を形成した。第２中間層２０６は形成しなかった。
　（７）実施例１１～１５
　図６に示す構成と厚みで２層又は単層の電極表面処理層２０２を形成した後、３２０℃に加熱して、図６に示す組成と厚みの第２中間層２０６を形成した。第１中間層２０７は形成しなかった。
　　　　　　　　　　　《　実装構造体の製造例　》
　図５に示すように、上記実施例により完成させた接合構造体１０６を使用して、ワイヤ１０７を用いてワイヤボンディング（リボンボンディングでも良い）を行い、封止を実施してパワー半導体モジュール１００を形成した後、このパワー半導体モジュール１００をはんだ材料で基板１０１に実装して、実装構造体１１０を形成した。
　上記はんだ材料１０９には、前述した通り、一般的なはんだ材料であるＳｎ－３重量％Ａｇ－０．５重量％Ｃｕ（融点２１７℃）を用いた。
　そこで、上記実装構造体１１０の製品歩留まりを評価した。
　　　　　　　《　実装構造体による歩留まり評価試験例　》
　低温側を－６５℃に固定し、高温側を１５０℃、１７５℃、２００℃の３段階に設定して、低温－高温間の温度サイクル試験（１サイクル３０分／３０分）を３００サイクル繰り返した後、製品を超音波映像で観察して、接合構造体の接合材料のクラック、剥離の有無を目視で判定し、接合部の表面積に対してクラック、剥離が２０％未満に収まる製品歩留まり（Ｎ数＝２０）を算出し、下記の基準でその優劣を評価した。
　　　○　：　歩留まりが８０％以上（良品）であった。
　　　×　：　歩留まりが８０％未満（不良品）であった。
　　　　　　　　　《　歩留まり試験の評価について　》
　図７は歩留まり試験の結果を表す。
　先ず、実施例１～１５では、温度サイクル試験条件の高温側が１５０℃、１７５℃、２００℃のいずれの場合も、歩留まりが８０％以上であり、良品（○）の判定であった。
　これに対して、比較例１では、温度サイクル試験条件の高温側が１５０℃の場合には、歩留まりは９５％であったが、高温側が１７５℃、２００に昇温すると、歩留まりは６５％、５０％に低下して、不良品（×）の判定となった。
　一般に、温度サイクル試験では、高温側と低温側の温度差ΔＴが大きいと半導体素子１０２の熱膨張係数（α≒３ｐｐｍ／Ｋ）、Ｃｕ電極１０３の材料であるＣｕの線膨張係数（α≒１８ｐｐｍ／Ｋ）の差に基づく熱応力が大きくなり、接合構造体における接合部２０８にその応力が加わる。
　比較例１（従来技術）を見ると、高温側が１５０℃に対する耐熱応力は有するが、１７５℃、２００℃に対する耐熱応力は具備しないことがわかる。
　これに対して、本発明の実施例１～１５では、いずれも良品の判定であった。
　そこで、実施例１を代表例として、比較例１に対する実施例の優位性の理由を考察する。
　先ず、接合部の各構成のヤング率を見ると、比較例１の構成は、Ｃｕ電極１０３と、Ａｇ層が拡散したＢｉ層２０３（接合材料）と、バリアメタル層２０４の最下層であるＣｕ層との３層構造なので、Ｃｕ（１１０×１０９Ｎ／ｍ２）／Ｂｉ－３．５重量％Ａｇ（３２×１０９Ｎ／ｍ２）／Ｃｕ（１１０×１０９Ｎ／ｍ２）となる。
　これに対して、実施例１の構成では、Ａｇ層が拡散したＢｉ層２０３（接合材料）の上・下面に第１，第２中間層２０７，２０６を積層するので、Ｃｕ（１１０×１０９Ｎ／ｍ２）／ＡｕＳｎ４（５５．６×１０９Ｎ／ｍ２））／Ｂｉ－３．５重量％Ａｇ（３２×１０９Ｎ／ｍ２）／ＡｕＳｎ４（５５．６×１０９Ｎ／ｍ２））／Ｃｕ（１１０×１０９Ｎ／ｍ２）となっている。
　下式（ｃ）のように、ヤング率は材料が弾性的に挙動する場合の応力とひずみの比であり、
　　　　　　　Ｅ ＝ σ ／ ε　　　　　…（ｃ）
式（ｃ）中、Ｅはヤング率、σは応力、εは歪みを表す。
　ヤング率とひずみ量は反比例するため、一定の応力が加わった場合、ヤング率が小さい方が、歪むことができる量が大きいことになる。
　従って、比較例１と実施例１の違いは、Ｃｕ層とＢｉ－３．５重量％Ａｇ層の間に中間層のＡｕＳｎ化合物（ＡｕＳｎ４）が介在するか否かということになるが、実施例１では、Ｂｉ－３．５重量％Ａｇの接合材料からＣｕに向けて、中間層があることで傾斜的にヤング率が増大することになり、バネ効果が働き応力緩和機能が発現したものと考えられる。
　しかしながら、比較例１では、このような傾斜的なヤング率の増大はなく、接合材料のヤング率と電極又はバリアメタル層のそれとの差異は大きいため、いわゆる、バネ効果は働かず、これが比較例１に対する実施例１の優位性、つまり、高温側の温度条件により歩留まりの差が生じた理由であると推定できる。
　他の実施例２～１５の各中間層についても同様であり、
　　試料２、７、１２の中間層（Ａｇ３Ｓｎ）　
                                 ：ヤング率＝７４．５×１０９Ｎ／ｍ２
　　試料３、８、１３の中間層（Ｃｕ６Ｓｎ５）
                                 ：ヤング率＝９３．５×１０９Ｎ／ｍ２
　　試料４、９、１４の中間層（Ａｕ）
                         　　　　：ヤング率＝８０×１０９Ｎ／ｍ２
　　試料５、１０、１５の中間層（Ａｇ）　
                             　　：ヤング率＝７６×１０９Ｎ／ｍ２
　ＣｕとＢｉ－３．５重量％Ａｇの間に上記各種の中間層が介在することにより、バネ効果が働き、応力緩和機能が発現したものと推定できる。
　そこで、以下では実施例１～１５の試験結果を詳細に検討する。
　接合材料１０４の両面に第１，第２中間層２０７，２０６が存在する実施例１～５と、第１中間層２０７のみの実施例６～１０、及び第２中間層２０６のみの実施例１１～１５とを対比すると、図７の歩留まりには１０～１５％の差があり、中間層が両方存在する実施例１～５の方が歩留まりに優位性があることが分かる。
　従って、中間層は接合材料１０４の前記半導体素子１０２又は前記Ｃｕ電極１０３側のみにあっても応力緩和機能は有効に発現するが、応力緩和機能をより促進するためには、接合材料１０４の前記半導体素子１０２側と前記Ｃｕ電極１０３の側の両方に中間層を設けることが望ましいといえる。
　また、実施例４～５、実施例９～１０、実施例１４～１５では、接合後の中間層の厚みは、接合前のＡｕ、Ａｇ層の厚みに比べて０．５μｍと大きく減少している。これは、接合前の電極表面処理層、Ｂｉ下地層に近い部分のＢｉ－３．５重量％Ａｇ中に拡散したためであるが、このような構成であっても、所望とするバネ効果の働きにより応力緩和機能は有効に発現することが上記歩留まり試験で裏付けられる。
　また、本発明は、積層体から半導体素子又は電極に向けてヤング率を傾斜的に増大させることに特徴があるが、例えば、実施例１の第１中間層２０７（ＡｕＳｎ４）のヤング率は５５．６×１０９Ｎ／ｍ２であり、バリアメタル層２０４の最下層であるＣｕ層のヤング率（１１０×１０９Ｎ／ｍ２）と、接合材料（Ｂｉ－３．５重量％Ａｇ）のヤング率（３２×１０９Ｎ／ｍ２）のほぼ中央寄りの数値であるが、実施例３では、第１中間層２０７（Ｃｕ６Ｓｎ５）のヤング率は９３．５×１０９Ｎ／ｍ２であり、バリアメタル層２０４のＣｕ層のヤング率（１１０×１０９Ｎ／ｍ２）に近い数値である。
　従って、第１，第２中間層２０７，２０６のヤング率は半導体素子の表面、つまり、バリアメタル層の下層のＣｕ又は電極Ｃｕのそれに近い値でも、上記試験結果に照らしてバネ効果が働くので、第１，第２中間層２０７，２０６のヤング率は半導体素子の表面のＣｕのそれと、Ｃｕ電極のそれとの間にあれば、中央付近の数値に設計しなくても差し支えないといえる。
　本発明の接合構造体を有する実装構造体は、接合材料から被接合材料（半導体素子、Ｃｕ電極）に向けて、ヤング率が傾斜的に増大するような積層構造を介して半導体素子とＣｕ電極とを接合することにより、パワー半導体モジュールの使用時における温度サイクルで生じる熱応力に対する応力緩和性を確保し、パワー半導体モジュール、小電力トランジスタ等の半導体パッケージの用途に適用できる。
　１００　　パワー半導体モジュール
　１０１　　基板
　１０２　　半導体素子
　１０３　　Ｃｕ電極
　１０４　　接合材料
　１０６　　接合構造体
　１０９　　はんだ材料
　１１０　　実装構造体
　２０１　　Ａｇ層
　２０２　　電極表面処理層
　２０３　　Ｂｉ層
　２０４　　バリアメタル層
　２０５　　Ｂｉ下地層
　２０６　　第２中間層
　２０７　　第１中間層
　２０９ａ，２０９ｂ，２０９ｃ　　積層体

Claims (6)

  1. 　半導体素子をＣｕ電極にＢｉを主成分とする接合材料により接合した接合構造体において、
    　前記接合材料とこの接合材料の表面に形成した中間層とから積層体を構成し、この積層体を介して半導体素子の表面のＣｕと前記Ｃｕ電極とを接合して、
    　前記半導体素子の表面のＣｕのヤング率をＥ１、前記中間層のヤング率をＥ２、前記接合材料のヤング率をＥ３、前記Ｃｕ電極のヤング率をＥ４とした場合に、
    　各ヤング率Ｅ１～Ｅ４が、次の条件（ｐ１），（ｑ１）
    　　　Ｅ３ ＜ Ｅ２ ＜ Ｅ１　　…（ｐ１）
    　　　Ｅ３ ＜ Ｅ２ ＜ Ｅ４　　…（ｑ１）
    の両方またはどちらかを満たすように、前記積層体を前記半導体素子及び前記Ｃｕ電極に対して構成したことを特徴とする
    接合構造体。
  2. 　前記積層体が、前記接合材料と、この接合材料の上・下両面に形成した２つの中間層からなる３層の積層体であって、前記半導体素子の側の第１中間層のヤング率をＥ２１とし、前記Ｃｕ電極の側の第２中間層のヤング率をＥ２４とすると、
    　各ヤング率Ｅ１、Ｅ２１、Ｅ２４、Ｅ３、Ｅ４が、次の条件（ｐ２）及び（ｑ２）
    　　　Ｅ３ ＜ Ｅ２１ ＜ Ｅ１　　…（ｐ２）
    　　　Ｅ３ ＜ Ｅ２４ ＜ Ｅ４　　…（ｑ２）
    を満たすように、前記３層の積層体を前記半導体素子及び前記Ｃｕ電極に対して構成したことを特徴とする請求項１に記載の接合構造体。
  3. 　前記積層体が、前記接合材料と、この接合材料の前記半導体素子の側に形成した中間層からなる２層であって、前記中間層のヤング率をＥ２１とした場合に、
    　各ヤング率Ｅ１、Ｅ２１、Ｅ３が、次の条件（ｐ２）
    　　　Ｅ３ ＜ Ｅ２１ ＜ Ｅ１　　…（ｐ２）
    を満たすように、前記２層の積層体を前記半導体素子及び前記Ｃｕ電極に対して構成したことを特徴とする請求項１に記載の接合構造体。
  4. 　前記積層体が、前記接合材料と、この接合材料の前記Ｃｕ電極の側に形成した中間層からなる２層の積層体であって、
    　前記中間層のヤング率をＥ２４とした場合に、
    　各ヤング率Ｅ２４、Ｅ３、Ｅ４が、次の条件（ｑ２）
    　　　Ｅ３ ＜ Ｅ２４ ＜ Ｅ４　　…（ｑ２）
    を満たすように、前記２層の積層体を前記半導体素子及び前記Ｃｕ電極に対して構成したことを特徴とする請求項１に記載の接合構造体。
  5. 　前記中間層が、ＡｕＳｎ化合物、ＡｇＳｎ化合物、ＣｕＳｎ化合物、Ａｕ、Ａｇよりなる群から選ばれた金属の少なくとも一種であることを特徴とする
    請求項１～４のいずれか１項に記載の接合構造体。
  6. 　前記中間層がＣｕＳｎ化合物であることを特徴とする
    請求項１～５のいずれか１項に記載の接合構造体。
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