WO2012132655A1 - Back-junction photoelectric conversion element and method for manufacturing back-junction photoelectric conversion element - Google Patents

Back-junction photoelectric conversion element and method for manufacturing back-junction photoelectric conversion element Download PDF

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WO2012132655A1
WO2012132655A1 PCT/JP2012/054233 JP2012054233W WO2012132655A1 WO 2012132655 A1 WO2012132655 A1 WO 2012132655A1 JP 2012054233 W JP2012054233 W JP 2012054233W WO 2012132655 A1 WO2012132655 A1 WO 2012132655A1
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insulating layer
layer
amorphous semiconductor
photoelectric conversion
semiconductor layer
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PCT/JP2012/054233
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French (fr)
Japanese (ja)
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三島　孝博
正人 重松
大樹 橋口
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三洋電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a back junction photoelectric conversion element and a method for manufacturing a back junction photoelectric conversion element, and in particular, a back surface that uses an insulating layer to separately form a p-type region and an n-type region for forming the photoelectric conversion element.
  • the present invention relates to a method for manufacturing a junction type photoelectric conversion element and a back surface junction type photoelectric conversion element.
  • a solar cell is also called a photovoltaic device or a photoelectric conversion element, but is expected as a clean energy source, and various structures are used to improve photoelectric conversion efficiency.
  • Patent Document 1 discloses a configuration in which i-type amorphous silicon and p-type amorphous silicon are stacked on n-type single crystal silicon as a photovoltaic device having a heterojunction.
  • a solar cell is formed across a pair of second semiconductor layers disposed on both sides of the first semiconductor layer and from one of the second semiconductor layers to the first semiconductor layer.
  • the structure provided with the insulating layer and the insulating layer formed ranging over the 1st semiconductor layer from the other 2nd semiconductor layer is disclosed.
  • the transparent electrode layer and the collecting electrode layer are separated into an electrode for the first semiconductor layer and an electrode for the second semiconductor layer by a pair of separation grooves formed on the insulating layer.
  • the solar cell described in Patent Document 2 is provided with an electrode for the first semiconductor layer and an electrode for the second semiconductor layer on the back surface opposite to the light receiving surface.
  • Such a structure is called a back junction type photoelectric conversion element, and since no electrode is arranged on the light receiving surface, a large light receiving area can be obtained and the photoelectric conversion efficiency can be improved.
  • an insulating layer is used to make a p type region and an n type region separately.
  • the electrode opens this insulating layer and is connected to the p-type region or the n-type region.
  • a residue of the insulating layer may remain in the opening process. This hinders the improvement of conversion efficiency.
  • An object of the present invention is to provide a back junction type photoelectric conversion element and a method for producing a back junction type photoelectric conversion element that can reliably remove residues at the time of opening an insulating layer and ensure improvement in conversion efficiency. It is.
  • the back junction type photoelectric conversion element includes a first conductivity type semiconductor substrate having a light receiving surface and a back surface opposite to the light receiving surface, and is disposed on the back surface and connected to the semiconductor substrate.
  • a first conductivity type region configured to include an amorphous semiconductor layer having a semiconductor layer, and an amorphous semiconductor layer disposed on the back surface and having a second conductivity type to form a pn junction with the semiconductor substrate.
  • the insulating layer formed on the amorphous semiconductor layer in either the first conductive type region or the second conductive type region, and the opening provided in the insulating layer An electrode layer connected to an amorphous semiconductor layer provided under the electrode layer and drawn to the outside, and the insulating layer includes a first insulating layer provided in contact with the amorphous semiconductor layer provided under the electrode layer; A second insulating layer formed on the first insulating layer, wherein the first insulating layer In forming the opening, characterized in that it comprises a second insulating layer having a film quality to be removed by a lift-off, the.
  • the manufacturing method of the back junction type photoelectric conversion element according to the present invention is a manufacturing method of a back junction type photoelectric conversion element in which a pn junction is formed on the back surface opposite to the light receiving surface of the first conductivity type silicon substrate.
  • the step of opening the second insulating layer, the etching rate with respect to the first insulating layer is faster than the etching rate with respect to the second insulating layer, and the non-insulating layer provided below the insulating layer than the etching rate with respect to the first insulating layer.
  • the insulating layer is formed on the first insulating layer and the first insulating layer provided in contact with the amorphous semiconductor layer provided therebelow. And a second insulating layer having a film quality that is removed by lift-off when the opening of the first insulating layer is formed.
  • the first insulating layer residues at the time of opening the second insulating layer can be reliably removed by lift-off.
  • FIG. 10 it is a figure explaining a mode that lift-off is performed. It is a figure which shows a mode that a resist is removed after the process of FIG. It is a figure which shows the mode of S40 of FIG. It is a figure which shows the mode of S42 of FIG. It is a figure which shows the mode of S44 of FIG. It is a figure which shows the mode of S46 of FIG. It is sectional drawing of the back junction type photoelectric conversion element as a comparative example. It is a flowchart which shows the procedure of the manufacturing method of the back junction type photoelectric conversion element as a comparative example. It is a figure which shows the mode of S10 in a comparative example. It is a figure which shows the mode of S12 in a comparative example.
  • the conductivity type of the semiconductor substrate is described as n-type, but it may be p-type. Further, the order of formation of the amorphous semiconductor layers is n-type first and p-type thereafter, but this may be interchanged.
  • the opening of the insulating layer for the contact is provided at the n-type amorphous semiconductor layer, it may be provided at the p-type amorphous semiconductor layer.
  • an i-type amorphous semiconductor layer is used in addition to the p-type amorphous semiconductor layer and the n-type amorphous semiconductor layer. Therefore, even if an i-type amorphous semiconductor layer is included between pn junctions, it belongs to the pn junction.
  • the insulating layer has a two-layer structure of SiO 2 and SiN x , but it may have a multilayer structure of two or more layers.
  • SiN x may have a laminated structure of silicon nitride films having different film qualities.
  • the materials, film thicknesses, and the like described below are exemplifications for explanation, and can be appropriately changed according to the specifications of the back junction photoelectric conversion element.
  • FIG. 1 is a cross-sectional view of a back contact type photoelectric conversion element 10.
  • the back junction type photoelectric conversion element 10 a pn junction for performing photoelectric conversion is formed on the back surface opposite to the light receiving surface, and electrodes are provided only on the back surface.
  • the lower side of the paper is the light-receiving surface side
  • the upper side is the back surface.
  • the back junction type photoelectric conversion element 10 is simply referred to as the photoelectric conversion element 10.
  • the photoelectric conversion element 10 is provided with an n-type region 100 and a p-type region 102 on the back surface of a semiconductor substrate 20 which is an n-type silicon single crystal substrate.
  • the n-type region 100 is connected to the semiconductor substrate 20 and includes an n-type amorphous semiconductor layer 28 having the same conductivity type.
  • the i-type amorphous semiconductor layer 24 is provided between the semiconductor substrate 20 and the n-type amorphous semiconductor layer 28, but the i-type amorphous semiconductor layer 24 is not necessarily an essential component.
  • the p-type region 102 includes a p-type amorphous semiconductor layer 44 and forms a pn junction with the semiconductor substrate 20.
  • an i-type amorphous semiconductor layer 42 is provided between the semiconductor substrate 20 and the p-type amorphous semiconductor layer 44, but the i-type amorphous semiconductor layer 42 is not necessarily an essential component. .
  • the n-type region electrode 70 is a plating electrode connected to the n-type amorphous semiconductor layer 28.
  • the electrode 70 has a laminated structure of Sn and Cu.
  • the base electrodes 60 and 62 provided between the n-type region electrode 70 and the n-type amorphous semiconductor layer 28 are seed layers used when the electrode 70 is plated.
  • the base electrodes 60 and 62 have a laminated structure of a transparent electrode layer 60 and a Cu layer 62.
  • the electrode 72 for the p-type region is a plating electrode connected to the p-type amorphous semiconductor layer 44. Similar to the electrode 70, the electrode 72 has a laminated structure of Sn and Cu, and is formed by plating using the base electrodes 60 and 62. Comparing the n-type region electrode 70 and the p-type region electrode 72, the former electrode height is higher than the latter electrode height. This is because the surface area of the former base electrodes 60 and 62 is set smaller than the surface area of the latter base electrodes 60 and 62. That is, when plating is performed using the base electrodes 60 and 62 in common, the plating current density varies depending on the surface area difference, and the smaller surface area grows faster.
  • the electrode 72 for the p-type region is provided directly on the p-type amorphous semiconductor layer 44 via the base electrodes 60 and 62.
  • the electrode 70 for the n-type region is provided with an opening in an insulating layer having a laminated structure of the silicon oxide layer 36 and the silicon nitride layer 40, and through the opening through the base electrodes 60 and 62, the n-type region It is connected to the amorphous semiconductor layer 28.
  • the photoelectric conversion element 10 is characterized in that the insulating layer has a laminated structure of a silicon oxide layer 36 and a silicon nitride layer 40.
  • the thickness of the silicon nitride layer 40 is about 10 nm to 500 nm, but the thickness of the silicon oxide layer 36 is thicker than the thickness of the natural oxide film, and may be about several nm to 200 nm.
  • the i-type amorphous semiconductor layer 22 and the n-type amorphous semiconductor layer 26 provided on the light receiving surface of the semiconductor substrate 20 are layers having a function as a passivation layer of the semiconductor substrate 20 on which photoelectric conversion is performed.
  • the antireflection layer 38 is an insulating film layer having a function of suppressing reflection on the light receiving surface.
  • FIG. 2 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 10. This procedure will be described with reference to FIGS.
  • a semiconductor substrate 20 which is an n-type silicon single crystal substrate is prepared.
  • the plane direction is preferably (100).
  • the surface serving as the light receiving surface has a texture structure. For example, pyramidal irregularities surrounded by the (111) plane can be provided on the surface by utilizing the plane anisotropy of silicon etching.
  • the semiconductor substrate 20 is entirely cleaned with an appropriate cleaning solution for the next step.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are sequentially deposited on the semiconductor substrate 20 having a clean surface (S10).
  • Deposition is also called deposition and is a process of forming a thin film. This step can be performed using a plasma CVD apparatus.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are both formed on the front surface and the back surface of the semiconductor substrate 20.
  • an i-type amorphous semiconductor layer 22 and an n-type amorphous semiconductor layer 26 are formed on the front surface, and an i-type amorphous semiconductor layer 24 and an n-type amorphous semiconductor layer 28 are formed on the back surface. Is shown.
  • a silicon oxide layer is deposited on the back surface (S11).
  • a representative example of silicon oxide is SiO 2 .
  • This step is performed using a plasma CVD apparatus. Since the natural oxide film has a thickness of 1 nm or less, the thickness of the silicon oxide layer is preferably about several nm to 200 nm thicker than this.
  • One of the roles of providing the silicon oxide layer is to protect the surface of the n-type amorphous semiconductor layer 24, thereby improving the photoelectric conversion efficiency. Another role is that it is easily dissolved in HF (hydrofluoric acid). Therefore, in the insulating film opening process described later, the SiN x residue is removed by lift-off, and the surface of the clean n-type amorphous semiconductor layer 24 is removed. It is to be.
  • the characteristic of the photoelectric conversion element 10 is that SiO 2 is provided.
  • FIG. 4 shows how the silicon oxide layer 36 is formed on the n-type amorphous semiconductor layer 28 on the back surface.
  • the silicon nitride layer is deposited (S12). This process is also performed using a plasma CVD apparatus.
  • a typical example of silicon nitride is Si 3 N 4 , but the composition of Si 3 N 4 does not necessarily depend on the manufacturing conditions of the plasma CVD apparatus. Generally, the composition is SiN x .
  • the thickness of the silicon nitride layer 40 is about 10 nm to 500 nm.
  • FIG. 5 shows a state in which the silicon nitride layer 40 is formed on the silicon oxide layer 36 on the back surface.
  • An antireflection layer 38 is formed on the surface that becomes the light receiving surface. Since a silicon nitride film can be used as the antireflection layer 38, the same film as the silicon nitride layer 40 on the back surface may be formed on the light receiving surface side at the same time. However, the silicon nitride layer 40 on the back surface is used for subsequent patterning and etching characteristics are important, whereas the antireflection layer 38 has optical characteristics important. Therefore, the back side silicon nitride layer 40 and the antireflection layer 38 are preferably insulating films having different film characteristics. In the following, the description will be made while distinguishing the silicon nitride layer 40 on the back surface and the antireflection layer 38 on the light receiving surface side.
  • the silicon nitride layer 40 on the back surface can be formed by changing the film composition, for example, so that the etching characteristics can be distinguished from those having alkali resistance and those having acid resistance.
  • the silicon oxide layer 36 side can be formed as an acid-resistant film, and an alkali-resistant film can be formed thereon.
  • the silicon nitride layer in contact with the resist film is preferably resistant to alkali.
  • the silicon nitride layer 40 is partially removed (S14).
  • a photolithography technique is used for this processing. That is, a photosensitive resist film is applied to the entire surface of the silicon nitride layer 40, the resist film in a portion where the silicon nitride layer 40 is to be removed is exposed, and the resist film in that portion is removed by development. This process is patterning of the resist film. Then, using the resist film as an etching mask, a portion of the silicon nitride layer 40 without the resist film is removed using an appropriate etching solution. As the etchant, hydrofluoric acid which is a mixture of HF and nitric acid can be used. After the etching, washing with water is performed.
  • FIG. 6 shows the patterned resist film 80 and the remaining silicon nitride layer 40 using the resist film 80 as an etching mask. Thereafter, the resist film 80 is removed. Since the resist film 80 is soluble in alkali, only the resist film 80 can be removed using caustic soda (NaOH) while leaving the silicon nitride layer 40 as it is.
  • CaOH caustic soda
  • the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 thereunder are formed using the silicon nitride layer 40 as an etching mask. It is removed (S16).
  • caustic soda (NaOH) is used by utilizing the fact that the amorphous semiconductor layer dissolves in alkali.
  • the treatment is performed in the order of organic cleaning, caustic soda, SC2 which is a mixed solution of hydrochloric acid (HCl) and hydrogen peroxide (H 2 O 2 ), hydrofluoric acid, and water washing.
  • the hydrofluoric acid is used to remove the oxide film formed by SC2.
  • the silicon oxide layer 36, the n-type amorphous semiconductor layer 28, and the i-type amorphous semiconductor layer 24 are left in the shape of the silicon nitride layer 40, and the semiconductor substrate 20 is exposed in other portions. The situation is shown. In this way, opening of the portion of the p-type region 102 is performed.
  • the i-type amorphous semiconductor layer 42 and the p-type amorphous semiconductor layer 44 are deposited on the entire surface (S18). This step is performed using a plasma CVD apparatus.
  • the i-type amorphous semiconductor layer 42 and the p-type amorphous semiconductor layer 44 are in contact with the semiconductor substrate 20 which is an n-type silicon single crystal substrate in the opened p-type region 102. Is shown. Note that an i-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer 44 are also deposited on the silicon nitride layer 40.
  • an opening process for contacting the electrode with the n-type amorphous semiconductor layer 28 is performed.
  • a contact is an electrical connection.
  • a silicon oxide layer 36, a silicon nitride layer 40, an i-type amorphous semiconductor layer 42, and a p-type amorphous semiconductor layer 44 are present on the n-type amorphous semiconductor layer 28. Therefore, a process for removing them in order is performed.
  • the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are removed (S20).
  • a photolithography technique is used for this processing. That is, a resist film is applied, and the applied resist film is patterned to remove the n-contact portion by exposure and development. A solvent-soluble type having acid resistance and alkali resistance is used for the resist film.
  • the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 can be removed using caustic soda (NaOH). Thereafter, cleaning is performed.
  • FIG. 9 shows a state where the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 in the opening 83 portion of the resist film 82 are removed.
  • the silicon nitride layer 40 is removed (S22) and the silicon oxide layer 36 is removed (S23).
  • hydrofluoric acid is used. Although hydrofluoric acid can etch both the silicon nitride layer 40 and the silicon oxide layer 36, the etching rate for the silicon oxide layer 36 is considerably faster than the etching rate for the silicon nitride layer 40. Further, the etching rate for the p-type amorphous semiconductor layer 28 is slower than the etching rate for the silicon oxide layer 36.
  • the silicon nitride layer 40 is first etched, and when the silicon oxide layer 36 is reached, the silicon oxide layer 36 is rapidly etched, but when the p-type amorphous semiconductor layer 28 is reached, the etching is performed. Stop.
  • a protective film is preferably provided so that the antireflection layer 38 on the light receiving surface side is not etched.
  • silicon nitride formed by plasma CVD can be removed by hydrofluoric acid, in practice, a minute residue remains, and it may take a considerable time to completely remove the residue.
  • silicon nitride formed by a plasma CVD apparatus may not have a stoichiometric composition of Si 3 N 4 but may have an excessively large Si composition such as Si 3.5 N 4. Conceivable.
  • electrical contact between the electrode and the n-type amorphous semiconductor layer 28 is hindered, and the photoelectric conversion efficiency of the photoelectric conversion element 10 is reduced. Become.
  • the silicon oxide layer 36 when the silicon oxide layer 36 is disposed between the silicon nitride layer 40 and the n-type amorphous semiconductor layer 28, the silicon oxide layer 36 can be easily removed using hydrofluoric acid. At this time, even if there is a residue of the silicon nitride layer 40 on the silicon oxide layer 36, the silicon nitride on the silicon oxide layer 36 is removed by a so-called lift-off phenomenon.
  • the silicon oxide layer 36 and hydrofluoric acid are used to remove the silicon nitride layer 40 by lift-off.
  • an intermediate film that can remove the residue of the insulating layer by lift-off and a remover for the intermediate film Can be used in combination.
  • FIG. 10 shows a state in which the silicon nitride layer 40 and the silicon oxide layer 36 are removed while leaving the resist film 82, and an opening 83 for contact with the n-type amorphous semiconductor layer 28 is formed. .
  • FIG. 11 is a diagram schematically showing how the silicon nitride residue 41 on the silicon oxide layer 36 is removed by the lift-off phenomenon.
  • hydrofluoric acid indicated as HF can reach the silicon oxide layer 36 through the gaps between the silicon nitride residues 41 and dissolve the silicon oxide layer 36.
  • the silicon oxide layer 36 is dissolved, the silicon nitride residue 41 is floated and separated from the silicon oxide layer 36.
  • the silicon nitride residue 41 is removed together with the removal of the silicon oxide layer 36.
  • FIG. 11 is a view showing a state where the resist film 82 has been removed.
  • the base electrode is a conductive seed layer for forming a plating electrode.
  • a transparent electrode layer called a TCO (Transparent Conductive Oxide) layer is formed over the entire surface, and a Cu layer is formed over the entire surface.
  • TCO Transparent Conductive Oxide
  • the light-transmitting conductive layer indium tin oxide or the like can be used.
  • the thickness of the TCO layer which is a transparent electrode layer, is about 100 nm, and the thickness of the Cu layer is about 100 nm to 1 ⁇ m.
  • This step is processed using a sputtering apparatus.
  • FIG. 13 shows a state in which a laminated structure of the transparent electrode layer 60 and the Cu layer 62 is formed on the entire surface as the base electrodes 60 and 62.
  • a resist film for electrode separation is formed (S42). This is because the n-type region electrode 70 and the p-type region electrode 72 are electrically separated and plated.
  • a resist film is applied, and patterning is performed by exposure and development to form a separation groove at the boundary between the n-type region portion and the p-type region portion.
  • FIG. 14 shows a resist film 84 in which a separation groove 85 is formed.
  • FIG. 15 shows a state in which the base electrodes 60 and 62 at the separation groove 85 are removed by this etching.
  • FIG. 16 shows a state in which the resist film is removed, and the base electrodes 60 and 62 are separated into the n-type region 100 and the p-type region 102 by the separation unit 86.
  • a plating electrode is formed (S48). Specifically, cleaning with sulfuric acid (H 2 SO 4 ), electrolytic plating of Cu using a plating bath and subsequent cleaning, electrolytic plating of Sn using a plating bath, and subsequent cleaning are sequentially performed.
  • the thickness of the Cu plating layer is about 10 ⁇ m to 20 ⁇ m, and the thickness of the Sn plating layer is 1 ⁇ m to 5 ⁇ m. In this way, the photoelectric conversion element 10 having the structure described in FIG. 1 is completed.
  • FIG. 17 corresponds to FIG. 1 and is a cross-sectional view of the photoelectric conversion element 12 that uses only the silicon nitride layer 40 as the insulating layer and does not use the silicon oxide layer. Since the configuration is the same as that of FIG. 1 except that the insulating layer is only the silicon nitride layer 40, a detailed description is omitted.
  • FIG. 18 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 12 of the comparative example. Compared with FIG. 2, it can be seen that the step S11 of silicon oxide layer deposition and the step S23 of removing the silicon oxide layer for n-contact are omitted.
  • FIG. 19 to FIG. 29 are diagrams showing a state in the procedure of FIG. FIG. 19 corresponds to FIG. 3, but here, an i-type amorphous semiconductor layer 22 and an n-type amorphous semiconductor layer 26 are formed on the front surface, and an i-type amorphous semiconductor layer 24 is formed on the back surface. A state in which the n-type amorphous semiconductor layer 28 is formed is shown. This structure is exactly the same as in FIG.
  • 20 and subsequent figures are different from the structures described in FIGS. 3 to 16 because the silicon oxide layer is not formed.
  • 20 shows the formation of the silicon nitride layer 40, which corresponds to FIG. 5, but the silicon oxide layer 36 is not formed between the n-type amorphous semiconductor layer 28 and the silicon nitride layer 40.
  • FIG. 5 shows the formation of the silicon nitride layer 40, which corresponds to FIG. 5, but the silicon oxide layer 36 is not formed between the n-type amorphous semiconductor layer 28 and the silicon nitride layer 40.
  • FIG. 21 and FIG. 6, FIG. 22 and FIG. 7, FIG. 23 and FIG. 8, and FIG. there is no removal process of the silicon oxide layer 36 described with reference to FIG. 10, and the removal of the silicon nitride residue 41 by lift-off described with reference to FIG. 11 is not performed.
  • FIG. 25 and FIG. 12, FIG. 26 and FIG. 13, FIG. 27 and FIG. 14, FIG. 28 and FIG. The difference is that there is no silicon oxide layer 36 in the layer.
  • the back junction type photoelectric conversion element and the back junction type photoelectric conversion element manufacturing method according to the present invention can be used for a photovoltaic power generation system or the like.

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Abstract

In this photoelectric conversion element (10), an n-type region (100) containing an n-type amorphous semiconductor layer (28) and a p-type region (102) containing a p-type amorphous semiconductor layer (44) are provided on the back surface of a semiconductor substrate (20), namely an n-type single-crystal silicon substrate. An electrode (70) for the n-type region is connected to the n-type amorphous semiconductor layer (28) via base electrodes (60 and 62) through an opening provided in a layered insulation layer consisting of a silicon-oxide layer (36) and a silicon-nitride layer (40). When forming said opening in the silicon-oxide layer (36), residue from the silicon nitride thereabove is removed via lift-off.

Description

裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法Back junction type photoelectric conversion element and method for manufacturing back junction type photoelectric conversion element
　本発明は、裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法に係り、特に、光電変換素子を形成するｐ型領域とｎ型領域を作り分けるために絶縁層を用いる裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法に関する。 The present invention relates to a back junction photoelectric conversion element and a method for manufacturing a back junction photoelectric conversion element, and in particular, a back surface that uses an insulating layer to separately form a p-type region and an n-type region for forming the photoelectric conversion element. The present invention relates to a method for manufacturing a junction type photoelectric conversion element and a back surface junction type photoelectric conversion element.
　太陽電池は、光起電力装置、あるいは光電変換素子とも呼ばれるが、クリーンなエネルギ源として期待され、光電変換効率を向上させるために、様々な構造が用いられる。 A solar cell is also called a photovoltaic device or a photoelectric conversion element, but is expected as a clean energy source, and various structures are used to improve photoelectric conversion efficiency.
　例えば、特許文献１には、ヘテロ接合を有する光起電力装置として、ｎ型単結晶シリコン上にｉ型非晶質シリコンおよびｐ型非晶質シリコンをそれぞれ積層する構成が開示されている。 For example, Patent Document 1 discloses a configuration in which i-type amorphous silicon and p-type amorphous silicon are stacked on n-type single crystal silicon as a photovoltaic device having a heterojunction.
　また、特許文献２には、太陽電池として、第１半導体層の両隣に配設される一対の第２半導体層と、一方の第２半導体層上から第１半導体層上まで跨って形成される絶縁層と、他方の第２半導体層上から第１半導体層上まで跨って形成される絶縁層を備える構成が開示されている。ここでは、透明電極層と収集電極層は、絶縁層上に形成される一対の分離溝によって、第１半導体層用の電極と第２半導体層用の電極とに分離される。 Further, in Patent Document 2, a solar cell is formed across a pair of second semiconductor layers disposed on both sides of the first semiconductor layer and from one of the second semiconductor layers to the first semiconductor layer. The structure provided with the insulating layer and the insulating layer formed ranging over the 1st semiconductor layer from the other 2nd semiconductor layer is disclosed. Here, the transparent electrode layer and the collecting electrode layer are separated into an electrode for the first semiconductor layer and an electrode for the second semiconductor layer by a pair of separation grooves formed on the insulating layer.
特開平７－１４２７５３号公報Japanese Patent Application Laid-Open No. 7-142753 特開２００９－２００２６７号公報JP 2009-200277 A
　特許文献２に記載される太陽電池は、受光面と反対側の裏面に第１半導体層用の電極と第２半導体層用の電極を設けるものである。このような構造は、裏面接合型の光電変換素子と呼ばれ、受光面に電極が配置されないので、受光面積を広く取れ、光電変換効率を向上させることができる。 The solar cell described in Patent Document 2 is provided with an electrode for the first semiconductor layer and an electrode for the second semiconductor layer on the back surface opposite to the light receiving surface. Such a structure is called a back junction type photoelectric conversion element, and since no electrode is arranged on the light receiving surface, a large light receiving area can be obtained and the photoelectric conversion efficiency can be improved.
　裏面接合型の光電変換素子では、裏面にｐｎ接合を形成するので、ｐ型領域とｎ型領域を作り分けるために絶縁層が用いられる。電極はこの絶縁層を開口してｐ型領域またはｎ型領域と接続される。ところが、絶縁層によっては、開口工程において、絶縁層の残渣が残ってしまうことが生じる。そのためにせっかくの変換効率向上が妨げられる。 In the back junction type photoelectric conversion element, since a pn junction is formed on the back surface, an insulating layer is used to make a p type region and an n type region separately. The electrode opens this insulating layer and is connected to the p-type region or the n-type region. However, depending on the insulating layer, a residue of the insulating layer may remain in the opening process. This hinders the improvement of conversion efficiency.
　本発明の目的は、絶縁層の開口の際の残渣を確実に除去して、変換効率の向上を確保できる裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法を提供することである。 An object of the present invention is to provide a back junction type photoelectric conversion element and a method for producing a back junction type photoelectric conversion element that can reliably remove residues at the time of opening an insulating layer and ensure improvement in conversion efficiency. It is.
　本発明に係る裏面接合型の光電変換素子は、受光面と、受光面の反対側の裏面とを有する第１導電型の半導体基板と、裏面に配置され、半導体基板に接続し第１導電型を有する非晶質半導体層を含んで構成される第１導電型領域と、裏面に配置され、第２導電型を有する非晶質半導体層を含んで構成され、半導体基板とｐｎ接合を形成する第２導電型領域と、第１導電型領域または第２導電型領域のいずれか一方の領域の非晶質半導体層の上に形成される絶縁層と、絶縁層に設けられた開口部を通して、その下部に設けられる非晶質半導体層に接続し、外部に引き出される電極層と、を備え、絶縁層は、その下部に設けられる非晶質半導体層に接触して設けられる第１絶縁層と、第１絶縁層の上に形成される第２絶縁層であって、第１絶縁層の開口部を形成する際に、リフトオフによって除去される膜質を有する第２絶縁層と、を含むことを特徴とする。 The back junction type photoelectric conversion element according to the present invention includes a first conductivity type semiconductor substrate having a light receiving surface and a back surface opposite to the light receiving surface, and is disposed on the back surface and connected to the semiconductor substrate. A first conductivity type region configured to include an amorphous semiconductor layer having a semiconductor layer, and an amorphous semiconductor layer disposed on the back surface and having a second conductivity type to form a pn junction with the semiconductor substrate. Through the second conductive type region, the insulating layer formed on the amorphous semiconductor layer in either the first conductive type region or the second conductive type region, and the opening provided in the insulating layer, An electrode layer connected to an amorphous semiconductor layer provided under the electrode layer and drawn to the outside, and the insulating layer includes a first insulating layer provided in contact with the amorphous semiconductor layer provided under the electrode layer; A second insulating layer formed on the first insulating layer, wherein the first insulating layer In forming the opening, characterized in that it comprises a second insulating layer having a film quality to be removed by a lift-off, the.
　本発明に係る裏面接合型の光電変換素子の製造方法は、第１導電型のシリコン基板の受光面とは反対側の裏面にｐｎ接合が形成される裏面接合型の光電変換素子の製造方法であって、第１導電型を有する非晶質半導体層を含んで構成され、半導体基板に接続する第１導電型領域を裏面に形成する工程と、第２導電型を有する非晶質半導体層を含んで構成され、半導体基板とｐｎ接合を形成する第２導電型領域を裏面に形成する工程と、第１導電型領域または第２導電型領域のいずれか一方の領域の非晶質半導体層の上に絶縁層を形成する工程と、絶縁層を開口する工程と、絶縁層に設けられた開口部を通して、その下部に設けられる非晶質半導体層に接続し、外部に引き出される電極層を形成する工程と、を含み、絶縁層を形成する工程は、絶縁層の下部に設けられる非晶質半導体層に接触して第１絶縁層を形成する工程と、第１絶縁層の上に第２絶縁層を形成する工程と、を含み、絶縁層を開口する工程は、第２絶縁層を開口する工程と、第２絶縁層に対するエッチングレートよりも第１絶縁層に対するエッチングレートが速く、第１絶縁層に対するエッチングレートよりも絶縁層の下部に設けられる非晶質半導体層に対するエッチングレートが遅いエッチングレートを有するエッチング剤で第１絶縁層を開口する工程と、を含むことを特徴とする。 The manufacturing method of the back junction type photoelectric conversion element according to the present invention is a manufacturing method of a back junction type photoelectric conversion element in which a pn junction is formed on the back surface opposite to the light receiving surface of the first conductivity type silicon substrate. A step of forming an amorphous semiconductor layer having a first conductivity type on the back surface, the step of forming a first conductivity type region connected to the semiconductor substrate; and an amorphous semiconductor layer having a second conductivity type. A step of forming a second conductivity type region that forms a pn junction with the semiconductor substrate on the back surface, and an amorphous semiconductor layer in one of the first conductivity type region and the second conductivity type region. Forming an insulating layer thereon, opening the insulating layer, and forming an electrode layer that is connected to the amorphous semiconductor layer provided below the opening through the opening provided in the insulating layer and drawn to the outside And a step of forming an insulating layer. Forming a first insulating layer in contact with an amorphous semiconductor layer provided under the insulating layer; and forming a second insulating layer on the first insulating layer, wherein the insulating layer is opened The step of opening the second insulating layer, the etching rate with respect to the first insulating layer is faster than the etching rate with respect to the second insulating layer, and the non-insulating layer provided below the insulating layer than the etching rate with respect to the first insulating layer. And a step of opening the first insulating layer with an etchant having an etching rate with a low etching rate with respect to the crystalline semiconductor layer.
　上記構成により、裏面接合型の光電変換素子において、絶縁層は、その下部に設けられる非晶質半導体層に接触して設けられる第１絶縁層と、第１絶縁層の上に形成される第２絶縁層であって、第１絶縁層の開口部を形成する際に、リフトオフによって除去される膜質を有する第２絶縁層とを含む。このように、第１絶縁層を設けることで第２絶縁層の開口の際に際の残渣をリフトオフにより確実に除去できる。 With the above structure, in the back junction photoelectric conversion element, the insulating layer is formed on the first insulating layer and the first insulating layer provided in contact with the amorphous semiconductor layer provided therebelow. And a second insulating layer having a film quality that is removed by lift-off when the opening of the first insulating layer is formed. As described above, by providing the first insulating layer, residues at the time of opening the second insulating layer can be reliably removed by lift-off.
本発明に係る実施の形態における裏面接合型の光電変換素子の断面図である。It is sectional drawing of the back junction type photoelectric conversion element in embodiment which concerns on this invention. 本発明に係る実施の形態における裏面接合型の光電変換素子の製造方法の手順を示すフローチャートである。It is a flowchart which shows the procedure of the manufacturing method of the back junction type photoelectric conversion element in embodiment which concerns on this invention. 図２のＳ１０の様子を示す図である。It is a figure which shows the mode of S10 of FIG. 図２のＳ１１の様子を示す図である。It is a figure which shows the mode of S11 of FIG. 図２のＳ１２の様子を示す図である。It is a figure which shows the mode of S12 of FIG. 図２のＳ１４の様子を示す図である。It is a figure which shows the mode of S14 of FIG. 図２のＳ１６の様子を示す図である。It is a figure which shows the mode of S16 of FIG. 図２のＳ１８の様子を示す図である。It is a figure which shows the mode of S18 of FIG. 図２のＳ２０の様子を示す図である。It is a figure which shows the mode of S20 of FIG. 図２のＳ２２，２３の様子を示す図である。It is a figure which shows the mode of S22 and 23 of FIG. 図１０において、リフトオフが行われる様子を説明する図である。In FIG. 10, it is a figure explaining a mode that lift-off is performed. 図１０の工程の後、レジストが除去される様子を示す図である。It is a figure which shows a mode that a resist is removed after the process of FIG. 図２のＳ４０の様子を示す図である。It is a figure which shows the mode of S40 of FIG. 図２のＳ４２の様子を示す図である。It is a figure which shows the mode of S42 of FIG. 図２のＳ４４の様子を示す図である。It is a figure which shows the mode of S44 of FIG. 図２のＳ４６の様子を示す図である。It is a figure which shows the mode of S46 of FIG. 比較例としての裏面接合型の光電変換素子の断面図である。It is sectional drawing of the back junction type photoelectric conversion element as a comparative example. 比較例としての裏面接合型の光電変換素子の製造方法の手順を示すフローチャートである。It is a flowchart which shows the procedure of the manufacturing method of the back junction type photoelectric conversion element as a comparative example. 比較例におけるＳ１０の様子を示す図である。It is a figure which shows the mode of S10 in a comparative example. 比較例におけるＳ１２の様子を示す図である。It is a figure which shows the mode of S12 in a comparative example. 比較例におけるＳ１４の様子を示す図である。It is a figure which shows the mode of S14 in a comparative example. 比較例におけるＳ１６の様子を示す図である。It is a figure which shows the mode of S16 in a comparative example. 比較例におけるＳ１８の様子を示す図である。It is a figure which shows the mode of S18 in a comparative example. 比較例におけるＳ２０の様子を示す図である。It is a figure which shows the mode of S20 in a comparative example. 比較例におけるＳ２２の様子を示す図である。It is a figure which shows the mode of S22 in a comparative example. 比較例におけるＳ４０の様子を示す図である。It is a figure which shows the mode of S40 in a comparative example. 比較例におけるＳ４２の様子を示す図である。It is a figure which shows the mode of S42 in a comparative example. 比較例におけるＳ４４の様子を示す図である。It is a figure which shows the mode of S44 in a comparative example. 比較例におけるＳ４６の様子を示す図である。It is a figure which shows the mode of S46 in a comparative example.
　以下に図面を用いて本発明に係る実施の形態につき、詳細に説明する。以下では、半導体基板の導電型をｎ型として説明するが、これをｐ型としても構わない。また、非晶質半導体層の形成の順序を、ｎ型を先とし、ｐ型をその後としたが、これを入れ替えても構わない。また、コンタクトのための絶縁層の開口部をｎ型非晶質半導体層のところに設けるものとしたが、これをｐ型非晶質半導体層のところに設けるものとしてもよい。また、以下では、ｐ型非晶質半導体層とｎ型非晶質半導体層の他に、ｉ型非晶質半導体層を用いる。そこで、ｐｎ接合の間にｉ型非晶質半導体層を含まれていても、これはｐｎ接合に属するものである。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the conductivity type of the semiconductor substrate is described as n-type, but it may be p-type. Further, the order of formation of the amorphous semiconductor layers is n-type first and p-type thereafter, but this may be interchanged. In addition, although the opening of the insulating layer for the contact is provided at the n-type amorphous semiconductor layer, it may be provided at the p-type amorphous semiconductor layer. In the following, an i-type amorphous semiconductor layer is used in addition to the p-type amorphous semiconductor layer and the n-type amorphous semiconductor layer. Therefore, even if an i-type amorphous semiconductor layer is included between pn junctions, it belongs to the pn junction.
　以下では、絶縁層をＳｉＯ2とＳｉＮXの二層構造としたが、二層以上の多層構造であっても構わない。例えば、ＳｉＮXを膜質の異なるシリコン窒化膜の積層構造としてもよい。以下で説明する材質、膜厚等は、説明のための例示であって、裏面接合型の光電変換素子の仕様に応じ適宜変更が可能である。 In the following, the insulating layer has a two-layer structure of SiO 2 and SiN x , but it may have a multilayer structure of two or more layers. For example, SiN x may have a laminated structure of silicon nitride films having different film qualities. The materials, film thicknesses, and the like described below are exemplifications for explanation, and can be appropriately changed according to the specifications of the back junction photoelectric conversion element.
　以下では、全ての図面において同様の要素には同一の符号を付し、重複する説明を省略する。また、本文中の説明においては、必要に応じそれ以前に述べた符号を用いるものとする。 In the following, similar elements are denoted by the same reference symbols in all drawings, and redundant description is omitted. In the description in the text, the symbols described before are used as necessary.
　図１は、裏面接合型の光電変換素子１０の断面図である。裏面接合型の光電変換素子１０は、その受光面の反対側の裏面に、光電変換を行うｐｎ接合を形成し、電極も裏面にのみ設けるものである。このように、受光面に電極を一切配置しないので、受光面積が広く取れ、面積当たりの光電変換効率が向上する。図１では、紙面の下側が受光面側で、上側が裏面である。なお、以下では、特に断らない限り、裏面接合型の光電変換素子１０のことを、単に光電変換素子１０と呼ぶことにする。 FIG. 1 is a cross-sectional view of a back contact type photoelectric conversion element 10. In the back junction type photoelectric conversion element 10, a pn junction for performing photoelectric conversion is formed on the back surface opposite to the light receiving surface, and electrodes are provided only on the back surface. Thus, since no electrode is disposed on the light receiving surface, a large light receiving area can be obtained, and the photoelectric conversion efficiency per area is improved. In FIG. 1, the lower side of the paper is the light-receiving surface side, and the upper side is the back surface. Hereinafter, unless otherwise specified, the back junction type photoelectric conversion element 10 is simply referred to as the photoelectric conversion element 10.
　光電変換素子１０には、ｎ型のシリコン単結晶基板である半導体基板２０の裏面に、ｎ型領域１００とｐ型領域１０２が設けられる。ｎ型領域１００は、半導体基板２０に接続し、これと同じ導電型であるｎ型非晶質半導体層２８を含んで構成される。図１では、半導体基板２０とｎ型非晶質半導体層２８との間に、ｉ型非晶質半導体層２４が設けられるが、ｉ型非晶質半導体層２４は必ずしも必須の構成要素ではない。ｐ型領域１０２は、ｐ型非晶質半導体層４４を含んで構成され、半導体基板２０とｐｎ接合を形成する。図１では、半導体基板２０とｐ型非晶質半導体層４４との間に、ｉ型非晶質半導体層４２が設けられるが、ｉ型非晶質半導体層４２は必ずしも必須の構成要素ではない。 The photoelectric conversion element 10 is provided with an n-type region 100 and a p-type region 102 on the back surface of a semiconductor substrate 20 which is an n-type silicon single crystal substrate. The n-type region 100 is connected to the semiconductor substrate 20 and includes an n-type amorphous semiconductor layer 28 having the same conductivity type. In FIG. 1, the i-type amorphous semiconductor layer 24 is provided between the semiconductor substrate 20 and the n-type amorphous semiconductor layer 28, but the i-type amorphous semiconductor layer 24 is not necessarily an essential component. . The p-type region 102 includes a p-type amorphous semiconductor layer 44 and forms a pn junction with the semiconductor substrate 20. In FIG. 1, an i-type amorphous semiconductor layer 42 is provided between the semiconductor substrate 20 and the p-type amorphous semiconductor layer 44, but the i-type amorphous semiconductor layer 42 is not necessarily an essential component. .
　ｎ型領域用の電極７０は、ｎ型非晶質半導体層２８に接続されるめっき電極である。電極７０は、ＳｎとＣｕの積層構造である。ｎ型領域用の電極７０とｎ型非晶質半導体層２８との間に設けられる下地電極６０，６２は、電極７０をめっきする際に用いられるシード層である。下地電極６０，６２は、透明電極層６０とＣｕ層６２の積層構造である。 The n-type region electrode 70 is a plating electrode connected to the n-type amorphous semiconductor layer 28. The electrode 70 has a laminated structure of Sn and Cu. The base electrodes 60 and 62 provided between the n-type region electrode 70 and the n-type amorphous semiconductor layer 28 are seed layers used when the electrode 70 is plated. The base electrodes 60 and 62 have a laminated structure of a transparent electrode layer 60 and a Cu layer 62.
　ｐ型領域用の電極７２は、ｐ型非晶質半導体層４４に接続されるめっき電極である。電極７２は、電極７０と同様に、ＳｎとＣｕの積層構造であり、下地電極６０，６２を用いてめっきによって形成される。ｎ型領域用の電極７０とｐ型領域用の電極７２を比べると、前者の電極高さの方が後者の電極高さよりも高い。これは、前者の下地電極６０，６２の表面積を後者の下地電極６０，６２の表面積よりも小さく設定したためである。すなわち、下地電極６０，６２を共通にしてめっきを行うと、その表面積の差によってめっき電流密度が異なり、小さい表面積の方が速く成長するためである。 The electrode 72 for the p-type region is a plating electrode connected to the p-type amorphous semiconductor layer 44. Similar to the electrode 70, the electrode 72 has a laminated structure of Sn and Cu, and is formed by plating using the base electrodes 60 and 62. Comparing the n-type region electrode 70 and the p-type region electrode 72, the former electrode height is higher than the latter electrode height. This is because the surface area of the former base electrodes 60 and 62 is set smaller than the surface area of the latter base electrodes 60 and 62. That is, when plating is performed using the base electrodes 60 and 62 in common, the plating current density varies depending on the surface area difference, and the smaller surface area grows faster.
　図１に示されるように、ｐ型領域用の電極７２は、下地電極６０，６２を介して、ｐ型非晶質半導体層４４の上に直接的に設けられる。これに対し、ｎ型領域用の電極７０は、酸化シリコン層３６と窒化シリコン層４０の積層構造の絶縁層に開口部を設け、その開口部を通して、下地電極６０，６２を介して、ｎ型非晶質半導体層２８と接続される。以下で説明するように、この光電変換素子１０においては、絶縁層が酸化シリコン層３６と窒化シリコン層４０の積層構造であることが特徴である。ここで、窒化シリコン層４０の厚さは、１０ｎｍから５００ｎｍ程度であるが、酸化シリコン層３６の厚さは自然酸化膜の厚さよりも厚く、数ｎｍから２００ｎｍ程度でよい。 As shown in FIG. 1, the electrode 72 for the p-type region is provided directly on the p-type amorphous semiconductor layer 44 via the base electrodes 60 and 62. On the other hand, the electrode 70 for the n-type region is provided with an opening in an insulating layer having a laminated structure of the silicon oxide layer 36 and the silicon nitride layer 40, and through the opening through the base electrodes 60 and 62, the n-type region It is connected to the amorphous semiconductor layer 28. As will be described below, the photoelectric conversion element 10 is characterized in that the insulating layer has a laminated structure of a silicon oxide layer 36 and a silicon nitride layer 40. Here, the thickness of the silicon nitride layer 40 is about 10 nm to 500 nm, but the thickness of the silicon oxide layer 36 is thicker than the thickness of the natural oxide film, and may be about several nm to 200 nm.
　半導体基板２０の受光面である表面に設けられるｉ型非晶質半導体層２２とｎ型非晶質半導体層２６は、光電変換が行われる半導体基板２０のパッシベーション層としての機能を有する層である。反射防止層３８は、受光面における反射を抑制する機能を有する絶縁膜層である。 The i-type amorphous semiconductor layer 22 and the n-type amorphous semiconductor layer 26 provided on the light receiving surface of the semiconductor substrate 20 are layers having a function as a passivation layer of the semiconductor substrate 20 on which photoelectric conversion is performed. . The antireflection layer 38 is an insulating film layer having a function of suppressing reflection on the light receiving surface.
　図２は、光電変換素子１０の製造手順を示すフローチャートである。この手順を図３から図１６の図を用いて説明する。 FIG. 2 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 10. This procedure will be described with reference to FIGS.
　最初に、ｎ型のシリコン単結晶基板である半導体基板２０が準備される。面方位としては（１００）が好ましい。受光面となる表面には、光入射効率を高めるため、テキスチャ構造とすることが好ましい。例えば、シリコンのエッチングの面異方性を利用して、（１１１）面で囲まれるピラミッド状の凹凸を表面に設けることができる。半導体基板２０は、次の工程のために、全体が適当な洗浄液で清浄にされる。 First, a semiconductor substrate 20 which is an n-type silicon single crystal substrate is prepared. The plane direction is preferably (100). In order to increase the light incident efficiency, it is preferable that the surface serving as the light receiving surface has a texture structure. For example, pyramidal irregularities surrounded by the (111) plane can be provided on the surface by utilizing the plane anisotropy of silicon etching. The semiconductor substrate 20 is entirely cleaned with an appropriate cleaning solution for the next step.
　清浄な表面とされた半導体基板２０について、次に、ｉ型非晶質半導体層と、ｎ型非晶質半導体層が順次デポジションされる（Ｓ１０）。デポジションは、堆積とも呼ばれ、薄膜を形成する工程のことである。この工程は、プラズマＣＶＤ装置を用いて行うことができる。ｉ型非晶質半導体層とｎ型非晶質半導体層は、半導体基板２０の表面と裏面に共に形成される。図３には、表面にｉ型非晶質半導体層２２とｎ型非晶質半導体層２６が形成され、裏面にｉ型非晶質半導体層２４とｎ型非晶質半導体層２８が形成される様子が示されている。 Next, the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are sequentially deposited on the semiconductor substrate 20 having a clean surface (S10). Deposition is also called deposition and is a process of forming a thin film. This step can be performed using a plasma CVD apparatus. The i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are both formed on the front surface and the back surface of the semiconductor substrate 20. In FIG. 3, an i-type amorphous semiconductor layer 22 and an n-type amorphous semiconductor layer 26 are formed on the front surface, and an i-type amorphous semiconductor layer 24 and an n-type amorphous semiconductor layer 28 are formed on the back surface. Is shown.
　次に、裏面に酸化シリコン層のデポジションが行われる（Ｓ１１）。酸化シリコンの代表はＳｉＯ2である。この工程は、プラズマＣＶＤ装置を用いて行なわれる。酸化シリコン層の厚さは、自然酸化膜が１ｎｍ以下であるので、これより厚い数ｎｍから２００ｎｍ程度が好ましい。酸化シリコン層を設ける役割の１つは、ｎ型非晶質半導体層２４の表面を保護し、これによって光電変換効率を向上させることである。もう１つの役割は、ＨＦ（弗酸）に溶けやすいので、後述する絶縁膜開口処理のときに、ＳｉＮXの残渣をリフトオフにより除去して、清浄なｎ型非晶質半導体層２４の表面とすることである。この役割を利用するために、ＳｉＯ2を設けているのが、光電変換素子１０の特徴である。図４には、裏面において、ｎ型非晶質半導体層２８の上に酸化シリコン層３６が形成される様子が示される。 Next, a silicon oxide layer is deposited on the back surface (S11). A representative example of silicon oxide is SiO 2 . This step is performed using a plasma CVD apparatus. Since the natural oxide film has a thickness of 1 nm or less, the thickness of the silicon oxide layer is preferably about several nm to 200 nm thicker than this. One of the roles of providing the silicon oxide layer is to protect the surface of the n-type amorphous semiconductor layer 24, thereby improving the photoelectric conversion efficiency. Another role is that it is easily dissolved in HF (hydrofluoric acid). Therefore, in the insulating film opening process described later, the SiN x residue is removed by lift-off, and the surface of the clean n-type amorphous semiconductor layer 24 is removed. It is to be. In order to utilize this role, the characteristic of the photoelectric conversion element 10 is that SiO 2 is provided. FIG. 4 shows how the silicon oxide layer 36 is formed on the n-type amorphous semiconductor layer 28 on the back surface.
　次に、窒化シリコン層のデポジションが行われる（Ｓ１２）。この工程もプラズマＣＶＤ装置を用いて行なわれる。窒化シリコンの代表はＳｉ3Ｎ4であるが、プラズマＣＶＤ装置の製造条件によっては必ずしもＳｉ3Ｎ4の組成とならない。一般的にはＳｉＮXの組成となる。窒化シリコン層４０の厚さは、１０ｎｍから５００ｎｍ程度である。 Next, the silicon nitride layer is deposited (S12). This process is also performed using a plasma CVD apparatus. A typical example of silicon nitride is Si 3 N 4 , but the composition of Si 3 N 4 does not necessarily depend on the manufacturing conditions of the plasma CVD apparatus. Generally, the composition is SiN x . The thickness of the silicon nitride layer 40 is about 10 nm to 500 nm.
　図５では、裏面において、酸化シリコン層３６の上に窒化シリコン層４０が形成される様子が示される。受光面となる表面には、反射防止層３８が形成される。反射防止層３８としては、窒化シリコン膜を用いることができるので、裏面の窒化シリコン層４０と同じ膜を受光面側にも同時に形成してもよい。しかし、裏面の窒化シリコン層４０は、以後のパターニングのために用いられるものでエッチング特性が重要であるのに対し、反射防止層３８は光学的特性が重要である。そこで、裏面の窒化シリコン層４０と反射防止層３８とは、膜特性が異なる絶縁膜とすることがよい。以下では、裏面の窒化シリコン層４０と受光面側の反射防止層３８とは区別して説明を進める。 FIG. 5 shows a state in which the silicon nitride layer 40 is formed on the silicon oxide layer 36 on the back surface. An antireflection layer 38 is formed on the surface that becomes the light receiving surface. Since a silicon nitride film can be used as the antireflection layer 38, the same film as the silicon nitride layer 40 on the back surface may be formed on the light receiving surface side at the same time. However, the silicon nitride layer 40 on the back surface is used for subsequent patterning and etching characteristics are important, whereas the antireflection layer 38 has optical characteristics important. Therefore, the back side silicon nitride layer 40 and the antireflection layer 38 are preferably insulating films having different film characteristics. In the following, the description will be made while distinguishing the silicon nitride layer 40 on the back surface and the antireflection layer 38 on the light receiving surface side.
　なお、裏面の窒化シリコン層４０としては、例えば、膜組成を変えることによって、エッチング特性が耐アルカリ性のものと、耐酸性のものと区別して形成することができる。工程の組み方によっては、酸化シリコン層３６側を耐酸性の特性の膜とし、その上に耐アルカリ性の膜とすることができる。例えば、レジスト膜をアルカリで除去するものとするときは、レジスト膜に接する側の窒化シリコン層を耐アルカリ性のものとすることがよい。 The silicon nitride layer 40 on the back surface can be formed by changing the film composition, for example, so that the etching characteristics can be distinguished from those having alkali resistance and those having acid resistance. Depending on how the processes are assembled, the silicon oxide layer 36 side can be formed as an acid-resistant film, and an alkali-resistant film can be formed thereon. For example, when the resist film is to be removed with alkali, the silicon nitride layer in contact with the resist film is preferably resistant to alkali.
　次に、ｐ型領域１０２に相当する部分を開口するため、窒化シリコン層４０を部分的に除去する（Ｓ１４）。この処理にはフォトリソグラフィ技術が用いられる。すなわち、窒化シリコン層４０の全面に感光性レジスト膜を塗布し、窒化シリコン層４０を除去したい部分のレジスト膜を露光して、現像によりその部分のレジスト膜を取り除く。この処理はレジスト膜のパターニングである。そして、レジスト膜をエッチングマスクとして、適当なエッチング液を用いてレジスト膜のない部分の窒化シリコン層４０を除去する。エッチング液としてはＨＦと硝酸の混合液である弗硝酸を用いることができる。エッチングの後は水洗が行われる。 Next, in order to open a portion corresponding to the p-type region 102, the silicon nitride layer 40 is partially removed (S14). A photolithography technique is used for this processing. That is, a photosensitive resist film is applied to the entire surface of the silicon nitride layer 40, the resist film in a portion where the silicon nitride layer 40 is to be removed is exposed, and the resist film in that portion is removed by development. This process is patterning of the resist film. Then, using the resist film as an etching mask, a portion of the silicon nitride layer 40 without the resist film is removed using an appropriate etching solution. As the etchant, hydrofluoric acid which is a mixture of HF and nitric acid can be used. After the etching, washing with water is performed.
　図６には、パターニングされたレジスト膜８０と、このレジスト膜８０をエッチングマスクとして、残された窒化シリコン層４０が示されている。その後、レジスト膜８０は除去される。レジスト膜８０はアルカリに溶けるので、苛性ソーダ（ＮａＯＨ）を用いて、窒化シリコン層４０をそのままとしてレジスト膜８０のみを除去することができる。 FIG. 6 shows the patterned resist film 80 and the remaining silicon nitride layer 40 using the resist film 80 as an etching mask. Thereafter, the resist film 80 is removed. Since the resist film 80 is soluble in alkali, only the resist film 80 can be removed using caustic soda (NaOH) while leaving the silicon nitride layer 40 as it is.
　次に、ｐ型領域１０２に相当する部分の半導体基板２０を露出させるため、窒化シリコン層４０をエッチングマスクとして、その下のｎ型非晶質半導体層２８とｉ型非晶質半導体層２４が除去される（Ｓ１６）。ここでは、非晶質半導体層がアルカリに溶けることを利用し、苛性ソーダ（ＮａＯＨ）が用いられる。具体的には、有機洗浄、苛性ソーダ、塩酸（ＨＣｌ）と過酸化水素（Ｈ2Ｏ2）の混合液であるＳＣ２、弗酸、水洗の順で処理が行われる。弗酸が用いられるのは、ＳＣ２によって酸化膜が形成されるので、それを除去するためである。 Next, in order to expose the portion of the semiconductor substrate 20 corresponding to the p-type region 102, the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 thereunder are formed using the silicon nitride layer 40 as an etching mask. It is removed (S16). Here, caustic soda (NaOH) is used by utilizing the fact that the amorphous semiconductor layer dissolves in alkali. Specifically, the treatment is performed in the order of organic cleaning, caustic soda, SC2 which is a mixed solution of hydrochloric acid (HCl) and hydrogen peroxide (H 2 O 2 ), hydrofluoric acid, and water washing. The hydrofluoric acid is used to remove the oxide film formed by SC2.
　図７には、窒化シリコン層４０の形状に、酸化シリコン層３６とｎ型非晶質半導体層２８とｉ型非晶質半導体層２４が残され、それ以外の部分に半導体基板２０が露出された様子が示される。このようにして、ｐ型領域１０２の部分の開口が行われる。 In FIG. 7, the silicon oxide layer 36, the n-type amorphous semiconductor layer 28, and the i-type amorphous semiconductor layer 24 are left in the shape of the silicon nitride layer 40, and the semiconductor substrate 20 is exposed in other portions. The situation is shown. In this way, opening of the portion of the p-type region 102 is performed.
　次に、ｉ型非晶質半導体層４２とｐ型非晶質半導体層４４が全面にデポジションされる（Ｓ１８）。この工程は、プラズマＣＶＤ装置を用いて行なわれる。図８には、開口されたｐ型領域１０２の部分において、ｎ型のシリコン単結晶基板である半導体基板２０に接触して、ｉ型非晶質半導体層４２とｐ型非晶質半導体層４４が配置される様子が示される。なお、窒化シリコン層４０の上にも、ｉ型非晶質半導体層４２とｐ型非晶質半導体層４４が堆積する。 Next, the i-type amorphous semiconductor layer 42 and the p-type amorphous semiconductor layer 44 are deposited on the entire surface (S18). This step is performed using a plasma CVD apparatus. In FIG. 8, the i-type amorphous semiconductor layer 42 and the p-type amorphous semiconductor layer 44 are in contact with the semiconductor substrate 20 which is an n-type silicon single crystal substrate in the opened p-type region 102. Is shown. Note that an i-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer 44 are also deposited on the silicon nitride layer 40.
　そして、次に、ｎ型非晶質半導体層２８に電極をコンタクトさせるための開口処理が行われる。コンタクトとは、電気的に導通をとることである。図８に示されるように、ｎ型非晶質半導体層２８の上には、酸化シリコン層３６、窒化シリコン層４０、ｉ型非晶質半導体層４２、ｐ型非晶質半導体層４４が存在しているので、これらを順番に除去する処理が行われる。 Then, an opening process for contacting the electrode with the n-type amorphous semiconductor layer 28 is performed. A contact is an electrical connection. As shown in FIG. 8, a silicon oxide layer 36, a silicon nitride layer 40, an i-type amorphous semiconductor layer 42, and a p-type amorphous semiconductor layer 44 are present on the n-type amorphous semiconductor layer 28. Therefore, a process for removing them in order is performed.
　最初に、ｐ型非晶質半導体層４４とｉ型非晶質半導体層４２の除去が行われる（Ｓ２０）。この処理にはフォトリソグラフィ技術が用いられる。すなわち、レジスト膜を塗布し、塗布されたレジスト膜について、ｎコンタクトの部分を露光と現像で除去するパターニングが行われる。レジスト膜には、耐酸性と耐アルカリ性を有する溶剤溶解型が用いられる。これによって、苛性ソーダ（ＮａＯＨ）を用いて、ｐ型非晶質半導体層４４とｉ型非晶質半導体層４２を除去することができる。その後洗浄が行われる。図９には、レジスト膜８２の開口部８３の部分のｐ型非晶質半導体層４４とｉ型非晶質半導体層４２が除去された様子が示される。 First, the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are removed (S20). A photolithography technique is used for this processing. That is, a resist film is applied, and the applied resist film is patterned to remove the n-contact portion by exposure and development. A solvent-soluble type having acid resistance and alkali resistance is used for the resist film. Thus, the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 can be removed using caustic soda (NaOH). Thereafter, cleaning is performed. FIG. 9 shows a state where the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 in the opening 83 portion of the resist film 82 are removed.
　次に、レジスト膜８２を残したままで、窒化シリコン層４０の除去（Ｓ２２）と酸化シリコン層３６の除去（Ｓ２３）が行われる。ここでは、弗酸が用いられる。弗酸は、窒化シリコン層４０も酸化シリコン層３６もエッチングできるが、窒化シリコン層４０に対するエッチングレートよりも酸化シリコン層３６に対するエッチングレートがかなり速い。また、酸化シリコン層３６に対するエッチングレートよりもｐ型非晶質半導体層２８に対するエッチングレートが遅い。すなわち、弗酸を用いると、まず窒化シリコン層４０がエッチングされ、酸化シリコン層３６に達すると、急速に酸化シリコン層３６がエッチングされるが、ｐ型非晶質半導体層２８に達するとエッチングが止まる。なお、これらの工程の際に、受光面側の反射防止層３８がエッチングされないように、保護膜を設けることが好ましい。 Next, with the resist film 82 left, the silicon nitride layer 40 is removed (S22) and the silicon oxide layer 36 is removed (S23). Here, hydrofluoric acid is used. Although hydrofluoric acid can etch both the silicon nitride layer 40 and the silicon oxide layer 36, the etching rate for the silicon oxide layer 36 is considerably faster than the etching rate for the silicon nitride layer 40. Further, the etching rate for the p-type amorphous semiconductor layer 28 is slower than the etching rate for the silicon oxide layer 36. That is, when hydrofluoric acid is used, the silicon nitride layer 40 is first etched, and when the silicon oxide layer 36 is reached, the silicon oxide layer 36 is rapidly etched, but when the p-type amorphous semiconductor layer 28 is reached, the etching is performed. Stop. In these steps, a protective film is preferably provided so that the antireflection layer 38 on the light receiving surface side is not etched.
　プラズマＣＶＤで形成した窒化シリコンは、弗酸によって除去できるとされるが、実際には、微小な残渣が残り、それを完全に除去するにはかなりの時間を要することがある。その原因としては、例えば、プラズマＣＶＤ装置で形成した窒化シリコンがＳｉ3Ｎ4の化学量論的な組成ではなく、Ｓｉ3.5Ｎ4のように、Ｓｉ組成が過剰に多い可能性があることが考えられる。このように、窒化シリコン層４０の除去の際に残渣があると、電極とｎ型非晶質半導体層２８との電気的接触が妨げられ、光電変換素子１０の光電変換効率が低下することになる。 Although silicon nitride formed by plasma CVD can be removed by hydrofluoric acid, in practice, a minute residue remains, and it may take a considerable time to completely remove the residue. As the cause, for example, silicon nitride formed by a plasma CVD apparatus may not have a stoichiometric composition of Si 3 N 4 but may have an excessively large Si composition such as Si 3.5 N 4. Conceivable. Thus, if there is a residue when removing the silicon nitride layer 40, electrical contact between the electrode and the n-type amorphous semiconductor layer 28 is hindered, and the photoelectric conversion efficiency of the photoelectric conversion element 10 is reduced. Become.
　上記のように、窒化シリコン層４０とｎ型非晶質半導体層２８との間に、酸化シリコン層３６を配置すると、弗酸を用いて酸化シリコン層３６を容易に除去できる。その際に、酸化シリコン層３６の上に窒化シリコン層４０の残渣があっても、いわゆるリフトオフ現象によって、酸化シリコン層３６の上の窒化シリコンが除去される。上記では、窒化シリコン層４０をリフトオフによって除去するために酸化シリコン層３６と弗酸を用いたが、それ以外でも、絶縁層の残渣をリフトオフで除去しえる中間膜と、その中間膜の除去剤とを組み合わせて用いることができる。 As described above, when the silicon oxide layer 36 is disposed between the silicon nitride layer 40 and the n-type amorphous semiconductor layer 28, the silicon oxide layer 36 can be easily removed using hydrofluoric acid. At this time, even if there is a residue of the silicon nitride layer 40 on the silicon oxide layer 36, the silicon nitride on the silicon oxide layer 36 is removed by a so-called lift-off phenomenon. In the above, the silicon oxide layer 36 and hydrofluoric acid are used to remove the silicon nitride layer 40 by lift-off. However, other than that, an intermediate film that can remove the residue of the insulating layer by lift-off and a remover for the intermediate film Can be used in combination.
　図１０は、レジスト膜８２を残したままで、窒化シリコン層４０と酸化シリコン層３６が除去されて、ｎ型非晶質半導体層２８のコンタクトのための開口部８３が形成された様子が示される。 FIG. 10 shows a state in which the silicon nitride layer 40 and the silicon oxide layer 36 are removed while leaving the resist film 82, and an opening 83 for contact with the n-type amorphous semiconductor layer 28 is formed. .
　図１１は、リフトオフ現象で、酸化シリコン層３６の上の窒化シリコンの残渣４１が除去される様子を模式的に示す図である。ここに示されるように、ＨＦとして示した弗酸は、窒化シリコンの残渣４１の隙間から酸化シリコン層３６に到達し、酸化シリコン層３６を溶かすことができる。酸化シリコン層３６が溶解すると、窒化シリコンの残渣４１は酸化シリコン層３６から浮かされて分離される。これによって、酸化シリコン層３６の除去と共に、窒化シリコンの残渣４１も除去される。 FIG. 11 is a diagram schematically showing how the silicon nitride residue 41 on the silicon oxide layer 36 is removed by the lift-off phenomenon. As shown here, hydrofluoric acid indicated as HF can reach the silicon oxide layer 36 through the gaps between the silicon nitride residues 41 and dissolve the silicon oxide layer 36. When the silicon oxide layer 36 is dissolved, the silicon nitride residue 41 is floated and separated from the silicon oxide layer 36. Thus, the silicon nitride residue 41 is removed together with the removal of the silicon oxide layer 36.
　このように、Ｓ２０、Ｓ２２，Ｓ２３の工程において、レジスト膜８２を用いて、ｐ型非晶質半導体層４４、ｉ型非晶質半導体層４２、窒化シリコン層４０、酸化シリコン層３６が順次除去されて開口部８３が形成される。その後、適当な有機溶剤を用いてレジスト膜８２が除去される。図１１は、レジスト膜８２が除去された状態を示す図である。 Thus, in the steps S20, S22, and S23, the p-type amorphous semiconductor layer 44, the i-type amorphous semiconductor layer 42, the silicon nitride layer 40, and the silicon oxide layer 36 are sequentially removed using the resist film 82. Thus, an opening 83 is formed. Thereafter, the resist film 82 is removed using an appropriate organic solvent. FIG. 11 is a view showing a state where the resist film 82 has been removed.
　次に、下地電極形成が行われる（Ｓ４０）。下地電極は、めっき電極を形成するための導電性のシード層である。具体的には、ＴＣＯ（Ｔｒａｎｓｐａｒｅｎｔ　Ｃｏｎｄｕｃｔｉｖｅ　Ｏｘｉｄｅ）層と呼ばれる透明電極層を全面に形成し、その上にＣｕ層を全面に形成する。透光性導電層としては、インジウム錫酸化物等を用いることができる。 Next, base electrode formation is performed (S40). The base electrode is a conductive seed layer for forming a plating electrode. Specifically, a transparent electrode layer called a TCO (Transparent Conductive Oxide) layer is formed over the entire surface, and a Cu layer is formed over the entire surface. As the light-transmitting conductive layer, indium tin oxide or the like can be used.
　透明電極層であるＴＣＯ層の厚さは１００ｎｍ程度、Ｃｕ層の厚さは１００ｎｍから１μｍ程度である。この工程は、スパッタ装置を用いて処理される。図１３には、下地電極６０，６２として、透明電極層６０とＣｕ層６２の積層構造が全面に形成される様子が示される。 The thickness of the TCO layer, which is a transparent electrode layer, is about 100 nm, and the thickness of the Cu layer is about 100 nm to 1 μm. This step is processed using a sputtering apparatus. FIG. 13 shows a state in which a laminated structure of the transparent electrode layer 60 and the Cu layer 62 is formed on the entire surface as the base electrodes 60 and 62.
　つぎに、電極分離用のレジスト膜が形成される（Ｓ４２）。これは、ｎ型領域用の電極７０とｐ型領域用の電極７２を電気的に分離してめっきするためである。ここでは、レジスト膜を塗布して、露光、現像によってパターニングを行い、ｎ型領域部分とｐ型領域部分の境界に分離溝を形成する。図１４には、分離溝８５が形成されたレジスト膜８４が示されている。 Next, a resist film for electrode separation is formed (S42). This is because the n-type region electrode 70 and the p-type region electrode 72 are electrically separated and plated. Here, a resist film is applied, and patterning is performed by exposure and development to form a separation groove at the boundary between the n-type region portion and the p-type region portion. FIG. 14 shows a resist film 84 in which a separation groove 85 is formed.
　そして、電極用のレジスト膜を用いて、下地電極のエッチングが行われる（Ｓ４４）。エッチングには、塩化第二鉄と塩酸（ＨＣｌ）が用いられる。図１５には、このエッチングによって、分離溝８５のところの下地電極６０，６２が除去された様子が示される。 Then, the base electrode is etched using the electrode resist film (S44). For the etching, ferric chloride and hydrochloric acid (HCl) are used. FIG. 15 shows a state in which the base electrodes 60 and 62 at the separation groove 85 are removed by this etching.
　その後、レジスト膜が除去される（Ｓ４６）。レジスト膜除去には、苛性ソーダ（ＮａＯＨ）が用いられる。図１６にはレジスト膜が除去され、下地電極６０，６２が分離部８６によって、ｎ型領域１００用と、ｐ型領域１０２用とに分離された様子が示される。 Thereafter, the resist film is removed (S46). Caustic soda (NaOH) is used for removing the resist film. FIG. 16 shows a state in which the resist film is removed, and the base electrodes 60 and 62 are separated into the n-type region 100 and the p-type region 102 by the separation unit 86.
　次にめっき電極の形成が行われる（Ｓ４８）。具体的には、硫酸（Ｈ2ＳＯ4）による洗浄、めっき浴を用いたＣｕの電解めっきとその後の洗浄、めっき浴を用いたＳｎの電解めっきとその後の洗浄が順次行われる。Ｃｕめっき層の厚さは１０μｍから２０μｍ程度、Ｓｎめっき層の厚さは１μｍから５μｍである。このようにして、図１で説明した構造の光電変換素子１０が完成する。 Next, a plating electrode is formed (S48). Specifically, cleaning with sulfuric acid (H 2 SO 4 ), electrolytic plating of Cu using a plating bath and subsequent cleaning, electrolytic plating of Sn using a plating bath, and subsequent cleaning are sequentially performed. The thickness of the Cu plating layer is about 10 μm to 20 μm, and the thickness of the Sn plating layer is 1 μm to 5 μm. In this way, the photoelectric conversion element 10 having the structure described in FIG. 1 is completed.
　次に、酸化シリコン層を用いない光電変換素子の構造と製造方法を比較例として説明する。図１７は、図１に対応する図で、絶縁層として、窒化シリコン層４０のみを用い、酸化シリコン層を用いない光電変換素子１２の断面図である。絶縁層が窒化シリコン層４０のみであることを除けば図１と同様の構成であるので、詳細な説明を省略する。 Next, the structure and manufacturing method of a photoelectric conversion element that does not use a silicon oxide layer will be described as a comparative example. FIG. 17 corresponds to FIG. 1 and is a cross-sectional view of the photoelectric conversion element 12 that uses only the silicon nitride layer 40 as the insulating layer and does not use the silicon oxide layer. Since the configuration is the same as that of FIG. 1 except that the insulating layer is only the silicon nitride layer 40, a detailed description is omitted.
　図１８は、比較例の光電変換素子１２の製造手順を示すフローチャートである。図２と比較すると、酸化シリコン層デポジションのＳ１１の工程と、ｎコンタクトのための酸化シリコン層の除去のＳ２３の工程が省略されていることが分かる。 FIG. 18 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 12 of the comparative example. Compared with FIG. 2, it can be seen that the step S11 of silicon oxide layer deposition and the step S23 of removing the silicon oxide layer for n-contact are omitted.
　図１９から図２９は、図１８の手順における様子を示す図である。図１９は、図３に対応する図であるが、ここでは、表面にｉ型非晶質半導体層２２とｎ型非晶質半導体層２６が形成され、裏面にｉ型非晶質半導体層２４とｎ型非晶質半導体層２８が形成される様子が示されている。この構造は、図３と全く同じである。 FIG. 19 to FIG. 29 are diagrams showing a state in the procedure of FIG. FIG. 19 corresponds to FIG. 3, but here, an i-type amorphous semiconductor layer 22 and an n-type amorphous semiconductor layer 26 are formed on the front surface, and an i-type amorphous semiconductor layer 24 is formed on the back surface. A state in which the n-type amorphous semiconductor layer 28 is formed is shown. This structure is exactly the same as in FIG.
　図２０以下は、酸化シリコン層の形成が行われないことから、図３から図１６で説明した構造と異なっている。図２０は窒化シリコン層４０の形成を示す図で、図５に相当するが、ｎ型非晶質半導体層２８と窒化シリコン層４０との間に酸化シリコン層３６が形成されていない。 20 and subsequent figures are different from the structures described in FIGS. 3 to 16 because the silicon oxide layer is not formed. 20 shows the formation of the silicon nitride layer 40, which corresponds to FIG. 5, but the silicon oxide layer 36 is not formed between the n-type amorphous semiconductor layer 28 and the silicon nitride layer 40. FIG.
　以下、図２１と図６、図２２と図７、図２３と図８、図２４と図９において、いずれも酸化シリコン層３６がないことが相違する。そして、図１０で説明した酸化シリコン層３６の除去工程がなく、図１１で説明したリフトオフによる窒化シリコンの残渣４１の除去も行われない。 Hereinafter, FIG. 21 and FIG. 6, FIG. 22 and FIG. 7, FIG. 23 and FIG. 8, and FIG. Then, there is no removal process of the silicon oxide layer 36 described with reference to FIG. 10, and the removal of the silicon nitride residue 41 by lift-off described with reference to FIG. 11 is not performed.
　その後、図２５と図１２、図２６と図１３、図２７と図１４、図２８と図１５、図２９と図１６と、処理内容は同じであるが、いずれも、ｎ型領域１００における絶縁層に酸化シリコン層３６がないことが相違する。 Thereafter, FIG. 25 and FIG. 12, FIG. 26 and FIG. 13, FIG. 27 and FIG. 14, FIG. 28 and FIG. The difference is that there is no silicon oxide layer 36 in the layer.
　このように、窒化シリコン層４０と非晶質半導体層との間に、酸化シリコン層３６を配置することで、窒化シリコン層４０の開口処理の際に、仮に残渣４１があっても、これを良好に除去することができる。 In this way, by disposing the silicon oxide layer 36 between the silicon nitride layer 40 and the amorphous semiconductor layer, even if there is a residue 41 during the opening process of the silicon nitride layer 40, It can be removed well.
　本発明に係る裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法は、太陽光発電システム等に利用できる。 The back junction type photoelectric conversion element and the back junction type photoelectric conversion element manufacturing method according to the present invention can be used for a photovoltaic power generation system or the like.
　１０，１２　光電変換素子、２０　半導体基板、２２，２４　ｎ型非晶質半導体層、２６，２８　ｉ型非晶質半導体層、３６　酸化シリコン層、３８　反射防止層、４０　窒化シリコン層、４１　残渣、４２，４４　ｐ型非晶質半導体層、６０，６２　下地電極（６０　透明電極層、６２　Ｃｕ層）、７０，７２　電極、８０，８２，８４　レジスト膜、８３　開口部、８５　分離溝、８６　分離部、１００　ｎ型領域、１０２　ｐ型領域。 10, 12 photoelectric conversion element, 20 semiconductor substrate, 22, 24 n-type amorphous semiconductor layer, 26, 28 i-type amorphous semiconductor layer, 36 silicon oxide layer, 38 antireflection layer, 40 silicon nitride layer, 41 residue , 42, 44 p-type amorphous semiconductor layer, 60, 62 ground electrode (60 transparent electrode layer, 62 Cu layer), 70, 72 electrode, 80, 82, 84 resist film, 83 opening, 85 separation groove, 86 Separation part, 100 n-type region, 102 p-type region.

Claims (4)

  1. 　受光面と、前記受光面の反対側の裏面とを有する第１導電型の半導体基板と、
    　前記裏面に配置され、前記半導体基板に接続し前記第１導電型を有する非晶質半導体層を含んで構成される第１導電型領域と、
    　前記裏面に配置され、第２導電型を有する非晶質半導体層を含んで構成され、前記半導体基板とｐｎ接合を形成する第２導電型領域と、
    　前記第１導電型領域または前記第２導電型領域のいずれか一方の領域の非晶質半導体層の上に形成される絶縁層と、
    　前記絶縁層に設けられた開口部を通して、その下部に設けられる前記非晶質半導体層に接続し、外部に引き出される電極層と、
    　を備え、
    　前記絶縁層は、
    　その下部に設けられる前記非晶質半導体層に接触して設けられる第１絶縁層と、
    　第１絶縁層の上に形成される第２絶縁層であって、前記第１絶縁層の開口部を形成する際に、リフトオフによって除去される膜質を有する第２絶縁層と、
    　を含むことを特徴とする裏面接合型の光電変換素子。     A first conductivity type semiconductor substrate having a light receiving surface and a back surface opposite to the light receiving surface;
    A first conductivity type region disposed on the back surface and connected to the semiconductor substrate and including an amorphous semiconductor layer having the first conductivity type;
    A second conductivity type region disposed on the back surface and including an amorphous semiconductor layer having a second conductivity type and forming a pn junction with the semiconductor substrate;
    An insulating layer formed on an amorphous semiconductor layer in one of the first conductivity type region and the second conductivity type region;
    An electrode layer connected to the amorphous semiconductor layer provided below the opening through the opening provided in the insulating layer, and drawn to the outside;
    With
    The insulating layer is
    A first insulating layer provided in contact with the amorphous semiconductor layer provided thereunder;
    A second insulating layer formed on the first insulating layer, the second insulating layer having a film quality removed by lift-off when forming the opening of the first insulating layer;
    A back contact type photoelectric conversion element comprising:
  2. 　請求項１に記載の裏面接合型の光電変換素子において、
    　前記第１絶縁層が酸化シリコン層であり、
    　前記第２絶縁層が窒化シリコン層であることを特徴とする裏面接合型の光電変換素子。     In the back junction type photoelectric conversion element according to claim 1,
    The first insulating layer is a silicon oxide layer;
    The back junction type photoelectric conversion element, wherein the second insulating layer is a silicon nitride layer.
  3. 　第１導電型のシリコン基板の受光面とは反対側の裏面にｐｎ接合が形成される裏面接合型の光電変換素子の製造方法であって、
    　前記第１導電型を有する非晶質半導体層を含んで構成され、前記半導体基板に接続する第１導電型領域を前記裏面に形成する工程と、
    　第２導電型を有する非晶質半導体層を含んで構成され、前記半導体基板とｐｎ接合を形成する第２導電型領域を前記裏面に形成する工程と、
    　前記第１導電型領域または前記第２導電型領域のいずれか一方の領域の非晶質半導体層の上に絶縁層を形成する工程と、
    　前記絶縁層を開口する工程と、
    　前記絶縁層に設けられた開口部を通して、その下部に設けられる前記非晶質半導体層に接続し、外部に引き出される電極層を形成する工程と、
    　を含み、
    　前記絶縁層を形成する工程は、
    　前記絶縁層の下部に設けられる前記非晶質半導体層に接触して第１絶縁層を形成する工程と、
    　前記第１絶縁層の上に第２絶縁層を形成する工程と、
    　を含み、
    　前記絶縁層を開口する工程は、
    　前記第２絶縁層を開口する工程と、
    　前記第２絶縁層に対するエッチングレートよりも前記第１絶縁層に対するエッチングレートが速く、前記第１絶縁層に対するエッチングレートよりも前記絶縁層の下部に設けられる前記非晶質半導体層に対するエッチングレートが遅いエッチングレートを有するエッチング剤で前記第１絶縁層を開口する工程と、
    　を含むことを特徴とする裏面接合型の光電変換素子の製造方法。     A method of manufacturing a back junction type photoelectric conversion element in which a pn junction is formed on the back surface opposite to the light receiving surface of a first conductivity type silicon substrate,
    Forming a first conductive type region on the back surface, the first conductive type region including an amorphous semiconductor layer having the first conductive type and connected to the semiconductor substrate;
    Forming a second conductive type region on the back surface, the second conductive type region including an amorphous semiconductor layer having a second conductive type and forming a pn junction with the semiconductor substrate;
    Forming an insulating layer on the amorphous semiconductor layer in one of the first conductivity type region and the second conductivity type region;
    Opening the insulating layer;
    A step of forming an electrode layer that is connected to the amorphous semiconductor layer provided below the opening through the opening provided in the insulating layer and led to the outside;
    Including
    The step of forming the insulating layer includes
    Forming a first insulating layer in contact with the amorphous semiconductor layer provided under the insulating layer;
    Forming a second insulating layer on the first insulating layer;
    Including
    The step of opening the insulating layer includes:
    Opening the second insulating layer;
    The etching rate for the first insulating layer is faster than the etching rate for the second insulating layer, and the etching rate for the amorphous semiconductor layer provided below the insulating layer is slower than the etching rate for the first insulating layer. Opening the first insulating layer with an etchant having an etching rate;
    The manufacturing method of the back junction type photoelectric conversion element characterized by including.
  4. 　請求項３に記載の裏面接合型の光電変換素子の製造方法において、
    　前記第１絶縁層を形成する工程は、前記第１絶縁層として酸化シリコン層を形成し、
    　前記第２絶縁層を形成する工程は、前記第２絶縁層として窒化シリコン層を形成し、
    　前記絶縁層を開口する工程は、
    　前記第１絶縁層を開口する前記エッチング剤として、ＨＦを含むエッチング液を用いることを特徴とする裏面接合型の光電変換素子の製造方法。     In the manufacturing method of the back junction type photoelectric conversion element of Claim 3,
    The step of forming the first insulating layer includes forming a silicon oxide layer as the first insulating layer,
    The step of forming the second insulating layer includes forming a silicon nitride layer as the second insulating layer,
    The step of opening the insulating layer includes:
    The manufacturing method of the back junction type photoelectric conversion element characterized by using the etching liquid containing HF as said etching agent which opens said 1st insulating layer.
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