WO2012132616A1 - Method for producing photoelectric conversion element - Google Patents

Method for producing photoelectric conversion element Download PDF

Info

Publication number
WO2012132616A1
WO2012132616A1 PCT/JP2012/053851 JP2012053851W WO2012132616A1 WO 2012132616 A1 WO2012132616 A1 WO 2012132616A1 JP 2012053851 W JP2012053851 W JP 2012053851W WO 2012132616 A1 WO2012132616 A1 WO 2012132616A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
photoelectric conversion
conversion element
amorphous silicon
type amorphous
Prior art date
Application number
PCT/JP2012/053851
Other languages
French (fr)
Japanese (ja)
Inventor
嶋田　聡
仁 坂田
藤田　和範
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Publication of WO2012132616A1 publication Critical patent/WO2012132616A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529—Shape of the potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a photoelectric conversion element.
  • Patent Document 1 discloses a semiconductor substrate having a light receiving surface and a back surface provided on the opposite side of the light receiving surface, a first semiconductor layer formed along a predetermined direction on the back surface, and a predetermined direction on the back surface. And a pair of second semiconductor layers disposed on both sides of the first semiconductor layer, and formed from one second semiconductor layer to the first semiconductor layer of the pair of second semiconductor layers.
  • the photoelectric conversion element provided with the transparent electrode layer which covers and the collection electrode layer formed on a transparent electrode layer is disclosed.
  • an insulating layer or the like may be stacked on a semiconductor layer formed on a semiconductor substrate.
  • pinholes may be formed in the insulating layer or the like due to dust or the like in the film forming apparatus.
  • the film quality may be adversely affected, for example, the semiconductor layer may be etched through the pinhole.
  • an amorphous semiconductor layer is formed on the back surface of a semiconductor substrate, an insulating layer is formed on the amorphous semiconductor layer, and a photoresist is formed on the insulating layer. Forming a layer, and etching the light-receiving surface opposite to the back surface of the semiconductor substrate in a state where the photoresist layer is formed on the insulating layer.
  • the power generation characteristics of the photoelectric conversion element can be improved.
  • it is sectional drawing of a photoelectric conversion element.
  • it is a flowchart which shows the procedure of the manufacturing method of a photoelectric conversion element.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • FIG. 1 is a cross-sectional view of the photoelectric conversion element 10.
  • the photoelectric conversion element 10 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an i-n stacked portion 21, and i.
  • an arrow A shown in FIG. 1 indicates a direction in which light such as sunlight enters the photoelectric conversion element 10.
  • the “light receiving surface” means a surface on which light such as sunlight is mainly incident.
  • the “back surface” means a surface opposite to the light receiving surface.
  • the n-type single crystal silicon substrate 18 is a power generation layer that receives carriers incident from the light receiving surface and generates carriers.
  • the n-type single crystal silicon substrate 18 is used.
  • the present invention is not limited to this, and an n-type or p-type conductive crystal semiconductor substrate can be used.
  • a polycrystalline silicon substrate, a gallium arsenide substrate (GaAs), an indium phosphorus substrate (InP), or the like can be used.
  • the i-type amorphous silicon layer 16 is a passivation layer formed on the light-receiving surface of the n-type single crystal silicon substrate 18.
  • the n-type amorphous silicon layer 14 is formed on the i-type amorphous silicon layer 16.
  • the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 constitute an amorphous semiconductor layer portion formed on the light receiving surface.
  • the i-type amorphous silicon layer 16 is a layer made of an intrinsic amorphous semiconductor film.
  • the i-type amorphous silicon layer 16 has a lower dopant concentration in the film than the n-type amorphous silicon layer 14.
  • the i-type amorphous silicon layer 16 preferably has an n-type or p-type conductivity of 10 ⁇ 11 s / cm or less.
  • the n-type amorphous silicon layer 14 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 14 has a higher dopant concentration in the film than the i-type amorphous silicon layer 16.
  • the n-type amorphous silicon layer 14 preferably has an n-type conductivity of 10 ⁇ 3 s / cm or more.
  • the amorphous silicon layer includes a microcrystalline semiconductor film.
  • a microcrystalline semiconductor film is a film in which crystal grains are precipitated in an amorphous semiconductor.
  • the average grain size of the crystal grains is not limited to this, but is estimated to be about 1 nm to 80 nm.
  • the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 and reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10.
  • the antireflection layer 12 also functions as a protective layer that protects the surface of the n-type amorphous silicon layer 14.
  • the antireflection layer 12 is made of a transparent material and has a refractive index that reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10 in relation to the refractive index of the layer covered by the antireflection layer 12. And a film thickness is preferred.
  • the antireflection layer 12 includes, for example, aluminum nitride, silicon nitride, silicon oxide, and the like.
  • the i-n laminated portion 21 is formed on the back surface of the n-type single crystal silicon substrate 18. It is preferable that the i-n stacked unit 21 is arranged so that current can be collected evenly from the surface of the photoelectric conversion element 10 in an n-side electrode unit 25 described later.
  • the i-n stacked portion 21 preferably has a comb-teeth shape in which a plurality of finger portions extend in parallel.
  • the i-n stacked unit 21 includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23.
  • the i-type amorphous silicon layer 22 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the n-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22.
  • the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 constitute a first amorphous semiconductor layer portion formed on the back surface.
  • the i-type amorphous silicon layer 22 is a layer made of an intrinsic amorphous semiconductor film.
  • the i-type amorphous silicon layer 22 has a lower dopant concentration in the film than the n-type amorphous silicon layer 23.
  • the i-type amorphous silicon layer 22 preferably has an n-type or p-type conductivity of 10 ⁇ 11 s / cm or less.
  • the n-type amorphous silicon layer 23 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 23 has a higher dopant concentration in the film than the i-type amorphous silicon layer 22.
  • the n-type amorphous silicon layer 23 preferably has an n-type conductivity of 10 ⁇ 3 s / cm or more.
  • the insulating layer 24 is formed to electrically insulate the i-n laminated portion 21 and the ip laminated portion 31.
  • the insulating layer 24 also functions as a protective layer formed on the n-type amorphous silicon layer 23.
  • the insulating layer 24 may be any material having electrical insulation properties, but preferably includes, for example, aluminum nitride, silicon nitride, silicon oxide, and the like.
  • the n-side electrode portion 25 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10.
  • the n-side electrode unit 25 includes a transparent conductive layer 26, a metal layer 27, a first electrode unit 28, and a second electrode unit 29.
  • the transparent conductive layer 26 is formed on the n-type amorphous silicon layer 23.
  • the transparent conductive layer 26 is made of a metal oxide such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), titanium oxide (TiO 2 ), and indium tin oxide (ITO). It is configured to include at least one.
  • the transparent conductive layer 26 is described as being formed using indium tin oxide (ITO).
  • the metal layer 27 is formed on the transparent conductive layer 26.
  • the metal layer 27 is a seed layer including a metal such as copper (Cu) or an alloy, for example.
  • the “seed layer” refers to a layer that is a starting point for plating growth.
  • the first electrode portion 28 is an electrode formed on the metal layer 27 by plating growth.
  • the 1st electrode part 28 is comprised including copper (Cu), for example.
  • the second electrode part 29 is an electrode formed on the first electrode part 28 by plating growth.
  • the second electrode unit 29 includes tin (Sn).
  • the ip laminated portion 31 is formed on the back surface of the n-type single crystal silicon substrate 18 so as to be inserted into the i-n laminated portion 21.
  • the ip laminated portion 31 is preferably arranged so that current can be collected evenly from within the surface of the photoelectric conversion element 10 in the p-side electrode portion 35 described later.
  • the ip laminated portion 31 is preferably, for example, in a comb-teeth shape in which a plurality of finger portions extend in parallel.
  • the ip laminated portion 31 includes an i-type amorphous silicon layer 32 and a p-type amorphous silicon layer 33.
  • the i-type amorphous silicon layer 32 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the p-type amorphous silicon layer 33 is formed on the i-type amorphous silicon layer 32.
  • the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 constitute a second amorphous semiconductor layer portion formed on the back surface.
  • the i-type amorphous silicon layer 32 is a layer made of an intrinsic amorphous semiconductor film.
  • the i-type amorphous silicon layer 32 has a lower dopant concentration in the film than the p-type amorphous silicon layer 33.
  • the i-type amorphous silicon layer 32 preferably has an n-type or p-type conductivity of 10 ⁇ 11 s / cm or less.
  • the p-type amorphous silicon layer 33 is a layer made of an amorphous semiconductor film containing a p-type conductive dopant.
  • the p-type amorphous silicon layer 33 has a higher dopant concentration in the film than the i-type amorphous silicon layer 32.
  • the p-type amorphous silicon layer 33 preferably has a p-type conductivity of 10 ⁇ 5 s / cm or more.
  • the p-side electrode portion 35 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10.
  • the p-side electrode part 35 includes a transparent conductive layer 36, a metal layer 37, a first electrode part 38, and a second electrode part 39.
  • the transparent conductive layer 36 is formed on the p-type amorphous silicon layer 33.
  • the metal layer 37 is formed on the transparent conductive layer 36.
  • the first electrode portion 38 is formed on the metal layer 37 by plating growth.
  • the second electrode portion 39 is formed on the first electrode portion 38 by plating growth.
  • FIG. 2 is a flowchart showing the procedure of the first embodiment of the method for manufacturing the photoelectric conversion element 10.
  • the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
  • an n-type single crystal silicon substrate 18 is prepared, and the light-receiving surface and the back surface of the n-type single crystal silicon substrate 18 are cleaned (S1).
  • the n-type single crystal silicon substrate 18 can be cleaned using, for example, an HF aqueous solution.
  • an i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a are formed on the back surface of the n-type single crystal silicon substrate 18 (S2).
  • each of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a can be formed by, for example, a plasma CVD method or the like.
  • an insulating layer 24a is formed on the n-type amorphous silicon layer 23a (S3).
  • the insulating layer 24a can be formed by, for example, a thin film forming method such as a sputtering method or a plasma CVD method.
  • a photoresist 20a is formed on the insulating layer 24a (S4).
  • the photoresist 20a can be formed, for example, by applying a thin film with a spin coater or a slit coater.
  • the unexposed photoresist 20a is excellent in alkali resistance.
  • a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S5).
  • a pyramidal uneven shape is formed on the light-receiving surface of the n-type single crystal silicon substrate 18 by using an alkaline anisotropic etching solution such as a potassium hydroxide aqueous solution (KOH aqueous solution). Can be formed.
  • KOH aqueous solution potassium hydroxide aqueous solution
  • the photoresist 20a is exposed based on a previously prepared pattern (S6). Thereby, in the photoresist 20a, a portion irradiated with light when exposed is in a state of being dissolved in an alkaline developer.
  • an alkaline developer is applied to the photoresist 20a, and the portion irradiated with light is removed from the photoresist 20a as shown in FIG. 6 (S7). Thereby, a photoresist 20 which is a mask for patterning the insulating layer 24 is formed.
  • the insulating layer 24a is etched to remove a part of the insulating layer 24a, and then the photoresist 20 is peeled off (S8).
  • the insulating layer 24b is formed by removing a portion of the insulating layer 24a located on a region for bonding the ip stacked portion 31 to the n-type single crystal silicon substrate 18 in a later step.
  • an acidic etching solution such as an HF aqueous solution is used for the etching of the insulating layer 24a.
  • each of the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 can be formed by, for example, a plasma CVD method or the like.
  • the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S10).
  • the antireflection layer 12 can be formed, for example, by a thin film forming method such as a sputtering method or a CVD method.
  • the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched using the insulating layer 24b patterned in S8 as a mask (S11). Specifically, portions of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a other than the portion covered with the insulating layer 24b are removed. Thus, the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 are formed by exposing a portion of the back surface of the n-type single crystal silicon substrate 18 where the insulating layer 24b is not located above. To do.
  • an alkaline etching solution such as an aqueous solution containing sodium hydroxide (NaOH) is used.
  • the insulating layer 24 b, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23 and the exposed back surface of the n-type single crystal silicon substrate 18 are covered with i
  • the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a can be formed by, for example, a plasma CVD method or the like.
  • a part of the portion located on the insulating layer 24b is etched (S13). .
  • the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are formed.
  • an alkaline etching solution such as an aqueous solution containing sodium hydroxide (NaOH) is used.
  • the insulating layer 24b is etched to further remove a part of the insulating layer 24b (S14). Specifically, the insulating layer 24 is formed by removing the exposed portion of the insulating layer 24b by etching using the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 as a mask.
  • an acidic etching solution such as an HF aqueous solution is used for the etching of the insulating layer 24b.
  • a transparent conductive layer 26a and a metal layer 27a are formed (S15). Specifically, it is formed by a thin film forming method such as a plasma CVD method or a sputtering method.
  • the transparent conductive layers 26 and 36 and the metal layers 27 and 37 are formed by dividing a portion of the transparent conductive layer 26 a and the metal layer 27 a located on the insulating layer 24. (S16).
  • the transparent conductive layer 26a and the metal layer 27a are divided by, for example, a lithography method.
  • the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating, and the first electrode portion 38 and the second electrode portion 29 are formed on the metal layer 37.
  • Two electrode portions 39 are sequentially formed (S17). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
  • a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 using an alkaline anisotropic etching solution such as an aqueous potassium hydroxide solution (KOH aqueous solution).
  • KOH aqueous solution aqueous potassium hydroxide solution
  • the substantially entire surface of the insulating layer 24b is excellent in alkali resistance. Covered with a photoresist 20a. As a result, even if a pinhole exists in the insulating layer 24b, since the pinhole is blocked by the insulating layer 24b, the alkaline anisotropic etching solution passes through the pinhole. Thus, it is possible to prevent adhesion to the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a. Therefore, according to the first embodiment of the method for manufacturing the photoelectric conversion element 10, the power generation characteristics of the photoelectric conversion element 10 can be improved.
  • the texture structure is formed only on the light receiving surface of the n-type single crystal silicon substrate 18 and the texture structure is not formed on the back surface, the texture structure is formed only on the light receiving surface by temporarily covering the back surface with a sacrificial layer having excellent alkali resistance. After that, a separate step of peeling the sacrificial layer is required.
  • the alkali resistance is excellent, and after the photoresist 20a used for patterning the insulating layer 24a is formed, Since the texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18, a separate process such as providing a special sacrificial layer on the back surface side as described above is not necessary.
  • the photoresist 20a for patterning the insulating layer 24a also serves as the sacrificial layer, the number of steps for manufacturing the photoelectric conversion element 10 can be reduced.
  • FIG. 15 is a flowchart showing the procedure of the second embodiment of the method for manufacturing the photoelectric conversion element 10.
  • the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
  • steps of the second embodiment of the method for manufacturing the photoelectric conversion element 10 and the first embodiment of the method for manufacturing the photoelectric conversion element 10 are the same in steps S1 to S4 and S8 to S17, and between S4 to S8. Since only the process is different, the difference will be mainly described.
  • S1 to S4 are performed as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
  • the photoresist 20a is exposed based on a pattern prepared in advance (S5a).
  • a portion irradiated with light when exposed is in a state of being dissolved in an alkaline developer.
  • an alkaline developer is applied to the photoresist 20a to remove the portion irradiated with light in the photoresist 20a (S6a). Thereby, a photoresist 20 which is a mask for patterning the insulating layer 24 is formed.
  • a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S7a).
  • a pyramidal uneven shape is formed on the light-receiving surface of the n-type single crystal silicon substrate 18 by using an alkaline anisotropic etching solution such as a potassium hydroxide aqueous solution (KOH aqueous solution). Can be formed.
  • KOH aqueous solution potassium hydroxide aqueous solution
  • S8 to S17 are performed as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
  • the second embodiment of the method for manufacturing the photoelectric conversion element 10 a part of the photoresist 20a is removed before the texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18. Therefore, it is possible to prevent damage to the i-type amorphous silicon layer 22a and the p-type amorphous silicon layer 23a located below the portion covered with the photoresist 20, but the removed portion The i-type amorphous silicon layer 22a and the p-type amorphous silicon layer 23a located below may be damaged. However, the portion that may be damaged is a region that is etched in the subsequent step S11. That is, since the portion that can be damaged is a portion that is eventually removed, the damage is not a problem. Therefore, also in the second embodiment of the method for manufacturing the photoelectric conversion element 10, the power generation characteristics of the photoelectric conversion element 10 can be improved as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
  • FIG. 16 is a flowchart showing the procedure of the third embodiment of the method for manufacturing the photoelectric conversion element 10.
  • the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
  • steps of the third embodiment of the method for manufacturing the photoelectric conversion element 10 and the first embodiment of the method for manufacturing the photoelectric conversion element 10 are the same in steps S1 to S4 and S8 to S17, and are between S4 to S8. Since only the process is different, the difference will be mainly described.
  • S1 to S4 are performed as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
  • the photoresist 20a is exposed based on a pattern prepared in advance (S5b).
  • a portion irradiated with light when exposed is in a state of being dissolved in an alkaline developer.
  • a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 using an alkaline anisotropic etching solution such as an aqueous potassium hydroxide solution (KOH aqueous solution), and the same anisotropic etching solution is used.
  • the photoresist 20a is developed (S6b). As a result, a pyramidal concavo-convex shape can be formed on the light receiving surface of the n-type single crystal silicon substrate 18, and a photoresist 20 which is a mask for patterning the insulating layer 24 is formed.
  • the power generation characteristics of the photoelectric conversion element 10 can be improved as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
  • a part of the photoresist 20a is removed using the same alkaline anisotropic etching solution, and a texture is formed on the light receiving surface of the n-type single crystal silicon substrate 18. Forming a structure. Therefore, the number of steps of the method for manufacturing the photoelectric conversion element 10 can be reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Sustainable Development (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The present invention provides a method for producing a photoelectric conversion element (10). According to this method, an amorphous semiconductor layer part is formed on the rear surface of an n-type single-crystal silicon substrate (18), an insulating layer (24a) is formed on the amorphous semiconductor layer part, a photoresist (20a) is formed on the insulating layer (24a), and the light-receiving surface on the opposite side of the n-type single-crystal silicon substrate (18) to the rear surface is etched in a state in which the photoresist (20a) is formed on the insulating layer (24a).

Description

光電変換素子の製造方法Method for manufacturing photoelectric conversion element
　本発明は、光電変換素子の製造方法に関する。 The present invention relates to a method for manufacturing a photoelectric conversion element.
　特許文献１には、受光面と、受光面の反対側に設けられる裏面とを有する半導体基板と、裏面上において所定の方向に沿って形成される第１半導体層と、裏面上において所定の方向に沿って形成され、第１半導体層の両隣に配設される一対の第２半導体層と、一対の第２半導体層のうち一方の第２半導体層上から第１半導体層上まで跨って形成される第１絶縁層と、一対の第２半導体層のうち他方の第２半導体層上から第１半導体層上まで跨って形成される第２絶縁層と、第１半導体層及び第２半導体層を覆う透明電極層と、透明電極層上に形成される収集電極層と、を備える光電変換素子が開示されている。 Patent Document 1 discloses a semiconductor substrate having a light receiving surface and a back surface provided on the opposite side of the light receiving surface, a first semiconductor layer formed along a predetermined direction on the back surface, and a predetermined direction on the back surface. And a pair of second semiconductor layers disposed on both sides of the first semiconductor layer, and formed from one second semiconductor layer to the first semiconductor layer of the pair of second semiconductor layers. A first insulating layer to be formed; a second insulating layer formed from the other second semiconductor layer to the first semiconductor layer of the pair of second semiconductor layers; a first semiconductor layer and a second semiconductor layer; The photoelectric conversion element provided with the transparent electrode layer which covers and the collection electrode layer formed on a transparent electrode layer is disclosed.
特開２００９－２００２６７号公報JP 2009-200277 A
　ところで、半導体基板上に形成される半導体層上に絶縁層等が積層されることがある。当該絶縁層等の成膜の際に、成膜装置内の塵等が原因で絶縁層等にピンホールが形成されることがある。このような絶縁層等に対してパターンニング処理を行うと、上記ピンホールを通して半導体層がエッチングされる等、膜質にも悪影響を及ぼす可能性がある。 By the way, an insulating layer or the like may be stacked on a semiconductor layer formed on a semiconductor substrate. When forming the insulating layer or the like, pinholes may be formed in the insulating layer or the like due to dust or the like in the film forming apparatus. When patterning treatment is performed on such an insulating layer, the film quality may be adversely affected, for example, the semiconductor layer may be etched through the pinhole.
　本発明に係る光電変換素子の製造方法は、半導体基板の裏面上に非晶質系半導体層を形成し、前記非晶質系半導体層上に絶縁層を形成し、前記絶縁層上にフォトレジスト層を形成し、前記絶縁層上に前記フォトレジスト層が形成されている状態で前記半導体基板の前記裏面の反対側の受光面をエッチング加工する。 In the method of manufacturing a photoelectric conversion element according to the present invention, an amorphous semiconductor layer is formed on the back surface of a semiconductor substrate, an insulating layer is formed on the amorphous semiconductor layer, and a photoresist is formed on the insulating layer. Forming a layer, and etching the light-receiving surface opposite to the back surface of the semiconductor substrate in a state where the photoresist layer is formed on the insulating layer.
　上記発明によれば、光電変換素子の発電特性を向上させることができる。 According to the above invention, the power generation characteristics of the photoelectric conversion element can be improved.
本発明に係る実施の形態において、光電変換素子の断面図である。In embodiment which concerns on this invention, it is sectional drawing of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を示すフローチャートである。In embodiment concerning this invention, it is a flowchart which shows the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を示すフローチャートである。In embodiment concerning this invention, it is a flowchart which shows the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を示すフローチャートである。In embodiment concerning this invention, it is a flowchart which shows the procedure of the manufacturing method of a photoelectric conversion element.
　以下に図面を用いて、本発明に係る実施の形態を詳細に説明する。以下では、全ての図面において、同様の要素には同一の符号を付し、重複する説明を省略する。本文中の説明においては、必要に応じそれ以前に述べた符号を用いるものとする。 Embodiments according to the present invention will be described below in detail with reference to the drawings. Hereinafter, in all the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. In the description in the text, the symbols described before are used as necessary.
　図１は、光電変換素子１０の断面図である。光電変換素子１０は、反射防止層１２と、ｎ型非晶質シリコン層１４と、ｉ型非晶質シリコン層１６と、ｎ型単結晶シリコン基板１８と、ｉ－ｎ積層部２１と、ｉ－ｐ積層部３１と、絶縁層２４と、ｎ側電極部２５と、ｐ側電極部３５とを備える。ここで、図１に示される矢印Ａは、光電変換素子１０に対して太陽光等の光が入射される方向を示している。なお、「受光面」とは、太陽光等の光が主に入射される面を意味する。また、「裏面」とは、受光面と反対側の面を意味する。 FIG. 1 is a cross-sectional view of the photoelectric conversion element 10. The photoelectric conversion element 10 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an i-n stacked portion 21, and i. A p-layer portion 31, an insulating layer 24, an n-side electrode portion 25, and a p-side electrode portion 35; Here, an arrow A shown in FIG. 1 indicates a direction in which light such as sunlight enters the photoelectric conversion element 10. The “light receiving surface” means a surface on which light such as sunlight is mainly incident. The “back surface” means a surface opposite to the light receiving surface.
　ｎ型単結晶シリコン基板１８は、受光面から入射された光を受けてキャリアを生成する発電層である。なお、本実施の形態では、ｎ型単結晶シリコン基板１８としたが、これに限定されるものではなく、ｎ型又はｐ型の導電型の結晶系半導体基板とすることができる。単結晶シリコン基板の他にも、例えば、多結晶シリコン基板、砒化ガリウム基板（ＧａＡｓ）、インジウム燐基板（ＩｎＰ）等を適用することができる。 The n-type single crystal silicon substrate 18 is a power generation layer that receives carriers incident from the light receiving surface and generates carriers. In this embodiment, the n-type single crystal silicon substrate 18 is used. However, the present invention is not limited to this, and an n-type or p-type conductive crystal semiconductor substrate can be used. In addition to the single crystal silicon substrate, for example, a polycrystalline silicon substrate, a gallium arsenide substrate (GaAs), an indium phosphorus substrate (InP), or the like can be used.
　ｉ型非晶質シリコン層１６は、ｎ型単結晶シリコン基板１８の受光面上に形成されるパッシベーション層である。ｎ型非晶質シリコン層１４は、ｉ型非晶質シリコン層１６上に形成される。ｉ型非晶質シリコン層１６及びｎ型非晶質シリコン層１４は、受光面に形成される非晶質系半導体層部を構成する。ｉ型非晶質シリコン層１６は、真性な非晶質半導体膜からなる層である。ｉ型非晶質シリコン層１６は、ｎ型非晶質シリコン層１４よりも膜中のドーパント濃度が低くされる。例えば、ｉ型非晶質シリコン層１６は、ｎ型又はｐ型の導電率を１０-11ｓ／ｃｍ以下とすることが好適である。ｎ型非晶質シリコン層１４は、ｎ型の導電型のドーパントを含む非晶質半導体膜からなる層である。ｎ型非晶質シリコン層１４は、ｉ型非晶質シリコン層１６よりも膜中のドーパント濃度が高くされる。例えば、ｎ型非晶質シリコン層１４は、ｎ型の導電率を１０-3ｓ／ｃｍ以上とすることが好適である。 The i-type amorphous silicon layer 16 is a passivation layer formed on the light-receiving surface of the n-type single crystal silicon substrate 18. The n-type amorphous silicon layer 14 is formed on the i-type amorphous silicon layer 16. The i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 constitute an amorphous semiconductor layer portion formed on the light receiving surface. The i-type amorphous silicon layer 16 is a layer made of an intrinsic amorphous semiconductor film. The i-type amorphous silicon layer 16 has a lower dopant concentration in the film than the n-type amorphous silicon layer 14. For example, the i-type amorphous silicon layer 16 preferably has an n-type or p-type conductivity of 10 −11 s / cm or less. The n-type amorphous silicon layer 14 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant. The n-type amorphous silicon layer 14 has a higher dopant concentration in the film than the i-type amorphous silicon layer 16. For example, the n-type amorphous silicon layer 14 preferably has an n-type conductivity of 10 −3 s / cm or more.
　なお、本実施の形態において非晶質シリコン層は、微結晶半導体膜を含む。微結晶半導体膜は、非晶質半導体中に結晶粒が析出している膜である。結晶粒の平均粒径は、これに限定されるものではないが、１ｎｍ以上８０ｎｍ以下程度であると推定されている。 Note that in this embodiment mode, the amorphous silicon layer includes a microcrystalline semiconductor film. A microcrystalline semiconductor film is a film in which crystal grains are precipitated in an amorphous semiconductor. The average grain size of the crystal grains is not limited to this, but is estimated to be about 1 nm to 80 nm.
　反射防止層１２は、ｎ型非晶質シリコン層１４上に形成され、光電変換素子１０の受光面から入射される光の反射を低減させる。反射防止層１２は、ｎ型非晶質シリコン層１４の表面を保護する保護層としても機能する。反射防止層１２は、透明な材料で構成され、反射防止層１２によって覆われる層の屈折率との関係で光電変換素子１０の受光面から入射される光の反射を低減させる屈折率を有する材料及び膜厚とすることが好適である。反射防止層１２は、例えば、窒化アルミニウム、窒化ケイ素及び酸化ケイ素等を含んで構成される。 The antireflection layer 12 is formed on the n-type amorphous silicon layer 14 and reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10. The antireflection layer 12 also functions as a protective layer that protects the surface of the n-type amorphous silicon layer 14. The antireflection layer 12 is made of a transparent material and has a refractive index that reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10 in relation to the refractive index of the layer covered by the antireflection layer 12. And a film thickness is preferred. The antireflection layer 12 includes, for example, aluminum nitride, silicon nitride, silicon oxide, and the like.
　ｉ－ｎ積層部２１は、ｎ型単結晶シリコン基板１８の裏面上に形成される。ｉ－ｎ積層部２１は、後述するｎ側電極部２５において、光電変換素子１０の面内からまんべんなく集電可能なように配置することが好適である。ｉ－ｎ積層部２１は、例えば、複数のフィンガー部が平行に延伸する櫛歯形状とすることが好適である。ｉ－ｎ積層部２１は、ｉ型非晶質シリコン層２２と、ｎ型非晶質シリコン層２３と、を備える。 The i-n laminated portion 21 is formed on the back surface of the n-type single crystal silicon substrate 18. It is preferable that the i-n stacked unit 21 is arranged so that current can be collected evenly from the surface of the photoelectric conversion element 10 in an n-side electrode unit 25 described later. For example, the i-n stacked portion 21 preferably has a comb-teeth shape in which a plurality of finger portions extend in parallel. The i-n stacked unit 21 includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23.
　ｉ型非晶質シリコン層２２は、ｎ型単結晶シリコン基板１８の裏面上に形成されるパッシベーション層である。ｎ型非晶質シリコン層２３は、ｉ型非晶質シリコン層２２上に形成される。ｉ型非晶質シリコン層２２及びｎ型非晶質シリコン層２３は、裏面に形成される第１の非晶質系半導体層部を構成する。ｉ型非晶質シリコン層２２は、真性な非晶質半導体膜からなる層である。ｉ型非晶質シリコン層２２は、ｎ型非晶質シリコン層２３よりも膜中のドーパント濃度が低くされる。例えば、ｉ型非晶質シリコン層２２は、ｎ型又はｐ型の導電率を１０-11ｓ／ｃｍ以下とすることが好適である。ｎ型非晶質シリコン層２３は、ｎ型の導電型のドーパントを含む非晶質半導体膜からなる層である。ｎ型非晶質シリコン層２３は、ｉ型非晶質シリコン層２２よりも膜中のドーパント濃度が高くされる。例えば、ｎ型非晶質シリコン層２３は、ｎ型の導電率を１０-3ｓ／ｃｍ以上とすることが好適である。 The i-type amorphous silicon layer 22 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18. The n-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22. The i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 constitute a first amorphous semiconductor layer portion formed on the back surface. The i-type amorphous silicon layer 22 is a layer made of an intrinsic amorphous semiconductor film. The i-type amorphous silicon layer 22 has a lower dopant concentration in the film than the n-type amorphous silicon layer 23. For example, the i-type amorphous silicon layer 22 preferably has an n-type or p-type conductivity of 10 −11 s / cm or less. The n-type amorphous silicon layer 23 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant. The n-type amorphous silicon layer 23 has a higher dopant concentration in the film than the i-type amorphous silicon layer 22. For example, the n-type amorphous silicon layer 23 preferably has an n-type conductivity of 10 −3 s / cm or more.
　絶縁層２４は、ｉ－ｎ積層部２１とｉ－ｐ積層部３１とを電気的に絶縁するために形成される。絶縁層２４は、ｎ型非晶質シリコン層２３上に形成される保護層としても機能する。絶縁層２４は、電気的な絶縁性を有する材料であればよいが、例えば、窒化アルミニウム、窒化ケイ素及び酸化ケイ素等を含んで構成することが好適である。 The insulating layer 24 is formed to electrically insulate the i-n laminated portion 21 and the ip laminated portion 31. The insulating layer 24 also functions as a protective layer formed on the n-type amorphous silicon layer 23. The insulating layer 24 may be any material having electrical insulation properties, but preferably includes, for example, aluminum nitride, silicon nitride, silicon oxide, and the like.
　ｎ側電極部２５は、光電変換素子１０において発電された電気を集電して取り出すために設けられる電極部材である。ｎ側電極部２５は、透明導電層２６と、金属層２７と、第１電極部２８と、第２電極部２９とを備える。透明導電層２６は、ｎ型非晶質シリコン層２３上に形成される。透明導電層２６は、酸化インジウム（Ｉｎ2Ｏ3）、酸化亜鉛（ＺｎＯ）、酸化錫（ＳｎＯ2）、酸化チタン（ＴｉＯ2）及びインジウム錫酸化物（ＩＴＯ）等の金属酸化物のうちの少なくとも１つを含んで構成される。ここでは、透明導電層２６はインジウム錫酸化物（ＩＴＯ）を用いて形成されているものとして説明する。金属層２７は、透明導電層２６上に形成される。金属層２７は、例えば、銅（Ｃｕ）等の金属や合金を含んで構成されるシード層である。ここで、「シード層」とは、めっき成長の起点となる層のことをいう。第１電極部２８は、めっき成長によって金属層２７上に形成される電極である。第１電極部２８は、例えば、銅（Ｃｕ）を含んで構成される。第２電極部２９は、めっき成長によって第１電極部２８上に形成される電極である。第２電極部２９は、例えば、錫（Ｓｎ）を含んで構成される。 The n-side electrode portion 25 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10. The n-side electrode unit 25 includes a transparent conductive layer 26, a metal layer 27, a first electrode unit 28, and a second electrode unit 29. The transparent conductive layer 26 is formed on the n-type amorphous silicon layer 23. The transparent conductive layer 26 is made of a metal oxide such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), titanium oxide (TiO 2 ), and indium tin oxide (ITO). It is configured to include at least one. Here, the transparent conductive layer 26 is described as being formed using indium tin oxide (ITO). The metal layer 27 is formed on the transparent conductive layer 26. The metal layer 27 is a seed layer including a metal such as copper (Cu) or an alloy, for example. Here, the “seed layer” refers to a layer that is a starting point for plating growth. The first electrode portion 28 is an electrode formed on the metal layer 27 by plating growth. The 1st electrode part 28 is comprised including copper (Cu), for example. The second electrode part 29 is an electrode formed on the first electrode part 28 by plating growth. For example, the second electrode unit 29 includes tin (Sn).
　ｉ－ｐ積層部３１は、ｎ型単結晶シリコン基板１８の裏面上にｉ－ｎ積層部２１と間挿し合うように形成される。ｉ－ｐ積層部３１は、後述するｐ側電極部３５において、光電変換素子１０の面内からまんべんなく集電可能なように配置することが好適である。ｉ－ｐ積層部３１は、例えば、複数のフィンガー部が平行に延伸する櫛歯形状とすることが好適である。ｉ－ｐ積層部３１は、ｉ型非晶質シリコン層３２と、ｐ型非晶質シリコン層３３と、を備える。ｉ型非晶質シリコン層３２は、ｎ型単結晶シリコン基板１８の裏面上に形成されるパッシベーション層である。ｐ型非晶質シリコン層３３は、ｉ型非晶質シリコン層３２上に形成される。ｉ型非晶質シリコン層３２及びｐ型非晶質シリコン層３３は、裏面に形成される第２の非晶質系半導体層部を構成する。ｉ型非晶質シリコン層３２は、真性な非晶質半導体膜からなる層である。ｉ型非晶質シリコン層３２は、ｐ型非晶質シリコン層３３よりも膜中のドーパント濃度が低くされる。例えば、ｉ型非晶質シリコン層３２は、ｎ型又はｐ型の導電率を１０-11ｓ／ｃｍ以下とすることが好適である。ｐ型非晶質シリコン層３３は、ｐ型の導電型のドーパントを含む非晶質半導体膜からなる層である。ｐ型非晶質シリコン層３３は、ｉ型非晶質シリコン層３２よりも膜中のドーパント濃度が高くされる。例えば、ｐ型非晶質シリコン層３３は、ｐ型の導電率を１０-5ｓ／ｃｍ以上とすることが好適である。 The ip laminated portion 31 is formed on the back surface of the n-type single crystal silicon substrate 18 so as to be inserted into the i-n laminated portion 21. The ip laminated portion 31 is preferably arranged so that current can be collected evenly from within the surface of the photoelectric conversion element 10 in the p-side electrode portion 35 described later. The ip laminated portion 31 is preferably, for example, in a comb-teeth shape in which a plurality of finger portions extend in parallel. The ip laminated portion 31 includes an i-type amorphous silicon layer 32 and a p-type amorphous silicon layer 33. The i-type amorphous silicon layer 32 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18. The p-type amorphous silicon layer 33 is formed on the i-type amorphous silicon layer 32. The i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 constitute a second amorphous semiconductor layer portion formed on the back surface. The i-type amorphous silicon layer 32 is a layer made of an intrinsic amorphous semiconductor film. The i-type amorphous silicon layer 32 has a lower dopant concentration in the film than the p-type amorphous silicon layer 33. For example, the i-type amorphous silicon layer 32 preferably has an n-type or p-type conductivity of 10 −11 s / cm or less. The p-type amorphous silicon layer 33 is a layer made of an amorphous semiconductor film containing a p-type conductive dopant. The p-type amorphous silicon layer 33 has a higher dopant concentration in the film than the i-type amorphous silicon layer 32. For example, the p-type amorphous silicon layer 33 preferably has a p-type conductivity of 10 −5 s / cm or more.
　ｐ側電極部３５は、光電変換素子１０において発電された電気を集電して取り出すために設けられる電極部材である。ｐ側電極部３５は、透明導電層３６と、金属層３７と、第１電極部３８と、第２電極部３９とを備える。透明導電層３６は、ｐ型非晶質シリコン層３３上に形成される。金属層３７は、透明導電層３６上に形成される。第１電極部３８は、めっき成長によって金属層３７上に形成される。第２電極部３９は、めっき成長によって第１電極部３８上に形成される。 The p-side electrode portion 35 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10. The p-side electrode part 35 includes a transparent conductive layer 36, a metal layer 37, a first electrode part 38, and a second electrode part 39. The transparent conductive layer 36 is formed on the p-type amorphous silicon layer 33. The metal layer 37 is formed on the transparent conductive layer 36. The first electrode portion 38 is formed on the metal layer 37 by plating growth. The second electrode portion 39 is formed on the first electrode portion 38 by plating growth.
　次に、光電変換素子１０の製造方法の第１実施例を説明する。図２は、光電変換素子１０の製造方法の第１実施例の手順を示すフローチャートである。なお、光電変換素子１０の製造方法は、各工程において示す製造方法に限定されない。各工程において、例えば、スパッタリング法、プラズマＣＶＤ法、スクリーン印刷法或いはめっき法等を適宜用いることができる。 Next, a first embodiment of the method for manufacturing the photoelectric conversion element 10 will be described. FIG. 2 is a flowchart showing the procedure of the first embodiment of the method for manufacturing the photoelectric conversion element 10. In addition, the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
　まず、ｎ型単結晶シリコン基板１８を用意して、ｎ型単結晶シリコン基板１８の受光面及び裏面の洗浄を行う（Ｓ１）。ここで、ｎ型単結晶シリコン基板１８の洗浄は、例えば、ＨＦ水溶液等を用いて行うことができる。そして、図３に示されるように、ｎ型単結晶シリコン基板１８の裏面上に、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａを形成する（Ｓ２）。ここで、ｉ型非晶質シリコン層２２ａ及びｎ型非晶質シリコン層２３ａのそれぞれは、例えば、プラズマＣＶＤ法等により形成することができる。 First, an n-type single crystal silicon substrate 18 is prepared, and the light-receiving surface and the back surface of the n-type single crystal silicon substrate 18 are cleaned (S1). Here, the n-type single crystal silicon substrate 18 can be cleaned using, for example, an HF aqueous solution. Then, as shown in FIG. 3, an i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a are formed on the back surface of the n-type single crystal silicon substrate 18 (S2). Here, each of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a can be formed by, for example, a plasma CVD method or the like.
　続いて、図４に示されるように、ｎ型非晶質シリコン層２３ａ上に絶縁層２４ａを形成する（Ｓ３）。絶縁層２４ａは、例えば、スパッタリング法やプラズマＣＶＤ法等の薄膜形成法等により形成することができる。 Subsequently, as shown in FIG. 4, an insulating layer 24a is formed on the n-type amorphous silicon layer 23a (S3). The insulating layer 24a can be formed by, for example, a thin film forming method such as a sputtering method or a plasma CVD method.
　その後、図５に示されるように、絶縁層２４ａ上にフォトレジスト２０ａを形成する（Ｓ４）。ここで、フォトレジスト２０ａは、例えば、スピンコーターやスリットコーター等で薄膜状に塗布すること等により形成することができる。また、未露光の状態のフォトレジスト２０ａは、耐アルカリ性に優れている。 Thereafter, as shown in FIG. 5, a photoresist 20a is formed on the insulating layer 24a (S4). Here, the photoresist 20a can be formed, for example, by applying a thin film with a spin coater or a slit coater. The unexposed photoresist 20a is excellent in alkali resistance.
　次に、ｎ型単結晶シリコン基板１８の受光面上にテクスチャ構造を形成する（Ｓ５）。ここで、テクスチャ構造の形成には、水酸化カリウム水溶液（ＫＯＨ水溶液）等のアルカリ性の異方性エッチング液を用いることで、ｎ型単結晶シリコン基板１８の受光面上にピラミッド状の凹凸形状を形成することができる。 Next, a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S5). Here, for the formation of the texture structure, a pyramidal uneven shape is formed on the light-receiving surface of the n-type single crystal silicon substrate 18 by using an alkaline anisotropic etching solution such as a potassium hydroxide aqueous solution (KOH aqueous solution). Can be formed.
　そして、フォトレジスト２０ａに対し、予め用意されたパターンに基づいて露光する（Ｓ６）。これにより、フォトレジスト２０ａにおいて、露光された際に光が照射された部分がアルカリ性の現像液に溶ける状態となる。 Then, the photoresist 20a is exposed based on a previously prepared pattern (S6). Thereby, in the photoresist 20a, a portion irradiated with light when exposed is in a state of being dissolved in an alkaline developer.
　続いて、フォトレジスト２０ａにアルカリ性の現像液を与えて、図６に示されるように、フォトレジスト２０ａにおいて、光が照射された部分を除去する（Ｓ７）。これにより、絶縁層２４をパターン処理するためのマスクであるフォトレジスト２０が形成される。 Subsequently, an alkaline developer is applied to the photoresist 20a, and the portion irradiated with light is removed from the photoresist 20a as shown in FIG. 6 (S7). Thereby, a photoresist 20 which is a mask for patterning the insulating layer 24 is formed.
　その後、図７に示されるように、フォトレジスト２０をマスクとして、絶縁層２４ａをエッチングすることにより、絶縁層２４ａの一部分を除去して、その後にフォトレジスト２０を剥離する（Ｓ８）。これにより、絶縁層２４ａのうち、後工程でｎ型単結晶シリコン基板１８にｉ－ｐ積層部３１を接合させるための領域の上に位置する部分を除去して絶縁層２４ｂを形成する。ここで、絶縁層２４ａのエッチングには、例えば、ＨＦ水溶液等の酸性のエッチング液を用いる。 Then, as shown in FIG. 7, by using the photoresist 20 as a mask, the insulating layer 24a is etched to remove a part of the insulating layer 24a, and then the photoresist 20 is peeled off (S8). As a result, the insulating layer 24b is formed by removing a portion of the insulating layer 24a located on a region for bonding the ip stacked portion 31 to the n-type single crystal silicon substrate 18 in a later step. Here, for the etching of the insulating layer 24a, for example, an acidic etching solution such as an HF aqueous solution is used.
　次に、ｎ型単結晶シリコン基板１８の受光面上に、ｉ型非晶質シリコン層１６とｎ型非晶質シリコン層１４を形成する（Ｓ９）。ここで、ｉ型非晶質シリコン層１６、ｎ型非晶質シリコン層１４のそれぞれは、例えば、プラズマＣＶＤ法等により形成することができる。 Next, the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 are formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S9). Here, each of the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 can be formed by, for example, a plasma CVD method or the like.
　そして、図８に示されるように、ｎ型非晶質シリコン層１４上に反射防止層１２を形成する（Ｓ１０）。反射防止層１２は、例えば、スパッタリング法やＣＶＤ法等の薄膜形成法等により形成することができる。 Then, as shown in FIG. 8, the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S10). The antireflection layer 12 can be formed, for example, by a thin film forming method such as a sputtering method or a CVD method.
　続いて、図９に示されるように、Ｓ８においてパターンニングされた絶縁層２４ｂをマスクとして用い、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａをエッチングする（Ｓ１１）。具体的には、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａのうち、絶縁層２４ｂによって覆われている部分以外の部分を除去する。これにより、ｎ型単結晶シリコン基板１８の裏面のうち、上方に絶縁層２４ｂが位置していない部分を露出させて、ｉ型非晶質シリコン層２２とｎ型非晶質シリコン層２３を形成する。ここで、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａのエッチングは、例えば、水酸化ナトリウム（ＮａＯＨ）を含む水溶液等のアルカリ性のエッチング液を用いる。 Subsequently, as shown in FIG. 9, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched using the insulating layer 24b patterned in S8 as a mask (S11). Specifically, portions of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a other than the portion covered with the insulating layer 24b are removed. Thus, the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 are formed by exposing a portion of the back surface of the n-type single crystal silicon substrate 18 where the insulating layer 24b is not located above. To do. Here, for etching the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a, for example, an alkaline etching solution such as an aqueous solution containing sodium hydroxide (NaOH) is used.
　その後、図１０に示されるように、絶縁層２４ｂ、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３及び露出されたｎ型単結晶シリコン基板１８の裏面を覆うように、ｉ型非晶質シリコン層３２ａとｐ型非晶質シリコン層３３ａを形成する（Ｓ１２）。ｉ型非晶質シリコン層３２ａ及びｐ型非晶質シリコン層３３ａは、例えば、プラズマＣＶＤ法等により形成することができる。 Thereafter, as shown in FIG. 10, the insulating layer 24 b, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23 and the exposed back surface of the n-type single crystal silicon substrate 18 are covered with i A type amorphous silicon layer 32a and a p type amorphous silicon layer 33a are formed (S12). The i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a can be formed by, for example, a plasma CVD method or the like.
　次に、図１１に示されるように、ｉ型非晶質シリコン層３２ａ及びｐ型非晶質シリコン層３３ａのうち、絶縁層２４ｂの上に位置している部分の一部分をエッチングする（Ｓ１３）。これにより、ｉ型非晶質シリコン層３２及びｐ型非晶質シリコン層３３を形成する。ここで、ｉ型非晶質シリコン層３２ａとｐ型非晶質シリコン層３３ａのエッチングは、例えば、水酸化ナトリウム（ＮａＯＨ）を含む水溶液等のアルカリ性のエッチング液を用いる。 Next, as shown in FIG. 11, in the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a, a part of the portion located on the insulating layer 24b is etched (S13). . Thereby, the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are formed. Here, for etching the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a, for example, an alkaline etching solution such as an aqueous solution containing sodium hydroxide (NaOH) is used.
　そして、図１２に示されるように、絶縁層２４ｂをエッチングすることにより、絶縁層２４ｂの一部分をさらに除去する（Ｓ１４）。具体的には、ｉ型非晶質シリコン層３２及びｐ型非晶質シリコン層３３をマスクとして用い、絶縁層２４ｂの露出部分をエッチングにより除去することで絶縁層２４を形成する。ここで、絶縁層２４ｂのエッチングには、例えば、ＨＦ水溶液等の酸性のエッチング液を用いる。 Then, as shown in FIG. 12, the insulating layer 24b is etched to further remove a part of the insulating layer 24b (S14). Specifically, the insulating layer 24 is formed by removing the exposed portion of the insulating layer 24b by etching using the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 as a mask. Here, for the etching of the insulating layer 24b, for example, an acidic etching solution such as an HF aqueous solution is used.
　続いて、透明導電層２６ａ、金属層２７ａを形成する（Ｓ１５）。具体的には、プラズマＣＶＤ法やスパッタリング法等の薄膜形成法により形成する。 Subsequently, a transparent conductive layer 26a and a metal layer 27a are formed (S15). Specifically, it is formed by a thin film forming method such as a plasma CVD method or a sputtering method.
　その後、図１３に示されるように、透明導電層２６ａ及び金属層２７ａのうち、絶縁層２４の上に位置する部分を分断することにより、透明導電層２６，３６及び金属層２７，３７を形成する（Ｓ１６）。ここで、透明導電層２６ａ及び金属層２７ａは、例えば、リソグラフィー法等によって分断する。 Thereafter, as shown in FIG. 13, the transparent conductive layers 26 and 36 and the metal layers 27 and 37 are formed by dividing a portion of the transparent conductive layer 26 a and the metal layer 27 a located on the insulating layer 24. (S16). Here, the transparent conductive layer 26a and the metal layer 27a are divided by, for example, a lithography method.
　次に、図１４に示されるように、電解めっきにより、金属層２７の上に第１電極部２８と第２電極部２９を順次形成し、金属層３７の上に第１電極部３８と第２電極部３９を順次形成する（Ｓ１７）。これにより、ｎ側電極部２５とｐ側電極部３５とが形成がされる。 Next, as shown in FIG. 14, the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating, and the first electrode portion 38 and the second electrode portion 29 are formed on the metal layer 37. Two electrode portions 39 are sequentially formed (S17). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
　絶縁層２４ａを成膜した際に、成膜装置内の塵等の存在が原因で、絶縁層２４ａにピンホールが形成されることがある。このため、絶縁層２４ａを成膜した後に、水酸化カリウム水溶液（ＫＯＨ水溶液）等のアルカリ性の異方性エッチング液を用いてｎ型単結晶シリコン基板１８の受光面上にテクスチャ構造を形成する場合には、当該アルカリ性の異方性エッチング液が当該ピンホールを通って、ｉ型非晶質シリコン層２２ａ及びｎ型非晶質シリコン層２３ａに付着して損傷を与える可能性がある。しかし、上記光電変換素子１０の製造方法の第１実施例によれば、ｎ型単結晶シリコン基板１８の受光面上にテクスチャ構造を形成する際に、絶縁層２４ｂの略全面が耐アルカリ性に優れたフォトレジスト２０ａによって覆われている。これにより、仮に絶縁層２４ｂにピンホールが存在している場合であっても、当該ピンホールは絶縁層２４ｂによって塞がれているため、アルカリ性の異方性エッチング液が当該ピンホールを通って、ｉ型非晶質シリコン層２２ａ及びｎ型非晶質シリコン層２３ａに付着してしまうことを防止することができる。したがって、上記光電変換素子１０の製造方法の第１実施例によれば、光電変換素子１０の発電特性を向上させることができる。 When the insulating layer 24a is formed, pinholes may be formed in the insulating layer 24a due to the presence of dust or the like in the film forming apparatus. Therefore, after forming the insulating layer 24a, a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 using an alkaline anisotropic etching solution such as an aqueous potassium hydroxide solution (KOH aqueous solution). There is a possibility that the alkaline anisotropic etching solution passes through the pinhole and adheres to the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a to cause damage. However, according to the first embodiment of the method for manufacturing the photoelectric conversion element 10, when the texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18, the substantially entire surface of the insulating layer 24b is excellent in alkali resistance. Covered with a photoresist 20a. As a result, even if a pinhole exists in the insulating layer 24b, since the pinhole is blocked by the insulating layer 24b, the alkaline anisotropic etching solution passes through the pinhole. Thus, it is possible to prevent adhesion to the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a. Therefore, according to the first embodiment of the method for manufacturing the photoelectric conversion element 10, the power generation characteristics of the photoelectric conversion element 10 can be improved.
　ｎ型単結晶シリコン基板１８の受光面のみにテクスチャ構造を形成し、裏面にテクスチャ構造を形成しない場合は、一旦、裏面を耐アルカリ性に優れた犠牲層で覆って受光面のみにテクスチャ構造を形成した後で、当該犠牲層を剥離する工程が別途必要となる。しかし、上記光電変換素子１０の製造方法の第１実施例によれば、耐アルカリ性に優れており、かつ、絶縁層２４ａのパターンニングを行う際に用いられるフォトレジスト２０ａが形成された後で、ｎ型単結晶シリコン基板１８の受光面にテクスチャ構造を形成しているため、上記のように裏面側に特別な犠牲層を設ける等の別工程が必要ない。このように、絶縁層２４ａをパターンニングするためのフォトレジスト２０ａに、上記犠牲層の役割も担わせているため、光電変換素子１０の製造の工程数を削減することができる。 When the texture structure is formed only on the light receiving surface of the n-type single crystal silicon substrate 18 and the texture structure is not formed on the back surface, the texture structure is formed only on the light receiving surface by temporarily covering the back surface with a sacrificial layer having excellent alkali resistance. After that, a separate step of peeling the sacrificial layer is required. However, according to the first embodiment of the method for manufacturing the photoelectric conversion element 10, the alkali resistance is excellent, and after the photoresist 20a used for patterning the insulating layer 24a is formed, Since the texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18, a separate process such as providing a special sacrificial layer on the back surface side as described above is not necessary. Thus, since the photoresist 20a for patterning the insulating layer 24a also serves as the sacrificial layer, the number of steps for manufacturing the photoelectric conversion element 10 can be reduced.
　次に、光電変換素子１０の製造方法の第２実施例を説明する。図１５は、光電変換素子１０の製造方法の第２実施例の手順を示すフローチャートである。なお、光電変換素子１０の製造方法は、各工程において示す製造方法に限定されない。各工程において、例えば、スパッタリング法、プラズマＣＶＤ法、スクリーン印刷法或いはめっき法等を適宜用いることができる。 Next, a second embodiment of the method for manufacturing the photoelectric conversion element 10 will be described. FIG. 15 is a flowchart showing the procedure of the second embodiment of the method for manufacturing the photoelectric conversion element 10. In addition, the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
　光電変換素子１０の製造方法の第２実施例と、上記光電変換素子１０の製造方法の第１実施例の各工程は、Ｓ１～Ｓ４及びＳ８～Ｓ１７工程が同じであり、Ｓ４～Ｓ８の間の工程のみが相違するため、その相違点を中心に説明する。 The steps of the second embodiment of the method for manufacturing the photoelectric conversion element 10 and the first embodiment of the method for manufacturing the photoelectric conversion element 10 are the same in steps S1 to S4 and S8 to S17, and between S4 to S8. Since only the process is different, the difference will be mainly described.
　最初に、光電変換素子１０の製造方法の第１実施例と同じように、Ｓ１～Ｓ４を実施する。 First, S1 to S4 are performed as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
　そして、フォトレジスト２０ａに対して予め用意されたパターンに基づいて露光する（Ｓ５ａ）。また、フォトレジスト２０ａにおいて、露光された際に光が照射された部分がアルカリ性の現像液に溶ける状態となる。 Then, the photoresist 20a is exposed based on a pattern prepared in advance (S5a). In addition, in the photoresist 20a, a portion irradiated with light when exposed is in a state of being dissolved in an alkaline developer.
　続いて、フォトレジスト２０ａにアルカリ性の現像液を与えて、フォトレジスト２０ａにおいて、光が照射された部分を除去する（Ｓ６ａ）。これにより、絶縁層２４をパターン処理するためのマスクであるフォトレジスト２０が形成される。 Subsequently, an alkaline developer is applied to the photoresist 20a to remove the portion irradiated with light in the photoresist 20a (S6a). Thereby, a photoresist 20 which is a mask for patterning the insulating layer 24 is formed.
　その後、ｎ型単結晶シリコン基板１８の受光面上にテクスチャ構造を形成する（Ｓ７ａ）。ここで、テクスチャ構造の形成には、水酸化カリウム水溶液（ＫＯＨ水溶液）等のアルカリ性の異方性エッチング液を用いることで、ｎ型単結晶シリコン基板１８の受光面上にピラミッド状の凹凸形状を形成することができる。 Thereafter, a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S7a). Here, for the formation of the texture structure, a pyramidal uneven shape is formed on the light-receiving surface of the n-type single crystal silicon substrate 18 by using an alkaline anisotropic etching solution such as a potassium hydroxide aqueous solution (KOH aqueous solution). Can be formed.
　次に、光電変換素子１０の製造方法の第１実施例と同じように、Ｓ８～Ｓ１７を実施する。 Next, S8 to S17 are performed as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
　光電変換素子１０の製造方法の第２実施例では、ｎ型単結晶シリコン基板１８の受光面上にテクスチャ構造を形成する前に、フォトレジスト２０ａの一部分を除去している。このため、フォトレジスト２０によって覆われている部分の下方に位置するｉ型非晶質シリコン層２２ａ及びｐ型非晶質シリコン層２３ａの損傷を防止することはできるが、この取り除かれた部分の下方に位置するｉ型非晶質シリコン層２２ａ及びｐ型非晶質シリコン層２３ａは損傷する可能性がある。しかし、当該損傷する可能性のある部分は、後の工程であるＳ１１においてエッチングされる領域である。つまり、当該損傷する可能性のある部分は、結果的に取り除かれる部分であるため、当該損傷は問題とならない。したがって、光電変換素子１０の製造方法の第２実施例においても、光電変換素子１０の製造方法の第１実施例と同様に、光電変換素子１０の発電特性を向上させることができる。 In the second embodiment of the method for manufacturing the photoelectric conversion element 10, a part of the photoresist 20a is removed before the texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18. Therefore, it is possible to prevent damage to the i-type amorphous silicon layer 22a and the p-type amorphous silicon layer 23a located below the portion covered with the photoresist 20, but the removed portion The i-type amorphous silicon layer 22a and the p-type amorphous silicon layer 23a located below may be damaged. However, the portion that may be damaged is a region that is etched in the subsequent step S11. That is, since the portion that can be damaged is a portion that is eventually removed, the damage is not a problem. Therefore, also in the second embodiment of the method for manufacturing the photoelectric conversion element 10, the power generation characteristics of the photoelectric conversion element 10 can be improved as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
　次に、光電変換素子１０の製造方法の第３実施例を説明する。図１６は、光電変換素子１０の製造方法の第３実施例の手順を示すフローチャートである。なお、光電変換素子１０の製造方法は、各工程において示す製造方法に限定されない。各工程において、例えば、スパッタリング法、プラズマＣＶＤ法、スクリーン印刷法或いはめっき法等を適宜用いることができる。 Next, a third embodiment of the method for manufacturing the photoelectric conversion element 10 will be described. FIG. 16 is a flowchart showing the procedure of the third embodiment of the method for manufacturing the photoelectric conversion element 10. In addition, the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
　光電変換素子１０の製造方法の第３実施例と、光電変換素子１０の製造方法の第１実施例の各工程は、Ｓ１～Ｓ４及びＳ８～Ｓ１７工程が同じであり、Ｓ４～Ｓ８の間の工程のみが相違するため、その相違点を中心に説明する。 The steps of the third embodiment of the method for manufacturing the photoelectric conversion element 10 and the first embodiment of the method for manufacturing the photoelectric conversion element 10 are the same in steps S1 to S4 and S8 to S17, and are between S4 to S8. Since only the process is different, the difference will be mainly described.
　最初に、光電変換素子１０の製造方法の第１実施例と同じように、Ｓ１～Ｓ４を実施する。 First, S1 to S4 are performed as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
　そして、フォトレジスト２０ａに対して予め用意されたパターンに基づいて露光する（Ｓ５ｂ）。また、フォトレジスト２０ａにおいて、露光された際に光が照射された部分がアルカリ性の現像液に溶ける状態となる。 Then, the photoresist 20a is exposed based on a pattern prepared in advance (S5b). In addition, in the photoresist 20a, a portion irradiated with light when exposed is in a state of being dissolved in an alkaline developer.
　その後、水酸化カリウム水溶液（ＫＯＨ水溶液）等のアルカリ性の異方性エッチング液を用いてｎ型単結晶シリコン基板１８の受光面上にテクスチャ構造を形成するとともに、同じ異方性エッチング液を用いて、フォトレジスト２０ａを現像する（Ｓ６ｂ）。これにより、ｎ型単結晶シリコン基板１８の受光面上にピラミッド状の凹凸形状を形成することができるとともに、絶縁層２４をパターン処理するためのマスクであるフォトレジスト２０が形成される。 Thereafter, a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 using an alkaline anisotropic etching solution such as an aqueous potassium hydroxide solution (KOH aqueous solution), and the same anisotropic etching solution is used. The photoresist 20a is developed (S6b). As a result, a pyramidal concavo-convex shape can be formed on the light receiving surface of the n-type single crystal silicon substrate 18, and a photoresist 20 which is a mask for patterning the insulating layer 24 is formed.
　続いて、光電変換素子１０の製造方法の第１実施例と同じように、Ｓ８～Ｓ１７を実施する。 Subsequently, S8 to S17 are performed in the same manner as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
　光電変換素子１０の製造方法の第３実施例では、光電変換素子１０の製造方法の第２実施例と同様に、フォトレジスト２０において、アルカリ性の異方性エッチング液によって取り除かれた部分の下方に位置するｉ型非晶質シリコン層２２ａ及びｐ型非晶質シリコン層２３ａを損傷する可能性があるが、これらは結果的に取り除かれる部分であるため、当該損傷は問題とならない。したがって、光電変換素子１０の製造方法の第３実施例においても、光電変換素子１０の製造方法の第１実施例と同様に光電変換素子１０の発電特性を向上させることができる。 In the third embodiment of the method for manufacturing the photoelectric conversion element 10, as in the second embodiment of the method for manufacturing the photoelectric conversion element 10, below the portion of the photoresist 20 that has been removed by the alkaline anisotropic etching solution. Although there is a possibility that the i-type amorphous silicon layer 22a and the p-type amorphous silicon layer 23a which are located may be damaged, since these are parts that are removed as a result, the damage is not a problem. Therefore, also in the third embodiment of the method for manufacturing the photoelectric conversion element 10, the power generation characteristics of the photoelectric conversion element 10 can be improved as in the first embodiment of the method for manufacturing the photoelectric conversion element 10.
　さらに、光電変換素子１０の製造方法の第３実施例では、同じアルカリ性の異方性エッチング液を用いてフォトレジスト２０ａの一部分を除去するとともに、ｎ型単結晶シリコン基板１８の受光面上にテクスチャ構造を形成している。したがって、光電変換素子１０の製造方法の工程数を削減することができる。 Furthermore, in the third embodiment of the manufacturing method of the photoelectric conversion element 10, a part of the photoresist 20a is removed using the same alkaline anisotropic etching solution, and a texture is formed on the light receiving surface of the n-type single crystal silicon substrate 18. Forming a structure. Therefore, the number of steps of the method for manufacturing the photoelectric conversion element 10 can be reduced.
　１０　光電変換素子、１２　反射防止層、１４　ｎ型非晶質シリコン層、１６　ｉ型非晶質シリコン層、１８　ｎ型単結晶シリコン基板、２０，２０ａ　フォトレジスト、２１　ｉ－ｎ積層部、２２，２２ａ　ｉ型非晶質シリコン層、２３，２３ａ　ｎ型非晶質シリコン層、２４，２４ａ，２４ｂ　絶縁層、２５　ｎ側電極部、２６，２６ａ，３６　透明導電層、２７，２７ａ，３７　金属層、２８，３８　第１電極部、２９，３９　第２電極部、３１　ｉ－ｐ積層部、３２，３２ａ　ｉ型非晶質シリコン層、３３，３３ａ　ｐ型非晶質シリコン層、３５　ｐ側電極部。 10 photoelectric conversion element, 12 antireflection layer, 14 n-type amorphous silicon layer, 16 i-type amorphous silicon layer, 18 n-type single crystal silicon substrate, 20, 20a photoresist, 21 in laminated layer, 22 , 22a i-type amorphous silicon layer, 23, 23a n-type amorphous silicon layer, 24, 24a, 24b insulating layer, 25 n-side electrode part, 26, 26a, 36 transparent conductive layer, 27, 27a, 37 metal Layer, 28, 38 1st electrode part, 29, 39 2nd electrode part, 31 ip stacked part, 32, 32a i-type amorphous silicon layer, 33, 33a p-type amorphous silicon layer, 35 p side Electrode part.

Claims (4)

  1. 　半導体基板の裏面上に非晶質系半導体層を形成し、
    　前記非晶質系半導体層上に絶縁層を形成し、
    　前記絶縁層上にフォトレジスト層を形成し、
    　前記絶縁層上に前記フォトレジスト層が形成されている状態で前記半導体基板の前記裏面の反対側の受光面をエッチング加工する光電変換素子の製造方法。     Forming an amorphous semiconductor layer on the back surface of the semiconductor substrate;
    Forming an insulating layer on the amorphous semiconductor layer;
    Forming a photoresist layer on the insulating layer;
    A method for manufacturing a photoelectric conversion element, comprising etching a light receiving surface opposite to the back surface of the semiconductor substrate in a state where the photoresist layer is formed on the insulating layer.
  2. 　請求項１に記載の光電変換素子の製造方法において、
    　前記エッチング加工を終えた後で、前記フォトレジスト層を現像し、前記絶縁層をパターニングする光電変換素子の製造方法。     In the manufacturing method of the photoelectric conversion element of Claim 1,
    The manufacturing method of the photoelectric conversion element which develops the said photoresist layer and patterns the said insulating layer after finishing the said etching process.
  3. 　請求項１または請求項２に記載の光電変換素子の製造方法において、
    　前記結晶系半導体基板は、ｎ型であり、
    　前記非晶質系半導体層部は、
    　前記結晶系半導体基板の裏面上に形成されるｉ型の非晶質系半導体層と、
    　前記ｉ型の非晶質系半導体層上に形成されるｎ型の非晶質系半導体層と、
    　を有する光電変換素子の製造方法。     In the manufacturing method of the photoelectric conversion element of Claim 1 or Claim 2,
    The crystalline semiconductor substrate is n-type,
    The amorphous semiconductor layer portion is
    An i-type amorphous semiconductor layer formed on the back surface of the crystalline semiconductor substrate;
    An n-type amorphous semiconductor layer formed on the i-type amorphous semiconductor layer;
    The manufacturing method of the photoelectric conversion element which has.
  4. 　請求項１から請求項３のいずれか１に記載の光電変換素子の製造方法において、
    　前記絶縁層は、窒化アルミニウム、窒化ケイ素及び酸化ケイ素のいずれか１つを含む光電変換素子の製造方法。     In the manufacturing method of the photoelectric conversion element of any one of Claims 1-3,
    The method for manufacturing a photoelectric conversion element, wherein the insulating layer includes any one of aluminum nitride, silicon nitride, and silicon oxide.
PCT/JP2012/053851 2011-03-25 2012-02-17 Method for producing photoelectric conversion element WO2012132616A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011068126 2011-03-25
JP2011-068126 2011-03-25

Publications (1)

Publication Number Publication Date
WO2012132616A1 true WO2012132616A1 (en) 2012-10-04

Family

ID=46930378

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/053851 WO2012132616A1 (en) 2011-03-25 2012-02-17 Method for producing photoelectric conversion element

Country Status (1)

Country Link
WO (1) WO2012132616A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016147565A1 (en) * 2015-03-16 2016-09-22 パナソニックＩｐマネジメント株式会社 Solar battery cell

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010504636A (en) * 2006-09-26 2010-02-12 コミサリア、ア、レネルジ、アトミク Back heterojunction solar cell manufacturing method
WO2010113750A1 (en) * 2009-03-30 2010-10-07 三洋電機株式会社 Solar cell

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010504636A (en) * 2006-09-26 2010-02-12 コミサリア、ア、レネルジ、アトミク Back heterojunction solar cell manufacturing method
WO2010113750A1 (en) * 2009-03-30 2010-10-07 三洋電機株式会社 Solar cell

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016147565A1 (en) * 2015-03-16 2016-09-22 パナソニックＩｐマネジメント株式会社 Solar battery cell
JPWO2016147565A1 (en) * 2015-03-16 2017-12-07 パナソニックＩｐマネジメント株式会社 Solar cells

Similar Documents

Publication Publication Date Title
JP5891382B2 (en) Method for manufacturing photoelectric conversion element
JP5705968B2 (en) Photoelectric conversion device and manufacturing method thereof
KR101863294B1 (en) Solar cell and method for fabricating the same
US9006564B2 (en) Method of manufacturing solar cell and solar cell
JP6817764B2 (en) Solar cell and manufacturing method of solar cell
WO2012132655A1 (en) Back-junction photoelectric conversion element and method for manufacturing back-junction photoelectric conversion element
JP2013219065A (en) Solar cell and method for manufacturing the same
JP6677801B2 (en) Crystalline silicon-based solar cell, method of manufacturing the same, and solar cell module
JP2013120863A (en) Method for manufacturing solar cell
JPWO2010064549A1 (en) Method for manufacturing thin film photoelectric conversion device
US20140024168A1 (en) Method for producing photoelectric conversion device
JP2013131586A (en) Manufacturing method for back electrode type solar cell
TWI587540B (en) Method of performing plating process on transparent conductive film for solar cells
JP5820989B2 (en) Method for manufacturing photoelectric conversion element
JP2014072209A (en) Photoelectric conversion element and photoelectric conversion element manufacturing method
WO2012132616A1 (en) Method for producing photoelectric conversion element
EP3576160A1 (en) Solar cell and preparation method thereof
WO2012132613A1 (en) Method for producing photoelectric conversion element
JP2013168605A (en) Manufacturing method of solar cell
JP2014183073A (en) Photoelectric conversion element and method of manufacturing photoelectric conversion element
JP7146786B2 (en) Solar cell manufacturing method, solar cell and solar cell module
WO2020149128A1 (en) Method for producing solar cells
WO2017203751A1 (en) Solar cell and method for manufacturing same, and solar cell panel
WO2012132064A1 (en) Photovoltaic element
JPWO2015145886A1 (en) Electrode pattern forming method and solar cell manufacturing method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12763538

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12763538

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP