WO2012132613A1 - Procédé de fabrication d'un élément de conversion photoélectrique - Google Patents

Procédé de fabrication d'un élément de conversion photoélectrique Download PDF

Info

Publication number
WO2012132613A1
WO2012132613A1 PCT/JP2012/053808 JP2012053808W WO2012132613A1 WO 2012132613 A1 WO2012132613 A1 WO 2012132613A1 JP 2012053808 W JP2012053808 W JP 2012053808W WO 2012132613 A1 WO2012132613 A1 WO 2012132613A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
photoelectric conversion
conversion element
amorphous silicon
semiconductor layer
Prior art date
Application number
PCT/JP2012/053808
Other languages
English (en)
Japanese (ja)
Inventor
大樹 橋口
三島　孝博
正人 重松
良 後藤
豊 桐畑
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Publication of WO2012132613A1 publication Critical patent/WO2012132613A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a method for manufacturing a photoelectric conversion element.
  • Patent Document 1 a light-receiving surface and a semiconductor substrate having a back surface opposite to the light-receiving surface, a first semiconductor layer formed on the back surface, formed on the back surface, and disposed on both sides of the first semiconductor layer.
  • a pair of second semiconductor layers, a first insulating layer formed from one second semiconductor layer to the first semiconductor layer of the pair of second semiconductor layers, and a pair of second semiconductor layers A second insulating layer formed over the other second semiconductor layer to the first semiconductor layer, a transparent electrode layer covering the first semiconductor layer and the second semiconductor layer, and a collection formed on the transparent electrode layer
  • a photoelectric conversion element including an electrode layer is disclosed.
  • a method for manufacturing a photoelectric conversion element in which a plurality of stacked portions including a semiconductor layer are stacked on a semiconductor substrate has been devised. Then, after each laminated portion is formed, an etching process for each laminated portion is performed using a mask or a resist for patterning each laminated portion.
  • an etching process for each laminated portion is performed using a mask or a resist for patterning each laminated portion.
  • alignment is performed using alignment marks provided in each stacked portion, but depending on the position where each alignment mark is formed, There is a possibility of adversely affecting the power generation characteristics of the photoelectric conversion element.
  • a first alignment mark is formed on a crystalline semiconductor substrate, and a first amorphous semiconductor layer is formed on the crystalline semiconductor substrate including the first alignment mark.
  • a first pattern forming unit having a first positioning unit for positioning with respect to the first alignment mark is prepared, and the first pattern forming unit is installed on the first amorphous semiconductor layer by performing the positioning.
  • the second alignment mark is formed on the first amorphous semiconductor layer using the first positioning portion, and the second amorphous semiconductor layer is formed on the crystalline semiconductor substrate including the second alignment mark.
  • a second pattern forming portion provided at a position not overlapping the second alignment mark and having a second positioning portion for positioning with respect to the first alignment mark or the second alignment mark. Preparation and positioning are performed to place a second pattern forming portion on the second amorphous semiconductor layer, and a third alignment mark is formed on the second amorphous semiconductor layer using the second positioning portion.
  • the power generation characteristics of the photoelectric conversion element can be improved.
  • it is a back surface side top view of a photoelectric conversion element.
  • it is sectional drawing of a photoelectric conversion element.
  • it is a flowchart which shows the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a back surface side top view which shows a mode that the 1st alignment mark is formed in the n-type single crystal silicon substrate.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a top view of a mask.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a figure showing positional relation of the 1st alignment mark and the 2nd alignment mark.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a top view of a mask.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a figure showing the positional relationship of the 1st alignment mark, the 2nd alignment mark, and the 3rd alignment mark.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • FIG. 1 is a plan view of the back side of the photoelectric conversion element 10.
  • FIG. 2 is a partial cross-sectional view taken along the line XX of FIG. 1 and shows a cross-sectional view of the photoelectric conversion element 10.
  • the photoelectric conversion element 10 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an i-n stacked portion 21, and i.
  • an arrow A shown in FIG. 2 indicates a direction in which light such as sunlight enters the photoelectric conversion element 10.
  • the “light receiving surface” means a surface on which light such as sunlight is mainly incident.
  • the “back surface” means a surface opposite to the light receiving surface.
  • the n-type single crystal silicon substrate 18 is a power generation layer that receives carriers incident from the light receiving surface and generates carriers.
  • the n-type single crystal silicon substrate 18 is used.
  • the present invention is not limited to this, and an n-type or p-type conductive crystal semiconductor substrate can be used.
  • a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium arsenide substrate (GaAs), an indium phosphorus substrate (InP), or the like can be used.
  • the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 are passivation layers formed on the light-receiving surface of the n-type single crystal silicon substrate 18.
  • the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 constitute an amorphous semiconductor layer formed on the light receiving surface.
  • the i-type amorphous silicon layer 16 is a layer made of an intrinsic amorphous semiconductor film.
  • the n-type amorphous silicon layer 14 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 14 preferably has an n-type dopant concentration of 1 ⁇ 10 21 / cm 3 or more.
  • the amorphous silicon layer includes a microcrystalline semiconductor film.
  • a microcrystalline semiconductor film is a film in which crystal grains are precipitated in an amorphous semiconductor.
  • the average grain size of the crystal grains is not limited to this, but is estimated to be about 1 nm to 80 nm.
  • the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 and reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10.
  • the antireflection layer 12 also functions as a protective layer that protects the surface of the n-type amorphous silicon layer 14.
  • the antireflection layer 12 is made of a transparent material and has a refractive index that reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10 in relation to the refractive index of the layer covered by the antireflection layer 12. And a film thickness is preferred.
  • the antireflection layer 12 includes, for example, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, and the like.
  • the i-n stacked unit 21 is formed on the back surface of the n-type single crystal silicon substrate 18 and includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23. It is preferable that the i-n stacked unit 21 be arranged so that a larger amount of current can be collected from the surface of the photoelectric conversion element 10 in the n-side electrode unit 25 described later.
  • the i-n stacked portion 21 preferably has a comb shape in which a plurality of finger portions extend in parallel.
  • the i-type amorphous silicon layer 22 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the n-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22.
  • the i-type amorphous silicon layer 22 is a layer made of an intrinsic amorphous semiconductor film.
  • the n-type amorphous silicon layer 23 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 23 preferably has an n-type dopant concentration of 1 ⁇ 10 21 / cm 3 or more.
  • the insulating layer 24 is formed to electrically insulate the i-n laminated portion 21 and the ip laminated portion 31.
  • the insulating layer 24 also functions as a protective layer formed on the n-type amorphous silicon layer 23.
  • the insulating layer 24 may be any material having electrical insulating properties, but preferably includes, for example, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, and the like.
  • the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23, and the insulating layer 24 constitute a first amorphous semiconductor layer formed on the back surface.
  • the n-side electrode portion 25 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10.
  • the n-side electrode unit 25 includes a transparent conductive layer 26, a metal layer 27, a first electrode unit 28, and a second electrode unit 29.
  • the transparent conductive layer 26 is formed on the n-type amorphous silicon layer 23.
  • the transparent conductive layer 26 is made of a metal oxide such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), titanium oxide (TiO 2 ), and indium tin oxide (ITO). It is configured to include at least one.
  • the transparent conductive layer 26 is described as being formed using indium tin oxide (ITO).
  • the metal layer 27 is formed on the transparent conductive layer 26.
  • the metal layer 27 is a seed layer including a metal such as copper (Cu) or an alloy, for example.
  • the “seed layer” refers to a layer that is a starting point for plating growth.
  • the first electrode portion 28 is an electrode formed on the metal layer 27 by plating growth.
  • the first electrode unit 28 includes, for example, copper (Cu).
  • the second electrode part 29 is an electrode formed on the first electrode part 28 by plating growth.
  • the second electrode unit 29 includes tin (Sn).
  • the i-p stacked portions 31 are formed on the back surface of the n-type single crystal silicon substrate 18 so as to be alternately arranged with the i-n stacked portions 21.
  • the ip laminated portion 31 includes an i-type amorphous silicon layer 32 and a p-type amorphous silicon layer 33, and more in the plane of the photoelectric conversion element 10 in the p-side electrode portion 35 described later. It is preferable to arrange so that the current can be collected.
  • the ip laminated portion 31 is preferably, for example, in a comb-teeth shape in which a plurality of finger portions extend in parallel.
  • the i-type amorphous silicon layer 32 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the p-type amorphous silicon layer 33 is formed on the i-type amorphous silicon layer 32.
  • the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 constitute a part of the second amorphous semiconductor layer formed on the back surface.
  • the i-type amorphous silicon layer 32 is a layer made of an intrinsic amorphous semiconductor film.
  • the p-type amorphous silicon layer 33 is a layer made of an amorphous semiconductor film containing a p-type conductive dopant.
  • the p-type amorphous silicon layer 33 preferably has a p-type dopant concentration of 1 ⁇ 10 21 / cm 3 or more.
  • the p-side electrode portion 35 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10.
  • the p-side electrode part 35 includes a transparent conductive layer 36, a metal layer 37, a first electrode part 38, and a second electrode part 39.
  • the transparent conductive layer 36 is formed on the p-type amorphous silicon layer 33.
  • the material and the like of the transparent conductive layer 36 are the same as those of the transparent conductive layer 26, detailed description thereof is omitted.
  • the metal layer 37 is formed on the transparent conductive layer 36.
  • the material and the like of the metal layer 37 are the same as those of the metal layer 27, detailed description thereof is omitted.
  • the first electrode portion 38 is formed on the metal layer 37 by plating growth.
  • the material and the like of the first electrode portion 38 are the same as those of the first electrode portion 28, detailed description thereof is omitted.
  • the second electrode part 39 is formed on the first electrode part 38 by plating growth.
  • the material and the like of the second electrode portion 39 are the same as those of the second electrode portion 29, detailed description thereof is omitted.
  • FIG. 3 is a flowchart showing a procedure of a method for manufacturing the photoelectric conversion element 10.
  • the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
  • an n-type single crystal silicon substrate 18 is prepared. As shown in FIG. 4 which is a plan view of the back surface side of the n-type single crystal silicon substrate 18, four corners are formed on the back surface of the n-type single crystal silicon substrate 18, respectively. A cross mark groove is formed (S1). The cross marks are formed by the laser marking device as the first alignment marks 41a to 41d. The first alignment marks 41a and 41b formed at one end of the n-type single crystal silicon substrate 18 and the first alignment marks 41c and 41d formed at the other end of the n-type single crystal silicon substrate 18. As shown in FIG. 4, it is formed at an asymmetrical position about the line BB.
  • the light receiving surface and the back surface of the n-type single crystal silicon substrate 18 are cleaned (S2).
  • the n-type single crystal silicon substrate 18 can be cleaned using, for example, an HF aqueous solution.
  • a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S3).
  • a pyramidal uneven shape is formed on the light-receiving surface of the n-type single crystal silicon substrate 18 by using an alkaline anisotropic etching solution such as a potassium hydroxide aqueous solution (KOH aqueous solution). Can be formed.
  • KOH aqueous solution potassium hydroxide aqueous solution
  • an i-type amorphous silicon layer 16 and an n-type amorphous silicon layer 14 are formed on the light-receiving surface of the n-type single crystal silicon substrate 18, and on the back surface of the n-type single crystal silicon substrate 18, An i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a are formed (S4).
  • each of the i-type amorphous silicon layer 16, the n-type amorphous silicon layer 14, the i-type amorphous silicon layer 22a, and the n-type amorphous silicon layer 23a is formed by, for example, a plasma CVD method or the like. can do.
  • the insulating layer 24a is formed on the n-type amorphous silicon layer 23a, and the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S5).
  • the insulating layer 24a and the antireflection layer 12 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
  • a cross-sectional laminated structure as shown in FIG. 5 is obtained.
  • an i-type amorphous silicon layer 22a, an n-type amorphous silicon layer 23a, and an insulating layer 24a are formed on the back surface of the n-type single crystal silicon substrate 18. These layers are, for example, 0 A thin film of about 5 nm to 50 nm. Therefore, even when the film is covered with such a thin film, the first alignment marks 41a to 41d can be visually recognized from above when performing alignment.
  • the mask 45 shown in FIG. 6 is prepared, the positioning portions 47a to 47d and the first alignment marks 41a to 41d are aligned, and the mask 45 is set (S6).
  • the mask 45 includes a pattern portion 46 that is an opening region for forming a predetermined pattern in the i-type amorphous silicon layer 22a, the n-type amorphous silicon layer 23a, and the insulating layer 24a, and a first alignment mark.
  • This is a pattern forming member including positioning portions 47a to 47d which are opening regions for positioning with respect to 41a to 41d.
  • the positioning portions 47a to 47d are formed at positions that do not overlap the first alignment marks 41a to 41d, respectively, when alignment is performed with respect to the first alignment marks 41a to 41d.
  • positioning portions 47a to 47d are regions located diagonally among regions divided by cross marks of first alignment marks 41a to 41d formed on the back surface of n-type single crystal silicon substrate 18.
  • a rectangular pattern is formed.
  • the mask 45 is arranged so that the rectangular patterns of the positioning portions 47a to 47d are located as far apart as possible from the cross marks of the first alignment marks 41a to 41d.
  • an etching paste is applied by a screen printing method, and the insulating layer 24a, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched, whereby the insulating layer 24a, the i-type amorphous silicon layer are etched.
  • Part of 22a and n-type amorphous silicon layer 23a is removed (S7). That is, of the insulating layer 24a, the i-type amorphous silicon layer 22a, and the n-type amorphous silicon layer 23a, a region for forming the ip stacked portion 31 on the n-type single crystal silicon substrate 18 in a later step. Remove the top part.
  • the insulating layer 24a, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are patterned, and as shown in FIG. 7, the insulating layer 24b, the i-type amorphous silicon layer 22, A cross-sectional laminated structure in which the n-type amorphous silicon layer 23 is formed is obtained.
  • FIG. 8 a diagram corresponding to an enlarged view of a region indicated by a dotted line C in the plan view on the back surface side of FIG. 4
  • the second alignment mark 42a is applied to the etching paste applied through the positioning portion 47a.
  • the second alignment mark 42a is formed at a position so as not to overlap the first alignment mark 41a.
  • the etching paste applied through the positioning portions 47b to 47d forms the second alignment marks 42b to 42d.
  • the second alignment marks 42b to 42d are also formed at positions that do not overlap with the first alignment marks 41b to 41d, respectively.
  • the insulating layer 24 b, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23 and the exposed back surface of the n-type single crystal silicon substrate 18 are covered.
  • An i-type amorphous silicon layer 32a and a p-type amorphous silicon layer 33a are formed (S8).
  • the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a can be formed by, for example, a plasma CVD method or the like.
  • the mask 48 shown in FIG. 10 is prepared, the positioning portions 50a to 50d and the first alignment marks 41a to 41d or the second alignment marks 42a to 42d are aligned, and the mask 48 is set ( S9).
  • the mask 48 includes a pattern portion 49 that is an opening region for forming a predetermined pattern in the i-type amorphous silicon layer 32a, the p-type amorphous silicon layer 33a, and the insulating layer 24b, and a first alignment mark.
  • This is a pattern forming member including positioning portions 50a to 50d which are opening regions for positioning with respect to 41a to 41d or the second alignment marks 42a to 42d.
  • the positioning portions 50a to 50d perform the first alignment marks 41a to 41d and the second alignment marks 42a to 42d when aligning the first alignment marks 41a to 41d or the second alignment marks 42a to 42d. It is preferable that it is formed at a position where it does not overlap with the other.
  • positioning portions 50a to 50d are formed of regions divided by cross marks of first alignment marks 41a to 41d formed on the back surface of n-type single crystal silicon substrate 18. A rectangular pattern is formed in a region located diagonally.
  • the mask 48 is arranged so that the rectangular patterns of the positioning portions 50a to 50d are located as far apart as possible from the cross marks of the first alignment marks 41a to 41d.
  • an etching paste is applied by a screen printing method, and the insulating layer 24b, the i-type amorphous silicon layer 32a, and the p-type amorphous silicon layer 33a are etched to thereby form the insulating layer 24b, the i-type amorphous silicon.
  • a part of the layer 32a and the p-type amorphous silicon layer 33a is removed (S10).
  • the insulating layer 24b, the i-type amorphous silicon layer 32a, and the p-type amorphous silicon layer 33a are patterned, and as shown in FIG.
  • the third alignment mark 43a is applied to the etching paste applied through the positioning portion 50a.
  • the third alignment mark 43a is formed at a position so as not to overlap the first alignment mark 41a and the second alignment mark 42a.
  • the etching paste applied through the positioning portions 50b to 50d forms the third alignment marks 43b to 43d.
  • the third alignment marks 43b to 43d are also formed at positions that do not overlap the first alignment marks 41b to 41d and the second alignment marks 42b to 42d, respectively.
  • the transparent conductive layer 26a and the metal layer 27a are formed (S11). Specifically, it is formed by a thin film forming method such as a plasma CVD method or a sputtering method.
  • the transparent conductive layers 26 and 36 and the metal layers 27 and 37 are separated by dividing a portion of the transparent conductive layer 26 a and the metal layer 27 a located on the insulating layer 24.
  • Form (S12) the transparent conductive layer 26a and the metal layer 27a are divided by, for example, a lithography method.
  • the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating, and the first electrode portion 38 and the second electrode portion 29 are formed on the metal layer 37.
  • the electrode part 39 is formed (S13). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
  • alignment is performed on the first alignment marks 41a to 41d using masks 45 and 48, and patterning processing is performed by applying an etching paste.
  • the second alignment marks 42a to 42d formed on the first and third alignment marks 43a to 43d formed on the second amorphous semiconductor portion are formed at the positions where they overlap each other, a hole penetrating in the stacking direction is formed. Is done. Therefore, the n-type single crystal silicon substrate 18 is exposed in the region where the alignment marks are formed. Therefore, since the passivation layer does not exist in the exposed portion of the n-type single crystal silicon substrate 18, carrier recombination may occur.
  • the second alignment marks 42a to 42d and the third alignment marks 43a to 43d are formed at positions that do not overlap.
  • the n-type single crystal silicon substrate 18 is covered with either the i-type amorphous silicon layer 22 or the i-type amorphous silicon layer 32, the i-type amorphous silicon layer 22 or the i-type amorphous silicon layer 22 is covered.
  • the amorphous silicon layer 32 is passivated. Therefore, recombination of carriers generated in the n-type single crystal silicon substrate 18 is suppressed, and the power generation characteristics of the photoelectric conversion element 10 can be improved.
  • the first alignment marks 41a to 41d are formed in the shape of a cross mark, and therefore, the position where the cross mark intersects can be set as an alignment target. . That is, since a point can be set as an object of alignment, for example, it is possible to perform alignment appropriately as compared with a shape that makes it difficult to set a point as an object of alignment such as a circle. Accordingly, the positioning of the positioning portions 47a to 47d and the positioning portions 50a to 50d can be suitably performed with respect to the first alignment marks 41a to 41d.
  • the first alignment marks 41a and 41b, the second alignment marks 42a and 42b, and the third alignment marks 43a and 43b provided at one end and the other end are provided.
  • the first alignment marks 41c and 41d, the second alignment marks 42c and 42d, and the third alignment marks 43c and 43d are provided at asymmetric positions around the line BB. Thereby, determination of the direction of one side edge part and the other side edge part can be performed easily.
  • the first alignment marks 41a and 41b, the second alignment marks 42a and 42b, the third alignment marks 43a and 43b provided at one end, and the other end are provided.
  • the first alignment marks 41c and 41d, the second alignment marks 42c and 42d, and the third alignment marks 43c and 43d have been described as having an asymmetric positional relationship around the BB line.
  • the shape of the first alignment marks 41a and 41b may be a cross mark
  • the shape of the first alignment marks 41c and 41d may be an x mark.
  • the second alignment marks 42a to 42d and the third alignment marks 43a to 43d are described as being provided at the four corners, respectively. However, as shown in FIG. Only the second alignment marks 42b and 42c may be formed for 42a to 42d, and only the third alignment marks 43a and 43d may be formed for the third alignment marks 43a to 43d. Thereby, the second alignment marks 42b and 42c and the third alignment marks 43a and 43d are arranged on different diagonal lines. That is, since the second alignment marks 42b and 42c and the third alignment marks 43a and 43d are formed at positions where they do not overlap, the n-type single crystal silicon substrate 18 has the i-type amorphous silicon layer 22 or the i-type amorphous silicon. Passivation is performed by either one of the quality silicon layers 32. Therefore, recombination of carriers generated in the n-type single crystal silicon substrate 18 is suppressed, and the power generation characteristics of the photoelectric conversion element 10 can be improved.
  • a mask is used as a pattern forming member for performing an etching process and an etching paste is used as an etching treatment agent.
  • an etching process is performed using a resist as a pattern forming member. It is good also as what performs using an etching liquid as an agent.

Landscapes

  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Sustainable Development (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L'invention porte sur un procédé de fabrication d'un élément de conversion photoélectrique qui forme des premières marques d'alignement (41a-41d) sur un substrat semi-conducteur cristallin, forme une première couche semi-conductrice non cristalline sur le substrat semi-conducteur cristallin, y compris sur les premières marques d'alignement (41a-41d), forme des deuxièmes marques d'alignement (42a-42d) sur la première couche semi-conductrice non cristalline à l'aide de sections de positionnement (47a-47d), forme une seconde couche semi-conductrice non cristalline sur le substrat semi-conducteur cristallin y compris sur les deuxièmes marques d'alignement (42a-42d), et forme des troisièmes marques d'alignement (43a-43d) qui sont au niveau de la seconde couche semi-conductrice non cristalline à l'aide de sections de positionnement (50a-50d) et qui sont disposées à une position qui ne chevauche pas les deuxièmes marques d'alignement.
PCT/JP2012/053808 2011-03-25 2012-02-17 Procédé de fabrication d'un élément de conversion photoélectrique WO2012132613A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011-067429 2011-03-25
JP2011067429 2011-03-25

Publications (1)

Publication Number Publication Date
WO2012132613A1 true WO2012132613A1 (fr) 2012-10-04

Family

ID=46930375

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/053808 WO2012132613A1 (fr) 2011-03-25 2012-02-17 Procédé de fabrication d'un élément de conversion photoélectrique

Country Status (1)

Country Link
WO (1) WO2012132613A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015079779A1 (fr) * 2013-11-29 2015-06-04 パナソニックＩｐマネジメント株式会社 Procédé de fabrication de cellule solaire
JP2016154169A (ja) * 2015-02-20 2016-08-25 シャープ株式会社 光電変換素子および光電変換素子の製造方法
EP3886185A1 (fr) * 2020-03-27 2021-09-29 Meyer Burger GmbH Dispositif photovoltaïque et son procédé de fabrication

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08148709A (ja) * 1994-11-15 1996-06-07 Mitsubishi Electric Corp 薄型太陽電池の製造方法及び薄型太陽電池の製造装置
JP2001203379A (ja) * 2000-01-19 2001-07-27 Mitsubishi Electric Corp 太陽電池およびその製造方法
JP2006278657A (ja) * 2005-03-29 2006-10-12 Seiko Epson Corp 半導体装置の製造方法
JP2007048777A (ja) * 2005-08-05 2007-02-22 Nec Lcd Technologies Ltd 薄膜トランジスタを備えた半導体装置及びその製造方法
JP2008010746A (ja) * 2006-06-30 2008-01-17 Sharp Corp 太陽電池、および太陽電池の製造方法
JP2009026689A (ja) * 2007-07-23 2009-02-05 Fujifilm Corp 素子の製造方法及びそれを用いた表示装置の製造方法
WO2010113750A1 (fr) * 2009-03-30 2010-10-07 三洋電機株式会社 Pile solaire

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08148709A (ja) * 1994-11-15 1996-06-07 Mitsubishi Electric Corp 薄型太陽電池の製造方法及び薄型太陽電池の製造装置
JP2001203379A (ja) * 2000-01-19 2001-07-27 Mitsubishi Electric Corp 太陽電池およびその製造方法
JP2006278657A (ja) * 2005-03-29 2006-10-12 Seiko Epson Corp 半導体装置の製造方法
JP2007048777A (ja) * 2005-08-05 2007-02-22 Nec Lcd Technologies Ltd 薄膜トランジスタを備えた半導体装置及びその製造方法
JP2008010746A (ja) * 2006-06-30 2008-01-17 Sharp Corp 太陽電池、および太陽電池の製造方法
JP2009026689A (ja) * 2007-07-23 2009-02-05 Fujifilm Corp 素子の製造方法及びそれを用いた表示装置の製造方法
WO2010113750A1 (fr) * 2009-03-30 2010-10-07 三洋電機株式会社 Pile solaire

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015079779A1 (fr) * 2013-11-29 2015-06-04 パナソニックＩｐマネジメント株式会社 Procédé de fabrication de cellule solaire
JPWO2015079779A1 (ja) * 2013-11-29 2017-03-16 パナソニックＩｐマネジメント株式会社 太陽電池の製造方法
US9705027B2 (en) 2013-11-29 2017-07-11 Panasonic Intellectual Property Management Co., Ltd. Solar cell manufacturing method using etching paste
JP2016154169A (ja) * 2015-02-20 2016-08-25 シャープ株式会社 光電変換素子および光電変換素子の製造方法
EP3886185A1 (fr) * 2020-03-27 2021-09-29 Meyer Burger GmbH Dispositif photovoltaïque et son procédé de fabrication
WO2021190945A1 (fr) * 2020-03-27 2021-09-30 Meyer Burger (Germany) Gmbh Dispositif photovoltaïque et son procédé de fabrication

Similar Documents

Publication Publication Date Title
JP5879538B2 (ja) 光電変換装置及びその製造方法
JP5820988B2 (ja) 光電変換装置及びその製造方法
JP5705968B2 (ja) 光電変換装置及びその製造方法
JP6351601B2 (ja) 電気めっき金属グリッドを用いた光起電力装置
JP5774204B2 (ja) 光起電力素子およびその製造方法、太陽電池モジュール
JP5891382B2 (ja) 光電変換素子の製造方法
WO2012018119A1 (fr) Cellule solaire et procédé de fabrication de cellule solaire
US20140024168A1 (en) Method for producing photoelectric conversion device
WO2012132613A1 (fr) Procédé de fabrication d'un élément de conversion photoélectrique
JP2013089954A (ja) 光電素子
JP5820989B2 (ja) 光電変換素子の製造方法
JP4641858B2 (ja) 太陽電池
JP6425195B2 (ja) 太陽電池
WO2018168180A1 (fr) Cellule solaire et son procédé de fabrication
JP2013168605A (ja) 太陽電池の製造方法
JP2014183073A (ja) 光電変換素子および光電変換素子の製造方法
WO2012132614A1 (fr) Dispositif de conversion photoélectrique
WO2015145886A1 (fr) Procédé de formation de motif d'électrode et procédé de fabrication de cellule solaire
WO2019163786A1 (fr) Procédé de fabrication de cellule solaire
WO2012132616A1 (fr) Procédé de fabrication d'un élément de conversion photoélectrique
JP6906195B2 (ja) 太陽電池
WO2015118740A1 (fr) Cellule solaire
JP2015185658A (ja) 太陽電池の製造方法
WO2012132064A1 (fr) Élément photovoltaïque
JP5957102B2 (ja) 太陽電池の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12765223

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12765223

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP