WO2012126186A1 - 一种阻变存储器及其制备方法 - Google Patents

一种阻变存储器及其制备方法 Download PDF

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WO2012126186A1
WO2012126186A1 PCT/CN2011/072639 CN2011072639W WO2012126186A1 WO 2012126186 A1 WO2012126186 A1 WO 2012126186A1 CN 2011072639 W CN2011072639 W CN 2011072639W WO 2012126186 A1 WO2012126186 A1 WO 2012126186A1
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substrate
lower electrode
strip
electrode
resistive
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PCT/CN2011/072639
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French (fr)
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蔡一茂
黄如
王阳元
黄英龙
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北京大学
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Priority to US13/254,570 priority Critical patent/US8513639B2/en
Publication of WO2012126186A1 publication Critical patent/WO2012126186A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/82—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays the switching components having a common active material layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

Definitions

  • the present invention relates to a resistive memory, and in particular to a structure of a low-power resistive memory and a method of fabricating the same, and relates to a structure of a nonvolatile memory (CMOS) in a CMOS Very Large Scale Integrated Circuit (ULSI) and a manufacturing technology thereof.
  • CMOS nonvolatile memory
  • ULSI Very Large Scale Integrated Circuit
  • Solid-state storage devices play a very important role in the modern information society. Most of the electronic products we use every day include PCs, mobile phones, cameras, music players, automotive systems, GPS. According to whether the data classification can be saved after power off, the memory is mainly divided into two categories: non-volatile memory and volatile memory. The data cannot be saved after the volatile memory is powered off, and the data can be saved after the non-volatile memory is powered off.
  • DRAM dynamic random access memory
  • Flash flash memory
  • ferroelectric memory magnetic memory
  • phase change memory resistive memory
  • resistive memory has become a research hotspot with much attention due to its advantages of low cost, high speed and low voltage.
  • Resistive memory is a new type of non-volatile memory. Its resistance value can be reversibly converted between high-resistance and low-resistance states under the applied electric field to realize information storage. In RRAM, the resistive material exhibits two completely different impedance states (low resistance and high resistance) at the same read voltage, and both of these resistive states can be maintained for a long time after the erase voltage is withdrawn. Therefore, non-volatile storage of data can be achieved.
  • RRAM is a flat-plate capacitor structure with a layer of resistive material sandwiched between two upper and lower metal electrodes. Due to its simple structure and excellent performance, RRAM is the most potential competitor for next-generation memory applications, and has received extensive attention and research.
  • RRAM resistive metal oxides
  • metal electrodes the resistance properties of transition metal oxides, perovskite oxides, rare metal oxides and ferromagnetic materials have been studied.
  • electrodes the effects of various electrode metal materials on the resistive properties of RRAM have been studied.
  • the RRAM conduction mainly relies on the movement of the oxygen vacancies inside the resistive material or the movement of the gate metal ions to form a conductive path to make the high-resistance resistive material low impedance.
  • the conventional RRAM structure uses a metal-resistive material-metal (MIM) planar capacitor structure, as shown in Figure 1.
  • the structure is mainly composed of the upper metal electrode 1, the lower metal electrode 3, and the resistive material 2 between the upper and lower electrodes.
  • the working state is as follows: In the initial state, the resistive material is in a high resistance state; when the voltage between the two plates increases to a certain voltage, the current between the two plates increases sharply, and the resistive material becomes low resistance, The voltage at the time is called Vset; when the applied voltage is a certain value, the current between the two plates becomes sharply smaller, and the voltage at this time is called Vre Se t .
  • the sharp increase in current in RRAM devices is primarily due to conductive paths formed within the resistive material.
  • the internal electric field causes oxygen vacancies or metal charged ions to move, and a conductive path is locally formed between the upper and lower electrodes, causing the current to increase sharply.
  • the voltage is Vreset, since the resistance is very low at this time, the current sharply increases, the channel is blown, the resistive material becomes high resistance, and the current is sharply reduced.
  • the upper and lower electrodes of the existing RRAM adopt a flat plate structure, and the electric field is evenly distributed between the two plates. Since the electrodes have local unevenness, a local strong electric field is formed, thereby causing the movement of ions, thereby forming a conductive path.
  • the object of the present invention is to change the planar capacitor structure of a conventional RRAM, and propose a new structure of the RRAM electrode to reduce the power consumption of the device.
  • a resistive memory comprising a substrate, an upper electrode, a lower electrode and a resistive material between the upper and lower electrodes, wherein the lower electrode is located on the substrate, the middle portion is convex upward in a peak shape, and the upper electrode is located The top of the device is flat.
  • the resistive memory may be formed by forming a peak structure on the surface of the substrate, and the lower electrode covering the peak structure of the surface of the substrate.
  • the resistive memory has parallel rows of lower electrode strips having a peak shape in a cross section on the surface of the substrate, and n flat strip-shaped upper electrode strips are arranged in parallel at the top of the device, and a resistive material is interposed between the lower electrode strip and the upper electrode strip.
  • the arrangement direction of the upper electrode strip and the lower electrode strip is a crisscross structure, and each intersection forms a memory unit, a total of mX n memory cells, where m and n are positive integers.
  • the resistive memory device forms a series of parallel strip-shaped sawtooth structures on the surface of the substrate, and the lower electrode strip covers the strip-shaped sawtooth structure and has a cross section of " ⁇ " shape.
  • the above substrate is a Si (100) substrate
  • the material of the lower electrode and the upper electrode is a conductive metal or a metal nitride such as Pt, Al, Cu, TiN or the like.
  • the resistive material may be any of the existing resistive materials, including metal oxides (eg, A1 2 0 3 , WO x , and SrTiOx , etc.) and silicides (such as SiO x , SiN x , and SiO x N y , etc.).
  • the resistive memory of the present invention can be prepared by the following method: 1) forming a strip-shaped sawtooth structure on the surface of the substrate;
  • lithography defines the lower electrode pattern, and then deposits the electrode material to cover the sawtooth peak on the surface of the substrate to form a peak-shaped lower electrode;
  • a mask material (usually silicon nitride or Si0 2 ) is formed on the silicon substrate by lithography to define and etch the mask material to form a strip-shaped hard mask. Then, the surface of the silicon substrate is etched with KOH to form a series of strip-shaped saw teeth arranged in parallel on the surface of the substrate.
  • the above step 2) forms a series of parallel-arranged lower electrode strips having a " ⁇ " shape in cross section on the surface of the substrate having a strip-shaped sawtooth structure.
  • the above step 4) defines the upper electrode pattern as a series of parallel strip patterns by photolithography, and the formed upper electrode strip and the lower electrode strip are arranged in a crisscross pattern.
  • the RRAM structure proposed by the present invention changes the conventional flat capacitor structure by forming a peak structure on the surface of the substrate by etching, and then growing the lower electrode of the RRAM thereon to form a peak-shaped lower electrode, and then depositing the resistive material and the upper electrode.
  • a sharp-shaped lower electrode is formed by etching the substrate and depositing.
  • the lower electrode of the spike structure reduces the power consumption of the RRAM device (reducing the Vset voltage).
  • a strong electric field is formed between the lower electrode peak and the upper electrode, where it is easier to form a conductive path for ions, which in turn reduces the Vset voltage of the RRAM.
  • the electrode material uses a conductive metal or a metal nitride, and the resistive material may be in the form of a metal oxide such as A1 2 0 3 , WO x and SrTiO x and a silicide such as SiO x , SiN x and SiO x N y . Resistance material.
  • a vertical cross-bar structure can be formed between the lower electrode and the upper electrode, and an RRAM memory cell is formed at the intersection of each of the upper electrode and the lower electrode, which can have a high degree of integration.
  • FIG. 1 is a schematic structural view of a conventional RRAM memory cell, wherein: 1-a metal upper electrode, a 2-resistive material, a 3-metal lower electrode, and a 4-silicon substrate.
  • FIG. 2 is a schematic structural view of an RRAM memory cell of the present invention, wherein: 21-upper electrode, 22-resistive material, 23-lower electrode, and 24-substrate.
  • FIG. 8 are flowcharts showing a specific implementation of the RRAM of the present invention, wherein:
  • FIG. 3 is a schematic structural view showing deposition of a silicon nitride hard mask strip on a silicon substrate;
  • Figure 4 is a schematic view of the KOH corrosion process;
  • Figure 5 is a schematic view showing the formation of a sawtooth silicon substrate
  • FIG. 6 is a schematic view of a device after photolithography on a substrate and forming a lower electrode
  • Figure 7 is a schematic view showing a device after depositing a resistive material and chemical mechanical polishing
  • Figure 8 is a schematic illustration of the device after deposition of the metal upper electrode. detailed description
  • the memory cell of the prepared RRAM includes a substrate 24 having a peak structure, a lower electrode 23 covering the substrate peak structure, and an upper electrode 21 of the flat structure at the top, and between the upper and lower electrodes. Resistive material 22.
  • the RRAM is prepared according to the following steps:
  • a 300 nm silicon nitride is grown by chemical vapor deposition (CVD) on the surface, and strip-shaped silicon nitride is formed by photolithography as a hard mask 25 having a width of about 1 ⁇ m ( See Figure 3), and then etch the surface of the Si substrate with KOH (see Figure 4), forming a series of parallel-array strip-shaped serrations on the surface of the substrate.
  • the longitudinal section of the substrate perpendicular to the strip-shaped serrations is shown in Figure 5.
  • the surface of the substrate has a series of peak structures.
  • the width of the substrate spike is controlled by controlling the width of the mask strip and the etching time.
  • the photoresist is spin-coated on the surface of the serrated substrate, the thickness of the photoresist is greater than the height of the substrate peak, and the lithography defines the pattern of the electrode structure.
  • the deposition of the lower electrode metal of the device is carried out by a lift-off process, and as shown in Fig. 6, a lower electrode 23 of a peak structure is formed.
  • the lower electrode metal has a thickness of about 100 nm.
  • a resistive material is deposited thereon by an atomic layer deposition system, the thickness of the resistive material is greater than the height of the lower electrode peak, and chemical mechanical polishing (CMP) is performed to flatten the surface.
  • CMP chemical mechanical polishing
  • the height of the peak to the lower electrode of the resistive material 22 after planarization is controlled to be about 30 nm, and the resistive material of the lower electrode 23 to the upper electrode is a major part of the resistive change.
  • the deposition of the upper electrode of the strip metal is achieved by a lift-off process.
  • a photoresist is spin-coated on the resistive material 22, and the upper electrode structure pattern is defined by photolithography to form a series of strip-shaped patterns arranged in parallel with the lower electrode.
  • the electrode metal was then sputtered to an electrode thickness of 100 nm.
  • the strip metal upper electrode 21 and the strip metal lower electrode 23 form a cross junction Structure.
  • Each of the upper and lower electrodes forms an RRAM memory cell at each intersection.

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Description

一种阻变存储器及其制备方法 技术领域
本发明涉及阻变存储器， 具体涉及一种低功耗阻变存储器的结构及其制备方法， 属于 CMOS超大规模集成电路 （ULSI) 中的非挥发存储器 （Nonvolatile memory) 的结构及其制 造技术领域。 背景技术
固态存储器件在现代信息社会中扮演着非常重要的角色， 我们日常使用的电子产品中 大都有它的存在， 包括个人电脑、 手机、 相机、 音乐播放器， 汽车***、 全球定位***等。 按断电后能否保存数据分类， 存储器主要分为， 非挥发性存储器和挥发性存储器两大类。 挥发存储器断电后不能保存数据， 而非挥发性存储器断电后仍能保存数据。
传统的存储主要是基于磁存储和光存储。 基于半导体技术的新型存储器由于其巨大的 优势逐渐占据了存储市场的主导地位。 尤其是动态随机存储器 （DRAM) 和闪存 （Flash) 出现， 引起了存储领域的一场革命。 然而， 随着半导体工业的不断发展， 器件尺寸不断地 缩小, DRAM和 Flash将会缩小到它的物理极限, 特别是进入到 22nm技术节点以后， 这两 种器件的缺陷凸显出来， 已不能满足存储发展的需求。 人们提出了各种新型存储器结构， 如： 铁电存储器、 磁存储器、 相变存储器， 阻变存储器等。 其中， 阻变存储器凭借低成本、 高速度、 低电压等优势已成为目前倍受关注的研究热点。
阻变存储器（RRAM)是一种全新的非易失性存储器， 其电阻值在外加电场作用下可在 高阻态和低阻态之间进行可逆转换， 从而实现信息存储。 在 RRAM中， 阻变材料会在同样 的读取电压下呈现出两种完全不同的阻抗状态 （低阻和高阻）， 并且这两种阻态均可以在擦 写电压撤离后长时间保持， 因此可以实现数据的非易失性存储。 RRAM是在上下两个金属 电极中间夹一层阻变材料的平板电容结构， 由于其结构简单和性能优异， 成为下一代存储 器应用的最有潜力竞争者， 因此受到人们的广泛关注和研究。
目前对 RRAM的研究主要集中在的阻变材料和金属电极的选择和制备方面。阻变材料 方面， 人们研究了过渡金属氧化物、 钙钛矿氧化物、 稀有金属氧化物和铁磁材料的阻变特 性。 电极方面， 人们研究了各种电极金属材料对 RRAM阻变特性的影响。在 RRAM器件方 面取得了大的进展。 RRAM 导通主要是靠阻变材料内部氧空位的移动或者是栅极金属离子 的移动而形成导电通道使高阻态的电阻材料变为低阻。
传统的 RRAM结构采用金属-阻变材料 -金属 （MIM) 的平板电容结构， 如图 1所示。 其结构主要由上金属电极 1， 下金属电极 3和上下两电极之间的阻变材料 2组成。其工作状 态如下： 初始状态下， 阻变材料呈高阻态； 当两极板之间的电压增大到一定电压时， 两极 板之间的电流急剧增大， 阻变材料变为低阻， 此时的电压称为 Vset; 当所加电压为某一值 后， 两极板之间的电流又急剧变小， 此时的电压称为 VreSet。 RRAM器件电流急剧增长主 要是由于阻变材料内部形成的导电通道导致的。 当电压增加到 Vset时， 其内部的电场使氧 空位或金属带电离子移动， 并在上下电极之间局部形成了导电通道， 使电流急剧增加。 当 电压为 Vreset时， 由于此时电阻很低， 电流急剧增大， 使通道熔断， 阻变材料变为高阻， 进而电流又急剧减小。 现有 RRAM上下电极采用平板结构， 电场在两板间均匀分布， 由于 电极会有局部的不平坦， 形成局部较强的电场， 从而引起离子的移动， 进而形成了导电通 道。但是这种导电通道的形成位置是随机的，不利于 RRAM性能的稳定，且 Vset电压较高， 不利于器件功耗的降低。 因此， 通过合理的结构以定位电场强度的位置是必要的。 发明内容
针对上述问题， 本发明的目的在于改变了传统 RRAM 的平板电容结构， 提出一种 RRAM电极的新结构， 以降低器件的功耗。
本发明的技术方案如下：
一种阻变存储器， 包括衬底、 上电极、 下电极和位于上下电极之间的阻变材料， 其中 所述下电极位于衬底上， 中部向上凸起成尖峰状， 而所述上电极位于器件顶部， 为平板状。
上述阻变存储器可以是在衬底表面形成尖峰结构， 下电极覆盖于衬底表面的尖峰结构 上。
进一步的， 上述阻变存储器在衬底表面平行排列有 m条截面为尖峰状的下电极条， 器 件顶部平行排列 n条平板状上电极带， 下电极条和上电极带之间是阻变材料， 上电极带与 下电极条二者的排列方向呈十字交叉结构， 每个交叉点形成一个存储单元， 共 mX n个存储 单元， 其中 m和 n为正整数。
优选的， 上述阻变存储器在衬底表面形成一系列平行排列的条状锯齿结构， 下电极条 覆盖于条状锯齿结构上， 其截面为 "Λ"形。
上述衬底是 Si(100)衬底， 而上述下电极和上电极的材料为导电金属或金属氮化物， 例 如 Pt、 Al、 Cu和 TiN等。 阻变材料可以是现有的任何一种阻变材料， 包括金属氧化物（如， A1203、 WOx和 SrTiOx等） 和硅化物 （如 SiOx、 SiNx和 SiOxNy等）。
本发明的阻变存储器可以通过下述方法制备： 1 ) 在衬底表面形成条状锯齿结构；
2) 光刻定义下电极图形， 再淀积电极材料覆盖衬底表面的锯齿峰， 形成尖峰状的下 电极；
3 ) 淀积阻变材料完全覆盖下电极， 并进行化学机械抛光使其表面平坦；
4) 在阻变材料上形成平板状上电极。
进一步的， 上述步骤 1 ) 在硅衬底上先生长一层掩膜材料 （通常是氮化硅， 也可以是 Si02) 通过光刻定义并刻蚀掩膜材料形成条带状的硬掩膜， 然后用 KOH腐蚀硅衬底表面， 在衬底表面形成一系列平行排列的条状锯齿。
上述步骤 2)在具有条状锯齿结构的衬底表面形成一系列平行排列的截面为 "Λ"形的 下电极条。
上述步骤 4) 通过光刻定义上电极图形为一系列平行排列的带状图形， 所形成的上电 极带与下电极条的排列方向呈十字交叉结构。
本发明提出的 RRAM结构改变了传统的平板电容结构，通过腐蚀在衬底表面形成尖峰 结构， 接着在其上生长 RRAM的下电极， 形成尖峰状下电极， 然后淀积阻变材料和上电极。 主要有以下三点优势：
( 1 ) 制作工艺容易实现。 通过腐蚀衬底和淀积形成尖峰状的下电极。
(2) 尖峰结构的下电极降低了 RRAM器件的功耗 （降低了 Vset电压）。 下电极尖峰 处和上电极之间会形成强电场， 在此处会更容易形成离子的导电通道， 进而降低了 RRAM 的 Vset电压。 电极材料使用导电金属或者金属氮化物， 阻变材料可以使用金属氧化物 （如 A1203、 WOx和 SrTiOx) 和硅化物 （如 SiOx、 SiNx和 SiOxNy) 等形式的阻变材料。
(3 ) 可实现器件的高集成度。 可以采用下电极与上电极形成垂直交叉 （cross-bar) 的 结构， 每个上电极与下电极的交叉处形成 RRAM存储单元， 可以有很高的集成度。 附图说明
图 1为现有 RRAM存储单元的结构示意图， 其中： 1-金属上电极， 2-阻变材料， 3-金属 下电极， 4-硅衬底。
图 2为本发明 RRAM存储单元的结构示意图， 其中： 21-上电极， 22-阻变材料， 23-下 电极， 24-衬底。
图 3〜图 8是本发明制备 RRAM的具体实施流程图， 其中：
图 3为在硅衬底上淀积形成氮化硅硬掩膜条的结构示意图； 图 4为 KOH腐蚀过程示意图；
图 5为形成锯齿状硅衬底的示意图；
图 6为在衬底上光刻并形成下电极后器件的示意图；
图 7为淀积阻变材料及化学机械抛光后器件的示意图；
图 8为淀积金属上电极后器件的示意图。 具体实施方式
下面结合附图， 通过实施例进一步描述本发明
如图 2所示， 所制备的 RRAM的存储单元包括具有尖峰结构的衬底 24， 覆盖在衬底尖 峰结构上的下电极 23 和位于顶部的平板结构的上电极 21， 以及上下电极之间的阻变材料 22。 根据下述步骤制备所述 RRAM:
1. 衬底的制备
使用 Si(100)衬底 24， 表面用化学气相淀积（CVD)生长一层 300nm的氮化硅， 光刻形 成条带状氮化硅作为腐蚀硬掩膜 25， 宽度约为 1 μ m (见图 3 )， 然后用 KOH腐蚀 Si衬底 表面 （参见图 4)， 在衬底表面形成一系列平行排列的条状锯齿， 垂直于条状锯齿走向的衬 底纵截面如图 5 所示， 衬底表面具有一系列尖峰结构。 通过控制掩膜条的宽度和腐蚀时间 来控制衬底尖峰的宽度。
2. 下电极的制备
在锯齿状衬底表面旋涂光刻胶， 光刻胶的厚度要大于衬底尖峰的高度， 光刻定义下电 极结构图形。 用 lift-off工艺实现器件下电极金属的淀积， 如图 6所示， 形成尖峰结构的下 电极 23。 下电极金属厚度约为 100nm。
3. 阻变材料的淀积
下电极 23制备完成后， 接着在其上用原子层淀积***淀积阻变材料， 阻变材料厚度为 大于下电极尖峰高度， 并进行化学机械抛光 （CMP) 使其表面平坦。 平坦化后阻变材料 22 的平面到下电极 23峰尖的高度控制约为 30nm， 下电极 23尖峰到上电极处的阻变材料是发 生阻变的主要部分。
4. 上电极的淀积
通过 lift-off工艺实现带状金属上电极的淀积。 首先在阻变材料 22上旋涂光刻胶， 光刻 定义上电极结构图形， 形成一系列与下电极十字交叉的平行排列的带状图形。 然后溅射上 电极金属， 电极厚度为 100nm。 带状金属上电极 21和条状金属下电极 23形成十字交叉结 构。 上下电极每个交叉点形成一个 RRAM存储单元。 虽然， 上文中已经用一般性说明及具体实施方案对本发明作了详尽的描述， 但在本发 明基础上， 可以对之作一些修改或改进， 这对本领域技术人员而言是显而易见的。 因此， 在不偏离本发明精神的基础上所做的这些修改或改进， 均属于本发明要求保护的范围。

Claims

权利 要求 书
1 . 一种阻变存储器， 包括衬底、 上电极、 下电极和位于上下电极之间的阻变材料， 其中下 电极位于衬底上， 上电极位于器件顶部， 其特征在于， 所述下电极中部向上凸起成尖峰 状， 而所述上电极为平板状。
2. 如权利要求 1所述的阻变存储器， 其特征在于， 所述衬底表面形成有尖峰结构， 下电极 覆盖于衬底表面的尖峰结构上。
3. 如权利要求 1所述的阻变存储器， 其特征在于， 在衬底表面平行排列 m条截面为尖峰状 的下电极条， 器件顶部平行排列 n条上电极带， 二者的排列方向呈十字交叉结构， 每个 交叉点形成一个存储单元， 共 mX n个存储单元， 其中 m和 n为正整数。
4. 如权利要求 3所述的阻变存储器， 其特征在于， 所述衬底表面形成有平行排列的条状锯 齿结构， 下电极条覆盖于条状锯齿结构上， 其截面为 "Λ"形。
5. 如权利要求 1〜4任一所述的阻变存储器， 其特征在于， 所述衬底材料是 Si(100)衬底； 所述下电极和上电极材料是导电金属或金属氮化物。
6. 如权利要求 1〜4任一所述的阻变存储器， 其特征在于， 所述阻变材料是金属氧化物阻 变材料或硅化物阻变材料
7. 一种阻变存储器的制备方法， 包括下述步骤：
1 ) 在衬底表面形成条状锯齿结构；
2)光刻定义下电极图形， 淀积电极材料覆盖衬底表面的锯齿峰， 形成尖峰状的下电极;
3 ) 淀积阻变材料完全覆盖下电极， 并进行化学机械抛光使其表面平坦；
4) 在阻变材料上形成平板状上电极。
8. 如权利要求 7所述的制备方法， 其特征在于， 步骤 1 )在硅衬底上先生长一层掩膜材料， 通过光刻定义并刻蚀掩膜材料形成条带状的硬掩膜， 然后用 KOH腐蚀硅衬底表面， 在 衬底表面形成一系列平行排列的条状锯齿。
9. 如权利要求 8所述的制备方法， 其特征在于， 步骤 2) 在衬底表面形成一系列平行排列 的截面为 "Λ"形的下电极条。
10. 如权利要求 9所述的制备方法， 其特征在于， 步骤 4) 通过光刻定义上电极图形为一系 列平行排列的带状图形， 形成上电极带， 上电极带与下电极条的排列方向呈十字交叉结 构。
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