WO2012100501A1 - 阻变型随机存储单元及存储器 - Google Patents
阻变型随机存储单元及存储器 Download PDFInfo
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- WO2012100501A1 WO2012100501A1 PCT/CN2011/076681 CN2011076681W WO2012100501A1 WO 2012100501 A1 WO2012100501 A1 WO 2012100501A1 CN 2011076681 W CN2011076681 W CN 2011076681W WO 2012100501 A1 WO2012100501 A1 WO 2012100501A1
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- resistive
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
Definitions
- the invention belongs to the field of microelectronics and memory technology, and in particular relates to a resistive random access memory unit and a memory for high density data storage. Background technique
- Resistive Random Access Memory As an emerging non-volatile memory technology, in terms of cell area, device density, power consumption, program/erase speed, 3D integration, and multi-value implementation Many aspects have great advantages over FLASH, and are highly concerned by large companies and research institutes at home and abroad. The continuous advancement of resistive memory technology has made it one of the most powerful competitors in the future market for non-volatile memory technology.
- the resistive random access memory has a simple cell structure of electrodes/insulator/electrodes. Therefore, the 1R type cross-array structure is the most ideal memory array structure, which enables three-dimensional ultra-high density integration.
- the cross-array structure memory cells are arranged at parallel intersections perpendicular to each other, and each memory cell can strobe and read and write the device.
- the symmetrical electrical characteristics of the memory cells there is a serious read crosstalk problem in the 1R type cross array structure.
- FIG. 1 is a schematic diagram of a read crosstalk problem in a prior art resistive random access memory. As shown in FIG. 1, each memory cell has an upper electrode, a resistive functional layer, and a lower electrode.
- the array structure is simple in preparation process and easy to realize low-cost and high-density three-dimensional integration. However, this structure has a significant read disturb phenomenon.
- the device with coordinates (1, 1) is in a high-impedance state
- the other three adjacent devices (1, 2), (2, 2), and (2, 1) are In the low-impedance state
- the desired current path is shown by the solid line in Figure 1
- the actual current path is as shown by the dotted line in Figure 1, making the read
- the resistance value is the resistance of the (1, 1) device, which is the read crosstalk phenomenon.
- the read crosstalk problem is generally solved by the introduction of a gating unit, such as a 1T1R structure and a 1D1R structure.
- a gating unit such as a 1T1R structure and a 1D1R structure.
- the device cell area in the 1T1R structure integration scheme is ultimately determined by the transistor.
- the minimum area of the resistive random access memory of the 1T1R structure is 6F 2 (F is the characteristic line width) without considering the influence of the transistor drive current. Therefore, the 1T1R structure cannot be realized high.
- the density of the array is integrated, and the 1D1R structure is considered to have more potential for application.
- FIG. 2 is a schematic structural view of a prior art 1D1R structure resistive random access memory.
- the problem of misreading can be effectively solved by connecting the rectifier diode to the resistive functional layer.
- the rectifier diode is realized by the PN junction.
- the resistive functional layer electrode is generally made of a metal material
- the n-type and p-type doping of the PN junction and the subsequent high-temperature activation process make the 1D1R unit using the PN junction rectifier diode realize the three-dimensional integration process as shown in FIG. Very complicated and difficult to control.
- the thickness of conventional PN junctions exceeds 100 nanometers, which also hinders their three-dimensional integration.
- the polysilicon PN junction diode can provide the large Set/Reset current required for the resistance, its leakage current is large. All of the above factors restrict the integration of conventional polysilicon PN junction rectifying resistive devices. Therefore, how to realize 1D1R structure Three-dimensional high-density integration of resistive random memory cells is an important topic in storage technology research.
- the applicant of the present invention is aware of the following technical problems in the prior art: in a resistive memory cell of a 1D1R structure using a PN junction as a gating cell, it is disadvantageous for three-dimensional high-density integration due to the need for additional doping and high-temperature activation processes. . Summary of the invention
- the present invention provides a resistive random access memory cell and a memory to avoid the use of a PN junction to implement a current gating function, thereby realizing a three-dimensional high-density integration of a resistive random memory cell.
- a resistive random access memory unit is provided.
- the memory unit is composed of an upper electrode, a resistive functional layer, an intermediate electrode, an asymmetric tunneling barrier layer and a lower electrode, wherein the upper electrode, the resistive functional layer and the intermediate electrode constitute a resistive memory portion, an intermediate electrode, and an asymmetric tunnel
- the barrier layer and the lower electrode form a gate function portion, the resistive memory portion and the gate function portion share the intermediate electrode, and the gate function portion may be located above or below the resistive memory portion;
- the asymmetric tunneling barrier layer is at least Two materials having different barrier heights are constructed to achieve rectification modulation of the forward and reverse tunneling currents through the resistive random access memory cell.
- an asymmetric tunneling barrier layer is formed.
- the type and thickness of each material is determined by preset rectification modulation characteristics, and the barrier height of each material is monotonically increasing or monotonically decreasing from bottom to top.
- the electrode is composed of a low work function conductive material; and the asymmetric tunneling barrier layer has a low barrier material On one side, the electrodes are composed of a high work function conductive material.
- the material having a difference in barrier height is Si0 2 , SiON, Si 3 N 4 , Hf0 2 , A1 2 0 3 , Zr0 2 , HfAlO, HfSiO, AlSiO, Ta 2 0 5 or Hf0 2 .
- the thickness of each sub-layer constituting the asymmetric tunneling barrier layer is 0.5 nn! ⁇ 50nm.
- the asymmetric tunneling barrier layer is Si0 2 /Si 3 N 4 , Si0 2 /Al 2 0 3 , Si0 2 /Hf0 2 , SiON/Hf0 2 , SiON/Al 2 0 3 , Al 2 0 3 /Hf0 2 ,
- the Al 2 0 3 /Si0 2 or Hf0 2 /SiON layer, or the asymmetric tunneling barrier layer is Si0 2 /Al 2 0 3 /Hf0 2 , SiON/Al 2 0 3 /Hf0 2 or Si0 2 /SiON/Hf0 2 layers.
- a resistive random access memory comprises a resistor read/write unit, an address selection unit and a plurality of the above-mentioned resistive random storage units, wherein: an address selection unit is connected to the plurality of resistive random storage units for selecting a resistive random storage unit for operation; The read/write unit is connected to the address selection unit and the plurality of resistive random storage units for setting, resetting or programming the selected resistive random storage unit.
- the present invention has the following beneficial effects:
- the height of the PN junction diode in the original 1D1R can be drastically reduced, for example, from a 100 nm polysilicon PN junction diode thickness to a thickness less than 10 nm, so new The unit structure will tend to be consistent with the ideal 1R structure in terms of integration density, and can also achieve three-dimensional high-density integration;
- the asymmetric barrier structure is used for the gating of the resistive region, and the implementation process is very simple, and the process requirements of injection, annealing, etc. required for the conventional polysilicon PN junction rectifier diode are avoided, thereby making the process complicated. Degree and manufacturing costs are greatly reduced;
- a 1TB1R structure based on an asymmetric tunneling barrier has a basic concept in that a tunneling current can pass through a non-polarized voltage across the asymmetric barrier.
- the symmetrical barrier height and the tunneling thickness are adjusted to obtain a large difference between positive and negative currents (such as 10 5 ), so that rectification can be effectively realized by this structure.
- the asymmetric tunneling barrier layer can be realized by high-k materials with different barrier heights, such as Si0 2 /Al 2 0 3 , Si0 2 /Hf0 2 , SiON/Hf0 2 , etc. And has been widely used in CMOS processes, so the new structure is fully compatible with CMOS processes;
- the asymmetric tunneling barrier layer is used as the strobe unit, which can effectively solve the problem of read crosstalk of the 1R type cross-array. Therefore, the structure can be well used to implement the cross-storage array design.
- FIG. 1 is a schematic diagram of a read crosstalk problem in a prior art resistive memory
- FIG. 2 is a schematic structural view of a prior art 1D1R structure resistive memory
- Embodiment 1 of a resistive random access memory unit is a schematic diagram of Embodiment 1 of a resistive random access memory unit according to the present invention.
- Embodiment 4 is a schematic diagram of Embodiment 2 of a resistive random access memory unit according to the present invention.
- FIG. 5 is a schematic diagram of a resistive random access memory unit according to an embodiment of the present invention.
- FIG. 6 is a schematic diagram of a resistive random access memory unit according to another embodiment of the present invention.
- FIG. 7 is a current test curve of a Si0 2 /Al 2 0 3 stack structure of different thickness ratios of a resistive random memory cell according to an embodiment of the present invention. detailed description
- a resistive random access memory unit is provided.
- the memory unit is composed of an upper electrode, a resistive functional layer, an intermediate electrode, an asymmetric tunneling barrier layer and a lower electrode, wherein the upper electrode, the resistive functional layer and the intermediate electrode constitute a resistive memory portion, an intermediate electrode, and an asymmetric tunnel
- the barrier layer and the lower electrode constitute a gate function portion, and the resistive memory portion and the gate function portion share the intermediate electrode.
- the strobe function portion may be located above or below the resistive memory portion. If the strobe function portion is located above the resistive memory portion, the structure of the memory cell is as shown in FIG.
- the asymmetric tunneling barrier layer is composed of at least two materials having different barrier heights to achieve positive and negative tunneling through the resistive random access memory cell. Rectifier modulation of current through.
- the kind and thickness of the material constituting the asymmetric tunneling barrier layer are determined by preset rectifying modulation characteristics.
- an asymmetric tunneling barrier layer is introduced for rectification, and the gating operation of the resistive switching unit is realized.
- the preparation of the asymmetric tunneling barrier layer does not involve a doping process, high temperature annealing is not required, and the thickness is thin, it is advantageous to realize three-dimensional high-density integration of the resistive random access memory.
- the introduction of the intermediate electrode of the present invention increases the number of process steps, the reliability of the resistive unit is also improved.
- the electrode is composed of a low work function conductive material; on the side of the low barrier material of the asymmetric tunneling barrier layer, The electrodes are composed of a high work function conductive material.
- the asymmetric tunneling barrier layer is comprised of a material having a difference in at least two barrier heights.
- the material with different difference in barrier height is Si0 2 , SiON, Si 3 N 4 , Hf0 2 , A1 2 0 3 , Zr0 2 , HfAlO, HfSiO, AlSiO, Ta 2 0 5 or Hf0 2 , which constitutes an asymmetric tunneling potential.
- the thickness of each sublayer of the barrier layer is from 0.5 nm to 50 nm. Preferably, however, the total thickness of the asymmetric tunneling barrier layer is 10-50 nm.
- the double-layer asymmetric tunneling barrier layer may be Si0 2 /Si 3 N 4 , Si0 2 /Al 2 0 3 , Si0 2 /Hf0 2 , SiO should be f0 2 , SiON/Al 2 0 3 , Al 2 0 3 /Hf0 2 , Al 2 0 3 /Si0 2 or Hf0 2 /SiON layer; the three-layer asymmetric tunneling barrier layer may be Si0 2 /Al 2 0 3 /Hf0 2 , SiON/Al 2 0 3 /Hf0 2 or Si0 2 /SiON/Hf0 2 .
- the material constituting the asymmetric tunneling barrier layer can be prepared by one of the following methods: electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, magnetron sputtering or oxidation.
- FIG. 5 is a schematic diagram of a resistive random access memory unit according to an embodiment of the present invention.
- the left figure in Figure 5 is the structure diagram of the resistive-type random memory cell
- the right side of Figure 5 is the energy band diagram of the strobe function part of the resistive-type random memory cell.
- the two figures are put together for explanation.
- the resistive random access memory cell includes a resistive memory portion (1R) and a gate function portion (TB).
- the strobe function portion located below the resistive memory portion, is composed of an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode.
- the asymmetric tunneling barrier layer is composed of two layers of a low barrier material and a high barrier material.
- the double barrier here consists of SiON and a high K material such as Hf0 2 .
- the voltage of the intermediate electrode will be higher than that of the lower electrode, so the energy band of the asymmetric barrier is as shown in the upper right diagram of FIG. 5, so that the electron is
- the tunneling thickness is dl when tunneling from the lower electrode to the upper electrode, and the tunneling barrier height is determined by the material SiON near the lower electrode.
- the tunneling distance of the electron from the upper electrode to the lower electrode is d2, and the barrier height is determined by the high-k material Hf0 2 close to the intermediate electrode. It can be seen that dl ⁇ d2, so that the tunneling current can be controlled by selecting the material and the thickness, so that the rectifying characteristics of the tunneling current can be effectively realized.
- the 1R cross-array operation can be implemented using the new structure in the left figure of Figure 5.
- an asymmetric tunneling barrier layer By using an asymmetric tunneling barrier layer, the height of the PN junction diode in the original 1D1R can be drastically reduced, for example, from a 100 nm polysilicon PN junction diode thickness to a thickness less than 10 nm, so a new resistive random access memory cell It will tend to be consistent with the ideal 1R structure in terms of integration density, and can also achieve three-dimensional high-density integration.
- the implementation process of the structure is very simple, and the process requirements of injection, annealing, etc. required for the conventional polysilicon PN junction rectifier diode are avoided, so that the process complexity and manufacturing cost can be greatly reduced.
- FIG. 6 is a schematic diagram of a resistive random access memory unit according to another embodiment of the present invention.
- the memory cell is based on a deformation of a new structure of a three-layer asymmetric tunneling barrier, that is, the gate function portion is composed of a high barrier material, a medium barrier material, and a low The barrier material is composed.
- the basic concept is similar to the double layer.
- the barrier height of the three barrier materials is monotonically increasing or decreasing, and the modulation effect on the current can be obtained. It should of course be noted that if the three materials are not monotonically increasing or decreasing, similar functions can still be obtained by selecting the appropriate dielectric constant and different thicknesses. Therefore, if the non-monotonically increasing or decreasing barrier is still within the scope of the present invention, the effect of current rectification is not described herein.
- the inventive idea is instantiated only by taking the barrier height near the intermediate electrode medium less than the barrier height near the lower electrode medium. It should be noted that any other deformation based on the current adjustment through the asymmetric barrier, including the barrier height near the intermediate electrode medium is greater than the barrier height near the lower electrode medium. Degrees, as well as more layers of tunneling barriers, etc., will be covered by the present invention.
- FIG. 7 shows a current test curve of a Si0 2 /Al 2 0 3 stack structure of different thickness ratios of the resistive random memory cell of the embodiment of the present invention.
- the thickness of A1 2 0 3 is fixed at 50 A, and the thickness of Si0 2 is split, and the equivalent oxide thickness (EOT) is also shown in the figure.
- EOT equivalent oxide thickness
- the current only needs to pass at (1, 1) 1 tunneling barrier, and the leakage channel (from the (1, 1) ( 1, 2) - (2, 2) - (2, 1)) path requires four tunneling barriers, and the leakage current will It is effectively suppressed to achieve the problem of preventing cross-array crosstalk.
- a new structure of a new resistive random access memory cell using a double-layer tunneling barrier (Fig. 5) and a three-layer tunneling barrier (Fig. 6) for rectification is given above, and of course,
- the resistive memory portion may have a unipolar or bipolar resistance transition characteristic.
- the conductive electrode material of the upper electrode, the intermediate electrode and the lower electrode is composed of at least one or more of the following materials: metal material, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo , Ir, Ni, electrically conductive metal compound TiN, TaN, WN, Ir0 2 , ITO, NiSi, CoSi, IZO, YBCO, LaA10 3, SrRu0 3, Si, polysilicon, or other conductive electrode material;
- the conductive electrode material is deposited by one of the following methods: Electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or magnetron sputtering; the thickness of the electrode material is from 1 nm to 500 nm.
- MO x where 0 ⁇
- the resistive functional layer of the resistive memory portion can also be realized by changing the phase state of the functional layer material (ie, a conventional phase change memory). Therefore, the functional material may also include various materials that can undergo phase change, such as Ge 2 Sb 2 Te 5 (GST), GeTe, GeTeC and the like.
- GST Ge 2 Sb 2 Te 5
- the resistive functional layer is prepared by one of the following methods: electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, spin coating or magnetron sputtering; the thickness of the storage medium layer is 1 nm. ⁇ 500 nm, preferably 200 nm.
- the asymmetric tunneling barrier layer may be composed of a single layer, a double layer, and a plurality of dielectric layers. It is characterized in that the height of the barrier on the side of the lower electrode and the height of the barrier on the side of the intermediate electrode are different, so that the current has a large difference when voltages of different polarities are applied.
- the dielectric barrier height near the intermediate electrode may be smaller than the dielectric barrier height near the lower electrode (as shown in FIGS. 3 and 4), or vice versa.
- the double layer medium can be formed of at least two of the following materials.
- Si0 2 /Al 2 0 3 is composed of two materials such as Si0 2 , SiON, Si 3 N 4 , Hf0 2 , A1 2 0 3 , Zr0 2 , ⁇ 10, HfSiO, AlSiO, Ta 2 0 5 , etc.
- a double barrier such as Si0 2 /Hf0 2 , SiON/Hf0 2 , SiON/Al 2 0 3 , Al 2 0 3 /Hf0 2 , or Si0 2 /Hf0 2 /Al 2 0 3 , SiON/Hf0 2 / Three or more layers of barriers such as Al 2 0 3 .
- each layer material has a thickness of 0.5 nm. ⁇ 50 nm, preferably 20 nm.
- a resistive random access memory comprises a resistor read/write unit, an address selection unit and a plurality of upper resistive random storage Unit.
- the deposition process may be: electron beam deposition, magnetron sputtering, sol-gel deposition, chemical vapor deposition, etc.;
- the etching process can be: wet etching, plasma dry etching, and the like.
- One of ordinary skill in the art, in conjunction with objective and environmental factors, may choose a suitable deposition, etching or other process.
- the objects and structural features of the present invention are intended to be included within the scope of the present invention.
- the present invention introduces an asymmetric tunneling barrier layer for rectification, thereby enabling gating operation of the resistor unit.
- the asymmetric tunneling barrier layer is not doped, high temperature annealing is not required, and the thickness is thin, it is advantageous to realize three-dimensional high-density integration of the resistive random access memory.
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Description
阻变型随机存储单元及存储器
技术领域
本发明属于微电子及存储器技术领域, 尤其涉及一种用于高密度数 据存储的阻变型随机存储单元及存储器。 背景技术
阻变型随机存取存储器 (Resistive Random Access Memory, 简称 RRAM)作为一种新兴的非易失性存储技术, 在单元面积、器件密度、 功 耗、 编程 /擦除速度、 3D集成和多值实现等诸多方面相对 FLASH都具有 极大的优势, 受到国内外大公司和科研院所的高度关注。 阻变存储技术 的不断进步使之成为未来非易失性存储技术市场主流产品的最有力竞争 者之一。
阻变型随机存储器具有电极 /绝缘层 /电极的简单单元结构, 因此, 1R 型交叉阵列结构是最理想的存储阵列结构, 其可以实现三维超高密度的 集成。 在交叉阵列结构中, 上下相互垂直的平行交叉点处设置存储单元, 每一个存储单元都可以实现器件的选通并进行读写。 但是, 由于存储单 元对称的电学特性, 使得 1R型交叉阵列结构中存在严重的读串扰问题。
图 1 为现有技术阻变型随机存储器中读串扰问题的示意图。 如图 1 所示, 每个存储单元有上电极、 阻变功能层和下电极构成。 该阵列结构 制备工艺简单, 易于实现低成本和高密度的三维集成。 然而, 该结构存 在明显的读扰动现象。 如图 1 所示相邻的四个器件, 坐标为 (1, 1 ) 的 器件处于高阻状态, 其余三个相邻器件 (1, 2 )、 (2, 2) 和 (2, 1 ) 都 处于低阻状态, 此时在 (1, 1 ) 器件上加读电压时, 希望的电流通路如 图 1 中实线所示, 但实际上的电流通路却如图 1 中虚线所示, 使得读出 来的电阻值木是 (1, 1 ) 器件的电阻了, 这就是读串扰现象。
读串扰问题一般通过引入选通单元得以解决, 如 1T1R结构和 1D1R 结构。 采用 1T1R结构集成方案中的器件单元面积最终是由晶体管决定 的。 如果不考虑晶体管驱动电流的影响的话, 1T1R结构的阻变型随机存 储单元的最小面积为 6F2 (F为特征线宽)。 因此, 1T1R结构无法实现高
密度的阵列集成, 而 1D1R结构被认为更有应用的潜力。
图 2为现有技术 1D1R结构阻变型随机存储器的结构示意图。如图 2 所示, 在阻变型存储单元中, 通过将整流二极管串联到阻变功能层上可 以有效解决误读的问题, 整流二极管通过 PN结实现。考虑到阻变功能层 电极一般采用金属材料,构成 PN结的 n型和 p型糁杂以及随后的高温激 活过程使得这种采用 PN结整流二极管的 1D1R单元实现如图 2所示的三 维集成工艺非常复杂和难以控制。 此外, 常规的 PN结的厚度超出了 100 纳米, 也阻碍了其三维集成。 最后, 尽管多晶硅 PN结二极管能够提供阻 变所需要的大 Set/Reset电流, 但是其泄露电流很大。 以上种种因素制约 了常规多晶硅 PN结整流型阻变器件的集成。 因此, 如何实现 1D1R结构 阻变型随机存储单元的三维高密度集成是存储技术研究的一个重要课 题。
本发明申请人意识到现有技术存在如下技术问题:釆用 PN结作为选 通单元的 1D1R结构的阻变型存储单元中,由于需要额外的掺杂和高温激 活过程, 不利于进行三维高密度集成。 发明内容
(一) 要解决的技术问题
为解决上述缺陷, 本发明提供了一种阻变型随机存储单元及存储器, 以避免采用 PN结实现电流选通功能,实现阻变型随机存储单元的三维高 密度集成。
(二) 技术方案
根据本发明的一个方面, 提供了一种阻变型随机存储单元。 该存储 单元由上电极、 阻变功能层、 中间电极、 非对称隧穿势垒层和下电极构 成, 其中上电极、 阻变功能层和中间电极构成阻变存储部分, 中间电极、 非对称隧穿势垒层和下电极构成选通功能部分, 阻变存储部分和选通功 能部分共用中间电极, 选通功能部分可以位于阻变存储部分的上方或下 方; 非对称隧穿势垒层由至少两种势垒高度存在差异的材料构成, 以实 现对穿过阻变型随机存储单元的正、 反向隧穿电流的整流调制。
优选地, 本发明阻变型随机存储单元中, 构成非对称隧穿势垒层的
各材料的种类和厚度由预设的整流调制特性确定, 并且各材料的势垒高 度自下至上单调递增或单调递减。
优选地, 本发明阻变型随机存储单元中, 在非对称隧穿势垒层高势 垒材料的一侧, 电极由低功函数导电材料构成; 在非对称隧穿势垒层低 势垒材料的一侧, 电极由高功函数导电材料构成。
优选地, 本发明阻变型随机存储单元中, 势垒高度存在差异的材料 为 Si02, SiON, Si3N4, Hf02, A1203, Zr02, HfAlO, HfSiO, AlSiO, Ta205或 Hf02。 构成非对称隧穿势垒层的各子层的厚度为 0.5nn!〜 50nm。 非对称隧穿势垒层为 Si02/Si3N4, Si02/Al203, Si02/Hf02, SiON/Hf02, SiON/Al203, Al203/Hf02, Al203/Si02或 Hf02/SiON层, 或非对称隧穿势 垒层为 Si02/Al203/Hf02, SiON/Al203/Hf02或 Si02/SiON/Hf02层。
根据本发明的另一个方面, 提供了一种阻变型随机存储器。 该存储 器包括电阻读写单元、 地址选择单元和若干个上述的阻变型随机存储单 元, 其中: 地址选择单元, 与若干阻变型随机存储单元相连, 用于选择 进行操作的阻变型随机存储单元; 电阻读写单元, 与地址选择单元和若 干阻变型随机存储单元相连, 用于对所选择的阻变型随机存储单元进行 置位、 复位或编程操作。
(三) 有益效果
从上述技术方案可以看出, 本发明具有以下有益效果:
1 ) 本发明中, 通过采用非对称隧穿势垒层, 原 1D1R中 PN结二极 管的高度可以急剧减小,比如从 100纳米的多晶硅 PN结二极管厚度减小 到小于 10纳米的厚度, 因此新的单元结构将与理想的 1R结构在集成密 度上趋向于一致, 也都可实现三维高密度集成;
2) 本发明中, 非对称势垒结构用于阻变区的选通, 其实现工艺非常 简单, 避免了常规多晶硅 PN结整流二极管所需的注入、退火等的工艺需 求, 因此可以使得工艺复杂度和制造成本大大降低;
3 ) 本发明中, 基于非对称隧穿势垒 (Tunneling Barrier, 简称 TB ) 的 1TB1R结构, 其基本概念在于通过在非对称势垒两端施加不同极性的 电压, 其隧穿电流可以通过非对称的势垒高度和隧穿厚度的调整而获得 很大的正反向电流差异 (如 105), 因此可以通过这种结构有效实现整流
特性;
4)非对称隧穿势垒层可以采用具有不同势垒高度的高 K材料予以实 现, 比如 Si02/Al203, Si02/Hf02, SiON/Hf02等, 其可选的材料很多, 且 已经被广泛用于 CMOS工艺, 因此该新结构与 CMOS工艺完全兼容;
5 ) 采用该非对称隧穿势垒层作为选通单元, 可以有效解决 1R型交 叉阵列的读串扰的问题, 因此该结构可以很好的用于实现交叉存储阵列 方式设计。 ' 附图说明
图 1为现有技术阻变型存储器中读串扰问题的示意图;
图 2为现有技术 1D1R结构阻变型存储器的结构示意图;
图 3为本发明阻变型随机存储单元实施例一的示意图;
图 4为本发明阻变型随机存储单元实施例二的示意图;
图 5为本发明实施例阻变型随机存储单元的示意图;
图 6为本发明另一实施例阻变型随机存储单元的示意图;
图 7本发明实施例阻变型随机存储单元不同厚度比的 Si02/Al203堆 栈结构的电流测试曲线。 具体实施方式
为使本发明的目的、 技术方案和优点更加清楚明白, 以下结合具体 实施例, 并参照附图, 对本发明进一步详细说明。
在本发明的示例性实施例中, 提供了一种阻变型随机存储单元。 该 存储单元由上电极、 阻变功能层、 中间电极、 非对称隧穿势垒层和下电 极构成, 其中上电极、 阻变功能层和中间电极构成阻变存储部分, 中间 电极、 非对称隧穿势垒层和下电极构成选通功能部分, 阻变存储部分和 选通功能部分共用中间电极。 选通功能部分可以位于阻变存储部分的上 方或下方, 如果选通功能部分位于阻变存储部分的上方, 则该存储单元 的结构如图 3 所示; 如果选通功能部分位于阻变存储部分的下方, 则该 存储单元的结构如图 4所示。 而非对称隧穿势垒层由至少两种势垒高度 存在差异的材料构成, 以实现对穿过阻变型随机存储单元的正、 反向隧
穿电流的整流调制。 优选地, 构成非对称隧穿势垒层的材料的种类和厚 度由预设的整流调制特性确定。
本实施例引入非对称隧穿势垒层用于整流, 实现了阻变单元的选通 操作。 同时, 由于非对称隧穿势垒层的制备不涉及掺杂工艺, 不用高温 退火, 并且厚度较薄, 因此有利于实现阻变型随机存储器进行三维高密 度集成。 虽然本发明引入中间电极增加了工艺步骤, 但也提高了该阻变 单元的可靠性。
在本发明优选的实施例中, 在非对称隧穿势垒层高势垒材料的一侧, 电极由低功函数导电材料构成; 在非对称隧穿势垒层低势垒材料的一侧, 电极由高功函数导电材料构成。 通过调整中间电极和下电极导电材料的 功函数来进行控制, 可以获得更小的反向泄露电流, 从而其整流比也可 以进一步扩大。
在本发明优选的实施例中, 非对称隧穿势垒层由至少两种势垒高度 存在差异的材料构成。该势垒高度存在差异的材料为 Si02, SiON, Si3N4, Hf02, A1203, Zr02, HfAlO, HfSiO, AlSiO, Ta205或 Hf02, 构成非对 称隧穿势垒层的各子层的厚度为 0.5nm~50nm。 但优选地, 非对称隧穿势 垒层的总厚度为 10-50nm。本实施例中,双层的非对称隧穿势垒层可以为 Si02/Si3N4, Si02/Al203, Si02/Hf02, SiO應 f02, SiON/Al203, Al203/Hf02, Al203/Si02 或 Hf02/SiON 层; 三层的非对称隧穿势垒层可以为 Si02/Al203/Hf02, SiON/Al203/Hf02或 Si02/SiON/Hf02。 构成非对称隧穿 势垒层的材料制备可以采用以下的方法中一种: 电子束蒸发、 化学气相 沉积、 脉冲激光沉积、 原子层沉积、 磁控溅射或氧化。
图 5为本发明实施例阻变型随机存储单元的示意图。 其中, 图 5 中 左图为阻变型随机存储单元的结构图, 图 5 右为阻变型随机存储单元选 通功能部分的能带图。 为直观起见, 将两幅图放在一起进行说明。
如图 5左图所示, 阻变型随机存储单元包括阻变存储部分 (1R) 和 选通功能部分(TB )。 选通功能部分, 位于阻变存储部分的下方, 由中间 电极、 非对称隧穿势垒层和下电极构成。 而非对称隧穿势垒层由低势垒 材料和高势垒材料两层构成。 通过在非对称势垒两端施加不同极性的电 压, 其隧穿电流可以通过非对称的势垒高度和隧穿厚度的调整而获得很
大的正反向电流差异 (其正向电流比负向电流高 5个数量级), 因此可以 通过这种结构有效实现整流特性。
作为一个例子, 这里的双层势垒由 SiON和高 K材料 (比如 Hf02) 构成。 当图 5的上电极接正电压, 下电极接负电压或者 0的时候, 中间 电极的电压将高于下电极, 所以非对称势垒的能带如图 5中右上图所示, 这样电子在从下电极向上电极隧穿的时候其隧穿厚度为 dl, 其隧穿势垒 高度由靠近下电极的材料 SiON决定。 同理, 在上电极接负电压下电极接 0 电压或者正电压时候, 其电子从上电极向下电极的隧穿距离为 d2, 势 垒高度由靠近中间电极的高 K材料 Hf02决定。 可以看出, dl<d2, 这样 通过选择材料和厚度可以控制隧穿电流, 从而可以有效实现隧穿电流的 整流特性。
采用图 5左图的新结构可以实现 1R的交叉阵列运作方式。通过采用 非对称隧穿势垒层, 原 1D1R中 PN结二极管的高度可以急剧减小, 比如 从 100纳米的多晶硅 PN结二极管厚度减小到小于 10纳米的厚度, 因此 新的阻变型随机存储单元将与理想的 1R结构在集成密度上趋向于一致, 也可实现三维高密度集成。 同时, 该结构的实现工艺非常简单, 避免了 常规多晶硅 PN结整流二极管所需的注入、退火等的工艺需求, 因此可以 使得工艺复杂度和制造成本大大降低。
图 6为本发明另一实施例阻变型随机存储单元的示意图。 与图 5 中 所示的阻变型随机存储单元不同, 该存储单元基于三层非对称隧穿势垒 的新结构的一个变形, 即选通功能部分由高势垒材料、 中势垒材料、 低 势垒材料构成。 其基本概念与双层类似, 三种势垒材料的势垒高度单调 递增或者递减, 就可以获得其对电流的调制效果。 当然应该指出的是, 三种材料如果不是单调递增或者递减, 但是通过选择合适的介电常数和 不同的厚度, 仍然可以获得相似的功能。 因此非单调递增或者递减的势 垒如果具有电流整流的效果仍然在本发明的涵盖范围内, 此处不做赘述。
图 5和图 6的阻变型随机存储单元中, 只以靠近中间电极介质的势 垒高度小于靠近下电极介质的势垒高度为例对我们的发明思路进行了实 例化。 应该指出的是, 基于通过非对称势垒来进行电流调整的其他任何 变形, 包括靠近中间电极介质的势垒高度大于靠近下电极介质的势垒高
度, 以及更多层隧穿势垒等都将受本发明的涵盖。
如上所述, 通过调整构成非对称隧穿势垒层的材料的种类和厚度, 可以获得预设的整流调制特性。 为了验证上述理论的可行性, 图 7本发 明实施例阻变型随机存储单元不同厚度比的 Si02/Al203堆栈结构的电流 测试曲线。此处固定了 A1203厚度为 50 A, 而对 Si02的厚度进行了***, 其等效氧化层厚度(EOT)也被标示在图中。比如对于 Si02 ( 10 A) /A1203 ( 50 A), 如果 A1203的介电常数为 9.3, 那么其等效氧化层厚度约为 EOT=30A。 从正反向电流曲线测试可以看出, 不同的介质厚度的调整将 产生不同的隧穿电流曲线。 同时, 在相同电压值但不同极性情况下 (V, -V), 其电流差可以达到 5个数量级的差值, 因此完全能够满足选通管的 整流特性。 如图 7 的实验结果可以看出, 通过选择不同的材料厚度, 通 过隧穿势垒的正向电流比反向电流大 5 个数量级, 因此可以满足选择管 的整流需求。
对于在图 1 的交叉阵列中采用该新阻变型随机存储单元, 则在选择 通道上 (从 (1, 1 ) ^ (2, 1 ) ), 则电流只需要经过在 (1, 1 ) 处的 1 个隧穿势垒, 而泄露通道 (从 (1 , 1 ) ( 1, 2) - (2, 2) - (2, 1 ) ) 路径上则需要经过四个隧穿势垒, 泄露电流会被有效抑制, 从而达到防 止交叉阵列串扰的问题。
作为一个具体实例, 上文给出了采用双层隧穿势垒(图 5 )和三层隧 穿势垒(图 6)做整流的新的阻变型随机存储单元的新结构, 当然也可以 采用更多层的隧穿势垒结构, 只要通过非对称隧穿势垒层实现对穿过阻 变型随机存储单元的正、 反向隧穿电流的整流调制, 均应涵盖在本发明 的范围之内。
上述技术方案中, 阻变存储部分可以具有单极或双极性电阻转变特 性。 其上电极、 中间电极以及下电极的导电电极材料由至少一种或者多 种以下材料构成: 金属材料\^、 Al、 Cu、 Au、 Ag、 Pt、 Ru、 Ti、 Ta、 Pb、 Co、 Mo、 Ir、 Ni, 导电金属化合物 TiN、 TaN、 WN、 Ir02、 ITO、 NiSi、 CoSi、 IZO、 YBCO、 LaA103、 SrRu03、 Si、 多晶硅或者其它的导电电极 材料;
上述技术方案中, 导电电极材料采用以下方法中的一种进行淀积:
电子束蒸发、 化学气相沉积、 脉冲激光沉积、 原子层沉积或磁控溅射; 电极材料的厚度为 lnm〜500nm。
上述技术方案中, 阻变存储部分的电阻转变功能层至少由一种或者 多种以下材料或者对它们进行掺杂后形成,如 MOx,其中 0<x<=2; TiOx, 其中 0<x<=2; CuOx,其中 0<x<=2; ZrOx,其中 0<x<=2; TaOx,其中 0<x<=2; WOx, 其中 0<x<=2; HfOx; 其中 0<x<=2; AlOy, 其中 l<y<2; CoO; ΜοΟ, ΖηΟ; PCMO; LCMO; SrTi03; BaTi03; SrZr03; CuS; AgS; AgGeSe; CuIxSy其中 0<x, y<2; Si02; Y203; Si; 非晶硅或有机材料。
上述技术方案中, 阻变存储部分的阻变功能层也可以通过改变功能 层材料的相状态予以实现 (即常规的相变存储器)。 因此, 该功能材料亦 可以包括各种可以发生相变的材料,比如 Ge2Sb2Te5 (GST), GeTe, GeTeC 等材料。
上述技术方案中, 阻变功能层的制备采用以下的方法中一种: 电子 束蒸发、 化学气相沉积、 脉冲激光沉积、 原子层沉积、 旋涂或磁控溅射; 存储介质层的厚度为 lnm〜500nm, 优选为 200nm。
上述技术方案中, 其非对称隧穿势垒层可以由单层、 双层、 以及多 层介质层构成。 其特点在于下电极一侧的势垒高度和中间电极一侧的势 垒高度有一定的差异, 这样在施加不同极性电压的时候其电流有比较大 的差异。
上述技术方案中, 靠近中间电极的介质势垒高度可以小于靠近下电 极的介质势垒高度 (如图 3和图 4所示), 也可以相反。 其双层介质可以 至少由两种以下材料形成。如由 Si02, SiON, Si3N4, Hf02, A1203, Zr02, ■10, HfSiO , AlSiO , Ta205等材料中的两种构成如 Si02/Al203, Si02/Hf02, SiON/Hf02, SiON/Al203, Al203/Hf02等双层势垒, 也可以构 成 Si02/Hf02/Al203, SiON/Hf02/Al203等三层或者多层势垒等。
上述构成非对称势垒的材料制备可以采用以下的方法中一种: 电子 束蒸发、 化学气相沉积、 脉冲激光沉积、 原子层沉积或磁控溅射、 氧化 等; 各层材料的厚度为 0.5nm〜50nm, 优选为 20nm。
根据本发明的另一个方面, 还提供了一种阻变型随机存储器。 该存 储器包括电阻读写单元、 地址选择单元和若干个上文中阻变型随机存储
单元。
需要说明的是, 本发明半导体存储单元、 器件及其制备方法中, 涉 及的沉积工艺可以为: 电子束沉积、 磁控溅射、 溶胶-凝胶法沉积、 化学 气相沉积等; 而涉及的刻蚀工艺可以为: 湿法刻蚀、 等离子体干法刻蚀 等。 本领域的普通技术人员结合客观条件和环境因素, 可以选择合理的 沉积、 刻蚀或其他工艺。 只要达到本发明所涉及的目的及结构特征, 均 应包括在本发明的保护范围之内。
综上所述, 本发明引入非对称隧穿势垒层用于整流, 从而实现电阻 单元的选通操作。 同时, 由于非对称隧穿势垒层不用掺杂, 不用高温退 火, 并且厚度较薄, 因此有利于实现阻变型随机存储器进行三维高密度 集成。
以上所述的具体实施例, 对本发明的目的、 技术方案和有益效果进 行了进一步详细说明, 所应理解的是, 以上所述仅为本发明的具体实施 例而已, 并不用于限制本发明, 凡在本发明的精神和原则之内, 所做的 任何修改、 等同替换、 改进等, 均应包含在本发明的保护范围之内。
Claims
权利要求
一种阻变型随机存储单元, 其特征在于, 该存储单元由上电 极、 阻变功能层、 中间电极、 非对称隧穿势垒层和下电极构成, 其中上电极、 阻变功能层和中间电极构成阻变存储部分, 中间电 极、非对称隧穿势垒层和下电极构成选通功能部分, 阻变存储部分和 选通功能部分共用中间电极,选通功能部分位于阻变存储部分的上方 或下方;
所述非对称隧穿势垒层由至少两种势垒高度存在差异的材料构 成, 以实现对穿过所述阻变型随机存储单元的正、反向隧穿电流的整 流调制。
2、 根据权利要求 1所述的阻变型随机存储单元, 其特征在于, 构成所述非对称隧穿势垒层的各材料的种类和厚度由预设的整流调 制特性确定, 并且各材料的势垒高度自下至上单调递增或单调递减。
3、 根据权利要求 1所述的阻变型随机存储单元, 其特征在于, 在所述非对称隧穿势垒层高势垒材料的一侧,电极由低功函数导电材 料构成; 在所述非对称隧穿势垒层低势垒材料的一侧, 电极由高功函 数导电材料构成。
4、 根据权利要求 1所述的阻变型随机存储单元, 其特征在于, 所述势垒高度存在差异的材料为 Si02, SiON, Si3N4, Hf02, A1203, Zr02, HfAlO, HfSiO, AlSiO, Ta205或 Hf02。
5、 根据权利要求 4所述的阻变型随机存储单元, 其特征在于, 所述非对称隧穿势垒层为双层的非对称隧穿势垒层或三层的非对称 隧穿势垒层;
所述双层的非对称隧穿势垒层为 Si02/Si3N4, Si02/Al203, Si02/Hf02 , SiON/Hf02, SiON/Al203, Al203/Hf02, Al203/Si02或 Hf02/SiON层;
所述三层的非对称隧穿势垒层为 Si02/Al203/Hf02, SiON/Al203/Hf02或 Si02/SiON/Hf02层。
6、 根据权利要求 5所述的阻变型随机存储单元, 其特征在于, 构成所述非对称隧穿势垒层的各子层的厚度为 0.5nm~50nm。
7、 根据权利要求 4所述的阻变型随机存储单元, 其特征在于, 所述构成非对称隧穿势垒层的材料制备采用以下方法中的一种: 电子 束蒸发、 化学气相沉积、 脉冲激光沉积、 原子层沉积、 磁控溅射或氧 化。
8、 根据权利要求 1至 7中任一项所述的阻变型随机存储单元, 其特征在于,
所述阻变功能层的厚度为 lnm〜500nm;
所述阻变功能层为单层阻变材料、 多层阻变材料或相变存储材 料;
所述阻变功能层的制备方法为以下方法中的一种或者多种: 电子 束蒸发、 化学气相沉积、 脉冲激光沉积、 原子层沉积、 旋涂或磁控溅 射。
9、 根据权利要求 8所述的阻变型随机存储单元, 其特征在于, 所述单层阻变材料、多层阻变材料包括至少一种或两种以下材料 或者以下材料经掺杂改性后形成的材料: NiOx, 其中 0<x<=2; TiOx, 其中 0<x<=2; CuOx, 其中 0<x<=2; ZrOx, 其中 0<x<=2; TaOx, 其 中 0<x<=2; WOx, 其中 0<x<=2; HfOx; 其中 0<x<=2; A10y, 其中 Ky<2; CoO; MoO; ZnO; PCMO; LCMO; SrTi03; BaTi03; SrZr03; CuS; AgS; AgGeSe; CuIxSy其中 0<x, y<2; Si02; Y203; Si; 非 晶硅或有机材料;
所述相变存储材料包括至少一种以下材料: Ge2Sb2Te5, GeTe, GeTeC。
10、 根据权利要求 1-9中任一项所述的阻变型随机存储单元, 其 特征在于,
所述上电极、 中间电极和下电极的厚度为 lnm〜500nm;
所述上电极、中间电极和下电极的导电电极材料为以下材料中的 一种或者多种: W、 Al、 Cu、 Au、 Ag、 Pt、 Ru、 Ti、 Ta、 Pb、 Co、 Mo、 Ir、 Ni、 TiN、 TaN、 WN、 Ir02、 ITO、 MSi、 CoSi、 IZO、 YBCO、 LaA103、 SrRu03、 Si或多晶硅;
所述上电极、 中间电极和下电极采用以下方法中的一种进行沉 积: 电子束蒸发、 化学气相沉积、 脉冲激光沉积、 原子层沉积或磁控 溅射。
11、 一种阻变型随机存储器, 其特征在于, 该存储器包括电阻读 写单元、 地址选择单元和若干个权利要求 1-10 中任一项所述的阻变 型随机存储单元, 其中:
所述地址选择单元, 与所述若干阻变型随机存储单元相连, 用于 选择进行操作的阻变型随机存储单元;
所述电阻读写单元,与所述地址选择单元和所述若干阻变型随机 存储单元相连, 用于对所选择的阻变型随机存储单元进行置位、 复位 或编程操作。
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Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8314024B2 (en) | 2008-12-19 | 2012-11-20 | Unity Semiconductor Corporation | Device fabrication |
CN103247696A (zh) * | 2012-02-07 | 2013-08-14 | 中国科学院微电子研究所 | 隧穿二极管整流器件及其制造方法 |
CN102664235B (zh) * | 2012-04-12 | 2013-12-04 | 北京大学 | 一种小电极结构阻变存储器及其制备方法 |
KR101929941B1 (ko) * | 2012-08-10 | 2018-12-18 | 삼성전자 주식회사 | 저항 변화 물질 소자 및 이를 적용한 디바이스 |
CN103682088A (zh) * | 2012-09-10 | 2014-03-26 | 中国科学院微电子研究所 | 一种制造交叉点器件的方法 |
US9991399B2 (en) | 2012-10-04 | 2018-06-05 | Cree, Inc. | Passivation structure for semiconductor devices |
US9812338B2 (en) * | 2013-03-14 | 2017-11-07 | Cree, Inc. | Encapsulation of advanced devices using novel PECVD and ALD schemes |
US9178011B2 (en) * | 2013-03-13 | 2015-11-03 | Intermolecular, Inc. | Deposition of anisotropic dielectric layers orientationally matched to the physically separated substrate |
CN103400596A (zh) * | 2013-05-21 | 2013-11-20 | 清华大学 | 用于WOx阻变存储器的写电路 |
KR20150043759A (ko) * | 2013-10-15 | 2015-04-23 | 에스케이하이닉스 주식회사 | 저항 변화 메모리 장치 및 그의 제조방법 |
TWI548127B (zh) * | 2014-09-19 | 2016-09-01 | 華邦電子股份有限公司 | 電阻式隨機存取記憶體 |
WO2016053262A1 (en) | 2014-09-30 | 2016-04-07 | Hewlett-Packard Development Company, L.P. | Memristors with oxide switching layers |
CN105448948B (zh) * | 2014-09-30 | 2019-01-11 | 华邦电子股份有限公司 | 电阻式随机存取存储器 |
CN105006248B (zh) * | 2015-07-14 | 2018-12-07 | 华中科技大学 | 一种基于隔离型存储阵列结构的固态存储器 |
CN106711326A (zh) * | 2015-11-18 | 2017-05-24 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 阻变存储器及其制备方法 |
CN110071136A (zh) * | 2018-01-21 | 2019-07-30 | 成都海存艾匹科技有限公司 | 三维纵向电编程存储器 |
CN106025066B (zh) * | 2016-06-02 | 2018-11-20 | 河北大学 | 一种基于二氧化硅隧道结的阻变存储器及其制备方法 |
JP2018152497A (ja) * | 2017-03-14 | 2018-09-27 | 東芝メモリ株式会社 | 抵抗変化素子及び記憶装置 |
CN106992251B (zh) * | 2017-05-12 | 2019-08-30 | 华中科技大学 | 一种基于VOx选通管的相变存储单元 |
US11152569B2 (en) * | 2017-11-30 | 2021-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | PCRAM structure with selector device |
CN108962725B (zh) * | 2018-07-30 | 2022-10-18 | 美国麦可松科技有限公司 | 一种人构性高介电常数的介电薄膜及其制备方法 |
CN109742231A (zh) * | 2018-12-19 | 2019-05-10 | 郑州轻工业学院 | 电阻存储器件 |
CN110379919B (zh) * | 2019-05-30 | 2021-04-02 | 西安电子科技大学 | 一种阻变存储器及其制备方法 |
CN110527952A (zh) * | 2019-07-26 | 2019-12-03 | 沈阳工业大学 | 一种钛酸钡/镍酸镧铁电超晶格薄膜材料及其制备方法 |
CN110767252B (zh) * | 2019-09-04 | 2021-10-01 | 华中科技大学 | 一种多值相变存储器单元、逻辑电路及多进制运算方法 |
CN110752293A (zh) * | 2019-09-27 | 2020-02-04 | 北京大学 | 一种双向阈值开关选择器件及其制备方法 |
CN112909161B (zh) * | 2021-01-05 | 2022-03-11 | 华中科技大学 | 一种具有缓冲层的低功耗的相变存储单元及其制备方法 |
US20220384366A1 (en) * | 2021-06-01 | 2022-12-01 | Cree, Inc. | Multilayer encapsulation for humidity robustness and related fabrication methods |
CN117012250A (zh) * | 2022-04-28 | 2023-11-07 | 华为技术有限公司 | 存储芯片、存储装置和电子设备 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101101964A (zh) * | 2006-07-06 | 2008-01-09 | 三星电子株式会社 | 包括可变电阻材料的非易失存储器件 |
CN101179095A (zh) * | 2007-11-13 | 2008-05-14 | 北京大学 | 一种实现存储器功能的场效应晶体管及其制备方法 |
CN101425559A (zh) * | 2008-12-05 | 2009-05-06 | 中国科学院微电子研究所 | 电阻转变型存储器及其制造方法 |
CN101828236A (zh) * | 2007-10-17 | 2010-09-08 | 株式会社东芝 | 非易失性半导体存储器件 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4818519B2 (ja) * | 2001-02-06 | 2011-11-16 | ルネサスエレクトロニクス株式会社 | 磁気記憶装置 |
KR20030060327A (ko) * | 2002-01-08 | 2003-07-16 | 삼성전자주식회사 | 고집적 자성체 메모리 소자 및 그 구동 방법 |
KR100579844B1 (ko) * | 2003-11-05 | 2006-05-12 | 동부일렉트로닉스 주식회사 | 비휘발성 메모리 소자 및 그 제조방법 |
US20060039183A1 (en) * | 2004-05-21 | 2006-02-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-sensing level MRAM structures |
US7359226B2 (en) * | 2006-08-28 | 2008-04-15 | Qimonda Ag | Transistor, memory cell array and method for forming and operating a memory device |
WO2009011113A1 (ja) * | 2007-07-18 | 2009-01-22 | Panasonic Corporation | 電流制限素子とそれを用いたメモリ装置およびその製造方法 |
US8158964B2 (en) * | 2009-07-13 | 2012-04-17 | Seagate Technology Llc | Schottky diode switch and memory units containing the same |
US7911833B2 (en) * | 2009-07-13 | 2011-03-22 | Seagate Technology Llc | Anti-parallel diode structure and method of fabrication |
-
2011
- 2011-01-25 CN CN201110026944.2A patent/CN102610749B/zh active Active
- 2011-06-30 WO PCT/CN2011/076681 patent/WO2012100501A1/zh active Application Filing
- 2011-06-30 US US13/502,832 patent/US8665631B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101101964A (zh) * | 2006-07-06 | 2008-01-09 | 三星电子株式会社 | 包括可变电阻材料的非易失存储器件 |
CN101828236A (zh) * | 2007-10-17 | 2010-09-08 | 株式会社东芝 | 非易失性半导体存储器件 |
CN101179095A (zh) * | 2007-11-13 | 2008-05-14 | 北京大学 | 一种实现存储器功能的场效应晶体管及其制备方法 |
CN101425559A (zh) * | 2008-12-05 | 2009-05-06 | 中国科学院微电子研究所 | 电阻转变型存储器及其制造方法 |
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