WO2012068777A1 - 一种用于制造大功率器件的半导体衬底的制造方法 - Google Patents
一种用于制造大功率器件的半导体衬底的制造方法 Download PDFInfo
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- WO2012068777A1 WO2012068777A1 PCT/CN2011/001926 CN2011001926W WO2012068777A1 WO 2012068777 A1 WO2012068777 A1 WO 2012068777A1 CN 2011001926 W CN2011001926 W CN 2011001926W WO 2012068777 A1 WO2012068777 A1 WO 2012068777A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 89
- 239000010703 silicon Substances 0.000 claims abstract description 89
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 88
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 230000008569 process Effects 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 18
- 229910004166 TaN Inorganic materials 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 14
- 239000002131 composite material Substances 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 229910052718 tin Inorganic materials 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- -1 hydrogen ions Chemical class 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 238000001465 metallisation Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 53
- 238000000137 annealing Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000011449 brick Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
Definitions
- the present invention relates to the field of high voltage and high power devices, and in particular to a method for fabricating a semiconductor substrate, and more particularly to a method for fabricating a semiconductor substrate for manufacturing a high power device. Background technique
- Power semiconductor devices are the intrinsic driving force of the ever-evolving power-electronic system, especially in terms of energy saving, dynamic control, and noise reduction. Power semiconductors are primarily used for control of energy transfer between energy and load, with high accuracy, fast speed, and low power consumption. In the past 20 years, power devices and their packaging technologies have developed rapidly. Especially for power MOS transistors, with their superior input impedance and short turn-off time, traditional bipolar transistors have been replaced in many applications. Today's power MOS transistors are mainly of the type of trench MOS transistor (UMOSFET) and insulated gate bipolar transistor (IGBT).
- UDMOSFET trench MOS transistor
- IGBT insulated gate bipolar transistor
- the IGBT is a composite full-control voltage-driven power semiconductor device composed of a BJT (bipolar transistor) and a MOS transistor.
- An N-channel enhancement type IGBT device has a structure as shown in FIG. 1.
- N-type source regions 104a, 104b are formed in a p-type base region (sub-channel region) 103a, 103b, respectively, and the gate stack region 110 includes a gate.
- the dielectric layer 105 and the gate electrode 106, the gate dielectric layer 105 is, for example, silicon dioxide, and the gate electrode 106 is, for example, doped polysilicon.
- the channel region in which the device operates is formed at the bottom surface of the substrate adjacent to the boundary of the gate stack region 110.
- the n-type drift region 102 is formed over the n-type drain region 101, and the p+ region 100 on the other side of the drain region 101 is referred to as a drain-injection region, which is a functional region unique to the IGBT, which is formed together with the drain region and the sub-channel region.
- the PNP bipolar transistor functions as an emitter, injects holes into the drain region, and conducts conductive modulation to lower the on-state voltage of the device.
- the switching function of the IGBT is to form a channel by adding a forward gate voltage, provide a base current to the PNP transistor, and turn the IGBT on. Conversely, add a reverse gate voltage to eliminate the channel, cut off the base current, and turn off the IGBT. .
- the IGBT combines the high input impedance of the MOSFET with the GTR (Giant Transistor) voltage drop, which is ideal for converter systems with DC voltages of 600V and above, such as AC motors, inverters. , switching power supply, lighting circuit, traction drive, etc.
- GTR Gate Transistor
- mainstream IGBT devices require a region-fused silicon material as a substrate, and a region-fused silicon substrate material is expensive.
- a backside ion implantation and a low temperature annealing process are required, which is liable to cause damage to the front metal, and a complicated thinning process on the back surface is required, which easily damages the silicon wafer. Disclosure of invention
- the object of the present invention is to propose a novel half for manufacturing IGBT devices.
- the conductor substrate manufacturing method is used to avoid the backside ion implantation and low-temperature annealing processes performed during the manufacture of the IGBT device, and the thinning process on the back side, to process the processing of the IGBT device, and to improve the production yield.
- the method for fabricating a semiconductor substrate for manufacturing a high-power device is a method for forming a semiconductor substrate by bonding a region-fused silicon wafer and a highly doped Czochral silicon wafer, and the specific steps include:
- the first step processing the required zone of molten silicon, the process is:
- the silicon substrate is subjected to hydrogen ion (H+) implantation and annealing, and the inside of the silicon wafer forms an H heavily doped layer; brick or boron ion implantation is performed to form between the H heavily doped layer and the surface of the silicon wafer a first doping type of buffer layer;
- H+ hydrogen ion
- boron ion implantation is performed to form between the H heavily doped layer and the surface of the silicon wafer a first doping type of buffer layer;
- the first doping type is phosphorus ion
- boron ion implantation is performed, and a high concentration doping having a second doping type is formed on the silicon surface and the buffer layer of the first doping type a dummy region having a depth smaller than a buffer layer of the first doping type
- the first doping type is boron ion
- performing phosphorus ion implantation on the silicon surface and the first a doping type upper portion of the buffer layer forms a high concentration doped region having a second doping type, the depth of which is smaller than the buffer layer of the first doping type
- the second step processing the required highly doped Czochralski silicon wafer, the process is:
- the third step bonding the diffusion barrier layer of the region-fused silicon wafer formed in the first step to the metal or metal nitride on the highly doped Czochral silicon wafer formed in the second step, and then stripping the region-fused silicon The H layer in the sheet and the portion of the H layer above the H layer.
- the first doping type is p-type doping or n-type doping.
- the diffusion barrier layer is a TaN, TiN, Ta/TaN composite layer or a Ti/TiN composite layer having a thickness ranging from 10 to 50 nm.
- the metal or metal nitride is a high temperature resistant metal material such as W, Ti, Ta, TiN or TaN.
- the metal island structure in the highly doped Czochralski silicon wafer needs to match the groove structure formed in the region-fused silicon wafer to ensure that there is no gap after bonding the two silicon wafers.
- the bonded region-fused silicon wafer is used to prepare the IGBT device, and the highly doped Czochralski wafer is used as the low-resistance back contact.
- the amount of molten silicon in the region is reduced, and a region of molten silicon can form a plurality of bonded composite silicon wafers, and the P strip has a low production cost.
- Figure 1 is a cross-sectional view showing a prior art N-channel enhancement type IGBT device.
- 2a to 2d are process flow diagrams of an embodiment of preparing a region-fused silicon wafer according to the present invention.
- 3a to 3c are process flow diagrams of an embodiment of preparing a highly doped Czochralski silicon wafer provided by the present invention.
- 4a to 4b are flow charts showing the process of bonding between a region-fused silicon wafer and a highly doped Czochralella wafer according to the present invention.
- 5a to 5b are process flow diagrams for fabricating an IGBT device using the semiconductor substrate provided by the present invention. The best way to implement the invention
- a lightly doped n-type zone fused silicon substrate 201 is provided, as shown in Figure 2a.
- an H layer 202 is formed in the region-fused silicon substrate 201 by hydrogen ion (H+) implantation, and the H layer 202 divides the region-fused silicon substrate 201 into upper and lower portions 201a and 201b, as shown in Fig. 2b.
- an n-type buffer layer 203 is formed by n-type ion implantation, and then a p-type doping region 204 is formed by p-type ion implantation as shown in Fig. 2c.
- an insulating medium 205 is deposited on the fused silicon substrate 201.
- the insulating medium is, for example, silicon nitride, and then the silicon nitride layer 205 is etched to form an opening, and then a diffusion barrier layer 206 is deposited to diffuse.
- the barrier layer 206 may be a TaN, TaN, Ti/TaN composite layer or a Ti/TiN composite layer. Since the etched silicon nitride layer 205 is formed with an opening, the diffusion barrier layer 206 is deposited to form a recess 207 in the region fused silicon substrate 201, as shown in Fig. 2d. Thus, the region-fused silicon wafer structure 200 required for fabricating the semiconductor substrate proposed by the present invention is formed.
- a highly doped p-type Czochralski silicon substrate 301 is provided, as shown in Figure 3a.
- a diffusion barrier layer 302 is deposited on the silicon substrate 301.
- the diffusion barrier layer 302 may be a TaN, TaN, Ti/TaN composite layer or a Ti/TiN composite layer.
- a layer of high temperature resistant metal is deposited on the diffusion barrier layer 302, such as W, Ti, Ta,
- TaN or TaN is then etched to form a metal island 303, as shown in Figure 3c.
- the low resistance silicon wafer structure 300 required for fabricating the semiconductor substrate proposed by the present invention is formed.
- the metal islands 303 formed in the low resistance silicon wafer 300 are matched with the groove structures 207 formed in the region melting silicon wafer 200.
- the formed region fused silicon wafer 200 is reversed and bonded to the low resistance silicon wafer 300 to form a structure as shown in FIG. 4a, wherein the metal island 303 in the low resistance silicon wafer 300 is placed just in the region fused silicon wafer 200. In the groove 207 in the middle.
- the semiconductor substrate structure 400 proposed by the present invention is formed.
- the semiconductor substrate of the present invention is not suitable for the fabrication of a large power device such as an IGBT.
- a silicon oxide layer 401 is formed on the semiconductor substrate 400 as shown in FIG. 4b, and then a metal is sequentially deposited to form a metal.
- the layer 402 and a layer of photoresist are then masked, exposed, and etched to form a gate structure of the IGBT device. After the photoresist is stripped, as shown in FIG. 5a, wherein the metal layer 402 is doped, for example. Multi-silicon.
- the p-type base regions 403a, 403b of the IGBT device are formed by an ion implantation process, and then the source regions 404a, 404b of the IGBT device are formed in the p-type base regions 403a, 403b by an ion implantation process, as shown in FIG. 5b. .
- the invention adopts the use of a region-fused silicon wafer to bond with a highly doped Czochralski silicon wafer to form a semiconductor substrate, and a region-fused silicon wafer and a highly doped silicon-drawn silicon wafer are bonded, and the bonded region-fused silicon wafer is bonded.
- a region-fused silicon wafer and a highly doped silicon-drawn silicon wafer are bonded, and the bonded region-fused silicon wafer is bonded.
- high-doped Czochralski wafers as low-resistance back contacts, so that the amount of molten silicon required is reduced, and a region of molten silicon can form multi-bonded composite silicon wafers, reducing production costs.
- the front surface of the fused silicon wafer before bonding becomes the back electrode of the IGBT device after bonding, ion implantation is performed on the front surface of the fused silicon wafer before bonding, and ion implantation of the back is no longer required after bonding
- the low-temperature annealing process simplifies the processing process; the high-temperature metal is used as the medium between the two wafers when the silicon wafer is bonded, which can eliminate the metallization process of the back and improve the production yield.
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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Description
一种用于制造大功率器件的半导体衬底的制造方法 技术领域
本发明属于高压大功率器件技术领域, 具体涉及一种半导体衬底的制造 方法, 特别涉及一种用于制造大功率器件的半导体衬底的制造方法。 背景技术
功率半导体器件是不断发展的功率 -电子***的内在驱动力,尤其是在节 约能源、 动态控制、 噪声减少等方面, 有着不可替代的功效。 功率半导体主 要应用于对能源与负载之间能量传递的控制, 拥有精度高、 速度快和功耗低 的特点。 最近 20年来, 功率器件及其封装技术迅猛发展, 尤其是功率 MOS 晶体管, 以其输入阻抗高、 关断时间短等优越的特性, 在许多应用领域中取 代了传统的双极型晶体管。如今的功率 MOS晶体管主要有沟槽型 MOS晶体 管 (UMOSFET )和绝缘栅双极型晶体管 (IGBT )等类型。
IGBT是由 BJT (双极型三极管)和 MOS晶体管组成的复合全控型电压驱 动式功率半导体器件。 一种 N沟道增强型 IGBT器件的结构如图 1所示, n 型源区 104a、 104b分别形成在 p型基区 (亚沟道区) 103a、 103b之中, 栅 叠层区 110包括栅介质层 105和栅电极 106,栅介质层 105比如为二氧化硅, 栅电极 106比如为掺杂的多晶硅。器件工作时的沟道区域在紧靠栅叠层区 110 边界的村底表面形成。 n型漂移区 102形成在 n型漏区 101之上,在漏区 101 另一侧的 p+区 100称为漏注入区, 它是 IGBT特有的功能区, 与漏区和亚沟 道区一起形成 PNP双极晶体管, 起发射极的作用, 向漏区注入空穴, 进行 导电调制, 以降低器件的通态电压。 IGBT 的开关作用是通过加正向栅极电 压形成沟道, 给 PNP晶体管提供基极电流, 使 IGBT导通, 反之, 加反向栅 极电压消除沟道, 切断基极电流, 使 IGBT 关断。 IGBT兼有 MOSFET的高 输入阻抗和 GTR(Giant Transistor, 电力晶体管) 的^ ί氏导通压降两方面的优点, 非常适合应用于直流电压为 600V及以上的变流***,如交流电机、 变频器、 开关电源、 照明电路、 牵引传动装置等。
目前, 主流的 IGBT器件需要以区熔硅材料作为衬底, 而区熔硅衬底材 料的价格昂贵。 而且, 在现有技术制造 IGBT器件时, 需要进行背面离子注 入与低温退火工艺, 容易对正面金属造成损伤, 同时还需要对背面进行复杂 的减薄工艺, 容易损坏硅片。 发明的公开
有鉴于此, 本发明的目的在于提出一种新型的用于制造 IGBT器件的半
导体衬底制造方法, 以避免在制造 IGBT器件时进行的背面离子注入与低温 退火工艺、 以及背面的减薄工艺, 筒化 IGBT器件的加工制程, 提高生产良 率。
本发明提出的用于制造大功率器件的半导体衬底制造方法, 是采用区熔 硅片与高掺杂直拉硅片进行键合形成半导体衬底的加工方法, 具体步骤包 括:
第一步: 加工出所需要的区熔硅片, 其过程为:
提供一个硅村底;
硅衬底进行氢离子(H+ )注入并退火, 硅片的内部形成 H重掺杂层; 进行磚或者硼离子注入, 以在介于 H重掺杂层和所述硅片表面之间形成 具有第一种掺杂类型的緩冲层;
如果所述第一种掺杂类型为磷离子, 则进行硼离子注入, 在所述硅表面 以及所述第一种掺杂类型的緩冲层上部形成具有第二种掺杂类型的高浓度掺 杂区, 其深度小于所述的第一种掺杂类型的緩冲层; 如果所述第一种掺杂类 型为硼离子, 则进行磷离子注入, 在所述硅表面以及所述第一种掺杂类型的 緩冲层上部形成具有第二种掺杂类型的高浓度掺杂区, 其深度小于所述的第 一种掺杂类型的緩冲层;
在所述硅片表面形成第一层绝缘薄膜,
在所述第一层绝缘薄膜之上形成第一层光刻胶;
进行掩膜、 曝光、 刻蚀, 留下硅片边缘一圈的第一层绝缘膜; 剥除第一层光刻胶; *
在所述硅片表面以及第一层绝缘膜之上形成一层扩散阻挡层;
第二步: 加工出所需要的高摻杂直拉硅片, 其过程为:
提供一个高掺杂直拉硅衬底, 所述直拉硅衬底具有与第一步的所述第一 种掺杂类型相同的掺杂类型;
在所述直拉硅衬底上表面形成一层扩散阻挡层;
在上一步形成的所述扩散阻挡层上面形成一层金属或者金属氮化物; 在上一步形成的所述金属或者金属氮化物上形成第一层光刻胶; 在上一步形成的所述第一层光刻胶进行光刻, 之后刻蚀掉所述直拉硅片 边缘一圈的扩散阻挡层和金属或金属氮化物;
剥除第一层光刻胶;
第三步: 将第一步中形成的区熔硅片的扩散阻挡层与第二步中形成的高 掺杂直拉硅片上的金属或金属氮化物进行键合,然后剥除区熔硅片中的 H层 以及 H层以上的区熔硅片部分。
进一步地, 所述的第一种掺杂类型为 p型掺杂或者为 n型掺杂。 所述的
扩散阻挡层为 TaN、 TiN、 Ta/TaN复合层或者为 Ti/TiN复合层, 其厚度范围 为 10-50纳米。 所述的金属或者金属氮化物为 W、 Ti、 Ta、 TiN或 TaN等耐 高温金属材料。
需要注意的是, 高掺杂直拉硅片中的金属岛结构需与区熔硅片中形成的 凹槽结构相匹配, 以保证两种硅片键合后无缝隙。
本发明所提出的采用区熔硅片与高掺杂直拉硅片进行键合形成半导体衬 底的优点是:
1、将区熔硅片和高掺杂直拉硅片进行键合,键合后的区熔硅片用于制备 IGBT 器件, 高掺杂直拉硅片作为低阻的背部接触, 这样所需要的区熔硅的 量减少, 一片区熔硅可以形成多片键合的复合硅片, P条低了生产成本。
2、 由于键合前的区熔硅片的正面在键合后成为 IGBT器件的背部电极, 因此在键合前对区熔硅片的正面进行离子注入, 键合后不再需要进行背部的 离子注入与低温退火工艺, 简化了加工制程。
3、采用耐高温金属作为硅片键合时两片硅片中间的媒介,可以省去背部 金属化的工艺, 提高生产良率。
附图的筒要说明
图 1为现有技术的一种 N沟道增强型 IGBT器件的剖面图。
图 2a至图 2d为本发明提供的一种制备区熔硅片的实施例工艺流程图。 图 3a至图 3c为本发明提供的一种制备高掺杂直拉硅片的实施例工艺流 程图。
图 4a至图 4b为本发明提出的采用区熔硅片与高掺杂直拉硅片进行键合 的工艺流程图。
图 5a至图 5b为采用本发明提供的半导体衬底制备 IGBT器件的工艺流 程图。 实现本发明的最佳方式
下面将参照附图对本发明的示例性实施方式作详细说明。 在图中, 为了 方便说明, 放大了层和区域的厚度, 所示大小并不代表实际尺寸。 尽管这些 图并不是完全准确的反映出器件的实际尺寸, 但是它们还是完整的反映了区 域和组成结构之间的相互位置, 特别是组成结构之间的上下和相邻关系。
参考图是本发明的理想化实施例的示意图, 本发明所示的实施例不应该 被认为仅限于图中所示区域的特定形状, 而是包括所得到的形状, 比如制造 引起的偏差。 同时在下面的描述中, 所使用的术语硅片和衬底可以理解为包
括正在工艺加工中的半导体晶片, 可能包括在其上所制备的其它薄膜层。 区熔硅片的制备:
首先, 提供一个轻掺杂 n型的区熔硅村底 201, 如图 2a所示。 接下来, 通过氢离子(H+ )注入在区熔硅衬底 201内形成 H层 202, H层 202将区熔 硅村底 201分割为 201a和 201b上下两个部分, 如图 2b所示。
接下来, 通过 n型离子注入形成 n型緩冲层 203, 接着通过 p型离子注 入形成 p型掺杂区 204, 如图 2c所示。
接下来, 在区熔硅村底 201上淀积一层绝缘介质 205, 绝缘介质比如为 氮化硅, 然后刻蚀氮化硅层 205形成开口, 接着再淀积一层扩散阻挡层 206, 扩散阻挡层 206可以为 TaN、 TaN、 Ti/TaN复合层或者为 Ti/TiN复合层。 由 于刻蚀氮化硅层 205形成开口的缘故, 淀积扩散阻挡层 206后会在区熔硅衬 底 201上形成一个凹槽 207, 如图 2d所示。 这样用于制造本发明提出的半导 体村底所需要的区熔硅片结构 200便形成了。
低阻硅片的制备:
首先, 提供一个高掺杂 p型的直拉硅村底 301, 如图 3a所示。 接下来, 在硅衬底 301上淀积形成扩散阻挡层 302, 如图 3b所示, 扩散阻挡层 302可 以为 TaN、 TaN、 Ti/TaN复合层或者为 Ti/TiN复合层。
接下来, 在扩散阻挡层 302上淀积一层耐高温金属, 比如为 W、 Ti、 Ta、
TaN或者为 TaN, 然后刻蚀所形成的金属层形成金属岛 303 , 如图 3c所示。 这样用于制造本发明提出的半导体衬底所需要的低阻硅片结构 300便形成 了。
需要注意的是, 低阻硅片 300中形成的金属岛 303需与区熔硅片 200中 形成的凹槽结构 207相匹配。
用于制造大功率器件的半导体衬底的制备:
将所形成的区熔硅片 200倒扣后与低阻硅片 300键合,形成如图 4a所示 的结构, 其中, 低阻硅片 300中的金属岛 303恰好置于区熔硅片 200中的凹 槽 207之中。
接下来, 剥除区熔硅村底 201中的衬底 201b部分和 H层 202, 然后采用 CMP工艺将其平坦化,如图 4b所示。这样本发明提出的半导体衬底结构 400 就形成了。
本发明所 出的半导体^"底非 适用于 IGBT等大功†器件的制造,口以 首先, 在如图 4b所示的半导体衬底 400上氧化形成二氧化硅层 401 , 然 后依次淀积形成金属层 402和一层光刻胶,接着掩膜、曝光、刻蚀形成 IGBT 器件的栅极结构, 剥除光刻胶后如图 5a所示, 其中, 金属层 402比如为掺杂
的多经硅。
接下来, 通过离子注入工艺, 形成 IGBT器件的 p型基区 403a、 403b, 然后继续通过离子注入工艺在 p型基区 403a、 403b中形成 IGBT器件的源区 404a、 404b, 如图 5b所示。 工业应用性
本发明所提出的采用区熔硅片与高掺杂直拉硅片进行键合形成半导体村 底将区熔硅片和高掺杂直拉硅片进行键合, 键合后的区熔硅片用于制备 IGBT 器件, 高掺杂直拉硅片作为低阻的背部接触, 这样所需要的区熔硅的 量减少, 一片区熔硅可以形成多片键合的复合硅片, 降低了生产成本; 由于 键合前的区熔硅片的正面在键合后成为 IGBT器件的背部电极, 因此在键合 前对区熔硅片的正面进行离子注入, 键合后不再需要进行背部的离子注入与 低温退火工艺, 简化了加工制程; 采用耐高温金属作为硅片键合时两片硅片 中间的媒介, 可以省去背部金属化的工艺, 提高生产良率。
如上所述, 在不偏离本发明精神和范围的情况下, 还可以构成许多有很 大差别的实施例。 应当理解, 除了如所附的权利要求所限定的, 本发明不限 于在说明书中所述的具体实例。
Claims
1、一种用于制造大功率器件的半导体衬底制造方法,其特征在于是采用 区熔硅片与高掺杂直拉硅片进行键合形成半导体衬底, 具体步骤为:
第一步: 加工出所需要的区熔硅片, 其过程为:
提供一个硅衬底;
硅衬底进行氢离子(H+ ) 注入并退火, 硅片的内部形成 H重掺杂层; 进行碑或者硼离子注入, 以在介于 H重掺杂层和所述硅片表面之间形成 具有第一种摻杂类型的緩冲层;
如果所述第一种掺杂类型为磷离子, 则进行硼离子注入, 在所述硅表面 以及所述第一种掺杂类型的緩冲层上部形成具有第二种掺杂类型的高浓度掺 杂区, 其深度小于所述的第一种掺杂类型的緩沖层; 如果所述第一种掺杂类 型为硼离子, 则进行碑离子注入, 在所述硅表面以及所述第一种掺杂类型的 緩冲层上部形成具有第二种渗杂类型的高浓度掺杂区, 其深度小于所述的第 一种掺杂类型的緩冲层;
在所述硅片表面形成第一层绝缘薄膜,
在所述第一层绝缘薄膜之上形成第一层光刻胶;
进行掩膜、 曝光、 刻蚀, 留下硅片边缘一圈的第一层绝缘膜; 剥除第一层光刻胶;
在所述硅片表面以及第一层绝缘膜之上形成一层扩散阻挡层; 第二步: 加工出所需要的高掺杂直拉硅片, 其过程为:
提供一个高掺杂直拉硅衬底, 所述直拉硅衬底具有与第一步的所述第一 种掺杂类型相同的渗杂类型;
在所述直拉硅衬底上表面形成一层扩散阻挡层;
在上一步形成的所述扩散阻挡层上面形成一层金属或者金属氮化物; 在上一步形成的所述金属或者金属氮化物上形成第一层光刻胶; 在上一步形成的所述第一层光刻胶进行光刻, 之后刻蚀掉所述直拉硅片 边缘一圏的扩散阻挡层和金属或金属氮化物;
剥除第一层光刻胶;
第三步: 将第一步中形成的区熔硅片的扩散阻挡层与第二步中形成的高 掺杂直拉硅片上的金属或金属氮化物进行键合, 然后剥除区熔硅片中的 H层 以及 H层以上的区熔硅片部分。
2、根据权利要求 1所述的制造方法, 其特征在于, 第一步中所述的第一 层绝缘薄膜为氧化硅或者为氮化硅。
3、根据权利要求 1或 2所述的制造方法, 其特征在于, 第一步中所述的 扩散阻挡层为 TaN、 TiN、 Ta/TaN复合层或者为 Ti/TiN复合层, 其厚度范围 为 10-50纳米。
4、根据权利要求 1或 2所述的制造方法, 其特征在于, 第一步中所述的 第一种掺杂类型为 n型掺杂, 第二种掺杂类型为 p型掺杂; 或者, 所述的第 一种掺杂类型为 p型掺杂, 第二种掺杂类型为 n型掺杂。
5、根据权利要求 1所述的制造方法, 其特征在于, 第二步中所述的第一 种掺杂类型为 p型掺杂或者为 n型掺杂。
6、根据权利要求 1所述的制造方法, 其特征在于, 第二步中所述的扩散 阻挡层为 Ta/TaN复合层、 Ti/TiN复合层、 TaN或者 TiN,其厚度范围为 10-50 纳米。
7、根据权利要求 1所述的制造方法, 其特征在于, 第二步中所述的金属 或金属氮化物为 W、 Ti、 Ta、 TiN或 TaN。
8、根据权利要求 1所述的制造方法, 其特征在于, 所述低阻硅片中的金 属岛结构与所述区熔硅片中形成的凹槽结构相匹配, 键合后无缝隙。
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