WO2012066804A1 - Procédé pour fabriquer un substrat semi-conducteur, et élément émetteur de lumière - Google Patents

Procédé pour fabriquer un substrat semi-conducteur, et élément émetteur de lumière Download PDF

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Publication number
WO2012066804A1
WO2012066804A1 PCT/JP2011/060151 JP2011060151W WO2012066804A1 WO 2012066804 A1 WO2012066804 A1 WO 2012066804A1 JP 2011060151 W JP2011060151 W JP 2011060151W WO 2012066804 A1 WO2012066804 A1 WO 2012066804A1
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WO
WIPO (PCT)
Prior art keywords
substrate
semiconductor layer
region
mask
semiconductor
Prior art date
Application number
PCT/JP2011/060151
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English (en)
Japanese (ja)
Inventor
義之 川口
啓一郎 渡辺
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京セラ株式会社
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Publication date
Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to JP2012544120A priority Critical patent/JP5591349B2/ja
Publication of WO2012066804A1 publication Critical patent/WO2012066804A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • a method of manufacturing a semiconductor substrate includes a step of covering a first region on a surface of a substrate with a mask, and a surface on which fluorine is attached to a second region exposed from the mask on the surface of the substrate. After the step of processing, the step of performing the surface processing, the step of removing the mask, and the step of growing a semiconductor layer from the first region to the second region where the mask is removed.
  • the mask is removed and the semiconductor layer is grown. Therefore, the crystallinity of the semiconductor layer stacked on the substrate can be improved.
  • the crystallinity of the optical semiconductor layer formed on the planar substrate is good, a light emitting device with high light emission efficiency can be provided.
  • the substrate 2 for example, single crystal or polycrystal such as sapphire, gallium nitride, aluminum nitride, zinc oxide, silicon carbide, silicon, or zirconium diboride can be used. Further, as the substrate 2, for example, a bonded substrate in which sapphire is bonded onto a silicon substrate may be used. In this example, the substrate 2 is composed of a single crystal of sapphire.
  • the first main surface 2A of the substrate 2 is a flat crystal growth surface.
  • the first main surface 2A of the substrate 2 for example, one having the crystal planes of the substrate 2 aligned can be used. If the substrate 2 is sapphire, the crystal plane of the substrate 2 can be, for example, the A-plane, C-plane or R-plane of sapphire.
  • gallium nitride having a crystal structure of hexagonal crystal is used as the semiconductor layer 7 grown on the substrate 2, so that the shape of the surface covered with the mask 3 (covered surface 2 a) in plan view Is set in a hexagonal shape.
  • processing solution 6 As a method of applying the processing solution 6 on the substrate 2, for example, spin coating application in which the processing solution 6 is applied by spin coating, or the processing solution 6 is dropped onto a roller and applied while pressing the substrate 2 with the roller. Roller coating, spray coating in which the processing solution 6 is sprayed toward the first exposed surface 2b of the substrate 2, or dip coating in which the substrate 2 is immersed in the processing solution 6 can be used.
  • fluorine can be attached to the first exposed surface 2 b of the substrate 2 as shown in FIG. 4.
  • the first exposed surface 2b to which fluorine of the substrate 2 is attached is appropriately referred to as an attached surface 2b '.
  • the mask 3 is removed from the substrate 2.
  • the surface of the first main surface 2A of the substrate 2 covered with the mask 3 is appropriately referred to as a second exposed surface 2a ′.
  • a solution that hardly dissolves the substrate 2 while dissolving the mask 3 may be used as a solution for removing the mask 3.
  • the material used for such a solution can be selected depending on, for example, the ratio between the amount that dissolves the mask 3 and the amount that dissolves the substrate 2.
  • hydrogen sulfide, hydrogen chloride, nitric acid, or the like can be used as a solution for removing the mask 3.
  • a solution containing nitric acid which is a solution that hardly dissolves sapphire of the substrate 2 while dissolving nickel of the mask 3, is used. it can.
  • a semiconductor growth substrate 2 ′ having a plurality of second exposed surfaces 2a ′ and an adhesion surface 2b ′ on which fluorine is present on the first main surface 2A is manufactured. Can do. As will be described later, by performing semiconductor growth using such a semiconductor growth substrate 2 ', a semiconductor layer with improved crystallinity can be provided.
  • the semiconductor layer 7 is configured by sequentially laminating a first semiconductor layer 7a, a light emitting layer 7b, and a second semiconductor layer 7c.
  • the entire thickness of the semiconductor layer 7 is set to, for example, 0.5 ⁇ m or more and 20 ⁇ m or less.
  • the first semiconductor layer 7a and the second semiconductor layer 7c are set so that either electrons or holes are majority carriers. Accordingly, the first semiconductor layer 7a and the second semiconductor layer 7c are set to exhibit opposite conductivity types.
  • a method for imparting conductivity type to a semiconductor for example, a method of adding magnesium, zinc, or silicon as an impurity can be used.
  • a molecular beam epitaxial method, an organic metal epitaxial method, a hydride vapor phase growth method, a pulse laser deposition method, or the like can be used.
  • a method for crystal growth of the semiconductor layer 7 from the second exposed surface 2a ′ to the adhesion surface 2b ′ of the substrate 2 a method of adjusting growth conditions such as the composition ratio, growth temperature, and growth pressure of the semiconductor layer 7 is used. Can do.
  • the crystal quality of the semiconductor layer 7 can be improved, and the light emission efficiency of the semiconductor layer 7 can be improved. Further, when the first semiconductor layer 7a is crystal-grown in the lateral direction and dislocations are coupled in the first semiconductor layer 7a of the semiconductor layer 7, dislocations extending to the light emitting layer 7b can be reduced. Therefore, it is possible to widen the region where the light emitting layer 7b emits light.
  • a substrate 2 having an attached surface 2b 'obtained by performing surface processing by attaching fluorine to the surface was produced as an example.
  • the analysis result of the substrate 2 is shown in FIG. Specifically, the substrate 2 produced this time was subjected to surface processing for adhering fluorine to the surface of the substrate 2 by immersing the substrate 2 made of sapphire in a 50% concentration hydrofluoric acid solution for 10 minutes. Thereafter, the surface-treated substrate 2 was washed with pure water for 3 minutes to wash the hydrofluoric acid solution adhering to the surface of the substrate 2.
  • the adhesion surface 2b 'of the substrate 2 is chemically terminated with fluorine, so that the fluorine can be adhered more firmly to the first exposed surface 2b of the substrate 2.
  • the semiconductor layer 7 can be made difficult to adhere to the attachment surface 2 b ′ of the substrate 2, so that the yield of the process of growing the semiconductor layer 7 on the substrate 2 can be improved.
  • a crystal 8 made of a constituent element of the semiconductor layer 7 is grown on the second exposed surface 2a ′ of the substrate 2.
  • the crystal body 8 has dislocations 9 extending inward from the second exposed surface 2 a ′ of the substrate 2, for example, because the lattice constant and the thermal expansion coefficient are different from those of the substrate 2. Dislocations 9 are likely to occur due to the occurrence of unintended crystal planes or atomic steps in the crystal plane of the semiconductor layer to be crystal-grown, and include, for example, edge dislocations or spiral dislocations.
  • the second crystal body 10 is further grown in the lateral direction so that the two adjacent second crystal bodies 10 are brought together as shown in FIG. 9C.
  • the dislocations 9 extending from the respective second crystal bodies 10 can be combined, and the number of dislocations 9 extending in the thickness direction from the bonding location can be reduced.
  • a process of forming the crystal body 8 on the low temperature buffer layer 13 performed after the process of forming the low temperature buffer layer 13 will be described.
  • the crystal 8 is grown on the upper surface of the low-temperature buffer layer 13 formed on the second exposed surface 2a 'of the substrate 2.
  • the temperature of the substrate 2 is lower than the normal crystal growth temperature, so that the semiconductor is further hardly grown on the adhesion surface 2b ′ of the substrate 2. be able to.
  • the crystal 8 since crystals easily grow on the upper surface of the low-temperature buffer layer 13 formed on the second exposed surface 2a ′ of the substrate 2, the crystal 8 is formed on the second exposed surface 2a ′ of the substrate 2. It can be easy to grow.
  • dip coating may be performed in which the laminated body in which the mask 3 is formed on the substrate 2 is immersed in the processing solution 6.
  • the immersion time can be set to, for example, 5 minutes or more and 60 minutes or less.
  • the surface processing of the substrate 2 is performed by dip coating in which the laminate is immersed in the processing solution 6, fluorine can be adhered to the side surface 2C and the second main surface 2B of the substrate 2 as well. Thereby, in the process of growing the semiconductor layer 7, it is possible to suppress the growth of the semiconductor from the surface of the substrate 2 other than the second exposed surface 2a 'of the substrate 2. Further, when surface processing is performed in this manner, the light-emitting element 1 is mounted on a circuit board or the like with the second main surface 2B of the substrate 2 as a mounting surface because it is easily attached to the second main surface 2B of the substrate 2 by fluorine. At this time, unnecessary surface potential is not formed, and current leakage to the surface can be suppressed.
  • the portion 7a ′ overlapping the second region 5b in plan view may be located away from the first major surface 2A of the substrate 2 as shown in FIG. Specifically, the portion 7a ′ overlapping the second region 5b on the lower surface of the first semiconductor layer 7a may be at least part of the lower surface of the first semiconductor layer 7a.
  • FIG. 15 is an enlarged cross-sectional view of a part of the substrate 2 and the semiconductor layer 7. Since the first semiconductor layer 7a is located away from a part of the first main surface 2A of the substrate 2, the entire lower surface of the first semiconductor layer 7a is not in contact with the entire first main surface 2A of the substrate 2. Yes. Therefore, compared with the case where the first semiconductor layer is in contact with the entire main surface of the substrate, the stress related to the interface between the substrate 2 and the first semiconductor layer 7a can be relaxed.
  • a portion 7a ′ overlapping the second region 5b of the lower surface of the first semiconductor layer 7a is separated from the first main surface 2A of the substrate 2, whereby a space 14 is formed between the substrate 2 and the first semiconductor layer 7a ′.
  • the space 14 between the substrate 2 and the first semiconductor layer 7a the light emitted from the light emitting layer 7b is converted into a difference in refractive index between the first semiconductor layer 7a and the space 14, Alternatively, it can be scattered by the difference in refractive index between the space 7a ′ and the substrate 2. As a result, light emission unevenness of the light emitting element 1 can be improved.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Led Devices (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

L'invention porte sur un procédé pour fabriquer un substrat semi-conducteur, lequel procédé comprend : une étape dans laquelle une première région de la surface d'un substrat est recouverte d'un masque ; une étape dans laquelle un traitement de surface, dans lequel du fluor adhère à une seconde région de la surface du substrat exposée à partir du masque, est effectuée ; une étape dans laquelle le masque est retiré après l'étape dans laquelle le traitement de surface est effectué ; et une étape dans laquelle une couche semi-conductrice croît à partir de la première région, à partir de laquelle le masque a été retiré, vers la seconde région.
PCT/JP2011/060151 2010-11-19 2011-04-26 Procédé pour fabriquer un substrat semi-conducteur, et élément émetteur de lumière WO2012066804A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012544120A JP5591349B2 (ja) 2010-11-19 2011-04-26 半導体基板の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-258793 2010-11-19
JP2010258793 2010-11-19

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WO2012066804A1 true WO2012066804A1 (fr) 2012-05-24

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000174393A (ja) * 1998-12-04 2000-06-23 Fuji Electric Co Ltd Ｉｉｉ族窒化物半導体およびその製造方法、およびｉｉｉ族窒化物半導体装置
JP2000340511A (ja) * 1999-03-23 2000-12-08 Mitsubishi Cable Ind Ltd ＧａＮ系化合物半導体結晶の成長方法及び半導体基材
JP2000357843A (ja) * 1999-06-15 2000-12-26 Nichia Chem Ind Ltd 窒化物半導体の成長方法
JP2002217116A (ja) * 2001-01-18 2002-08-02 Sony Corp 結晶膜、結晶基板および半導体装置の製造方法
JP2004288934A (ja) * 2003-03-24 2004-10-14 Kyocera Corp サファイア基板とその製造方法、エピタキシャル基板および半導体装置とその製造方法
JP2006278477A (ja) * 2005-03-28 2006-10-12 Kyocera Corp 半導体成長用基板、エピタキシャル基板とそれを用いた半導体装置、および、エピタキシャル基板の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000174393A (ja) * 1998-12-04 2000-06-23 Fuji Electric Co Ltd Ｉｉｉ族窒化物半導体およびその製造方法、およびｉｉｉ族窒化物半導体装置
JP2000340511A (ja) * 1999-03-23 2000-12-08 Mitsubishi Cable Ind Ltd ＧａＮ系化合物半導体結晶の成長方法及び半導体基材
JP2000357843A (ja) * 1999-06-15 2000-12-26 Nichia Chem Ind Ltd 窒化物半導体の成長方法
JP2002217116A (ja) * 2001-01-18 2002-08-02 Sony Corp 結晶膜、結晶基板および半導体装置の製造方法
JP2004288934A (ja) * 2003-03-24 2004-10-14 Kyocera Corp サファイア基板とその製造方法、エピタキシャル基板および半導体装置とその製造方法
JP2006278477A (ja) * 2005-03-28 2006-10-12 Kyocera Corp 半導体成長用基板、エピタキシャル基板とそれを用いた半導体装置、および、エピタキシャル基板の製造方法

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